xref: /OK3568_Linux_fs/kernel/drivers/media/pci/ddbridge/ddbridge.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ddbridge.h: Digital Devices PCIe bridge driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2010-2017 Digital Devices GmbH
6*4882a593Smuzhiyun  *                         Ralph Metzler <rmetzler@digitaldevices.de>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
9*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License
10*4882a593Smuzhiyun  * version 2 only, as published by the Free Software Foundation.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful,
13*4882a593Smuzhiyun  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15*4882a593Smuzhiyun  * GNU General Public License for more details.
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #ifndef _DDBRIDGE_H_
19*4882a593Smuzhiyun #define _DDBRIDGE_H_
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/clk.h>
22*4882a593Smuzhiyun #include <linux/completion.h>
23*4882a593Smuzhiyun #include <linux/delay.h>
24*4882a593Smuzhiyun #include <linux/device.h>
25*4882a593Smuzhiyun #include <linux/dvb/ca.h>
26*4882a593Smuzhiyun #include <linux/gpio.h>
27*4882a593Smuzhiyun #include <linux/i2c.h>
28*4882a593Smuzhiyun #include <linux/init.h>
29*4882a593Smuzhiyun #include <linux/interrupt.h>
30*4882a593Smuzhiyun #include <linux/io.h>
31*4882a593Smuzhiyun #include <linux/kthread.h>
32*4882a593Smuzhiyun #include <linux/module.h>
33*4882a593Smuzhiyun #include <linux/mutex.h>
34*4882a593Smuzhiyun #include <linux/pci.h>
35*4882a593Smuzhiyun #include <linux/platform_device.h>
36*4882a593Smuzhiyun #include <linux/poll.h>
37*4882a593Smuzhiyun #include <linux/sched.h>
38*4882a593Smuzhiyun #include <linux/slab.h>
39*4882a593Smuzhiyun #include <linux/socket.h>
40*4882a593Smuzhiyun #include <linux/spi/spi.h>
41*4882a593Smuzhiyun #include <linux/swab.h>
42*4882a593Smuzhiyun #include <linux/timer.h>
43*4882a593Smuzhiyun #include <linux/types.h>
44*4882a593Smuzhiyun #include <linux/uaccess.h>
45*4882a593Smuzhiyun #include <linux/vmalloc.h>
46*4882a593Smuzhiyun #include <linux/workqueue.h>
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #include <asm/dma.h>
49*4882a593Smuzhiyun #include <asm/irq.h>
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #include <media/dmxdev.h>
52*4882a593Smuzhiyun #include <media/dvb_ca_en50221.h>
53*4882a593Smuzhiyun #include <media/dvb_demux.h>
54*4882a593Smuzhiyun #include <media/dvbdev.h>
55*4882a593Smuzhiyun #include <media/dvb_frontend.h>
56*4882a593Smuzhiyun #include <media/dvb_net.h>
57*4882a593Smuzhiyun #include <media/dvb_ringbuffer.h>
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun #define DDBRIDGE_VERSION "0.9.33-integrated"
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define DDB_MAX_I2C    32
62*4882a593Smuzhiyun #define DDB_MAX_PORT   32
63*4882a593Smuzhiyun #define DDB_MAX_INPUT  64
64*4882a593Smuzhiyun #define DDB_MAX_OUTPUT 32
65*4882a593Smuzhiyun #define DDB_MAX_LINK    4
66*4882a593Smuzhiyun #define DDB_LINK_SHIFT 28
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun #define DDB_LINK_TAG(_x) (_x << DDB_LINK_SHIFT)
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun struct ddb_regset {
71*4882a593Smuzhiyun 	u32 base;
72*4882a593Smuzhiyun 	u32 num;
73*4882a593Smuzhiyun 	u32 size;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun struct ddb_regmap {
77*4882a593Smuzhiyun 	u32 irq_base_i2c;
78*4882a593Smuzhiyun 	u32 irq_base_idma;
79*4882a593Smuzhiyun 	u32 irq_base_odma;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	const struct ddb_regset *i2c;
82*4882a593Smuzhiyun 	const struct ddb_regset *i2c_buf;
83*4882a593Smuzhiyun 	const struct ddb_regset *idma;
84*4882a593Smuzhiyun 	const struct ddb_regset *idma_buf;
85*4882a593Smuzhiyun 	const struct ddb_regset *odma;
86*4882a593Smuzhiyun 	const struct ddb_regset *odma_buf;
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	const struct ddb_regset *input;
89*4882a593Smuzhiyun 	const struct ddb_regset *output;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	const struct ddb_regset *channel;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun struct ddb_ids {
95*4882a593Smuzhiyun 	u16 vendor;
96*4882a593Smuzhiyun 	u16 device;
97*4882a593Smuzhiyun 	u16 subvendor;
98*4882a593Smuzhiyun 	u16 subdevice;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	u32 hwid;
101*4882a593Smuzhiyun 	u32 regmapid;
102*4882a593Smuzhiyun 	u32 devid;
103*4882a593Smuzhiyun 	u32 mac;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct ddb_info {
107*4882a593Smuzhiyun 	int   type;
108*4882a593Smuzhiyun #define DDB_NONE            0
109*4882a593Smuzhiyun #define DDB_OCTOPUS         1
110*4882a593Smuzhiyun #define DDB_OCTOPUS_CI      2
111*4882a593Smuzhiyun #define DDB_OCTOPUS_MAX     5
112*4882a593Smuzhiyun #define DDB_OCTOPUS_MAX_CT  6
113*4882a593Smuzhiyun #define DDB_OCTOPUS_MCI     9
114*4882a593Smuzhiyun 	char *name;
115*4882a593Smuzhiyun 	u32   i2c_mask;
116*4882a593Smuzhiyun 	u32   board_control;
117*4882a593Smuzhiyun 	u32   board_control_2;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	u8    port_num;
120*4882a593Smuzhiyun 	u8    led_num;
121*4882a593Smuzhiyun 	u8    fan_num;
122*4882a593Smuzhiyun 	u8    temp_num;
123*4882a593Smuzhiyun 	u8    temp_bus;
124*4882a593Smuzhiyun 	u8    con_clock; /* use a continuous clock */
125*4882a593Smuzhiyun 	u8    ts_quirks;
126*4882a593Smuzhiyun #define TS_QUIRK_SERIAL   1
127*4882a593Smuzhiyun #define TS_QUIRK_REVERSED 2
128*4882a593Smuzhiyun #define TS_QUIRK_ALT_OSC  8
129*4882a593Smuzhiyun 	u8    mci_ports;
130*4882a593Smuzhiyun 	u8    mci_type;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	u32   tempmon_irq;
133*4882a593Smuzhiyun 	const struct ddb_regmap *regmap;
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define DMA_MAX_BUFS 32      /* hardware table limit */
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun struct ddb;
139*4882a593Smuzhiyun struct ddb_port;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun struct ddb_dma {
142*4882a593Smuzhiyun 	void                  *io;
143*4882a593Smuzhiyun 	u32                    regs;
144*4882a593Smuzhiyun 	u32                    bufregs;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	dma_addr_t             pbuf[DMA_MAX_BUFS];
147*4882a593Smuzhiyun 	u8                    *vbuf[DMA_MAX_BUFS];
148*4882a593Smuzhiyun 	u32                    num;
149*4882a593Smuzhiyun 	u32                    size;
150*4882a593Smuzhiyun 	u32                    div;
151*4882a593Smuzhiyun 	u32                    bufval;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	struct work_struct     work;
154*4882a593Smuzhiyun 	spinlock_t             lock; /* DMA lock */
155*4882a593Smuzhiyun 	wait_queue_head_t      wq;
156*4882a593Smuzhiyun 	int                    running;
157*4882a593Smuzhiyun 	u32                    stat;
158*4882a593Smuzhiyun 	u32                    ctrl;
159*4882a593Smuzhiyun 	u32                    cbuf;
160*4882a593Smuzhiyun 	u32                    coff;
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun struct ddb_dvb {
164*4882a593Smuzhiyun 	struct dvb_adapter    *adap;
165*4882a593Smuzhiyun 	int                    adap_registered;
166*4882a593Smuzhiyun 	struct dvb_device     *dev;
167*4882a593Smuzhiyun 	struct i2c_client     *i2c_client[1];
168*4882a593Smuzhiyun 	struct dvb_frontend   *fe;
169*4882a593Smuzhiyun 	struct dvb_frontend   *fe2;
170*4882a593Smuzhiyun 	struct dmxdev          dmxdev;
171*4882a593Smuzhiyun 	struct dvb_demux       demux;
172*4882a593Smuzhiyun 	struct dvb_net         dvbnet;
173*4882a593Smuzhiyun 	struct dmx_frontend    hw_frontend;
174*4882a593Smuzhiyun 	struct dmx_frontend    mem_frontend;
175*4882a593Smuzhiyun 	int                    users;
176*4882a593Smuzhiyun 	u32                    attached;
177*4882a593Smuzhiyun 	u8                     input;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	enum fe_sec_tone_mode  tone;
180*4882a593Smuzhiyun 	enum fe_sec_voltage    voltage;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	int (*i2c_gate_ctrl)(struct dvb_frontend *, int);
183*4882a593Smuzhiyun 	int (*set_voltage)(struct dvb_frontend *fe,
184*4882a593Smuzhiyun 			   enum fe_sec_voltage voltage);
185*4882a593Smuzhiyun 	int (*set_input)(struct dvb_frontend *fe, int input);
186*4882a593Smuzhiyun 	int (*diseqc_send_master_cmd)(struct dvb_frontend *fe,
187*4882a593Smuzhiyun 				      struct dvb_diseqc_master_cmd *cmd);
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun struct ddb_ci {
191*4882a593Smuzhiyun 	struct dvb_ca_en50221  en;
192*4882a593Smuzhiyun 	struct ddb_port       *port;
193*4882a593Smuzhiyun 	u32                    nr;
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun struct ddb_io {
197*4882a593Smuzhiyun 	struct ddb_port       *port;
198*4882a593Smuzhiyun 	u32                    nr;
199*4882a593Smuzhiyun 	u32                    regs;
200*4882a593Smuzhiyun 	struct ddb_dma        *dma;
201*4882a593Smuzhiyun 	struct ddb_io         *redo;
202*4882a593Smuzhiyun 	struct ddb_io         *redi;
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun #define ddb_output ddb_io
206*4882a593Smuzhiyun #define ddb_input ddb_io
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun struct ddb_i2c {
209*4882a593Smuzhiyun 	struct ddb            *dev;
210*4882a593Smuzhiyun 	u32                    nr;
211*4882a593Smuzhiyun 	u32                    regs;
212*4882a593Smuzhiyun 	u32                    link;
213*4882a593Smuzhiyun 	struct i2c_adapter     adap;
214*4882a593Smuzhiyun 	u32                    rbuf;
215*4882a593Smuzhiyun 	u32                    wbuf;
216*4882a593Smuzhiyun 	u32                    bsize;
217*4882a593Smuzhiyun 	struct completion      completion;
218*4882a593Smuzhiyun };
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun struct ddb_port {
221*4882a593Smuzhiyun 	struct ddb            *dev;
222*4882a593Smuzhiyun 	u32                    nr;
223*4882a593Smuzhiyun 	u32                    pnr;
224*4882a593Smuzhiyun 	u32                    regs;
225*4882a593Smuzhiyun 	u32                    lnr;
226*4882a593Smuzhiyun 	struct ddb_i2c        *i2c;
227*4882a593Smuzhiyun 	struct mutex           i2c_gate_lock; /* I2C access lock */
228*4882a593Smuzhiyun 	u32                    class;
229*4882a593Smuzhiyun #define DDB_PORT_NONE           0
230*4882a593Smuzhiyun #define DDB_PORT_CI             1
231*4882a593Smuzhiyun #define DDB_PORT_TUNER          2
232*4882a593Smuzhiyun #define DDB_PORT_LOOP           3
233*4882a593Smuzhiyun 	char                   *name;
234*4882a593Smuzhiyun 	char                   *type_name;
235*4882a593Smuzhiyun 	u32                     type;
236*4882a593Smuzhiyun #define DDB_TUNER_DUMMY          0xffffffff
237*4882a593Smuzhiyun #define DDB_TUNER_NONE           0
238*4882a593Smuzhiyun #define DDB_TUNER_DVBS_ST        1
239*4882a593Smuzhiyun #define DDB_TUNER_DVBS_ST_AA     2
240*4882a593Smuzhiyun #define DDB_TUNER_DVBCT_TR       3
241*4882a593Smuzhiyun #define DDB_TUNER_DVBCT_ST       4
242*4882a593Smuzhiyun #define DDB_CI_INTERNAL          5
243*4882a593Smuzhiyun #define DDB_CI_EXTERNAL_SONY     6
244*4882a593Smuzhiyun #define DDB_TUNER_DVBCT2_SONY_P  7
245*4882a593Smuzhiyun #define DDB_TUNER_DVBC2T2_SONY_P 8
246*4882a593Smuzhiyun #define DDB_TUNER_ISDBT_SONY_P   9
247*4882a593Smuzhiyun #define DDB_TUNER_DVBS_STV0910_P 10
248*4882a593Smuzhiyun #define DDB_TUNER_MXL5XX         11
249*4882a593Smuzhiyun #define DDB_CI_EXTERNAL_XO2      12
250*4882a593Smuzhiyun #define DDB_CI_EXTERNAL_XO2_B    13
251*4882a593Smuzhiyun #define DDB_TUNER_DVBS_STV0910_PR 14
252*4882a593Smuzhiyun #define DDB_TUNER_DVBC2T2I_SONY_P 15
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun #define DDB_TUNER_XO2            32
255*4882a593Smuzhiyun #define DDB_TUNER_DVBS_STV0910   (DDB_TUNER_XO2 + 0)
256*4882a593Smuzhiyun #define DDB_TUNER_DVBCT2_SONY    (DDB_TUNER_XO2 + 1)
257*4882a593Smuzhiyun #define DDB_TUNER_ISDBT_SONY     (DDB_TUNER_XO2 + 2)
258*4882a593Smuzhiyun #define DDB_TUNER_DVBC2T2_SONY   (DDB_TUNER_XO2 + 3)
259*4882a593Smuzhiyun #define DDB_TUNER_ATSC_ST        (DDB_TUNER_XO2 + 4)
260*4882a593Smuzhiyun #define DDB_TUNER_DVBC2T2I_SONY  (DDB_TUNER_XO2 + 5)
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun #define DDB_TUNER_MCI            48
263*4882a593Smuzhiyun #define DDB_TUNER_MCI_SX8        (DDB_TUNER_MCI + 0)
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	struct ddb_input      *input[2];
266*4882a593Smuzhiyun 	struct ddb_output     *output;
267*4882a593Smuzhiyun 	struct dvb_ca_en50221 *en;
268*4882a593Smuzhiyun 	u8                     en_freedata;
269*4882a593Smuzhiyun 	struct ddb_dvb         dvb[2];
270*4882a593Smuzhiyun 	u32                    gap;
271*4882a593Smuzhiyun 	u32                    obr;
272*4882a593Smuzhiyun 	u8                     creg;
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun #define CM_STARTUP_DELAY 2
276*4882a593Smuzhiyun #define CM_AVERAGE  20
277*4882a593Smuzhiyun #define CM_GAIN     10
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun #define HW_LSB_SHIFT    12
280*4882a593Smuzhiyun #define HW_LSB_MASK     0x1000
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun #define CM_IDLE    0
283*4882a593Smuzhiyun #define CM_STARTUP 1
284*4882a593Smuzhiyun #define CM_ADJUST  2
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun #define TS_CAPTURE_LEN  (4096)
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun struct ddb_lnb {
289*4882a593Smuzhiyun 	struct mutex           lock; /* lock lnb access */
290*4882a593Smuzhiyun 	u32                    tone;
291*4882a593Smuzhiyun 	enum fe_sec_voltage    oldvoltage[4];
292*4882a593Smuzhiyun 	u32                    voltage[4];
293*4882a593Smuzhiyun 	u32                    voltages;
294*4882a593Smuzhiyun 	u32                    fmode;
295*4882a593Smuzhiyun };
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun struct ddb_irq {
298*4882a593Smuzhiyun 	void                   (*handler)(void *);
299*4882a593Smuzhiyun 	void                  *data;
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun struct ddb_link {
303*4882a593Smuzhiyun 	struct ddb            *dev;
304*4882a593Smuzhiyun 	const struct ddb_info *info;
305*4882a593Smuzhiyun 	u32                    nr;
306*4882a593Smuzhiyun 	u32                    regs;
307*4882a593Smuzhiyun 	spinlock_t             lock; /* lock link access */
308*4882a593Smuzhiyun 	struct mutex           flash_mutex; /* lock flash access */
309*4882a593Smuzhiyun 	struct ddb_lnb         lnb;
310*4882a593Smuzhiyun 	struct tasklet_struct  tasklet;
311*4882a593Smuzhiyun 	struct ddb_ids         ids;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	spinlock_t             temp_lock; /* lock temp chip access */
314*4882a593Smuzhiyun 	int                    overtemperature_error;
315*4882a593Smuzhiyun 	u8                     temp_tab[11];
316*4882a593Smuzhiyun 	struct ddb_irq         irq[256];
317*4882a593Smuzhiyun };
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun struct ddb {
320*4882a593Smuzhiyun 	struct pci_dev          *pdev;
321*4882a593Smuzhiyun 	struct platform_device  *pfdev;
322*4882a593Smuzhiyun 	struct device           *dev;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	int                      msi;
325*4882a593Smuzhiyun 	struct workqueue_struct *wq;
326*4882a593Smuzhiyun 	u32                      has_dma;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	struct ddb_link          link[DDB_MAX_LINK];
329*4882a593Smuzhiyun 	unsigned char __iomem   *regs;
330*4882a593Smuzhiyun 	u32                      regs_len;
331*4882a593Smuzhiyun 	u32                      port_num;
332*4882a593Smuzhiyun 	struct ddb_port          port[DDB_MAX_PORT];
333*4882a593Smuzhiyun 	u32                      i2c_num;
334*4882a593Smuzhiyun 	struct ddb_i2c           i2c[DDB_MAX_I2C];
335*4882a593Smuzhiyun 	struct ddb_input         input[DDB_MAX_INPUT];
336*4882a593Smuzhiyun 	struct ddb_output        output[DDB_MAX_OUTPUT];
337*4882a593Smuzhiyun 	struct dvb_adapter       adap[DDB_MAX_INPUT];
338*4882a593Smuzhiyun 	struct ddb_dma           idma[DDB_MAX_INPUT];
339*4882a593Smuzhiyun 	struct ddb_dma           odma[DDB_MAX_OUTPUT];
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	struct device           *ddb_dev;
342*4882a593Smuzhiyun 	u32                      ddb_dev_users;
343*4882a593Smuzhiyun 	u32                      nr;
344*4882a593Smuzhiyun 	u8                       iobuf[1028];
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	u8                       leds;
347*4882a593Smuzhiyun 	u32                      ts_irq;
348*4882a593Smuzhiyun 	u32                      i2c_irq;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	struct mutex             mutex; /* lock access to global ddb array */
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	u8                       tsbuf[TS_CAPTURE_LEN];
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun /****************************************************************************/
356*4882a593Smuzhiyun /****************************************************************************/
357*4882a593Smuzhiyun /****************************************************************************/
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun int ddbridge_flashread(struct ddb *dev, u32 link, u8 *buf, u32 addr, u32 len);
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun /****************************************************************************/
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun /* ddbridge-core.c */
364*4882a593Smuzhiyun struct ddb_irq *ddb_irq_set(struct ddb *dev, u32 link, u32 nr,
365*4882a593Smuzhiyun 			    void (*handler)(void *), void *data);
366*4882a593Smuzhiyun void ddb_ports_detach(struct ddb *dev);
367*4882a593Smuzhiyun void ddb_ports_release(struct ddb *dev);
368*4882a593Smuzhiyun void ddb_buffers_free(struct ddb *dev);
369*4882a593Smuzhiyun void ddb_device_destroy(struct ddb *dev);
370*4882a593Smuzhiyun irqreturn_t ddb_irq_handler0(int irq, void *dev_id);
371*4882a593Smuzhiyun irqreturn_t ddb_irq_handler1(int irq, void *dev_id);
372*4882a593Smuzhiyun irqreturn_t ddb_irq_handler(int irq, void *dev_id);
373*4882a593Smuzhiyun void ddb_ports_init(struct ddb *dev);
374*4882a593Smuzhiyun int ddb_buffers_alloc(struct ddb *dev);
375*4882a593Smuzhiyun int ddb_ports_attach(struct ddb *dev);
376*4882a593Smuzhiyun int ddb_device_create(struct ddb *dev);
377*4882a593Smuzhiyun int ddb_init(struct ddb *dev);
378*4882a593Smuzhiyun void ddb_unmap(struct ddb *dev);
379*4882a593Smuzhiyun int ddb_exit_ddbridge(int stage, int error);
380*4882a593Smuzhiyun int ddb_init_ddbridge(void);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun #endif /* DDBRIDGE_H */
383