1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ddbridge-regs.h: Digital Devices PCIe bridge driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010-2017 Digital Devices GmbH 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 8*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License 9*4882a593Smuzhiyun * version 2 only, as published by the Free Software Foundation. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 12*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*4882a593Smuzhiyun * GNU General Public License for more details. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef __DDBRIDGE_REGS_H__ 18*4882a593Smuzhiyun #define __DDBRIDGE_REGS_H__ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 21*4882a593Smuzhiyun /* SPI Controller */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SPI_CONTROL 0x10 24*4882a593Smuzhiyun #define SPI_DATA 0x14 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 27*4882a593Smuzhiyun /* GPIO */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define GPIO_OUTPUT 0x20 30*4882a593Smuzhiyun #define GPIO_INPUT 0x24 31*4882a593Smuzhiyun #define GPIO_DIRECTION 0x28 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define BOARD_CONTROL 0x30 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Interrupt controller 40*4882a593Smuzhiyun * How many MSI's are available depends on HW (Min 2 max 8) 41*4882a593Smuzhiyun * How many are usable also depends on Host platform 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define INTERRUPT_BASE (0x40) 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00) 47*4882a593Smuzhiyun #define MSI1_ENABLE (INTERRUPT_BASE + 0x04) 48*4882a593Smuzhiyun #define MSI2_ENABLE (INTERRUPT_BASE + 0x08) 49*4882a593Smuzhiyun #define MSI3_ENABLE (INTERRUPT_BASE + 0x0C) 50*4882a593Smuzhiyun #define MSI4_ENABLE (INTERRUPT_BASE + 0x10) 51*4882a593Smuzhiyun #define MSI5_ENABLE (INTERRUPT_BASE + 0x14) 52*4882a593Smuzhiyun #define MSI6_ENABLE (INTERRUPT_BASE + 0x18) 53*4882a593Smuzhiyun #define MSI7_ENABLE (INTERRUPT_BASE + 0x1C) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20) 56*4882a593Smuzhiyun #define INTERRUPT_ACK (INTERRUPT_BASE + 0x20) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */ 59*4882a593Smuzhiyun #define TEMPMON_BASE (0x1c0) 60*4882a593Smuzhiyun #define TEMPMON_CONTROL (TEMPMON_BASE + 0x00) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define TEMPMON_CONTROL_AUTOSCAN (0x00000002) 63*4882a593Smuzhiyun #define TEMPMON_CONTROL_INTENABLE (0x00000004) 64*4882a593Smuzhiyun #define TEMPMON_CONTROL_OVERTEMP (0x00008000) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* SHORT Temperature in Celsius x 256 */ 67*4882a593Smuzhiyun #define TEMPMON_SENSOR0 (TEMPMON_BASE + 0x04) 68*4882a593Smuzhiyun #define TEMPMON_SENSOR1 (TEMPMON_BASE + 0x08) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define TEMPMON_FANCONTROL (TEMPMON_BASE + 0x10) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 73*4882a593Smuzhiyun /* I2C Master Controller */ 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define I2C_COMMAND (0x00) 76*4882a593Smuzhiyun #define I2C_TIMING (0x04) 77*4882a593Smuzhiyun #define I2C_TASKLENGTH (0x08) /* High read, low write */ 78*4882a593Smuzhiyun #define I2C_TASKADDRESS (0x0C) /* High read, low write */ 79*4882a593Smuzhiyun #define I2C_MONITOR (0x1C) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define I2C_SPEED_400 (0x04030404) 82*4882a593Smuzhiyun #define I2C_SPEED_100 (0x13121313) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 85*4882a593Smuzhiyun /* DMA Controller */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define DMA_BASE_WRITE (0x100) 88*4882a593Smuzhiyun #define DMA_BASE_READ (0x140) 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define TS_CONTROL(_io) ((_io)->regs + 0x00) 91*4882a593Smuzhiyun #define TS_CONTROL2(_io) ((_io)->regs + 0x04) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 94*4882a593Smuzhiyun /* DMA Buffer */ 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define DMA_BUFFER_CONTROL(_dma) ((_dma)->regs + 0x00) 97*4882a593Smuzhiyun #define DMA_BUFFER_ACK(_dma) ((_dma)->regs + 0x04) 98*4882a593Smuzhiyun #define DMA_BUFFER_CURRENT(_dma) ((_dma)->regs + 0x08) 99*4882a593Smuzhiyun #define DMA_BUFFER_SIZE(_dma) ((_dma)->regs + 0x0c) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 102*4882a593Smuzhiyun /* CI Interface (only CI-Bridge) */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define CI_BASE (0x400) 105*4882a593Smuzhiyun #define CI_CONTROL(i) (CI_BASE + (i) * 32 + 0x00) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define CI_DO_ATTRIBUTE_RW(i) (CI_BASE + (i) * 32 + 0x04) 108*4882a593Smuzhiyun #define CI_DO_IO_RW(i) (CI_BASE + (i) * 32 + 0x08) 109*4882a593Smuzhiyun #define CI_READDATA(i) (CI_BASE + (i) * 32 + 0x0c) 110*4882a593Smuzhiyun #define CI_DO_READ_ATTRIBUTES(i) (CI_BASE + (i) * 32 + 0x10) 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define CI_RESET_CAM (0x00000001) 113*4882a593Smuzhiyun #define CI_POWER_ON (0x00000002) 114*4882a593Smuzhiyun #define CI_ENABLE (0x00000004) 115*4882a593Smuzhiyun #define CI_BYPASS_DISABLE (0x00000010) 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define CI_CAM_READY (0x00010000) 118*4882a593Smuzhiyun #define CI_CAM_DETECT (0x00020000) 119*4882a593Smuzhiyun #define CI_READY (0x80000000) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CI_READ_CMD (0x40000000) 122*4882a593Smuzhiyun #define CI_WRITE_CMD (0x80000000) 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define CI_BUFFER_BASE (0x3000) 125*4882a593Smuzhiyun #define CI_BUFFER_SIZE (0x0800) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define CI_BUFFER(i) (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 130*4882a593Smuzhiyun /* LNB commands (mxl5xx / Max S8) */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define LNB_BASE (0x400) 133*4882a593Smuzhiyun #define LNB_CONTROL(i) (LNB_BASE + (i) * 0x20 + 0x00) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define LNB_CMD (7ULL << 0) 136*4882a593Smuzhiyun #define LNB_CMD_NOP 0 137*4882a593Smuzhiyun #define LNB_CMD_INIT 1 138*4882a593Smuzhiyun #define LNB_CMD_LOW 3 139*4882a593Smuzhiyun #define LNB_CMD_HIGH 4 140*4882a593Smuzhiyun #define LNB_CMD_OFF 5 141*4882a593Smuzhiyun #define LNB_CMD_DISEQC 6 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define LNB_BUSY BIT_ULL(4) 144*4882a593Smuzhiyun #define LNB_TONE BIT_ULL(15) 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define LNB_BUF_LEVEL(i) (LNB_BASE + (i) * 0x20 + 0x10) 147*4882a593Smuzhiyun #define LNB_BUF_WRITE(i) (LNB_BASE + (i) * 0x20 + 0x14) 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #endif /* __DDBRIDGE_REGS_H__ */ 150