xref: /OK3568_Linux_fs/kernel/drivers/media/pci/ddbridge/ddbridge-mci.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * ddbridge-mci.c: Digital Devices microcode interface
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017-2018 Digital Devices GmbH
6*4882a593Smuzhiyun  *                         Ralph Metzler <rjkm@metzlerbros.de>
7*4882a593Smuzhiyun  *                         Marcus Metzler <mocm@metzlerbros.de>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
10*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License
11*4882a593Smuzhiyun  * version 2 only, as published by the Free Software Foundation.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful,
14*4882a593Smuzhiyun  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16*4882a593Smuzhiyun  * GNU General Public License for more details.
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "ddbridge.h"
20*4882a593Smuzhiyun #include "ddbridge-io.h"
21*4882a593Smuzhiyun #include "ddbridge-mci.h"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun static LIST_HEAD(mci_list);
24*4882a593Smuzhiyun 
mci_reset(struct mci * state)25*4882a593Smuzhiyun static int mci_reset(struct mci *state)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun 	struct ddb_link *link = state->base->link;
28*4882a593Smuzhiyun 	u32 status = 0;
29*4882a593Smuzhiyun 	u32 timeout = 40;
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	ddblwritel(link, MCI_CONTROL_RESET, MCI_CONTROL);
32*4882a593Smuzhiyun 	ddblwritel(link, 0, MCI_CONTROL + 4); /* 1= no internal init */
33*4882a593Smuzhiyun 	msleep(300);
34*4882a593Smuzhiyun 	ddblwritel(link, 0, MCI_CONTROL);
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	while (1) {
37*4882a593Smuzhiyun 		status = ddblreadl(link, MCI_CONTROL);
38*4882a593Smuzhiyun 		if ((status & MCI_CONTROL_READY) == MCI_CONTROL_READY)
39*4882a593Smuzhiyun 			break;
40*4882a593Smuzhiyun 		if (--timeout == 0)
41*4882a593Smuzhiyun 			break;
42*4882a593Smuzhiyun 		msleep(50);
43*4882a593Smuzhiyun 	}
44*4882a593Smuzhiyun 	if ((status & MCI_CONTROL_READY) == 0)
45*4882a593Smuzhiyun 		return -1;
46*4882a593Smuzhiyun 	if (link->ids.device == 0x0009)
47*4882a593Smuzhiyun 		ddblwritel(link, SX8_TSCONFIG_MODE_NORMAL, SX8_TSCONFIG);
48*4882a593Smuzhiyun 	return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
ddb_mci_config(struct mci * state,u32 config)51*4882a593Smuzhiyun int ddb_mci_config(struct mci *state, u32 config)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	struct ddb_link *link = state->base->link;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	if (link->ids.device != 0x0009)
56*4882a593Smuzhiyun 		return -EINVAL;
57*4882a593Smuzhiyun 	ddblwritel(link, config, SX8_TSCONFIG);
58*4882a593Smuzhiyun 	return 0;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun 
_mci_cmd_unlocked(struct mci * state,u32 * cmd,u32 cmd_len,u32 * res,u32 res_len)61*4882a593Smuzhiyun static int _mci_cmd_unlocked(struct mci *state,
62*4882a593Smuzhiyun 			     u32 *cmd, u32 cmd_len,
63*4882a593Smuzhiyun 			     u32 *res, u32 res_len)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	struct ddb_link *link = state->base->link;
66*4882a593Smuzhiyun 	u32 i, val;
67*4882a593Smuzhiyun 	unsigned long stat;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	val = ddblreadl(link, MCI_CONTROL);
70*4882a593Smuzhiyun 	if (val & (MCI_CONTROL_RESET | MCI_CONTROL_START_COMMAND))
71*4882a593Smuzhiyun 		return -EIO;
72*4882a593Smuzhiyun 	if (cmd && cmd_len)
73*4882a593Smuzhiyun 		for (i = 0; i < cmd_len; i++)
74*4882a593Smuzhiyun 			ddblwritel(link, cmd[i], MCI_COMMAND + i * 4);
75*4882a593Smuzhiyun 	val |= (MCI_CONTROL_START_COMMAND | MCI_CONTROL_ENABLE_DONE_INTERRUPT);
76*4882a593Smuzhiyun 	ddblwritel(link, val, MCI_CONTROL);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	stat = wait_for_completion_timeout(&state->base->completion, HZ);
79*4882a593Smuzhiyun 	if (stat == 0) {
80*4882a593Smuzhiyun 		dev_warn(state->base->dev, "MCI-%d: MCI timeout\n", state->nr);
81*4882a593Smuzhiyun 		return -EIO;
82*4882a593Smuzhiyun 	}
83*4882a593Smuzhiyun 	if (res && res_len)
84*4882a593Smuzhiyun 		for (i = 0; i < res_len; i++)
85*4882a593Smuzhiyun 			res[i] = ddblreadl(link, MCI_RESULT + i * 4);
86*4882a593Smuzhiyun 	return 0;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
ddb_mci_cmd(struct mci * state,struct mci_command * command,struct mci_result * result)89*4882a593Smuzhiyun int ddb_mci_cmd(struct mci *state,
90*4882a593Smuzhiyun 		struct mci_command *command,
91*4882a593Smuzhiyun 		struct mci_result *result)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	int stat;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	mutex_lock(&state->base->mci_lock);
96*4882a593Smuzhiyun 	stat = _mci_cmd_unlocked(state,
97*4882a593Smuzhiyun 				 (u32 *)command, sizeof(*command) / sizeof(u32),
98*4882a593Smuzhiyun 				 (u32 *)result,	sizeof(*result) / sizeof(u32));
99*4882a593Smuzhiyun 	mutex_unlock(&state->base->mci_lock);
100*4882a593Smuzhiyun 	return stat;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
mci_handler(void * priv)103*4882a593Smuzhiyun static void mci_handler(void *priv)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	struct mci_base *base = (struct mci_base *)priv;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	complete(&base->completion);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
match_base(void * key)110*4882a593Smuzhiyun static struct mci_base *match_base(void *key)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	struct mci_base *p;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	list_for_each_entry(p, &mci_list, mci_list)
115*4882a593Smuzhiyun 		if (p->key == key)
116*4882a593Smuzhiyun 			return p;
117*4882a593Smuzhiyun 	return NULL;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
probe(struct mci * state)120*4882a593Smuzhiyun static int probe(struct mci *state)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	mci_reset(state);
123*4882a593Smuzhiyun 	return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun struct dvb_frontend
ddb_mci_attach(struct ddb_input * input,struct mci_cfg * cfg,int nr,int (** fn_set_input)(struct dvb_frontend * fe,int input))127*4882a593Smuzhiyun *ddb_mci_attach(struct ddb_input *input, struct mci_cfg *cfg, int nr,
128*4882a593Smuzhiyun 		int (**fn_set_input)(struct dvb_frontend *fe, int input))
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun 	struct ddb_port *port = input->port;
131*4882a593Smuzhiyun 	struct ddb *dev = port->dev;
132*4882a593Smuzhiyun 	struct ddb_link *link = &dev->link[port->lnr];
133*4882a593Smuzhiyun 	struct mci_base *base;
134*4882a593Smuzhiyun 	struct mci *state;
135*4882a593Smuzhiyun 	void *key = cfg->type ? (void *)port : (void *)link;
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun 	state = kzalloc(cfg->state_size, GFP_KERNEL);
138*4882a593Smuzhiyun 	if (!state)
139*4882a593Smuzhiyun 		return NULL;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	base = match_base(key);
142*4882a593Smuzhiyun 	if (base) {
143*4882a593Smuzhiyun 		base->count++;
144*4882a593Smuzhiyun 		state->base = base;
145*4882a593Smuzhiyun 	} else {
146*4882a593Smuzhiyun 		base = kzalloc(cfg->base_size, GFP_KERNEL);
147*4882a593Smuzhiyun 		if (!base)
148*4882a593Smuzhiyun 			goto fail;
149*4882a593Smuzhiyun 		base->key = key;
150*4882a593Smuzhiyun 		base->count = 1;
151*4882a593Smuzhiyun 		base->link = link;
152*4882a593Smuzhiyun 		base->dev = dev->dev;
153*4882a593Smuzhiyun 		mutex_init(&base->mci_lock);
154*4882a593Smuzhiyun 		mutex_init(&base->tuner_lock);
155*4882a593Smuzhiyun 		ddb_irq_set(dev, link->nr, 0, mci_handler, base);
156*4882a593Smuzhiyun 		init_completion(&base->completion);
157*4882a593Smuzhiyun 		state->base = base;
158*4882a593Smuzhiyun 		if (probe(state) < 0) {
159*4882a593Smuzhiyun 			kfree(base);
160*4882a593Smuzhiyun 			goto fail;
161*4882a593Smuzhiyun 		}
162*4882a593Smuzhiyun 		list_add(&base->mci_list, &mci_list);
163*4882a593Smuzhiyun 		if (cfg->base_init)
164*4882a593Smuzhiyun 			cfg->base_init(base);
165*4882a593Smuzhiyun 	}
166*4882a593Smuzhiyun 	memcpy(&state->fe.ops, cfg->fe_ops, sizeof(struct dvb_frontend_ops));
167*4882a593Smuzhiyun 	state->fe.demodulator_priv = state;
168*4882a593Smuzhiyun 	state->nr = nr;
169*4882a593Smuzhiyun 	*fn_set_input = cfg->set_input;
170*4882a593Smuzhiyun 	state->tuner = nr;
171*4882a593Smuzhiyun 	state->demod = nr;
172*4882a593Smuzhiyun 	if (cfg->init)
173*4882a593Smuzhiyun 		cfg->init(state);
174*4882a593Smuzhiyun 	return &state->fe;
175*4882a593Smuzhiyun fail:
176*4882a593Smuzhiyun 	kfree(state);
177*4882a593Smuzhiyun 	return NULL;
178*4882a593Smuzhiyun }
179