xref: /OK3568_Linux_fs/kernel/drivers/media/pci/cx88/cx88-vbi.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  */
4*4882a593Smuzhiyun 
5*4882a593Smuzhiyun #include "cx88.h"
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/kernel.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun static unsigned int vbi_debug;
12*4882a593Smuzhiyun module_param(vbi_debug, int, 0644);
13*4882a593Smuzhiyun MODULE_PARM_DESC(vbi_debug, "enable debug messages [vbi]");
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define dprintk(level, fmt, arg...) do {			\
16*4882a593Smuzhiyun 	if (vbi_debug >= level)					\
17*4882a593Smuzhiyun 		printk(KERN_DEBUG pr_fmt("%s: vbi:" fmt),	\
18*4882a593Smuzhiyun 			__func__, ##arg);			\
19*4882a593Smuzhiyun } while (0)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* ------------------------------------------------------------------ */
22*4882a593Smuzhiyun 
cx8800_vbi_fmt(struct file * file,void * priv,struct v4l2_format * f)23*4882a593Smuzhiyun int cx8800_vbi_fmt(struct file *file, void *priv,
24*4882a593Smuzhiyun 		   struct v4l2_format *f)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun 	struct cx8800_dev *dev = video_drvdata(file);
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	f->fmt.vbi.samples_per_line = VBI_LINE_LENGTH;
29*4882a593Smuzhiyun 	f->fmt.vbi.sample_format = V4L2_PIX_FMT_GREY;
30*4882a593Smuzhiyun 	f->fmt.vbi.offset = 244;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun 	if (dev->core->tvnorm & V4L2_STD_525_60) {
33*4882a593Smuzhiyun 		/* ntsc */
34*4882a593Smuzhiyun 		f->fmt.vbi.sampling_rate = 28636363;
35*4882a593Smuzhiyun 		f->fmt.vbi.start[0] = 10;
36*4882a593Smuzhiyun 		f->fmt.vbi.start[1] = 273;
37*4882a593Smuzhiyun 		f->fmt.vbi.count[0] = VBI_LINE_NTSC_COUNT;
38*4882a593Smuzhiyun 		f->fmt.vbi.count[1] = VBI_LINE_NTSC_COUNT;
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 	} else if (dev->core->tvnorm & V4L2_STD_625_50) {
41*4882a593Smuzhiyun 		/* pal */
42*4882a593Smuzhiyun 		f->fmt.vbi.sampling_rate = 35468950;
43*4882a593Smuzhiyun 		f->fmt.vbi.start[0] = V4L2_VBI_ITU_625_F1_START + 5;
44*4882a593Smuzhiyun 		f->fmt.vbi.start[1] = V4L2_VBI_ITU_625_F2_START + 5;
45*4882a593Smuzhiyun 		f->fmt.vbi.count[0] = VBI_LINE_PAL_COUNT;
46*4882a593Smuzhiyun 		f->fmt.vbi.count[1] = VBI_LINE_PAL_COUNT;
47*4882a593Smuzhiyun 	}
48*4882a593Smuzhiyun 	return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun 
cx8800_start_vbi_dma(struct cx8800_dev * dev,struct cx88_dmaqueue * q,struct cx88_buffer * buf)51*4882a593Smuzhiyun static int cx8800_start_vbi_dma(struct cx8800_dev    *dev,
52*4882a593Smuzhiyun 				struct cx88_dmaqueue *q,
53*4882a593Smuzhiyun 				struct cx88_buffer   *buf)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	struct cx88_core *core = dev->core;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/* setup fifo + format */
58*4882a593Smuzhiyun 	cx88_sram_channel_setup(dev->core, &cx88_sram_channels[SRAM_CH24],
59*4882a593Smuzhiyun 				VBI_LINE_LENGTH, buf->risc.dma);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	cx_write(MO_VBOS_CONTROL, (1 << 18) |  /* comb filter delay fixup */
62*4882a593Smuzhiyun 				  (1 << 15) |  /* enable vbi capture */
63*4882a593Smuzhiyun 				  (1 << 11));
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	/* reset counter */
66*4882a593Smuzhiyun 	cx_write(MO_VBI_GPCNTRL, GP_COUNT_CONTROL_RESET);
67*4882a593Smuzhiyun 	q->count = 0;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	/* enable irqs */
70*4882a593Smuzhiyun 	cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT);
71*4882a593Smuzhiyun 	cx_set(MO_VID_INTMSK, 0x0f0088);
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* enable capture */
74*4882a593Smuzhiyun 	cx_set(VID_CAPTURE_CONTROL, 0x18);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	/* start dma */
77*4882a593Smuzhiyun 	cx_set(MO_DEV_CNTRL2, (1 << 5));
78*4882a593Smuzhiyun 	cx_set(MO_VID_DMACNTRL, 0x88);
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	return 0;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
cx8800_stop_vbi_dma(struct cx8800_dev * dev)83*4882a593Smuzhiyun void cx8800_stop_vbi_dma(struct cx8800_dev *dev)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	struct cx88_core *core = dev->core;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	/* stop dma */
88*4882a593Smuzhiyun 	cx_clear(MO_VID_DMACNTRL, 0x88);
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	/* disable capture */
91*4882a593Smuzhiyun 	cx_clear(VID_CAPTURE_CONTROL, 0x18);
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	/* disable irqs */
94*4882a593Smuzhiyun 	cx_clear(MO_PCI_INTMSK, PCI_INT_VIDINT);
95*4882a593Smuzhiyun 	cx_clear(MO_VID_INTMSK, 0x0f0088);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun 
cx8800_restart_vbi_queue(struct cx8800_dev * dev,struct cx88_dmaqueue * q)98*4882a593Smuzhiyun int cx8800_restart_vbi_queue(struct cx8800_dev    *dev,
99*4882a593Smuzhiyun 			     struct cx88_dmaqueue *q)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	struct cx88_buffer *buf;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	if (list_empty(&q->active))
104*4882a593Smuzhiyun 		return 0;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	buf = list_entry(q->active.next, struct cx88_buffer, list);
107*4882a593Smuzhiyun 	dprintk(2, "restart_queue [%p/%d]: restart dma\n",
108*4882a593Smuzhiyun 		buf, buf->vb.vb2_buf.index);
109*4882a593Smuzhiyun 	cx8800_start_vbi_dma(dev, q, buf);
110*4882a593Smuzhiyun 	return 0;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun /* ------------------------------------------------------------------ */
114*4882a593Smuzhiyun 
queue_setup(struct vb2_queue * q,unsigned int * num_buffers,unsigned int * num_planes,unsigned int sizes[],struct device * alloc_devs[])115*4882a593Smuzhiyun static int queue_setup(struct vb2_queue *q,
116*4882a593Smuzhiyun 		       unsigned int *num_buffers, unsigned int *num_planes,
117*4882a593Smuzhiyun 		       unsigned int sizes[], struct device *alloc_devs[])
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	struct cx8800_dev *dev = q->drv_priv;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	*num_planes = 1;
122*4882a593Smuzhiyun 	if (dev->core->tvnorm & V4L2_STD_525_60)
123*4882a593Smuzhiyun 		sizes[0] = VBI_LINE_NTSC_COUNT * VBI_LINE_LENGTH * 2;
124*4882a593Smuzhiyun 	else
125*4882a593Smuzhiyun 		sizes[0] = VBI_LINE_PAL_COUNT * VBI_LINE_LENGTH * 2;
126*4882a593Smuzhiyun 	return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
buffer_prepare(struct vb2_buffer * vb)129*4882a593Smuzhiyun static int buffer_prepare(struct vb2_buffer *vb)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
132*4882a593Smuzhiyun 	struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
133*4882a593Smuzhiyun 	struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
134*4882a593Smuzhiyun 	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
135*4882a593Smuzhiyun 	unsigned int lines;
136*4882a593Smuzhiyun 	unsigned int size;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	if (dev->core->tvnorm & V4L2_STD_525_60)
139*4882a593Smuzhiyun 		lines = VBI_LINE_NTSC_COUNT;
140*4882a593Smuzhiyun 	else
141*4882a593Smuzhiyun 		lines = VBI_LINE_PAL_COUNT;
142*4882a593Smuzhiyun 	size = lines * VBI_LINE_LENGTH * 2;
143*4882a593Smuzhiyun 	if (vb2_plane_size(vb, 0) < size)
144*4882a593Smuzhiyun 		return -EINVAL;
145*4882a593Smuzhiyun 	vb2_set_plane_payload(vb, 0, size);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	return cx88_risc_buffer(dev->pci, &buf->risc, sgt->sgl,
148*4882a593Smuzhiyun 				0, VBI_LINE_LENGTH * lines,
149*4882a593Smuzhiyun 				VBI_LINE_LENGTH, 0,
150*4882a593Smuzhiyun 				lines);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
buffer_finish(struct vb2_buffer * vb)153*4882a593Smuzhiyun static void buffer_finish(struct vb2_buffer *vb)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
156*4882a593Smuzhiyun 	struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
157*4882a593Smuzhiyun 	struct cx88_buffer *buf = container_of(vbuf, struct cx88_buffer, vb);
158*4882a593Smuzhiyun 	struct cx88_riscmem *risc = &buf->risc;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	if (risc->cpu)
161*4882a593Smuzhiyun 		pci_free_consistent(dev->pci, risc->size, risc->cpu, risc->dma);
162*4882a593Smuzhiyun 	memset(risc, 0, sizeof(*risc));
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
buffer_queue(struct vb2_buffer * vb)165*4882a593Smuzhiyun static void buffer_queue(struct vb2_buffer *vb)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
168*4882a593Smuzhiyun 	struct cx8800_dev *dev = vb->vb2_queue->drv_priv;
169*4882a593Smuzhiyun 	struct cx88_buffer    *buf = container_of(vbuf, struct cx88_buffer, vb);
170*4882a593Smuzhiyun 	struct cx88_buffer    *prev;
171*4882a593Smuzhiyun 	struct cx88_dmaqueue  *q    = &dev->vbiq;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	/* add jump to start */
174*4882a593Smuzhiyun 	buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 8);
175*4882a593Smuzhiyun 	buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC);
176*4882a593Smuzhiyun 	buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 8);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	if (list_empty(&q->active)) {
179*4882a593Smuzhiyun 		list_add_tail(&buf->list, &q->active);
180*4882a593Smuzhiyun 		dprintk(2, "[%p/%d] vbi_queue - first active\n",
181*4882a593Smuzhiyun 			buf, buf->vb.vb2_buf.index);
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	} else {
184*4882a593Smuzhiyun 		buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1);
185*4882a593Smuzhiyun 		prev = list_entry(q->active.prev, struct cx88_buffer, list);
186*4882a593Smuzhiyun 		list_add_tail(&buf->list, &q->active);
187*4882a593Smuzhiyun 		prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
188*4882a593Smuzhiyun 		dprintk(2, "[%p/%d] buffer_queue - append to active\n",
189*4882a593Smuzhiyun 			buf, buf->vb.vb2_buf.index);
190*4882a593Smuzhiyun 	}
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
start_streaming(struct vb2_queue * q,unsigned int count)193*4882a593Smuzhiyun static int start_streaming(struct vb2_queue *q, unsigned int count)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct cx8800_dev *dev = q->drv_priv;
196*4882a593Smuzhiyun 	struct cx88_dmaqueue *dmaq = &dev->vbiq;
197*4882a593Smuzhiyun 	struct cx88_buffer *buf = list_entry(dmaq->active.next,
198*4882a593Smuzhiyun 			struct cx88_buffer, list);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	cx8800_start_vbi_dma(dev, dmaq, buf);
201*4882a593Smuzhiyun 	return 0;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
stop_streaming(struct vb2_queue * q)204*4882a593Smuzhiyun static void stop_streaming(struct vb2_queue *q)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	struct cx8800_dev *dev = q->drv_priv;
207*4882a593Smuzhiyun 	struct cx88_core *core = dev->core;
208*4882a593Smuzhiyun 	struct cx88_dmaqueue *dmaq = &dev->vbiq;
209*4882a593Smuzhiyun 	unsigned long flags;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	cx_clear(MO_VID_DMACNTRL, 0x11);
212*4882a593Smuzhiyun 	cx_clear(VID_CAPTURE_CONTROL, 0x06);
213*4882a593Smuzhiyun 	cx8800_stop_vbi_dma(dev);
214*4882a593Smuzhiyun 	spin_lock_irqsave(&dev->slock, flags);
215*4882a593Smuzhiyun 	while (!list_empty(&dmaq->active)) {
216*4882a593Smuzhiyun 		struct cx88_buffer *buf = list_entry(dmaq->active.next,
217*4882a593Smuzhiyun 			struct cx88_buffer, list);
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 		list_del(&buf->list);
220*4882a593Smuzhiyun 		vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 	spin_unlock_irqrestore(&dev->slock, flags);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun const struct vb2_ops cx8800_vbi_qops = {
226*4882a593Smuzhiyun 	.queue_setup    = queue_setup,
227*4882a593Smuzhiyun 	.buf_prepare  = buffer_prepare,
228*4882a593Smuzhiyun 	.buf_finish = buffer_finish,
229*4882a593Smuzhiyun 	.buf_queue    = buffer_queue,
230*4882a593Smuzhiyun 	.wait_prepare = vb2_ops_wait_prepare,
231*4882a593Smuzhiyun 	.wait_finish = vb2_ops_wait_finish,
232*4882a593Smuzhiyun 	.start_streaming = start_streaming,
233*4882a593Smuzhiyun 	.stop_streaming = stop_streaming,
234*4882a593Smuzhiyun };
235