1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Conexant CX25821 PCIe bridge
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 Conexant Systems Inc.
6*4882a593Smuzhiyun * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7*4882a593Smuzhiyun * Based on Steven Toth <stoth@linuxtv.org> cx23885 driver
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef CX25821_H_
11*4882a593Smuzhiyun #define CX25821_H_
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/pci.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/sched.h>
18*4882a593Smuzhiyun #include <linux/kdev_t.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <media/v4l2-common.h>
21*4882a593Smuzhiyun #include <media/v4l2-device.h>
22*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
23*4882a593Smuzhiyun #include <media/videobuf2-v4l2.h>
24*4882a593Smuzhiyun #include <media/videobuf2-dma-sg.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "cx25821-reg.h"
27*4882a593Smuzhiyun #include "cx25821-medusa-reg.h"
28*4882a593Smuzhiyun #include "cx25821-sram.h"
29*4882a593Smuzhiyun #include "cx25821-audio.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #include <linux/version.h>
32*4882a593Smuzhiyun #include <linux/mutex.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define UNSET (-1U)
35*4882a593Smuzhiyun #define NO_SYNC_LINE (-1U)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define CX25821_MAXBOARDS 2
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define LINE_SIZE_D1 1440
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Number of decoders and encoders */
42*4882a593Smuzhiyun #define MAX_DECODERS 8
43*4882a593Smuzhiyun #define MAX_ENCODERS 2
44*4882a593Smuzhiyun #define QUAD_DECODERS 4
45*4882a593Smuzhiyun #define MAX_CAMERAS 16
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* Max number of inputs by card */
48*4882a593Smuzhiyun #define MAX_CX25821_INPUT 8
49*4882a593Smuzhiyun #define RESOURCE_VIDEO0 1
50*4882a593Smuzhiyun #define RESOURCE_VIDEO1 2
51*4882a593Smuzhiyun #define RESOURCE_VIDEO2 4
52*4882a593Smuzhiyun #define RESOURCE_VIDEO3 8
53*4882a593Smuzhiyun #define RESOURCE_VIDEO4 16
54*4882a593Smuzhiyun #define RESOURCE_VIDEO5 32
55*4882a593Smuzhiyun #define RESOURCE_VIDEO6 64
56*4882a593Smuzhiyun #define RESOURCE_VIDEO7 128
57*4882a593Smuzhiyun #define RESOURCE_VIDEO8 256
58*4882a593Smuzhiyun #define RESOURCE_VIDEO9 512
59*4882a593Smuzhiyun #define RESOURCE_VIDEO10 1024
60*4882a593Smuzhiyun #define RESOURCE_VIDEO11 2048
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define UNKNOWN_BOARD 0
65*4882a593Smuzhiyun #define CX25821_BOARD 1
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Currently supported by the driver */
68*4882a593Smuzhiyun #define CX25821_NORMS (\
69*4882a593Smuzhiyun V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_M_KR | \
70*4882a593Smuzhiyun V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
71*4882a593Smuzhiyun V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_H | \
72*4882a593Smuzhiyun V4L2_STD_PAL_Nc)
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define CX25821_BOARD_CONEXANT_ATHENA10 1
75*4882a593Smuzhiyun #define MAX_VID_CHANNEL_NUM 12
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * Maximum capture-only channels. This can go away once video/audio output
79*4882a593Smuzhiyun * is fully supported in this driver.
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun #define MAX_VID_CAP_CHANNEL_NUM 10
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define VID_CHANNEL_NUM 8
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun struct cx25821_fmt {
86*4882a593Smuzhiyun u32 fourcc; /* v4l2 format id */
87*4882a593Smuzhiyun int depth;
88*4882a593Smuzhiyun int flags;
89*4882a593Smuzhiyun u32 cxformat;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct cx25821_tvnorm {
93*4882a593Smuzhiyun char *name;
94*4882a593Smuzhiyun v4l2_std_id id;
95*4882a593Smuzhiyun u32 cxiformat;
96*4882a593Smuzhiyun u32 cxoformat;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun enum cx25821_src_sel_type {
100*4882a593Smuzhiyun CX25821_SRC_SEL_EXT_656_VIDEO = 0,
101*4882a593Smuzhiyun CX25821_SRC_SEL_PARALLEL_MPEG_VIDEO
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun struct cx25821_riscmem {
105*4882a593Smuzhiyun unsigned int size;
106*4882a593Smuzhiyun __le32 *cpu;
107*4882a593Smuzhiyun __le32 *jmp;
108*4882a593Smuzhiyun dma_addr_t dma;
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* buffer for one video frame */
112*4882a593Smuzhiyun struct cx25821_buffer {
113*4882a593Smuzhiyun /* common v4l buffer stuff -- must be first */
114*4882a593Smuzhiyun struct vb2_v4l2_buffer vb;
115*4882a593Smuzhiyun struct list_head queue;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* cx25821 specific */
118*4882a593Smuzhiyun unsigned int bpl;
119*4882a593Smuzhiyun struct cx25821_riscmem risc;
120*4882a593Smuzhiyun const struct cx25821_fmt *fmt;
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun enum port {
124*4882a593Smuzhiyun CX25821_UNDEFINED = 0,
125*4882a593Smuzhiyun CX25821_RAW,
126*4882a593Smuzhiyun CX25821_264
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun struct cx25821_board {
130*4882a593Smuzhiyun const char *name;
131*4882a593Smuzhiyun enum port porta;
132*4882a593Smuzhiyun enum port portb;
133*4882a593Smuzhiyun enum port portc;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun u32 clk_freq;
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun struct cx25821_i2c {
139*4882a593Smuzhiyun struct cx25821_dev *dev;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun int nr;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* i2c i/o */
144*4882a593Smuzhiyun struct i2c_adapter i2c_adap;
145*4882a593Smuzhiyun struct i2c_client i2c_client;
146*4882a593Smuzhiyun u32 i2c_rc;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun /* cx25821 registers used for raw address */
149*4882a593Smuzhiyun u32 i2c_period;
150*4882a593Smuzhiyun u32 reg_ctrl;
151*4882a593Smuzhiyun u32 reg_stat;
152*4882a593Smuzhiyun u32 reg_addr;
153*4882a593Smuzhiyun u32 reg_rdata;
154*4882a593Smuzhiyun u32 reg_wdata;
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun struct cx25821_dmaqueue {
158*4882a593Smuzhiyun struct list_head active;
159*4882a593Smuzhiyun u32 count;
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun struct cx25821_dev;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun struct cx25821_channel;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun struct cx25821_video_out_data {
167*4882a593Smuzhiyun struct cx25821_channel *chan;
168*4882a593Smuzhiyun int _line_size;
169*4882a593Smuzhiyun int _prog_cnt;
170*4882a593Smuzhiyun int _pixel_format;
171*4882a593Smuzhiyun int _is_first_frame;
172*4882a593Smuzhiyun int _is_running;
173*4882a593Smuzhiyun int _file_status;
174*4882a593Smuzhiyun int _lines_count;
175*4882a593Smuzhiyun int _frame_count;
176*4882a593Smuzhiyun unsigned int _risc_size;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun __le32 *_dma_virt_start_addr;
179*4882a593Smuzhiyun __le32 *_dma_virt_addr;
180*4882a593Smuzhiyun dma_addr_t _dma_phys_addr;
181*4882a593Smuzhiyun dma_addr_t _dma_phys_start_addr;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun unsigned int _data_buf_size;
184*4882a593Smuzhiyun __le32 *_data_buf_virt_addr;
185*4882a593Smuzhiyun dma_addr_t _data_buf_phys_addr;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun u32 upstream_riscbuf_size;
188*4882a593Smuzhiyun u32 upstream_databuf_size;
189*4882a593Smuzhiyun int is_60hz;
190*4882a593Smuzhiyun int _frame_index;
191*4882a593Smuzhiyun int cur_frame_index;
192*4882a593Smuzhiyun int curpos;
193*4882a593Smuzhiyun wait_queue_head_t waitq;
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun struct cx25821_channel {
197*4882a593Smuzhiyun unsigned id;
198*4882a593Smuzhiyun struct cx25821_dev *dev;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun struct v4l2_ctrl_handler hdl;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun struct video_device vdev;
203*4882a593Smuzhiyun struct cx25821_dmaqueue dma_vidq;
204*4882a593Smuzhiyun struct vb2_queue vidq;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun const struct sram_channel *sram_channels;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun const struct cx25821_fmt *fmt;
209*4882a593Smuzhiyun unsigned field;
210*4882a593Smuzhiyun unsigned int width, height;
211*4882a593Smuzhiyun int pixel_formats;
212*4882a593Smuzhiyun int use_cif_resolution;
213*4882a593Smuzhiyun int cif_width;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /* video output data for the video output channel */
216*4882a593Smuzhiyun struct cx25821_video_out_data *out;
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun struct snd_card;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun struct cx25821_dev {
222*4882a593Smuzhiyun struct v4l2_device v4l2_dev;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* pci stuff */
225*4882a593Smuzhiyun struct pci_dev *pci;
226*4882a593Smuzhiyun unsigned char pci_rev, pci_lat;
227*4882a593Smuzhiyun int pci_bus, pci_slot;
228*4882a593Smuzhiyun u32 base_io_addr;
229*4882a593Smuzhiyun u32 __iomem *lmmio;
230*4882a593Smuzhiyun u8 __iomem *bmmio;
231*4882a593Smuzhiyun int pci_irqmask;
232*4882a593Smuzhiyun int hwrevision;
233*4882a593Smuzhiyun /* used by cx25821-alsa */
234*4882a593Smuzhiyun struct snd_card *card;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun u32 clk_freq;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
239*4882a593Smuzhiyun struct cx25821_i2c i2c_bus[3];
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun int nr;
242*4882a593Smuzhiyun struct mutex lock;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun struct cx25821_channel channels[MAX_VID_CHANNEL_NUM];
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* board details */
247*4882a593Smuzhiyun unsigned int board;
248*4882a593Smuzhiyun char name[32];
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* Analog video */
251*4882a593Smuzhiyun unsigned int input;
252*4882a593Smuzhiyun v4l2_std_id tvnorm;
253*4882a593Smuzhiyun unsigned short _max_num_decoders;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /* Analog Audio Upstream */
256*4882a593Smuzhiyun int _audio_is_running;
257*4882a593Smuzhiyun int _audiopixel_format;
258*4882a593Smuzhiyun int _is_first_audio_frame;
259*4882a593Smuzhiyun int _audiofile_status;
260*4882a593Smuzhiyun int _audio_lines_count;
261*4882a593Smuzhiyun int _audioframe_count;
262*4882a593Smuzhiyun int _audio_upstream_channel;
263*4882a593Smuzhiyun int _last_index_irq; /* The last interrupt index processed. */
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun __le32 *_risc_audio_jmp_addr;
266*4882a593Smuzhiyun __le32 *_risc_virt_start_addr;
267*4882a593Smuzhiyun __le32 *_risc_virt_addr;
268*4882a593Smuzhiyun dma_addr_t _risc_phys_addr;
269*4882a593Smuzhiyun dma_addr_t _risc_phys_start_addr;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun unsigned int _audiorisc_size;
272*4882a593Smuzhiyun unsigned int _audiodata_buf_size;
273*4882a593Smuzhiyun __le32 *_audiodata_buf_virt_addr;
274*4882a593Smuzhiyun dma_addr_t _audiodata_buf_phys_addr;
275*4882a593Smuzhiyun char *_audiofilename;
276*4882a593Smuzhiyun u32 audio_upstream_riscbuf_size;
277*4882a593Smuzhiyun u32 audio_upstream_databuf_size;
278*4882a593Smuzhiyun int _audioframe_index;
279*4882a593Smuzhiyun struct work_struct _audio_work_entry;
280*4882a593Smuzhiyun char *input_audiofilename;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun /* V4l */
283*4882a593Smuzhiyun spinlock_t slock;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /* Video Upstream */
286*4882a593Smuzhiyun struct cx25821_video_out_data vid_out_data[2];
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun
get_cx25821(struct v4l2_device * v4l2_dev)289*4882a593Smuzhiyun static inline struct cx25821_dev *get_cx25821(struct v4l2_device *v4l2_dev)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun return container_of(v4l2_dev, struct cx25821_dev, v4l2_dev);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun extern struct cx25821_board cx25821_boards[];
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun #define SRAM_CH00 0 /* Video A */
297*4882a593Smuzhiyun #define SRAM_CH01 1 /* Video B */
298*4882a593Smuzhiyun #define SRAM_CH02 2 /* Video C */
299*4882a593Smuzhiyun #define SRAM_CH03 3 /* Video D */
300*4882a593Smuzhiyun #define SRAM_CH04 4 /* Video E */
301*4882a593Smuzhiyun #define SRAM_CH05 5 /* Video F */
302*4882a593Smuzhiyun #define SRAM_CH06 6 /* Video G */
303*4882a593Smuzhiyun #define SRAM_CH07 7 /* Video H */
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun #define SRAM_CH08 8 /* Audio A */
306*4882a593Smuzhiyun #define SRAM_CH09 9 /* Video Upstream I */
307*4882a593Smuzhiyun #define SRAM_CH10 10 /* Video Upstream J */
308*4882a593Smuzhiyun #define SRAM_CH11 11 /* Audio Upstream AUD_CHANNEL_B */
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun #define VID_UPSTREAM_SRAM_CHANNEL_I SRAM_CH09
311*4882a593Smuzhiyun #define VID_UPSTREAM_SRAM_CHANNEL_J SRAM_CH10
312*4882a593Smuzhiyun #define AUDIO_UPSTREAM_SRAM_CHANNEL_B SRAM_CH11
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun struct sram_channel {
315*4882a593Smuzhiyun char *name;
316*4882a593Smuzhiyun u32 i;
317*4882a593Smuzhiyun u32 cmds_start;
318*4882a593Smuzhiyun u32 ctrl_start;
319*4882a593Smuzhiyun u32 cdt;
320*4882a593Smuzhiyun u32 fifo_start;
321*4882a593Smuzhiyun u32 fifo_size;
322*4882a593Smuzhiyun u32 ptr1_reg;
323*4882a593Smuzhiyun u32 ptr2_reg;
324*4882a593Smuzhiyun u32 cnt1_reg;
325*4882a593Smuzhiyun u32 cnt2_reg;
326*4882a593Smuzhiyun u32 int_msk;
327*4882a593Smuzhiyun u32 int_stat;
328*4882a593Smuzhiyun u32 int_mstat;
329*4882a593Smuzhiyun u32 dma_ctl;
330*4882a593Smuzhiyun u32 gpcnt_ctl;
331*4882a593Smuzhiyun u32 gpcnt;
332*4882a593Smuzhiyun u32 aud_length;
333*4882a593Smuzhiyun u32 aud_cfg;
334*4882a593Smuzhiyun u32 fld_aud_fifo_en;
335*4882a593Smuzhiyun u32 fld_aud_risc_en;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun /* For Upstream Video */
338*4882a593Smuzhiyun u32 vid_fmt_ctl;
339*4882a593Smuzhiyun u32 vid_active_ctl1;
340*4882a593Smuzhiyun u32 vid_active_ctl2;
341*4882a593Smuzhiyun u32 vid_cdt_size;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun u32 vip_ctl;
344*4882a593Smuzhiyun u32 pix_frmt;
345*4882a593Smuzhiyun u32 jumponly;
346*4882a593Smuzhiyun u32 irq_bit;
347*4882a593Smuzhiyun };
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun extern const struct sram_channel cx25821_sram_channels[];
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
352*4882a593Smuzhiyun #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun #define cx_andor(reg, mask, value) \
355*4882a593Smuzhiyun writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
356*4882a593Smuzhiyun ((value) & (mask)), dev->lmmio+((reg)>>2))
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
359*4882a593Smuzhiyun #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun #define Set_GPIO_Bit(Bit) (1 << Bit)
362*4882a593Smuzhiyun #define Clear_GPIO_Bit(Bit) (~(1 << Bit))
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun #define CX25821_ERR(fmt, args...) \
365*4882a593Smuzhiyun pr_err("(%d): " fmt, dev->board, ##args)
366*4882a593Smuzhiyun #define CX25821_WARN(fmt, args...) \
367*4882a593Smuzhiyun pr_warn("(%d): " fmt, dev->board, ##args)
368*4882a593Smuzhiyun #define CX25821_INFO(fmt, args...) \
369*4882a593Smuzhiyun pr_info("(%d): " fmt, dev->board, ##args)
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun extern int cx25821_i2c_register(struct cx25821_i2c *bus);
372*4882a593Smuzhiyun extern int cx25821_i2c_read(struct cx25821_i2c *bus, u16 reg_addr, int *value);
373*4882a593Smuzhiyun extern int cx25821_i2c_write(struct cx25821_i2c *bus, u16 reg_addr, int value);
374*4882a593Smuzhiyun extern int cx25821_i2c_unregister(struct cx25821_i2c *bus);
375*4882a593Smuzhiyun extern void cx25821_gpio_init(struct cx25821_dev *dev);
376*4882a593Smuzhiyun extern void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
377*4882a593Smuzhiyun int pin_number, int pin_logic_value);
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun extern int medusa_video_init(struct cx25821_dev *dev);
380*4882a593Smuzhiyun extern int medusa_set_videostandard(struct cx25821_dev *dev);
381*4882a593Smuzhiyun extern void medusa_set_resolution(struct cx25821_dev *dev, int width,
382*4882a593Smuzhiyun int decoder_select);
383*4882a593Smuzhiyun extern int medusa_set_brightness(struct cx25821_dev *dev, int brightness,
384*4882a593Smuzhiyun int decoder);
385*4882a593Smuzhiyun extern int medusa_set_contrast(struct cx25821_dev *dev, int contrast,
386*4882a593Smuzhiyun int decoder);
387*4882a593Smuzhiyun extern int medusa_set_hue(struct cx25821_dev *dev, int hue, int decoder);
388*4882a593Smuzhiyun extern int medusa_set_saturation(struct cx25821_dev *dev, int saturation,
389*4882a593Smuzhiyun int decoder);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun extern int cx25821_sram_channel_setup(struct cx25821_dev *dev,
392*4882a593Smuzhiyun const struct sram_channel *ch, unsigned int bpl,
393*4882a593Smuzhiyun u32 risc);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun extern int cx25821_riscmem_alloc(struct pci_dev *pci,
396*4882a593Smuzhiyun struct cx25821_riscmem *risc,
397*4882a593Smuzhiyun unsigned int size);
398*4882a593Smuzhiyun extern int cx25821_risc_buffer(struct pci_dev *pci, struct cx25821_riscmem *risc,
399*4882a593Smuzhiyun struct scatterlist *sglist,
400*4882a593Smuzhiyun unsigned int top_offset,
401*4882a593Smuzhiyun unsigned int bottom_offset,
402*4882a593Smuzhiyun unsigned int bpl,
403*4882a593Smuzhiyun unsigned int padding, unsigned int lines);
404*4882a593Smuzhiyun extern int cx25821_risc_databuffer_audio(struct pci_dev *pci,
405*4882a593Smuzhiyun struct cx25821_riscmem *risc,
406*4882a593Smuzhiyun struct scatterlist *sglist,
407*4882a593Smuzhiyun unsigned int bpl,
408*4882a593Smuzhiyun unsigned int lines, unsigned int lpi);
409*4882a593Smuzhiyun extern void cx25821_free_buffer(struct cx25821_dev *dev,
410*4882a593Smuzhiyun struct cx25821_buffer *buf);
411*4882a593Smuzhiyun extern void cx25821_sram_channel_dump(struct cx25821_dev *dev,
412*4882a593Smuzhiyun const struct sram_channel *ch);
413*4882a593Smuzhiyun extern void cx25821_sram_channel_dump_audio(struct cx25821_dev *dev,
414*4882a593Smuzhiyun const struct sram_channel *ch);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun extern struct cx25821_dev *cx25821_dev_get(struct pci_dev *pci);
417*4882a593Smuzhiyun extern void cx25821_print_irqbits(char *name, char *tag, char **strings,
418*4882a593Smuzhiyun int len, u32 bits, u32 mask);
419*4882a593Smuzhiyun extern void cx25821_dev_unregister(struct cx25821_dev *dev);
420*4882a593Smuzhiyun extern int cx25821_sram_channel_setup_audio(struct cx25821_dev *dev,
421*4882a593Smuzhiyun const struct sram_channel *ch,
422*4882a593Smuzhiyun unsigned int bpl, u32 risc);
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun extern void cx25821_set_pixel_format(struct cx25821_dev *dev, int channel,
425*4882a593Smuzhiyun u32 format);
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun #endif
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