1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for the Conexant CX25821 PCIe bridge 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Conexant Systems Inc. 6*4882a593Smuzhiyun * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __MEDUSA_REGISTERS__ 10*4882a593Smuzhiyun #define __MEDUSA_REGISTERS__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* Serial Slave Registers */ 13*4882a593Smuzhiyun #define HOST_REGISTER1 0x0000 14*4882a593Smuzhiyun #define HOST_REGISTER2 0x0001 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Chip Configuration Registers */ 17*4882a593Smuzhiyun #define CHIP_CTRL 0x0100 18*4882a593Smuzhiyun #define AFE_AB_CTRL 0x0104 19*4882a593Smuzhiyun #define AFE_CD_CTRL 0x0108 20*4882a593Smuzhiyun #define AFE_EF_CTRL 0x010C 21*4882a593Smuzhiyun #define AFE_GH_CTRL 0x0110 22*4882a593Smuzhiyun #define DENC_AB_CTRL 0x0114 23*4882a593Smuzhiyun #define BYP_AB_CTRL 0x0118 24*4882a593Smuzhiyun #define MON_A_CTRL 0x011C 25*4882a593Smuzhiyun #define DISP_SEQ_A 0x0120 26*4882a593Smuzhiyun #define DISP_SEQ_B 0x0124 27*4882a593Smuzhiyun #define DISP_AB_CNT 0x0128 28*4882a593Smuzhiyun #define DISP_CD_CNT 0x012C 29*4882a593Smuzhiyun #define DISP_EF_CNT 0x0130 30*4882a593Smuzhiyun #define DISP_GH_CNT 0x0134 31*4882a593Smuzhiyun #define DISP_IJ_CNT 0x0138 32*4882a593Smuzhiyun #define PIN_OE_CTRL 0x013C 33*4882a593Smuzhiyun #define PIN_SPD_CTRL 0x0140 34*4882a593Smuzhiyun #define PIN_SPD_CTRL2 0x0144 35*4882a593Smuzhiyun #define IRQ_STAT_CTRL 0x0148 36*4882a593Smuzhiyun #define POWER_CTRL_AB 0x014C 37*4882a593Smuzhiyun #define POWER_CTRL_CD 0x0150 38*4882a593Smuzhiyun #define POWER_CTRL_EF 0x0154 39*4882a593Smuzhiyun #define POWER_CTRL_GH 0x0158 40*4882a593Smuzhiyun #define TUNE_CTRL 0x015C 41*4882a593Smuzhiyun #define BIAS_CTRL 0x0160 42*4882a593Smuzhiyun #define AFE_AB_DIAG_CTRL 0x0164 43*4882a593Smuzhiyun #define AFE_CD_DIAG_CTRL 0x0168 44*4882a593Smuzhiyun #define AFE_EF_DIAG_CTRL 0x016C 45*4882a593Smuzhiyun #define AFE_GH_DIAG_CTRL 0x0170 46*4882a593Smuzhiyun #define PLL_AB_DIAG_CTRL 0x0174 47*4882a593Smuzhiyun #define PLL_CD_DIAG_CTRL 0x0178 48*4882a593Smuzhiyun #define PLL_EF_DIAG_CTRL 0x017C 49*4882a593Smuzhiyun #define PLL_GH_DIAG_CTRL 0x0180 50*4882a593Smuzhiyun #define TEST_CTRL 0x0184 51*4882a593Smuzhiyun #define BIST_STAT 0x0188 52*4882a593Smuzhiyun #define BIST_STAT2 0x018C 53*4882a593Smuzhiyun #define BIST_VID_PLL_AB_STAT 0x0190 54*4882a593Smuzhiyun #define BIST_VID_PLL_CD_STAT 0x0194 55*4882a593Smuzhiyun #define BIST_VID_PLL_EF_STAT 0x0198 56*4882a593Smuzhiyun #define BIST_VID_PLL_GH_STAT 0x019C 57*4882a593Smuzhiyun #define DLL_DIAG_CTRL 0x01A0 58*4882a593Smuzhiyun #define DEV_CH_ID_CTRL 0x01A4 59*4882a593Smuzhiyun #define ABIST_CTRL_STATUS 0x01A8 60*4882a593Smuzhiyun #define ABIST_FREQ 0x01AC 61*4882a593Smuzhiyun #define ABIST_GOERT_SHIFT 0x01B0 62*4882a593Smuzhiyun #define ABIST_COEF12 0x01B4 63*4882a593Smuzhiyun #define ABIST_COEF34 0x01B8 64*4882a593Smuzhiyun #define ABIST_COEF56 0x01BC 65*4882a593Smuzhiyun #define ABIST_COEF7_SNR 0x01C0 66*4882a593Smuzhiyun #define ABIST_ADC_CAL 0x01C4 67*4882a593Smuzhiyun #define ABIST_BIN1_VGA0 0x01C8 68*4882a593Smuzhiyun #define ABIST_BIN2_VGA1 0x01CC 69*4882a593Smuzhiyun #define ABIST_BIN3_VGA2 0x01D0 70*4882a593Smuzhiyun #define ABIST_BIN4_VGA3 0x01D4 71*4882a593Smuzhiyun #define ABIST_BIN5_VGA4 0x01D8 72*4882a593Smuzhiyun #define ABIST_BIN6_VGA5 0x01DC 73*4882a593Smuzhiyun #define ABIST_BIN7_VGA6 0x01E0 74*4882a593Smuzhiyun #define ABIST_CLAMP_A 0x01E4 75*4882a593Smuzhiyun #define ABIST_CLAMP_B 0x01E8 76*4882a593Smuzhiyun #define ABIST_CLAMP_C 0x01EC 77*4882a593Smuzhiyun #define ABIST_CLAMP_D 0x01F0 78*4882a593Smuzhiyun #define ABIST_CLAMP_E 0x01F4 79*4882a593Smuzhiyun #define ABIST_CLAMP_F 0x01F8 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* Digital Video Encoder A Registers */ 82*4882a593Smuzhiyun #define DENC_A_REG_1 0x0200 83*4882a593Smuzhiyun #define DENC_A_REG_2 0x0204 84*4882a593Smuzhiyun #define DENC_A_REG_3 0x0208 85*4882a593Smuzhiyun #define DENC_A_REG_4 0x020C 86*4882a593Smuzhiyun #define DENC_A_REG_5 0x0210 87*4882a593Smuzhiyun #define DENC_A_REG_6 0x0214 88*4882a593Smuzhiyun #define DENC_A_REG_7 0x0218 89*4882a593Smuzhiyun #define DENC_A_REG_8 0x021C 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* Digital Video Encoder B Registers */ 92*4882a593Smuzhiyun #define DENC_B_REG_1 0x0300 93*4882a593Smuzhiyun #define DENC_B_REG_2 0x0304 94*4882a593Smuzhiyun #define DENC_B_REG_3 0x0308 95*4882a593Smuzhiyun #define DENC_B_REG_4 0x030C 96*4882a593Smuzhiyun #define DENC_B_REG_5 0x0310 97*4882a593Smuzhiyun #define DENC_B_REG_6 0x0314 98*4882a593Smuzhiyun #define DENC_B_REG_7 0x0318 99*4882a593Smuzhiyun #define DENC_B_REG_8 0x031C 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Video Decoder A Registers */ 102*4882a593Smuzhiyun #define MODE_CTRL 0x1000 103*4882a593Smuzhiyun #define OUT_CTRL1 0x1004 104*4882a593Smuzhiyun #define OUT_CTRL_NS 0x1008 105*4882a593Smuzhiyun #define GEN_STAT 0x100C 106*4882a593Smuzhiyun #define INT_STAT_MASK 0x1010 107*4882a593Smuzhiyun #define LUMA_CTRL 0x1014 108*4882a593Smuzhiyun #define CHROMA_CTRL 0x1018 109*4882a593Smuzhiyun #define CRUSH_CTRL 0x101C 110*4882a593Smuzhiyun #define HORIZ_TIM_CTRL 0x1020 111*4882a593Smuzhiyun #define VERT_TIM_CTRL 0x1024 112*4882a593Smuzhiyun #define MISC_TIM_CTRL 0x1028 113*4882a593Smuzhiyun #define FIELD_COUNT 0x102C 114*4882a593Smuzhiyun #define HSCALE_CTRL 0x1030 115*4882a593Smuzhiyun #define VSCALE_CTRL 0x1034 116*4882a593Smuzhiyun #define MAN_VGA_CTRL 0x1038 117*4882a593Smuzhiyun #define MAN_AGC_CTRL 0x103C 118*4882a593Smuzhiyun #define DFE_CTRL1 0x1040 119*4882a593Smuzhiyun #define DFE_CTRL2 0x1044 120*4882a593Smuzhiyun #define DFE_CTRL3 0x1048 121*4882a593Smuzhiyun #define PLL_CTRL 0x104C 122*4882a593Smuzhiyun #define PLL_CTRL_FAST 0x1050 123*4882a593Smuzhiyun #define HTL_CTRL 0x1054 124*4882a593Smuzhiyun #define SRC_CFG 0x1058 125*4882a593Smuzhiyun #define SC_STEP_SIZE 0x105C 126*4882a593Smuzhiyun #define SC_CONVERGE_CTRL 0x1060 127*4882a593Smuzhiyun #define SC_LOOP_CTRL 0x1064 128*4882a593Smuzhiyun #define COMB_2D_HFS_CFG 0x1068 129*4882a593Smuzhiyun #define COMB_2D_HFD_CFG 0x106C 130*4882a593Smuzhiyun #define COMB_2D_LF_CFG 0x1070 131*4882a593Smuzhiyun #define COMB_2D_BLEND 0x1074 132*4882a593Smuzhiyun #define COMB_MISC_CTRL 0x1078 133*4882a593Smuzhiyun #define COMB_FLAT_THRESH_CTRL 0x107C 134*4882a593Smuzhiyun #define COMB_TEST 0x1080 135*4882a593Smuzhiyun #define BP_MISC_CTRL 0x1084 136*4882a593Smuzhiyun #define VCR_DET_CTRL 0x1088 137*4882a593Smuzhiyun #define NOISE_DET_CTRL 0x108C 138*4882a593Smuzhiyun #define COMB_FLAT_NOISE_CTRL 0x1090 139*4882a593Smuzhiyun #define VERSION 0x11F8 140*4882a593Smuzhiyun #define SOFT_RST_CTRL 0x11FC 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* Video Decoder B Registers */ 143*4882a593Smuzhiyun #define VDEC_B_MODE_CTRL 0x1200 144*4882a593Smuzhiyun #define VDEC_B_OUT_CTRL1 0x1204 145*4882a593Smuzhiyun #define VDEC_B_OUT_CTRL_NS 0x1208 146*4882a593Smuzhiyun #define VDEC_B_GEN_STAT 0x120C 147*4882a593Smuzhiyun #define VDEC_B_INT_STAT_MASK 0x1210 148*4882a593Smuzhiyun #define VDEC_B_LUMA_CTRL 0x1214 149*4882a593Smuzhiyun #define VDEC_B_CHROMA_CTRL 0x1218 150*4882a593Smuzhiyun #define VDEC_B_CRUSH_CTRL 0x121C 151*4882a593Smuzhiyun #define VDEC_B_HORIZ_TIM_CTRL 0x1220 152*4882a593Smuzhiyun #define VDEC_B_VERT_TIM_CTRL 0x1224 153*4882a593Smuzhiyun #define VDEC_B_MISC_TIM_CTRL 0x1228 154*4882a593Smuzhiyun #define VDEC_B_FIELD_COUNT 0x122C 155*4882a593Smuzhiyun #define VDEC_B_HSCALE_CTRL 0x1230 156*4882a593Smuzhiyun #define VDEC_B_VSCALE_CTRL 0x1234 157*4882a593Smuzhiyun #define VDEC_B_MAN_VGA_CTRL 0x1238 158*4882a593Smuzhiyun #define VDEC_B_MAN_AGC_CTRL 0x123C 159*4882a593Smuzhiyun #define VDEC_B_DFE_CTRL1 0x1240 160*4882a593Smuzhiyun #define VDEC_B_DFE_CTRL2 0x1244 161*4882a593Smuzhiyun #define VDEC_B_DFE_CTRL3 0x1248 162*4882a593Smuzhiyun #define VDEC_B_PLL_CTRL 0x124C 163*4882a593Smuzhiyun #define VDEC_B_PLL_CTRL_FAST 0x1250 164*4882a593Smuzhiyun #define VDEC_B_HTL_CTRL 0x1254 165*4882a593Smuzhiyun #define VDEC_B_SRC_CFG 0x1258 166*4882a593Smuzhiyun #define VDEC_B_SC_STEP_SIZE 0x125C 167*4882a593Smuzhiyun #define VDEC_B_SC_CONVERGE_CTRL 0x1260 168*4882a593Smuzhiyun #define VDEC_B_SC_LOOP_CTRL 0x1264 169*4882a593Smuzhiyun #define VDEC_B_COMB_2D_HFS_CFG 0x1268 170*4882a593Smuzhiyun #define VDEC_B_COMB_2D_HFD_CFG 0x126C 171*4882a593Smuzhiyun #define VDEC_B_COMB_2D_LF_CFG 0x1270 172*4882a593Smuzhiyun #define VDEC_B_COMB_2D_BLEND 0x1274 173*4882a593Smuzhiyun #define VDEC_B_COMB_MISC_CTRL 0x1278 174*4882a593Smuzhiyun #define VDEC_B_COMB_FLAT_THRESH_CTRL 0x127C 175*4882a593Smuzhiyun #define VDEC_B_COMB_TEST 0x1280 176*4882a593Smuzhiyun #define VDEC_B_BP_MISC_CTRL 0x1284 177*4882a593Smuzhiyun #define VDEC_B_VCR_DET_CTRL 0x1288 178*4882a593Smuzhiyun #define VDEC_B_NOISE_DET_CTRL 0x128C 179*4882a593Smuzhiyun #define VDEC_B_COMB_FLAT_NOISE_CTRL 0x1290 180*4882a593Smuzhiyun #define VDEC_B_VERSION 0x13F8 181*4882a593Smuzhiyun #define VDEC_B_SOFT_RST_CTRL 0x13FC 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* Video Decoder C Registers */ 184*4882a593Smuzhiyun #define VDEC_C_MODE_CTRL 0x1400 185*4882a593Smuzhiyun #define VDEC_C_OUT_CTRL1 0x1404 186*4882a593Smuzhiyun #define VDEC_C_OUT_CTRL_NS 0x1408 187*4882a593Smuzhiyun #define VDEC_C_GEN_STAT 0x140C 188*4882a593Smuzhiyun #define VDEC_C_INT_STAT_MASK 0x1410 189*4882a593Smuzhiyun #define VDEC_C_LUMA_CTRL 0x1414 190*4882a593Smuzhiyun #define VDEC_C_CHROMA_CTRL 0x1418 191*4882a593Smuzhiyun #define VDEC_C_CRUSH_CTRL 0x141C 192*4882a593Smuzhiyun #define VDEC_C_HORIZ_TIM_CTRL 0x1420 193*4882a593Smuzhiyun #define VDEC_C_VERT_TIM_CTRL 0x1424 194*4882a593Smuzhiyun #define VDEC_C_MISC_TIM_CTRL 0x1428 195*4882a593Smuzhiyun #define VDEC_C_FIELD_COUNT 0x142C 196*4882a593Smuzhiyun #define VDEC_C_HSCALE_CTRL 0x1430 197*4882a593Smuzhiyun #define VDEC_C_VSCALE_CTRL 0x1434 198*4882a593Smuzhiyun #define VDEC_C_MAN_VGA_CTRL 0x1438 199*4882a593Smuzhiyun #define VDEC_C_MAN_AGC_CTRL 0x143C 200*4882a593Smuzhiyun #define VDEC_C_DFE_CTRL1 0x1440 201*4882a593Smuzhiyun #define VDEC_C_DFE_CTRL2 0x1444 202*4882a593Smuzhiyun #define VDEC_C_DFE_CTRL3 0x1448 203*4882a593Smuzhiyun #define VDEC_C_PLL_CTRL 0x144C 204*4882a593Smuzhiyun #define VDEC_C_PLL_CTRL_FAST 0x1450 205*4882a593Smuzhiyun #define VDEC_C_HTL_CTRL 0x1454 206*4882a593Smuzhiyun #define VDEC_C_SRC_CFG 0x1458 207*4882a593Smuzhiyun #define VDEC_C_SC_STEP_SIZE 0x145C 208*4882a593Smuzhiyun #define VDEC_C_SC_CONVERGE_CTRL 0x1460 209*4882a593Smuzhiyun #define VDEC_C_SC_LOOP_CTRL 0x1464 210*4882a593Smuzhiyun #define VDEC_C_COMB_2D_HFS_CFG 0x1468 211*4882a593Smuzhiyun #define VDEC_C_COMB_2D_HFD_CFG 0x146C 212*4882a593Smuzhiyun #define VDEC_C_COMB_2D_LF_CFG 0x1470 213*4882a593Smuzhiyun #define VDEC_C_COMB_2D_BLEND 0x1474 214*4882a593Smuzhiyun #define VDEC_C_COMB_MISC_CTRL 0x1478 215*4882a593Smuzhiyun #define VDEC_C_COMB_FLAT_THRESH_CTRL 0x147C 216*4882a593Smuzhiyun #define VDEC_C_COMB_TEST 0x1480 217*4882a593Smuzhiyun #define VDEC_C_BP_MISC_CTRL 0x1484 218*4882a593Smuzhiyun #define VDEC_C_VCR_DET_CTRL 0x1488 219*4882a593Smuzhiyun #define VDEC_C_NOISE_DET_CTRL 0x148C 220*4882a593Smuzhiyun #define VDEC_C_COMB_FLAT_NOISE_CTRL 0x1490 221*4882a593Smuzhiyun #define VDEC_C_VERSION 0x15F8 222*4882a593Smuzhiyun #define VDEC_C_SOFT_RST_CTRL 0x15FC 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* Video Decoder D Registers */ 225*4882a593Smuzhiyun #define VDEC_D_MODE_CTRL 0x1600 226*4882a593Smuzhiyun #define VDEC_D_OUT_CTRL1 0x1604 227*4882a593Smuzhiyun #define VDEC_D_OUT_CTRL_NS 0x1608 228*4882a593Smuzhiyun #define VDEC_D_GEN_STAT 0x160C 229*4882a593Smuzhiyun #define VDEC_D_INT_STAT_MASK 0x1610 230*4882a593Smuzhiyun #define VDEC_D_LUMA_CTRL 0x1614 231*4882a593Smuzhiyun #define VDEC_D_CHROMA_CTRL 0x1618 232*4882a593Smuzhiyun #define VDEC_D_CRUSH_CTRL 0x161C 233*4882a593Smuzhiyun #define VDEC_D_HORIZ_TIM_CTRL 0x1620 234*4882a593Smuzhiyun #define VDEC_D_VERT_TIM_CTRL 0x1624 235*4882a593Smuzhiyun #define VDEC_D_MISC_TIM_CTRL 0x1628 236*4882a593Smuzhiyun #define VDEC_D_FIELD_COUNT 0x162C 237*4882a593Smuzhiyun #define VDEC_D_HSCALE_CTRL 0x1630 238*4882a593Smuzhiyun #define VDEC_D_VSCALE_CTRL 0x1634 239*4882a593Smuzhiyun #define VDEC_D_MAN_VGA_CTRL 0x1638 240*4882a593Smuzhiyun #define VDEC_D_MAN_AGC_CTRL 0x163C 241*4882a593Smuzhiyun #define VDEC_D_DFE_CTRL1 0x1640 242*4882a593Smuzhiyun #define VDEC_D_DFE_CTRL2 0x1644 243*4882a593Smuzhiyun #define VDEC_D_DFE_CTRL3 0x1648 244*4882a593Smuzhiyun #define VDEC_D_PLL_CTRL 0x164C 245*4882a593Smuzhiyun #define VDEC_D_PLL_CTRL_FAST 0x1650 246*4882a593Smuzhiyun #define VDEC_D_HTL_CTRL 0x1654 247*4882a593Smuzhiyun #define VDEC_D_SRC_CFG 0x1658 248*4882a593Smuzhiyun #define VDEC_D_SC_STEP_SIZE 0x165C 249*4882a593Smuzhiyun #define VDEC_D_SC_CONVERGE_CTRL 0x1660 250*4882a593Smuzhiyun #define VDEC_D_SC_LOOP_CTRL 0x1664 251*4882a593Smuzhiyun #define VDEC_D_COMB_2D_HFS_CFG 0x1668 252*4882a593Smuzhiyun #define VDEC_D_COMB_2D_HFD_CFG 0x166C 253*4882a593Smuzhiyun #define VDEC_D_COMB_2D_LF_CFG 0x1670 254*4882a593Smuzhiyun #define VDEC_D_COMB_2D_BLEND 0x1674 255*4882a593Smuzhiyun #define VDEC_D_COMB_MISC_CTRL 0x1678 256*4882a593Smuzhiyun #define VDEC_D_COMB_FLAT_THRESH_CTRL 0x167C 257*4882a593Smuzhiyun #define VDEC_D_COMB_TEST 0x1680 258*4882a593Smuzhiyun #define VDEC_D_BP_MISC_CTRL 0x1684 259*4882a593Smuzhiyun #define VDEC_D_VCR_DET_CTRL 0x1688 260*4882a593Smuzhiyun #define VDEC_D_NOISE_DET_CTRL 0x168C 261*4882a593Smuzhiyun #define VDEC_D_COMB_FLAT_NOISE_CTRL 0x1690 262*4882a593Smuzhiyun #define VDEC_D_VERSION 0x17F8 263*4882a593Smuzhiyun #define VDEC_D_SOFT_RST_CTRL 0x17FC 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun /* Video Decoder E Registers */ 266*4882a593Smuzhiyun #define VDEC_E_MODE_CTRL 0x1800 267*4882a593Smuzhiyun #define VDEC_E_OUT_CTRL1 0x1804 268*4882a593Smuzhiyun #define VDEC_E_OUT_CTRL_NS 0x1808 269*4882a593Smuzhiyun #define VDEC_E_GEN_STAT 0x180C 270*4882a593Smuzhiyun #define VDEC_E_INT_STAT_MASK 0x1810 271*4882a593Smuzhiyun #define VDEC_E_LUMA_CTRL 0x1814 272*4882a593Smuzhiyun #define VDEC_E_CHROMA_CTRL 0x1818 273*4882a593Smuzhiyun #define VDEC_E_CRUSH_CTRL 0x181C 274*4882a593Smuzhiyun #define VDEC_E_HORIZ_TIM_CTRL 0x1820 275*4882a593Smuzhiyun #define VDEC_E_VERT_TIM_CTRL 0x1824 276*4882a593Smuzhiyun #define VDEC_E_MISC_TIM_CTRL 0x1828 277*4882a593Smuzhiyun #define VDEC_E_FIELD_COUNT 0x182C 278*4882a593Smuzhiyun #define VDEC_E_HSCALE_CTRL 0x1830 279*4882a593Smuzhiyun #define VDEC_E_VSCALE_CTRL 0x1834 280*4882a593Smuzhiyun #define VDEC_E_MAN_VGA_CTRL 0x1838 281*4882a593Smuzhiyun #define VDEC_E_MAN_AGC_CTRL 0x183C 282*4882a593Smuzhiyun #define VDEC_E_DFE_CTRL1 0x1840 283*4882a593Smuzhiyun #define VDEC_E_DFE_CTRL2 0x1844 284*4882a593Smuzhiyun #define VDEC_E_DFE_CTRL3 0x1848 285*4882a593Smuzhiyun #define VDEC_E_PLL_CTRL 0x184C 286*4882a593Smuzhiyun #define VDEC_E_PLL_CTRL_FAST 0x1850 287*4882a593Smuzhiyun #define VDEC_E_HTL_CTRL 0x1854 288*4882a593Smuzhiyun #define VDEC_E_SRC_CFG 0x1858 289*4882a593Smuzhiyun #define VDEC_E_SC_STEP_SIZE 0x185C 290*4882a593Smuzhiyun #define VDEC_E_SC_CONVERGE_CTRL 0x1860 291*4882a593Smuzhiyun #define VDEC_E_SC_LOOP_CTRL 0x1864 292*4882a593Smuzhiyun #define VDEC_E_COMB_2D_HFS_CFG 0x1868 293*4882a593Smuzhiyun #define VDEC_E_COMB_2D_HFD_CFG 0x186C 294*4882a593Smuzhiyun #define VDEC_E_COMB_2D_LF_CFG 0x1870 295*4882a593Smuzhiyun #define VDEC_E_COMB_2D_BLEND 0x1874 296*4882a593Smuzhiyun #define VDEC_E_COMB_MISC_CTRL 0x1878 297*4882a593Smuzhiyun #define VDEC_E_COMB_FLAT_THRESH_CTRL 0x187C 298*4882a593Smuzhiyun #define VDEC_E_COMB_TEST 0x1880 299*4882a593Smuzhiyun #define VDEC_E_BP_MISC_CTRL 0x1884 300*4882a593Smuzhiyun #define VDEC_E_VCR_DET_CTRL 0x1888 301*4882a593Smuzhiyun #define VDEC_E_NOISE_DET_CTRL 0x188C 302*4882a593Smuzhiyun #define VDEC_E_COMB_FLAT_NOISE_CTRL 0x1890 303*4882a593Smuzhiyun #define VDEC_E_VERSION 0x19F8 304*4882a593Smuzhiyun #define VDEC_E_SOFT_RST_CTRL 0x19FC 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun /* Video Decoder F Registers */ 307*4882a593Smuzhiyun #define VDEC_F_MODE_CTRL 0x1A00 308*4882a593Smuzhiyun #define VDEC_F_OUT_CTRL1 0x1A04 309*4882a593Smuzhiyun #define VDEC_F_OUT_CTRL_NS 0x1A08 310*4882a593Smuzhiyun #define VDEC_F_GEN_STAT 0x1A0C 311*4882a593Smuzhiyun #define VDEC_F_INT_STAT_MASK 0x1A10 312*4882a593Smuzhiyun #define VDEC_F_LUMA_CTRL 0x1A14 313*4882a593Smuzhiyun #define VDEC_F_CHROMA_CTRL 0x1A18 314*4882a593Smuzhiyun #define VDEC_F_CRUSH_CTRL 0x1A1C 315*4882a593Smuzhiyun #define VDEC_F_HORIZ_TIM_CTRL 0x1A20 316*4882a593Smuzhiyun #define VDEC_F_VERT_TIM_CTRL 0x1A24 317*4882a593Smuzhiyun #define VDEC_F_MISC_TIM_CTRL 0x1A28 318*4882a593Smuzhiyun #define VDEC_F_FIELD_COUNT 0x1A2C 319*4882a593Smuzhiyun #define VDEC_F_HSCALE_CTRL 0x1A30 320*4882a593Smuzhiyun #define VDEC_F_VSCALE_CTRL 0x1A34 321*4882a593Smuzhiyun #define VDEC_F_MAN_VGA_CTRL 0x1A38 322*4882a593Smuzhiyun #define VDEC_F_MAN_AGC_CTRL 0x1A3C 323*4882a593Smuzhiyun #define VDEC_F_DFE_CTRL1 0x1A40 324*4882a593Smuzhiyun #define VDEC_F_DFE_CTRL2 0x1A44 325*4882a593Smuzhiyun #define VDEC_F_DFE_CTRL3 0x1A48 326*4882a593Smuzhiyun #define VDEC_F_PLL_CTRL 0x1A4C 327*4882a593Smuzhiyun #define VDEC_F_PLL_CTRL_FAST 0x1A50 328*4882a593Smuzhiyun #define VDEC_F_HTL_CTRL 0x1A54 329*4882a593Smuzhiyun #define VDEC_F_SRC_CFG 0x1A58 330*4882a593Smuzhiyun #define VDEC_F_SC_STEP_SIZE 0x1A5C 331*4882a593Smuzhiyun #define VDEC_F_SC_CONVERGE_CTRL 0x1A60 332*4882a593Smuzhiyun #define VDEC_F_SC_LOOP_CTRL 0x1A64 333*4882a593Smuzhiyun #define VDEC_F_COMB_2D_HFS_CFG 0x1A68 334*4882a593Smuzhiyun #define VDEC_F_COMB_2D_HFD_CFG 0x1A6C 335*4882a593Smuzhiyun #define VDEC_F_COMB_2D_LF_CFG 0x1A70 336*4882a593Smuzhiyun #define VDEC_F_COMB_2D_BLEND 0x1A74 337*4882a593Smuzhiyun #define VDEC_F_COMB_MISC_CTRL 0x1A78 338*4882a593Smuzhiyun #define VDEC_F_COMB_FLAT_THRESH_CTRL 0x1A7C 339*4882a593Smuzhiyun #define VDEC_F_COMB_TEST 0x1A80 340*4882a593Smuzhiyun #define VDEC_F_BP_MISC_CTRL 0x1A84 341*4882a593Smuzhiyun #define VDEC_F_VCR_DET_CTRL 0x1A88 342*4882a593Smuzhiyun #define VDEC_F_NOISE_DET_CTRL 0x1A8C 343*4882a593Smuzhiyun #define VDEC_F_COMB_FLAT_NOISE_CTRL 0x1A90 344*4882a593Smuzhiyun #define VDEC_F_VERSION 0x1BF8 345*4882a593Smuzhiyun #define VDEC_F_SOFT_RST_CTRL 0x1BFC 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /* Video Decoder G Registers */ 348*4882a593Smuzhiyun #define VDEC_G_MODE_CTRL 0x1C00 349*4882a593Smuzhiyun #define VDEC_G_OUT_CTRL1 0x1C04 350*4882a593Smuzhiyun #define VDEC_G_OUT_CTRL_NS 0x1C08 351*4882a593Smuzhiyun #define VDEC_G_GEN_STAT 0x1C0C 352*4882a593Smuzhiyun #define VDEC_G_INT_STAT_MASK 0x1C10 353*4882a593Smuzhiyun #define VDEC_G_LUMA_CTRL 0x1C14 354*4882a593Smuzhiyun #define VDEC_G_CHROMA_CTRL 0x1C18 355*4882a593Smuzhiyun #define VDEC_G_CRUSH_CTRL 0x1C1C 356*4882a593Smuzhiyun #define VDEC_G_HORIZ_TIM_CTRL 0x1C20 357*4882a593Smuzhiyun #define VDEC_G_VERT_TIM_CTRL 0x1C24 358*4882a593Smuzhiyun #define VDEC_G_MISC_TIM_CTRL 0x1C28 359*4882a593Smuzhiyun #define VDEC_G_FIELD_COUNT 0x1C2C 360*4882a593Smuzhiyun #define VDEC_G_HSCALE_CTRL 0x1C30 361*4882a593Smuzhiyun #define VDEC_G_VSCALE_CTRL 0x1C34 362*4882a593Smuzhiyun #define VDEC_G_MAN_VGA_CTRL 0x1C38 363*4882a593Smuzhiyun #define VDEC_G_MAN_AGC_CTRL 0x1C3C 364*4882a593Smuzhiyun #define VDEC_G_DFE_CTRL1 0x1C40 365*4882a593Smuzhiyun #define VDEC_G_DFE_CTRL2 0x1C44 366*4882a593Smuzhiyun #define VDEC_G_DFE_CTRL3 0x1C48 367*4882a593Smuzhiyun #define VDEC_G_PLL_CTRL 0x1C4C 368*4882a593Smuzhiyun #define VDEC_G_PLL_CTRL_FAST 0x1C50 369*4882a593Smuzhiyun #define VDEC_G_HTL_CTRL 0x1C54 370*4882a593Smuzhiyun #define VDEC_G_SRC_CFG 0x1C58 371*4882a593Smuzhiyun #define VDEC_G_SC_STEP_SIZE 0x1C5C 372*4882a593Smuzhiyun #define VDEC_G_SC_CONVERGE_CTRL 0x1C60 373*4882a593Smuzhiyun #define VDEC_G_SC_LOOP_CTRL 0x1C64 374*4882a593Smuzhiyun #define VDEC_G_COMB_2D_HFS_CFG 0x1C68 375*4882a593Smuzhiyun #define VDEC_G_COMB_2D_HFD_CFG 0x1C6C 376*4882a593Smuzhiyun #define VDEC_G_COMB_2D_LF_CFG 0x1C70 377*4882a593Smuzhiyun #define VDEC_G_COMB_2D_BLEND 0x1C74 378*4882a593Smuzhiyun #define VDEC_G_COMB_MISC_CTRL 0x1C78 379*4882a593Smuzhiyun #define VDEC_G_COMB_FLAT_THRESH_CTRL 0x1C7C 380*4882a593Smuzhiyun #define VDEC_G_COMB_TEST 0x1C80 381*4882a593Smuzhiyun #define VDEC_G_BP_MISC_CTRL 0x1C84 382*4882a593Smuzhiyun #define VDEC_G_VCR_DET_CTRL 0x1C88 383*4882a593Smuzhiyun #define VDEC_G_NOISE_DET_CTRL 0x1C8C 384*4882a593Smuzhiyun #define VDEC_G_COMB_FLAT_NOISE_CTRL 0x1C90 385*4882a593Smuzhiyun #define VDEC_G_VERSION 0x1DF8 386*4882a593Smuzhiyun #define VDEC_G_SOFT_RST_CTRL 0x1DFC 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* Video Decoder H Registers */ 389*4882a593Smuzhiyun #define VDEC_H_MODE_CTRL 0x1E00 390*4882a593Smuzhiyun #define VDEC_H_OUT_CTRL1 0x1E04 391*4882a593Smuzhiyun #define VDEC_H_OUT_CTRL_NS 0x1E08 392*4882a593Smuzhiyun #define VDEC_H_GEN_STAT 0x1E0C 393*4882a593Smuzhiyun #define VDEC_H_INT_STAT_MASK 0x1E1E 394*4882a593Smuzhiyun #define VDEC_H_LUMA_CTRL 0x1E14 395*4882a593Smuzhiyun #define VDEC_H_CHROMA_CTRL 0x1E18 396*4882a593Smuzhiyun #define VDEC_H_CRUSH_CTRL 0x1E1C 397*4882a593Smuzhiyun #define VDEC_H_HORIZ_TIM_CTRL 0x1E20 398*4882a593Smuzhiyun #define VDEC_H_VERT_TIM_CTRL 0x1E24 399*4882a593Smuzhiyun #define VDEC_H_MISC_TIM_CTRL 0x1E28 400*4882a593Smuzhiyun #define VDEC_H_FIELD_COUNT 0x1E2C 401*4882a593Smuzhiyun #define VDEC_H_HSCALE_CTRL 0x1E30 402*4882a593Smuzhiyun #define VDEC_H_VSCALE_CTRL 0x1E34 403*4882a593Smuzhiyun #define VDEC_H_MAN_VGA_CTRL 0x1E38 404*4882a593Smuzhiyun #define VDEC_H_MAN_AGC_CTRL 0x1E3C 405*4882a593Smuzhiyun #define VDEC_H_DFE_CTRL1 0x1E40 406*4882a593Smuzhiyun #define VDEC_H_DFE_CTRL2 0x1E44 407*4882a593Smuzhiyun #define VDEC_H_DFE_CTRL3 0x1E48 408*4882a593Smuzhiyun #define VDEC_H_PLL_CTRL 0x1E4C 409*4882a593Smuzhiyun #define VDEC_H_PLL_CTRL_FAST 0x1E50 410*4882a593Smuzhiyun #define VDEC_H_HTL_CTRL 0x1E54 411*4882a593Smuzhiyun #define VDEC_H_SRC_CFG 0x1E58 412*4882a593Smuzhiyun #define VDEC_H_SC_STEP_SIZE 0x1E5C 413*4882a593Smuzhiyun #define VDEC_H_SC_CONVERGE_CTRL 0x1E60 414*4882a593Smuzhiyun #define VDEC_H_SC_LOOP_CTRL 0x1E64 415*4882a593Smuzhiyun #define VDEC_H_COMB_2D_HFS_CFG 0x1E68 416*4882a593Smuzhiyun #define VDEC_H_COMB_2D_HFD_CFG 0x1E6C 417*4882a593Smuzhiyun #define VDEC_H_COMB_2D_LF_CFG 0x1E70 418*4882a593Smuzhiyun #define VDEC_H_COMB_2D_BLEND 0x1E74 419*4882a593Smuzhiyun #define VDEC_H_COMB_MISC_CTRL 0x1E78 420*4882a593Smuzhiyun #define VDEC_H_COMB_FLAT_THRESH_CTRL 0x1E7C 421*4882a593Smuzhiyun #define VDEC_H_COMB_TEST 0x1E80 422*4882a593Smuzhiyun #define VDEC_H_BP_MISC_CTRL 0x1E84 423*4882a593Smuzhiyun #define VDEC_H_VCR_DET_CTRL 0x1E88 424*4882a593Smuzhiyun #define VDEC_H_NOISE_DET_CTRL 0x1E8C 425*4882a593Smuzhiyun #define VDEC_H_COMB_FLAT_NOISE_CTRL 0x1E90 426*4882a593Smuzhiyun #define VDEC_H_VERSION 0x1FF8 427*4882a593Smuzhiyun #define VDEC_H_SOFT_RST_CTRL 0x1FFC 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun /*****************************************************************************/ 430*4882a593Smuzhiyun /* LUMA_CTRL register fields */ 431*4882a593Smuzhiyun #define VDEC_A_BRITE_CTRL 0x1014 432*4882a593Smuzhiyun #define VDEC_A_CNTRST_CTRL 0x1015 433*4882a593Smuzhiyun #define VDEC_A_PEAK_SEL 0x1016 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun /*****************************************************************************/ 436*4882a593Smuzhiyun /* CHROMA_CTRL register fields */ 437*4882a593Smuzhiyun #define VDEC_A_USAT_CTRL 0x1018 438*4882a593Smuzhiyun #define VDEC_A_VSAT_CTRL 0x1019 439*4882a593Smuzhiyun #define VDEC_A_HUE_CTRL 0x101A 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun #endif 442