1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Conexant CX25821 PCIe bridge
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2009 Conexant Systems Inc.
6*4882a593Smuzhiyun * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include "cx25821.h"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /********************* GPIO stuffs *********************/
cx25821_set_gpiopin_direction(struct cx25821_dev * dev,int pin_number,int pin_logic_value)13*4882a593Smuzhiyun void cx25821_set_gpiopin_direction(struct cx25821_dev *dev,
14*4882a593Smuzhiyun int pin_number, int pin_logic_value)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun int bit = pin_number;
17*4882a593Smuzhiyun u32 gpio_oe_reg = GPIO_LO_OE;
18*4882a593Smuzhiyun u32 gpio_register = 0;
19*4882a593Smuzhiyun u32 value = 0;
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Check for valid pinNumber */
22*4882a593Smuzhiyun if (pin_number >= 47)
23*4882a593Smuzhiyun return;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun if (pin_number > 31) {
26*4882a593Smuzhiyun bit = pin_number - 31;
27*4882a593Smuzhiyun gpio_oe_reg = GPIO_HI_OE;
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun /* Here we will make sure that the GPIOs 0 and 1 are output. keep the
30*4882a593Smuzhiyun * rest as is */
31*4882a593Smuzhiyun gpio_register = cx_read(gpio_oe_reg);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun if (pin_logic_value == 1)
34*4882a593Smuzhiyun value = gpio_register | Set_GPIO_Bit(bit);
35*4882a593Smuzhiyun else
36*4882a593Smuzhiyun value = gpio_register & Clear_GPIO_Bit(bit);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun cx_write(gpio_oe_reg, value);
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun EXPORT_SYMBOL(cx25821_set_gpiopin_direction);
41*4882a593Smuzhiyun
cx25821_set_gpiopin_logicvalue(struct cx25821_dev * dev,int pin_number,int pin_logic_value)42*4882a593Smuzhiyun static void cx25821_set_gpiopin_logicvalue(struct cx25821_dev *dev,
43*4882a593Smuzhiyun int pin_number, int pin_logic_value)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun int bit = pin_number;
46*4882a593Smuzhiyun u32 gpio_reg = GPIO_LO;
47*4882a593Smuzhiyun u32 value = 0;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Check for valid pinNumber */
50*4882a593Smuzhiyun if (pin_number >= 47)
51*4882a593Smuzhiyun return;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* change to output direction */
54*4882a593Smuzhiyun cx25821_set_gpiopin_direction(dev, pin_number, 0);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (pin_number > 31) {
57*4882a593Smuzhiyun bit = pin_number - 31;
58*4882a593Smuzhiyun gpio_reg = GPIO_HI;
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun value = cx_read(gpio_reg);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (pin_logic_value == 0)
64*4882a593Smuzhiyun value &= Clear_GPIO_Bit(bit);
65*4882a593Smuzhiyun else
66*4882a593Smuzhiyun value |= Set_GPIO_Bit(bit);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun cx_write(gpio_reg, value);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
cx25821_gpio_init(struct cx25821_dev * dev)71*4882a593Smuzhiyun void cx25821_gpio_init(struct cx25821_dev *dev)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun if (dev == NULL)
74*4882a593Smuzhiyun return;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun switch (dev->board) {
77*4882a593Smuzhiyun case CX25821_BOARD_CONEXANT_ATHENA10:
78*4882a593Smuzhiyun default:
79*4882a593Smuzhiyun /* set GPIO 5 to select the path for Medusa/Athena */
80*4882a593Smuzhiyun cx25821_set_gpiopin_logicvalue(dev, 5, 1);
81*4882a593Smuzhiyun msleep(20);
82*4882a593Smuzhiyun break;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun }
86