1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * netup-init.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * NetUP Dual DVB-S2 CI driver
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2009 NetUP Inc.
8*4882a593Smuzhiyun * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9*4882a593Smuzhiyun * Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "cx23885.h"
13*4882a593Smuzhiyun #include "netup-init.h"
14*4882a593Smuzhiyun
i2c_av_write(struct i2c_adapter * i2c,u16 reg,u8 val)15*4882a593Smuzhiyun static void i2c_av_write(struct i2c_adapter *i2c, u16 reg, u8 val)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun int ret;
18*4882a593Smuzhiyun u8 buf[3];
19*4882a593Smuzhiyun struct i2c_msg msg = {
20*4882a593Smuzhiyun .addr = 0x88 >> 1,
21*4882a593Smuzhiyun .flags = 0,
22*4882a593Smuzhiyun .buf = buf,
23*4882a593Smuzhiyun .len = 3
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun buf[0] = reg >> 8;
27*4882a593Smuzhiyun buf[1] = reg & 0xff;
28*4882a593Smuzhiyun buf[2] = val;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun ret = i2c_transfer(i2c, &msg, 1);
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun if (ret != 1)
33*4882a593Smuzhiyun pr_err("%s: i2c write error!\n", __func__);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
i2c_av_write4(struct i2c_adapter * i2c,u16 reg,u32 val)36*4882a593Smuzhiyun static void i2c_av_write4(struct i2c_adapter *i2c, u16 reg, u32 val)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun int ret;
39*4882a593Smuzhiyun u8 buf[6];
40*4882a593Smuzhiyun struct i2c_msg msg = {
41*4882a593Smuzhiyun .addr = 0x88 >> 1,
42*4882a593Smuzhiyun .flags = 0,
43*4882a593Smuzhiyun .buf = buf,
44*4882a593Smuzhiyun .len = 6
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun buf[0] = reg >> 8;
48*4882a593Smuzhiyun buf[1] = reg & 0xff;
49*4882a593Smuzhiyun buf[2] = val & 0xff;
50*4882a593Smuzhiyun buf[3] = (val >> 8) & 0xff;
51*4882a593Smuzhiyun buf[4] = (val >> 16) & 0xff;
52*4882a593Smuzhiyun buf[5] = val >> 24;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun ret = i2c_transfer(i2c, &msg, 1);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (ret != 1)
57*4882a593Smuzhiyun pr_err("%s: i2c write error!\n", __func__);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
i2c_av_read(struct i2c_adapter * i2c,u16 reg)60*4882a593Smuzhiyun static u8 i2c_av_read(struct i2c_adapter *i2c, u16 reg)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun int ret;
63*4882a593Smuzhiyun u8 buf[2];
64*4882a593Smuzhiyun struct i2c_msg msg = {
65*4882a593Smuzhiyun .addr = 0x88 >> 1,
66*4882a593Smuzhiyun .flags = 0,
67*4882a593Smuzhiyun .buf = buf,
68*4882a593Smuzhiyun .len = 2
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun buf[0] = reg >> 8;
72*4882a593Smuzhiyun buf[1] = reg & 0xff;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun ret = i2c_transfer(i2c, &msg, 1);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun if (ret != 1)
77*4882a593Smuzhiyun pr_err("%s: i2c write error!\n", __func__);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun msg.flags = I2C_M_RD;
80*4882a593Smuzhiyun msg.len = 1;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ret = i2c_transfer(i2c, &msg, 1);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun if (ret != 1)
85*4882a593Smuzhiyun pr_err("%s: i2c read error!\n", __func__);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return buf[0];
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
i2c_av_and_or(struct i2c_adapter * i2c,u16 reg,unsigned and_mask,u8 or_value)90*4882a593Smuzhiyun static void i2c_av_and_or(struct i2c_adapter *i2c, u16 reg, unsigned and_mask,
91*4882a593Smuzhiyun u8 or_value)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun i2c_av_write(i2c, reg, (i2c_av_read(i2c, reg) & and_mask) | or_value);
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun /* set 27MHz on AUX_CLK */
netup_initialize(struct cx23885_dev * dev)96*4882a593Smuzhiyun void netup_initialize(struct cx23885_dev *dev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun struct cx23885_i2c *i2c_bus = &dev->i2c_bus[2];
99*4882a593Smuzhiyun struct i2c_adapter *i2c = &i2c_bus->i2c_adap;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* Stop microcontroller */
102*4882a593Smuzhiyun i2c_av_and_or(i2c, 0x803, ~0x10, 0x00);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Aux PLL frac for 27 MHz */
105*4882a593Smuzhiyun i2c_av_write4(i2c, 0x114, 0xea0eb3);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Aux PLL int for 27 MHz */
108*4882a593Smuzhiyun i2c_av_write4(i2c, 0x110, 0x090319);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* start microcontroller */
111*4882a593Smuzhiyun i2c_av_and_or(i2c, 0x803, ~0x10, 0x10);
112*4882a593Smuzhiyun }
113