1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the Conexant CX23885 PCIe bridge
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/pci.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/kdev_t.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <media/v4l2-device.h>
16*4882a593Smuzhiyun #include <media/v4l2-fh.h>
17*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
18*4882a593Smuzhiyun #include <media/tuner.h>
19*4882a593Smuzhiyun #include <media/tveeprom.h>
20*4882a593Smuzhiyun #include <media/videobuf2-dma-sg.h>
21*4882a593Smuzhiyun #include <media/videobuf2-dvb.h>
22*4882a593Smuzhiyun #include <media/rc-core.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "cx23885-reg.h"
25*4882a593Smuzhiyun #include "media/drv-intf/cx2341x.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/mutex.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define CX23885_VERSION "0.0.4"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define UNSET (-1U)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define CX23885_MAXBOARDS 8
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Max number of inputs by card */
36*4882a593Smuzhiyun #define MAX_CX23885_INPUT 8
37*4882a593Smuzhiyun #define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define CX23885_BOARD_NOAUTO UNSET
42*4882a593Smuzhiyun #define CX23885_BOARD_UNKNOWN 0
43*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
44*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1800 2
45*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1250 3
46*4882a593Smuzhiyun #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
47*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
48*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1500 6
49*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1200 7
50*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1700 8
51*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1400 9
52*4882a593Smuzhiyun #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
53*4882a593Smuzhiyun #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
54*4882a593Smuzhiyun #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
55*4882a593Smuzhiyun #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
56*4882a593Smuzhiyun #define CX23885_BOARD_TBS_6920 14
57*4882a593Smuzhiyun #define CX23885_BOARD_TEVII_S470 15
58*4882a593Smuzhiyun #define CX23885_BOARD_DVBWORLD_2005 16
59*4882a593Smuzhiyun #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
60*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1270 18
61*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1275 19
62*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1255 20
63*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1210 21
64*4882a593Smuzhiyun #define CX23885_BOARD_MYGICA_X8506 22
65*4882a593Smuzhiyun #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
66*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1850 24
67*4882a593Smuzhiyun #define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
68*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1290 26
69*4882a593Smuzhiyun #define CX23885_BOARD_MYGICA_X8558PRO 27
70*4882a593Smuzhiyun #define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
71*4882a593Smuzhiyun #define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
72*4882a593Smuzhiyun #define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
73*4882a593Smuzhiyun #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
74*4882a593Smuzhiyun #define CX23885_BOARD_MPX885 32
75*4882a593Smuzhiyun #define CX23885_BOARD_MYGICA_X8507 33
76*4882a593Smuzhiyun #define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
77*4882a593Smuzhiyun #define CX23885_BOARD_TEVII_S471 35
78*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
79*4882a593Smuzhiyun #define CX23885_BOARD_PROF_8000 37
80*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR4400 38
81*4882a593Smuzhiyun #define CX23885_BOARD_AVERMEDIA_HC81R 39
82*4882a593Smuzhiyun #define CX23885_BOARD_TBS_6981 40
83*4882a593Smuzhiyun #define CX23885_BOARD_TBS_6980 41
84*4882a593Smuzhiyun #define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
85*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
86*4882a593Smuzhiyun #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44
87*4882a593Smuzhiyun #define CX23885_BOARD_DVBSKY_T9580 45
88*4882a593Smuzhiyun #define CX23885_BOARD_DVBSKY_T980C 46
89*4882a593Smuzhiyun #define CX23885_BOARD_DVBSKY_S950C 47
90*4882a593Smuzhiyun #define CX23885_BOARD_TT_CT2_4500_CI 48
91*4882a593Smuzhiyun #define CX23885_BOARD_DVBSKY_S950 49
92*4882a593Smuzhiyun #define CX23885_BOARD_DVBSKY_S952 50
93*4882a593Smuzhiyun #define CX23885_BOARD_DVBSKY_T982 51
94*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR5525 52
95*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_STARBURST 53
96*4882a593Smuzhiyun #define CX23885_BOARD_VIEWCAST_260E 54
97*4882a593Smuzhiyun #define CX23885_BOARD_VIEWCAST_460E 55
98*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB 56
99*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC 57
100*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_HVR1265_K4 58
101*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_STARBURST2 59
102*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_QUADHD_DVB_885 60
103*4882a593Smuzhiyun #define CX23885_BOARD_HAUPPAUGE_QUADHD_ATSC_885 61
104*4882a593Smuzhiyun #define CX23885_BOARD_AVERMEDIA_CE310B 62
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun #define GPIO_0 0x00000001
107*4882a593Smuzhiyun #define GPIO_1 0x00000002
108*4882a593Smuzhiyun #define GPIO_2 0x00000004
109*4882a593Smuzhiyun #define GPIO_3 0x00000008
110*4882a593Smuzhiyun #define GPIO_4 0x00000010
111*4882a593Smuzhiyun #define GPIO_5 0x00000020
112*4882a593Smuzhiyun #define GPIO_6 0x00000040
113*4882a593Smuzhiyun #define GPIO_7 0x00000080
114*4882a593Smuzhiyun #define GPIO_8 0x00000100
115*4882a593Smuzhiyun #define GPIO_9 0x00000200
116*4882a593Smuzhiyun #define GPIO_10 0x00000400
117*4882a593Smuzhiyun #define GPIO_11 0x00000800
118*4882a593Smuzhiyun #define GPIO_12 0x00001000
119*4882a593Smuzhiyun #define GPIO_13 0x00002000
120*4882a593Smuzhiyun #define GPIO_14 0x00004000
121*4882a593Smuzhiyun #define GPIO_15 0x00008000
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
124*4882a593Smuzhiyun #define CX23885_NORMS (\
125*4882a593Smuzhiyun V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
126*4882a593Smuzhiyun V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
127*4882a593Smuzhiyun V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
128*4882a593Smuzhiyun V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun struct cx23885_fmt {
131*4882a593Smuzhiyun u32 fourcc; /* v4l2 format id */
132*4882a593Smuzhiyun int depth;
133*4882a593Smuzhiyun int flags;
134*4882a593Smuzhiyun u32 cxformat;
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun struct cx23885_tvnorm {
138*4882a593Smuzhiyun char *name;
139*4882a593Smuzhiyun v4l2_std_id id;
140*4882a593Smuzhiyun u32 cxiformat;
141*4882a593Smuzhiyun u32 cxoformat;
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun enum cx23885_itype {
145*4882a593Smuzhiyun CX23885_VMUX_COMPOSITE1 = 1,
146*4882a593Smuzhiyun CX23885_VMUX_COMPOSITE2,
147*4882a593Smuzhiyun CX23885_VMUX_COMPOSITE3,
148*4882a593Smuzhiyun CX23885_VMUX_COMPOSITE4,
149*4882a593Smuzhiyun CX23885_VMUX_SVIDEO,
150*4882a593Smuzhiyun CX23885_VMUX_COMPONENT,
151*4882a593Smuzhiyun CX23885_VMUX_TELEVISION,
152*4882a593Smuzhiyun CX23885_VMUX_CABLE,
153*4882a593Smuzhiyun CX23885_VMUX_DVB,
154*4882a593Smuzhiyun CX23885_VMUX_DEBUG,
155*4882a593Smuzhiyun CX23885_RADIO,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun enum cx23885_src_sel_type {
159*4882a593Smuzhiyun CX23885_SRC_SEL_EXT_656_VIDEO = 0,
160*4882a593Smuzhiyun CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun struct cx23885_riscmem {
164*4882a593Smuzhiyun unsigned int size;
165*4882a593Smuzhiyun __le32 *cpu;
166*4882a593Smuzhiyun __le32 *jmp;
167*4882a593Smuzhiyun dma_addr_t dma;
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* buffer for one video frame */
171*4882a593Smuzhiyun struct cx23885_buffer {
172*4882a593Smuzhiyun /* common v4l buffer stuff -- must be first */
173*4882a593Smuzhiyun struct vb2_v4l2_buffer vb;
174*4882a593Smuzhiyun struct list_head queue;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun /* cx23885 specific */
177*4882a593Smuzhiyun unsigned int bpl;
178*4882a593Smuzhiyun struct cx23885_riscmem risc;
179*4882a593Smuzhiyun struct cx23885_fmt *fmt;
180*4882a593Smuzhiyun u32 count;
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun struct cx23885_input {
184*4882a593Smuzhiyun enum cx23885_itype type;
185*4882a593Smuzhiyun unsigned int vmux;
186*4882a593Smuzhiyun unsigned int amux;
187*4882a593Smuzhiyun u32 gpio0, gpio1, gpio2, gpio3;
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun typedef enum {
191*4882a593Smuzhiyun CX23885_MPEG_UNDEFINED = 0,
192*4882a593Smuzhiyun CX23885_MPEG_DVB,
193*4882a593Smuzhiyun CX23885_ANALOG_VIDEO,
194*4882a593Smuzhiyun CX23885_MPEG_ENCODER,
195*4882a593Smuzhiyun } port_t;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun struct cx23885_board {
198*4882a593Smuzhiyun char *name;
199*4882a593Smuzhiyun port_t porta, portb, portc;
200*4882a593Smuzhiyun int num_fds_portb, num_fds_portc;
201*4882a593Smuzhiyun unsigned int tuner_type;
202*4882a593Smuzhiyun unsigned int radio_type;
203*4882a593Smuzhiyun unsigned char tuner_addr;
204*4882a593Smuzhiyun unsigned char radio_addr;
205*4882a593Smuzhiyun unsigned int tuner_bus;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* Vendors can and do run the PCIe bridge at different
208*4882a593Smuzhiyun * clock rates, driven physically by crystals on the PCBs.
209*4882a593Smuzhiyun * The core has to accommodate this. This allows the user
210*4882a593Smuzhiyun * to add new boards with new frequencys. The value is
211*4882a593Smuzhiyun * expressed in Hz.
212*4882a593Smuzhiyun *
213*4882a593Smuzhiyun * The core framework will default this value based on
214*4882a593Smuzhiyun * current designs, but it can vary.
215*4882a593Smuzhiyun */
216*4882a593Smuzhiyun u32 clk_freq;
217*4882a593Smuzhiyun struct cx23885_input input[MAX_CX23885_INPUT];
218*4882a593Smuzhiyun int ci_type; /* for NetUP */
219*4882a593Smuzhiyun /* Force bottom field first during DMA (888 workaround) */
220*4882a593Smuzhiyun u32 force_bff;
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun struct cx23885_subid {
224*4882a593Smuzhiyun u16 subvendor;
225*4882a593Smuzhiyun u16 subdevice;
226*4882a593Smuzhiyun u32 card;
227*4882a593Smuzhiyun };
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun struct cx23885_i2c {
230*4882a593Smuzhiyun struct cx23885_dev *dev;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun int nr;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* i2c i/o */
235*4882a593Smuzhiyun struct i2c_adapter i2c_adap;
236*4882a593Smuzhiyun struct i2c_client i2c_client;
237*4882a593Smuzhiyun u32 i2c_rc;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /* 885 registers used for raw address */
240*4882a593Smuzhiyun u32 i2c_period;
241*4882a593Smuzhiyun u32 reg_ctrl;
242*4882a593Smuzhiyun u32 reg_stat;
243*4882a593Smuzhiyun u32 reg_addr;
244*4882a593Smuzhiyun u32 reg_rdata;
245*4882a593Smuzhiyun u32 reg_wdata;
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun struct cx23885_dmaqueue {
249*4882a593Smuzhiyun struct list_head active;
250*4882a593Smuzhiyun u32 count;
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun struct cx23885_tsport {
254*4882a593Smuzhiyun struct cx23885_dev *dev;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun unsigned nr;
257*4882a593Smuzhiyun int sram_chno;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun struct vb2_dvb_frontends frontends;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* dma queues */
262*4882a593Smuzhiyun struct cx23885_dmaqueue mpegq;
263*4882a593Smuzhiyun u32 ts_packet_size;
264*4882a593Smuzhiyun u32 ts_packet_count;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun int width;
267*4882a593Smuzhiyun int height;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun spinlock_t slock;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun /* registers */
272*4882a593Smuzhiyun u32 reg_gpcnt;
273*4882a593Smuzhiyun u32 reg_gpcnt_ctl;
274*4882a593Smuzhiyun u32 reg_dma_ctl;
275*4882a593Smuzhiyun u32 reg_lngth;
276*4882a593Smuzhiyun u32 reg_hw_sop_ctrl;
277*4882a593Smuzhiyun u32 reg_gen_ctrl;
278*4882a593Smuzhiyun u32 reg_bd_pkt_status;
279*4882a593Smuzhiyun u32 reg_sop_status;
280*4882a593Smuzhiyun u32 reg_fifo_ovfl_stat;
281*4882a593Smuzhiyun u32 reg_vld_misc;
282*4882a593Smuzhiyun u32 reg_ts_clk_en;
283*4882a593Smuzhiyun u32 reg_ts_int_msk;
284*4882a593Smuzhiyun u32 reg_ts_int_stat;
285*4882a593Smuzhiyun u32 reg_src_sel;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /* Default register vals */
288*4882a593Smuzhiyun int pci_irqmask;
289*4882a593Smuzhiyun u32 dma_ctl_val;
290*4882a593Smuzhiyun u32 ts_int_msk_val;
291*4882a593Smuzhiyun u32 gen_ctrl_val;
292*4882a593Smuzhiyun u32 ts_clk_en_val;
293*4882a593Smuzhiyun u32 src_sel_val;
294*4882a593Smuzhiyun u32 vld_misc_val;
295*4882a593Smuzhiyun u32 hw_sop_ctrl_val;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* Allow a single tsport to have multiple frontends */
298*4882a593Smuzhiyun u32 num_frontends;
299*4882a593Smuzhiyun void (*gate_ctrl)(struct cx23885_tsport *port, int open);
300*4882a593Smuzhiyun void *port_priv;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /* Workaround for a temp dvb_frontend that the tuner can attached to */
303*4882a593Smuzhiyun struct dvb_frontend analog_fe;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun struct i2c_client *i2c_client_demod;
306*4882a593Smuzhiyun struct i2c_client *i2c_client_tuner;
307*4882a593Smuzhiyun struct i2c_client *i2c_client_sec;
308*4882a593Smuzhiyun struct i2c_client *i2c_client_ci;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun int (*set_frontend)(struct dvb_frontend *fe);
311*4882a593Smuzhiyun int (*fe_set_voltage)(struct dvb_frontend *fe,
312*4882a593Smuzhiyun enum fe_sec_voltage voltage);
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun struct cx23885_kernel_ir {
316*4882a593Smuzhiyun struct cx23885_dev *cx;
317*4882a593Smuzhiyun char *name;
318*4882a593Smuzhiyun char *phys;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun struct rc_dev *rc;
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun struct cx23885_audio_buffer {
324*4882a593Smuzhiyun unsigned int bpl;
325*4882a593Smuzhiyun struct cx23885_riscmem risc;
326*4882a593Smuzhiyun void *vaddr;
327*4882a593Smuzhiyun struct scatterlist *sglist;
328*4882a593Smuzhiyun int sglen;
329*4882a593Smuzhiyun unsigned long nr_pages;
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun struct cx23885_audio_dev {
333*4882a593Smuzhiyun struct cx23885_dev *dev;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun struct pci_dev *pci;
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun struct snd_card *card;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun spinlock_t lock;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun atomic_t count;
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun unsigned int dma_size;
344*4882a593Smuzhiyun unsigned int period_size;
345*4882a593Smuzhiyun unsigned int num_periods;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun struct cx23885_audio_buffer *buf;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun struct snd_pcm_substream *substream;
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun struct cx23885_dev {
353*4882a593Smuzhiyun atomic_t refcount;
354*4882a593Smuzhiyun struct v4l2_device v4l2_dev;
355*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun /* pci stuff */
358*4882a593Smuzhiyun struct pci_dev *pci;
359*4882a593Smuzhiyun unsigned char pci_rev, pci_lat;
360*4882a593Smuzhiyun int pci_bus, pci_slot;
361*4882a593Smuzhiyun u32 __iomem *lmmio;
362*4882a593Smuzhiyun u8 __iomem *bmmio;
363*4882a593Smuzhiyun int pci_irqmask;
364*4882a593Smuzhiyun spinlock_t pci_irqmask_lock; /* protects mask reg too */
365*4882a593Smuzhiyun int hwrevision;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /* This valud is board specific and is used to configure the
368*4882a593Smuzhiyun * AV core so we see nice clean and stable video and audio. */
369*4882a593Smuzhiyun u32 clk_freq;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
372*4882a593Smuzhiyun struct cx23885_i2c i2c_bus[3];
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun int nr;
375*4882a593Smuzhiyun struct mutex lock;
376*4882a593Smuzhiyun struct mutex gpio_lock;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* board details */
379*4882a593Smuzhiyun unsigned int board;
380*4882a593Smuzhiyun char name[32];
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun struct cx23885_tsport ts1, ts2;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun /* sram configuration */
385*4882a593Smuzhiyun struct sram_channel *sram_channels;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun enum {
388*4882a593Smuzhiyun CX23885_BRIDGE_UNDEFINED = 0,
389*4882a593Smuzhiyun CX23885_BRIDGE_885 = 885,
390*4882a593Smuzhiyun CX23885_BRIDGE_887 = 887,
391*4882a593Smuzhiyun CX23885_BRIDGE_888 = 888,
392*4882a593Smuzhiyun } bridge;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun /* Analog video */
395*4882a593Smuzhiyun unsigned int input;
396*4882a593Smuzhiyun unsigned int audinput; /* Selectable audio input */
397*4882a593Smuzhiyun u32 tvaudio;
398*4882a593Smuzhiyun v4l2_std_id tvnorm;
399*4882a593Smuzhiyun unsigned int tuner_type;
400*4882a593Smuzhiyun unsigned char tuner_addr;
401*4882a593Smuzhiyun unsigned int tuner_bus;
402*4882a593Smuzhiyun unsigned int radio_type;
403*4882a593Smuzhiyun unsigned char radio_addr;
404*4882a593Smuzhiyun struct v4l2_subdev *sd_cx25840;
405*4882a593Smuzhiyun struct work_struct cx25840_work;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* Infrared */
408*4882a593Smuzhiyun struct v4l2_subdev *sd_ir;
409*4882a593Smuzhiyun struct work_struct ir_rx_work;
410*4882a593Smuzhiyun unsigned long ir_rx_notifications;
411*4882a593Smuzhiyun struct work_struct ir_tx_work;
412*4882a593Smuzhiyun unsigned long ir_tx_notifications;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun struct cx23885_kernel_ir *kernel_ir;
415*4882a593Smuzhiyun atomic_t ir_input_stopping;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun /* V4l */
418*4882a593Smuzhiyun u32 freq;
419*4882a593Smuzhiyun struct video_device *video_dev;
420*4882a593Smuzhiyun struct video_device *vbi_dev;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun /* video capture */
423*4882a593Smuzhiyun struct cx23885_fmt *fmt;
424*4882a593Smuzhiyun unsigned int width, height;
425*4882a593Smuzhiyun unsigned field;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun struct cx23885_dmaqueue vidq;
428*4882a593Smuzhiyun struct vb2_queue vb2_vidq;
429*4882a593Smuzhiyun struct cx23885_dmaqueue vbiq;
430*4882a593Smuzhiyun struct vb2_queue vb2_vbiq;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun spinlock_t slock;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun /* MPEG Encoder ONLY settings */
435*4882a593Smuzhiyun u32 cx23417_mailbox;
436*4882a593Smuzhiyun struct cx2341x_handler cxhdl;
437*4882a593Smuzhiyun struct video_device *v4l_device;
438*4882a593Smuzhiyun struct vb2_queue vb2_mpegq;
439*4882a593Smuzhiyun struct cx23885_tvnorm encodernorm;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun /* Analog raw audio */
442*4882a593Smuzhiyun struct cx23885_audio_dev *audio_dev;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun /* Does the system require periodic DMA resets? */
445*4882a593Smuzhiyun unsigned int need_dma_reset:1;
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun
to_cx23885(struct v4l2_device * v4l2_dev)448*4882a593Smuzhiyun static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun #define call_all(dev, o, f, args...) \
454*4882a593Smuzhiyun v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun #define CX23885_HW_888_IR (1 << 0)
457*4882a593Smuzhiyun #define CX23885_HW_AV_CORE (1 << 1)
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun #define call_hw(dev, grpid, o, f, args...) \
460*4882a593Smuzhiyun v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun #define SRAM_CH01 0 /* Video A */
465*4882a593Smuzhiyun #define SRAM_CH02 1 /* VBI A */
466*4882a593Smuzhiyun #define SRAM_CH03 2 /* Video B */
467*4882a593Smuzhiyun #define SRAM_CH04 3 /* Transport via B */
468*4882a593Smuzhiyun #define SRAM_CH05 4 /* VBI B */
469*4882a593Smuzhiyun #define SRAM_CH06 5 /* Video C */
470*4882a593Smuzhiyun #define SRAM_CH07 6 /* Transport via C */
471*4882a593Smuzhiyun #define SRAM_CH08 7 /* Audio Internal A */
472*4882a593Smuzhiyun #define SRAM_CH09 8 /* Audio Internal B */
473*4882a593Smuzhiyun #define SRAM_CH10 9 /* Audio External */
474*4882a593Smuzhiyun #define SRAM_CH11 10 /* COMB_3D_N */
475*4882a593Smuzhiyun #define SRAM_CH12 11 /* Comb 3D N1 */
476*4882a593Smuzhiyun #define SRAM_CH13 12 /* Comb 3D N2 */
477*4882a593Smuzhiyun #define SRAM_CH14 13 /* MOE Vid */
478*4882a593Smuzhiyun #define SRAM_CH15 14 /* MOE RSLT */
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun struct sram_channel {
481*4882a593Smuzhiyun char *name;
482*4882a593Smuzhiyun u32 cmds_start;
483*4882a593Smuzhiyun u32 ctrl_start;
484*4882a593Smuzhiyun u32 cdt;
485*4882a593Smuzhiyun u32 fifo_start;
486*4882a593Smuzhiyun u32 fifo_size;
487*4882a593Smuzhiyun u32 ptr1_reg;
488*4882a593Smuzhiyun u32 ptr2_reg;
489*4882a593Smuzhiyun u32 cnt1_reg;
490*4882a593Smuzhiyun u32 cnt2_reg;
491*4882a593Smuzhiyun u32 jumponly;
492*4882a593Smuzhiyun };
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun /* ----------------------------------------------------------- */
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun #define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
497*4882a593Smuzhiyun #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun #define cx_andor(reg, mask, value) \
500*4882a593Smuzhiyun writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
501*4882a593Smuzhiyun ((value) & (mask)), dev->lmmio+((reg)>>2))
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun #define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
504*4882a593Smuzhiyun #define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun /* ----------------------------------------------------------- */
507*4882a593Smuzhiyun /* cx23885-core.c */
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
510*4882a593Smuzhiyun struct sram_channel *ch,
511*4882a593Smuzhiyun unsigned int bpl, u32 risc);
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
514*4882a593Smuzhiyun struct sram_channel *ch);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun extern int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
517*4882a593Smuzhiyun struct scatterlist *sglist,
518*4882a593Smuzhiyun unsigned int top_offset, unsigned int bottom_offset,
519*4882a593Smuzhiyun unsigned int bpl, unsigned int padding, unsigned int lines);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
522*4882a593Smuzhiyun struct cx23885_riscmem *risc, struct scatterlist *sglist,
523*4882a593Smuzhiyun unsigned int top_offset, unsigned int bottom_offset,
524*4882a593Smuzhiyun unsigned int bpl, unsigned int padding, unsigned int lines);
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun int cx23885_start_dma(struct cx23885_tsport *port,
527*4882a593Smuzhiyun struct cx23885_dmaqueue *q,
528*4882a593Smuzhiyun struct cx23885_buffer *buf);
529*4882a593Smuzhiyun void cx23885_cancel_buffers(struct cx23885_tsport *port);
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
533*4882a593Smuzhiyun extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
534*4882a593Smuzhiyun extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
535*4882a593Smuzhiyun extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
536*4882a593Smuzhiyun int asoutput);
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
539*4882a593Smuzhiyun extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
540*4882a593Smuzhiyun extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
541*4882a593Smuzhiyun extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /* ----------------------------------------------------------- */
544*4882a593Smuzhiyun /* cx23885-cards.c */
545*4882a593Smuzhiyun extern struct cx23885_board cx23885_boards[];
546*4882a593Smuzhiyun extern const unsigned int cx23885_bcount;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun extern struct cx23885_subid cx23885_subids[];
549*4882a593Smuzhiyun extern const unsigned int cx23885_idcount;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun extern int cx23885_tuner_callback(void *priv, int component,
552*4882a593Smuzhiyun int command, int arg);
553*4882a593Smuzhiyun extern void cx23885_card_list(struct cx23885_dev *dev);
554*4882a593Smuzhiyun extern int cx23885_ir_init(struct cx23885_dev *dev);
555*4882a593Smuzhiyun extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
556*4882a593Smuzhiyun extern void cx23885_ir_fini(struct cx23885_dev *dev);
557*4882a593Smuzhiyun extern void cx23885_gpio_setup(struct cx23885_dev *dev);
558*4882a593Smuzhiyun extern void cx23885_card_setup(struct cx23885_dev *dev);
559*4882a593Smuzhiyun extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun extern int cx23885_dvb_register(struct cx23885_tsport *port);
562*4882a593Smuzhiyun extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun extern int cx23885_buf_prepare(struct cx23885_buffer *buf,
565*4882a593Smuzhiyun struct cx23885_tsport *port);
566*4882a593Smuzhiyun extern void cx23885_buf_queue(struct cx23885_tsport *port,
567*4882a593Smuzhiyun struct cx23885_buffer *buf);
568*4882a593Smuzhiyun extern void cx23885_free_buffer(struct cx23885_dev *dev,
569*4882a593Smuzhiyun struct cx23885_buffer *buf);
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun /* ----------------------------------------------------------- */
572*4882a593Smuzhiyun /* cx23885-video.c */
573*4882a593Smuzhiyun /* Video */
574*4882a593Smuzhiyun extern int cx23885_video_register(struct cx23885_dev *dev);
575*4882a593Smuzhiyun extern void cx23885_video_unregister(struct cx23885_dev *dev);
576*4882a593Smuzhiyun extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
577*4882a593Smuzhiyun extern void cx23885_video_wakeup(struct cx23885_dev *dev,
578*4882a593Smuzhiyun struct cx23885_dmaqueue *q, u32 count);
579*4882a593Smuzhiyun int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
580*4882a593Smuzhiyun int cx23885_set_input(struct file *file, void *priv, unsigned int i);
581*4882a593Smuzhiyun int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
582*4882a593Smuzhiyun int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
583*4882a593Smuzhiyun int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /* ----------------------------------------------------------- */
586*4882a593Smuzhiyun /* cx23885-vbi.c */
587*4882a593Smuzhiyun extern int cx23885_vbi_fmt(struct file *file, void *priv,
588*4882a593Smuzhiyun struct v4l2_format *f);
589*4882a593Smuzhiyun extern void cx23885_vbi_timeout(unsigned long data);
590*4882a593Smuzhiyun extern const struct vb2_ops cx23885_vbi_qops;
591*4882a593Smuzhiyun extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun /* cx23885-i2c.c */
594*4882a593Smuzhiyun extern int cx23885_i2c_register(struct cx23885_i2c *bus);
595*4882a593Smuzhiyun extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
596*4882a593Smuzhiyun extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun /* ----------------------------------------------------------- */
599*4882a593Smuzhiyun /* cx23885-417.c */
600*4882a593Smuzhiyun extern int cx23885_417_register(struct cx23885_dev *dev);
601*4882a593Smuzhiyun extern void cx23885_417_unregister(struct cx23885_dev *dev);
602*4882a593Smuzhiyun extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
603*4882a593Smuzhiyun extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
604*4882a593Smuzhiyun extern void cx23885_mc417_init(struct cx23885_dev *dev);
605*4882a593Smuzhiyun extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
606*4882a593Smuzhiyun extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
607*4882a593Smuzhiyun extern int mc417_register_read(struct cx23885_dev *dev,
608*4882a593Smuzhiyun u16 address, u32 *value);
609*4882a593Smuzhiyun extern int mc417_register_write(struct cx23885_dev *dev,
610*4882a593Smuzhiyun u16 address, u32 value);
611*4882a593Smuzhiyun extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
612*4882a593Smuzhiyun extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
613*4882a593Smuzhiyun extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun /* ----------------------------------------------------------- */
616*4882a593Smuzhiyun /* cx23885-alsa.c */
617*4882a593Smuzhiyun extern struct cx23885_audio_dev *cx23885_audio_register(
618*4882a593Smuzhiyun struct cx23885_dev *dev);
619*4882a593Smuzhiyun extern void cx23885_audio_unregister(struct cx23885_dev *dev);
620*4882a593Smuzhiyun extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
621*4882a593Smuzhiyun extern int cx23885_risc_databuffer(struct pci_dev *pci,
622*4882a593Smuzhiyun struct cx23885_riscmem *risc,
623*4882a593Smuzhiyun struct scatterlist *sglist,
624*4882a593Smuzhiyun unsigned int bpl,
625*4882a593Smuzhiyun unsigned int lines,
626*4882a593Smuzhiyun unsigned int lpi);
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun /* ----------------------------------------------------------- */
629*4882a593Smuzhiyun /* tv norms */
630*4882a593Smuzhiyun
norm_maxh(v4l2_std_id norm)631*4882a593Smuzhiyun static inline unsigned int norm_maxh(v4l2_std_id norm)
632*4882a593Smuzhiyun {
633*4882a593Smuzhiyun return (norm & V4L2_STD_525_60) ? 480 : 576;
634*4882a593Smuzhiyun }
635