1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * cimax2.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * CIMax2(R) SP2 driver in conjunction with NetUp Dual DVB-S2 CI card
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2009 NetUP Inc.
8*4882a593Smuzhiyun * Copyright (C) 2009 Igor M. Liplianin <liplianin@netup.ru>
9*4882a593Smuzhiyun * Copyright (C) 2009 Abylay Ospan <aospan@netup.ru>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "cx23885.h"
13*4882a593Smuzhiyun #include "cimax2.h"
14*4882a593Smuzhiyun #include <media/dvb_ca_en50221.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Max transfer size done by I2C transfer functions */
17*4882a593Smuzhiyun #define MAX_XFER_SIZE 64
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
20*4882a593Smuzhiyun bits 31-16
21*4882a593Smuzhiyun +-----------+
22*4882a593Smuzhiyun | Reserved |
23*4882a593Smuzhiyun +-----------+
24*4882a593Smuzhiyun bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
25*4882a593Smuzhiyun +-------+-------+-------+-------+-------+-------+-------+-------+
26*4882a593Smuzhiyun | WR# | RD# | | ACK# | ADHI | ADLO | CS1# | CS0# |
27*4882a593Smuzhiyun +-------+-------+-------+-------+-------+-------+-------+-------+
28*4882a593Smuzhiyun bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
29*4882a593Smuzhiyun +-------+-------+-------+-------+-------+-------+-------+-------+
30*4882a593Smuzhiyun | DATA7| DATA6| DATA5| DATA4| DATA3| DATA2| DATA1| DATA0|
31*4882a593Smuzhiyun +-------+-------+-------+-------+-------+-------+-------+-------+
32*4882a593Smuzhiyun ***/
33*4882a593Smuzhiyun /* MC417 */
34*4882a593Smuzhiyun #define NETUP_DATA 0x000000ff
35*4882a593Smuzhiyun #define NETUP_WR 0x00008000
36*4882a593Smuzhiyun #define NETUP_RD 0x00004000
37*4882a593Smuzhiyun #define NETUP_ACK 0x00001000
38*4882a593Smuzhiyun #define NETUP_ADHI 0x00000800
39*4882a593Smuzhiyun #define NETUP_ADLO 0x00000400
40*4882a593Smuzhiyun #define NETUP_CS1 0x00000200
41*4882a593Smuzhiyun #define NETUP_CS0 0x00000100
42*4882a593Smuzhiyun #define NETUP_EN_ALL 0x00001000
43*4882a593Smuzhiyun #define NETUP_CTRL_OFF (NETUP_CS1 | NETUP_CS0 | NETUP_WR | NETUP_RD)
44*4882a593Smuzhiyun #define NETUP_CI_CTL 0x04
45*4882a593Smuzhiyun #define NETUP_CI_RD 1
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define NETUP_IRQ_DETAM 0x1
48*4882a593Smuzhiyun #define NETUP_IRQ_IRQAM 0x4
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static unsigned int ci_dbg;
51*4882a593Smuzhiyun module_param(ci_dbg, int, 0644);
52*4882a593Smuzhiyun MODULE_PARM_DESC(ci_dbg, "Enable CI debugging");
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static unsigned int ci_irq_enable;
55*4882a593Smuzhiyun module_param(ci_irq_enable, int, 0644);
56*4882a593Smuzhiyun MODULE_PARM_DESC(ci_irq_enable, "Enable IRQ from CAM");
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define ci_dbg_print(fmt, args...) \
59*4882a593Smuzhiyun do { \
60*4882a593Smuzhiyun if (ci_dbg) \
61*4882a593Smuzhiyun printk(KERN_DEBUG pr_fmt("%s: " fmt), \
62*4882a593Smuzhiyun __func__, ##args); \
63*4882a593Smuzhiyun } while (0)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define ci_irq_flags() (ci_irq_enable ? NETUP_IRQ_IRQAM : 0)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* stores all private variables for communication with CI */
68*4882a593Smuzhiyun struct netup_ci_state {
69*4882a593Smuzhiyun struct dvb_ca_en50221 ca;
70*4882a593Smuzhiyun struct mutex ca_mutex;
71*4882a593Smuzhiyun struct i2c_adapter *i2c_adap;
72*4882a593Smuzhiyun u8 ci_i2c_addr;
73*4882a593Smuzhiyun int status;
74*4882a593Smuzhiyun struct work_struct work;
75*4882a593Smuzhiyun void *priv;
76*4882a593Smuzhiyun u8 current_irq_mode;
77*4882a593Smuzhiyun int current_ci_flag;
78*4882a593Smuzhiyun unsigned long next_status_checked_time;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun
netup_read_i2c(struct i2c_adapter * i2c_adap,u8 addr,u8 reg,u8 * buf,int len)82*4882a593Smuzhiyun static int netup_read_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
83*4882a593Smuzhiyun u8 *buf, int len)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun int ret;
86*4882a593Smuzhiyun struct i2c_msg msg[] = {
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun .addr = addr,
89*4882a593Smuzhiyun .flags = 0,
90*4882a593Smuzhiyun .buf = ®,
91*4882a593Smuzhiyun .len = 1
92*4882a593Smuzhiyun }, {
93*4882a593Smuzhiyun .addr = addr,
94*4882a593Smuzhiyun .flags = I2C_M_RD,
95*4882a593Smuzhiyun .buf = buf,
96*4882a593Smuzhiyun .len = len
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = i2c_transfer(i2c_adap, msg, 2);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (ret != 2) {
103*4882a593Smuzhiyun ci_dbg_print("%s: i2c read error, Reg = 0x%02x, Status = %d\n",
104*4882a593Smuzhiyun __func__, reg, ret);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return -1;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun ci_dbg_print("%s: i2c read Addr=0x%04x, Reg = 0x%02x, data = %02x\n",
110*4882a593Smuzhiyun __func__, addr, reg, buf[0]);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
netup_write_i2c(struct i2c_adapter * i2c_adap,u8 addr,u8 reg,u8 * buf,int len)115*4882a593Smuzhiyun static int netup_write_i2c(struct i2c_adapter *i2c_adap, u8 addr, u8 reg,
116*4882a593Smuzhiyun u8 *buf, int len)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun int ret;
119*4882a593Smuzhiyun u8 buffer[MAX_XFER_SIZE];
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun struct i2c_msg msg = {
122*4882a593Smuzhiyun .addr = addr,
123*4882a593Smuzhiyun .flags = 0,
124*4882a593Smuzhiyun .buf = &buffer[0],
125*4882a593Smuzhiyun .len = len + 1
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (1 + len > sizeof(buffer)) {
129*4882a593Smuzhiyun pr_warn("%s: i2c wr reg=%04x: len=%d is too big!\n",
130*4882a593Smuzhiyun KBUILD_MODNAME, reg, len);
131*4882a593Smuzhiyun return -EINVAL;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun buffer[0] = reg;
135*4882a593Smuzhiyun memcpy(&buffer[1], buf, len);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun ret = i2c_transfer(i2c_adap, &msg, 1);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (ret != 1) {
140*4882a593Smuzhiyun ci_dbg_print("%s: i2c write error, Reg=[0x%02x], Status=%d\n",
141*4882a593Smuzhiyun __func__, reg, ret);
142*4882a593Smuzhiyun return -1;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return 0;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
netup_ci_get_mem(struct cx23885_dev * dev)148*4882a593Smuzhiyun static int netup_ci_get_mem(struct cx23885_dev *dev)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun int mem;
151*4882a593Smuzhiyun unsigned long timeout = jiffies + msecs_to_jiffies(1);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun for (;;) {
154*4882a593Smuzhiyun mem = cx_read(MC417_RWD);
155*4882a593Smuzhiyun if ((mem & NETUP_ACK) == 0)
156*4882a593Smuzhiyun break;
157*4882a593Smuzhiyun if (time_after(jiffies, timeout))
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun udelay(1);
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun cx_set(MC417_RWD, NETUP_CTRL_OFF);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return mem & 0xff;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
netup_ci_op_cam(struct dvb_ca_en50221 * en50221,int slot,u8 flag,u8 read,int addr,u8 data)167*4882a593Smuzhiyun static int netup_ci_op_cam(struct dvb_ca_en50221 *en50221, int slot,
168*4882a593Smuzhiyun u8 flag, u8 read, int addr, u8 data)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun struct netup_ci_state *state = en50221->data;
171*4882a593Smuzhiyun struct cx23885_tsport *port = state->priv;
172*4882a593Smuzhiyun struct cx23885_dev *dev = port->dev;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun u8 store;
175*4882a593Smuzhiyun int mem;
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun if (0 != slot)
179*4882a593Smuzhiyun return -EINVAL;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (state->current_ci_flag != flag) {
182*4882a593Smuzhiyun ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
183*4882a593Smuzhiyun 0, &store, 1);
184*4882a593Smuzhiyun if (ret != 0)
185*4882a593Smuzhiyun return ret;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun store &= ~0x0c;
188*4882a593Smuzhiyun store |= flag;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
191*4882a593Smuzhiyun 0, &store, 1);
192*4882a593Smuzhiyun if (ret != 0)
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun state->current_ci_flag = flag;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun mutex_lock(&dev->gpio_lock);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* write addr */
200*4882a593Smuzhiyun cx_write(MC417_OEN, NETUP_EN_ALL);
201*4882a593Smuzhiyun cx_write(MC417_RWD, NETUP_CTRL_OFF |
202*4882a593Smuzhiyun NETUP_ADLO | (0xff & addr));
203*4882a593Smuzhiyun cx_clear(MC417_RWD, NETUP_ADLO);
204*4882a593Smuzhiyun cx_write(MC417_RWD, NETUP_CTRL_OFF |
205*4882a593Smuzhiyun NETUP_ADHI | (0xff & (addr >> 8)));
206*4882a593Smuzhiyun cx_clear(MC417_RWD, NETUP_ADHI);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun if (read) { /* data in */
209*4882a593Smuzhiyun cx_write(MC417_OEN, NETUP_EN_ALL | NETUP_DATA);
210*4882a593Smuzhiyun } else /* data out */
211*4882a593Smuzhiyun cx_write(MC417_RWD, NETUP_CTRL_OFF | data);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun /* choose chip */
214*4882a593Smuzhiyun cx_clear(MC417_RWD,
215*4882a593Smuzhiyun (state->ci_i2c_addr == 0x40) ? NETUP_CS0 : NETUP_CS1);
216*4882a593Smuzhiyun /* read/write */
217*4882a593Smuzhiyun cx_clear(MC417_RWD, (read) ? NETUP_RD : NETUP_WR);
218*4882a593Smuzhiyun mem = netup_ci_get_mem(dev);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun mutex_unlock(&dev->gpio_lock);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun if (!read)
223*4882a593Smuzhiyun if (mem < 0)
224*4882a593Smuzhiyun return -EREMOTEIO;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun ci_dbg_print("%s: %s: chipaddr=[0x%x] addr=[0x%02x], %s=%x\n", __func__,
227*4882a593Smuzhiyun (read) ? "read" : "write", state->ci_i2c_addr, addr,
228*4882a593Smuzhiyun (flag == NETUP_CI_CTL) ? "ctl" : "mem",
229*4882a593Smuzhiyun (read) ? mem : data);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun if (read)
232*4882a593Smuzhiyun return mem;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
netup_ci_read_attribute_mem(struct dvb_ca_en50221 * en50221,int slot,int addr)237*4882a593Smuzhiyun int netup_ci_read_attribute_mem(struct dvb_ca_en50221 *en50221,
238*4882a593Smuzhiyun int slot, int addr)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun return netup_ci_op_cam(en50221, slot, 0, NETUP_CI_RD, addr, 0);
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
netup_ci_write_attribute_mem(struct dvb_ca_en50221 * en50221,int slot,int addr,u8 data)243*4882a593Smuzhiyun int netup_ci_write_attribute_mem(struct dvb_ca_en50221 *en50221,
244*4882a593Smuzhiyun int slot, int addr, u8 data)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun return netup_ci_op_cam(en50221, slot, 0, 0, addr, data);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
netup_ci_read_cam_ctl(struct dvb_ca_en50221 * en50221,int slot,u8 addr)249*4882a593Smuzhiyun int netup_ci_read_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
250*4882a593Smuzhiyun u8 addr)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL,
253*4882a593Smuzhiyun NETUP_CI_RD, addr, 0);
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
netup_ci_write_cam_ctl(struct dvb_ca_en50221 * en50221,int slot,u8 addr,u8 data)256*4882a593Smuzhiyun int netup_ci_write_cam_ctl(struct dvb_ca_en50221 *en50221, int slot,
257*4882a593Smuzhiyun u8 addr, u8 data)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun return netup_ci_op_cam(en50221, slot, NETUP_CI_CTL, 0, addr, data);
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
netup_ci_slot_reset(struct dvb_ca_en50221 * en50221,int slot)262*4882a593Smuzhiyun int netup_ci_slot_reset(struct dvb_ca_en50221 *en50221, int slot)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun struct netup_ci_state *state = en50221->data;
265*4882a593Smuzhiyun u8 buf = 0x80;
266*4882a593Smuzhiyun int ret;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun if (0 != slot)
269*4882a593Smuzhiyun return -EINVAL;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun udelay(500);
272*4882a593Smuzhiyun ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
273*4882a593Smuzhiyun 0, &buf, 1);
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun if (ret != 0)
276*4882a593Smuzhiyun return ret;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun udelay(500);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun buf = 0x00;
281*4882a593Smuzhiyun ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
282*4882a593Smuzhiyun 0, &buf, 1);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun msleep(1000);
285*4882a593Smuzhiyun dvb_ca_en50221_camready_irq(&state->ca, 0);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
netup_ci_slot_shutdown(struct dvb_ca_en50221 * en50221,int slot)291*4882a593Smuzhiyun int netup_ci_slot_shutdown(struct dvb_ca_en50221 *en50221, int slot)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun /* not implemented */
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
netup_ci_set_irq(struct dvb_ca_en50221 * en50221,u8 irq_mode)297*4882a593Smuzhiyun static int netup_ci_set_irq(struct dvb_ca_en50221 *en50221, u8 irq_mode)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct netup_ci_state *state = en50221->data;
300*4882a593Smuzhiyun int ret;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun if (irq_mode == state->current_irq_mode)
303*4882a593Smuzhiyun return 0;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun ci_dbg_print("%s: chipaddr=[0x%x] setting ci IRQ to [0x%x] \n",
306*4882a593Smuzhiyun __func__, state->ci_i2c_addr, irq_mode);
307*4882a593Smuzhiyun ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
308*4882a593Smuzhiyun 0x1b, &irq_mode, 1);
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun if (ret != 0)
311*4882a593Smuzhiyun return ret;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun state->current_irq_mode = irq_mode;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun return 0;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
netup_ci_slot_ts_ctl(struct dvb_ca_en50221 * en50221,int slot)318*4882a593Smuzhiyun int netup_ci_slot_ts_ctl(struct dvb_ca_en50221 *en50221, int slot)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun struct netup_ci_state *state = en50221->data;
321*4882a593Smuzhiyun u8 buf;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun if (0 != slot)
324*4882a593Smuzhiyun return -EINVAL;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
327*4882a593Smuzhiyun 0, &buf, 1);
328*4882a593Smuzhiyun buf |= 0x60;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
331*4882a593Smuzhiyun 0, &buf, 1);
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* work handler */
netup_read_ci_status(struct work_struct * work)335*4882a593Smuzhiyun static void netup_read_ci_status(struct work_struct *work)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun struct netup_ci_state *state =
338*4882a593Smuzhiyun container_of(work, struct netup_ci_state, work);
339*4882a593Smuzhiyun u8 buf[33];
340*4882a593Smuzhiyun int ret;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun /* CAM module IRQ processing. fast operation */
343*4882a593Smuzhiyun dvb_ca_en50221_frda_irq(&state->ca, 0);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /* CAM module INSERT/REMOVE processing. slow operation because of i2c
346*4882a593Smuzhiyun * transfers */
347*4882a593Smuzhiyun if (time_after(jiffies, state->next_status_checked_time)
348*4882a593Smuzhiyun || !state->status) {
349*4882a593Smuzhiyun ret = netup_read_i2c(state->i2c_adap, state->ci_i2c_addr,
350*4882a593Smuzhiyun 0, &buf[0], 33);
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun state->next_status_checked_time = jiffies
353*4882a593Smuzhiyun + msecs_to_jiffies(1000);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun if (ret != 0)
356*4882a593Smuzhiyun return;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun ci_dbg_print("%s: Slot Status Addr=[0x%04x], Reg=[0x%02x], data=%02x, TS config = %02x\n",
359*4882a593Smuzhiyun __func__, state->ci_i2c_addr, 0, buf[0], buf[0]);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun if (buf[0] & 1)
363*4882a593Smuzhiyun state->status = DVB_CA_EN50221_POLL_CAM_PRESENT |
364*4882a593Smuzhiyun DVB_CA_EN50221_POLL_CAM_READY;
365*4882a593Smuzhiyun else
366*4882a593Smuzhiyun state->status = 0;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun /* CI irq handler */
netup_ci_slot_status(struct cx23885_dev * dev,u32 pci_status)371*4882a593Smuzhiyun int netup_ci_slot_status(struct cx23885_dev *dev, u32 pci_status)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun struct cx23885_tsport *port = NULL;
374*4882a593Smuzhiyun struct netup_ci_state *state = NULL;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun ci_dbg_print("%s:\n", __func__);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (0 == (pci_status & (PCI_MSK_GPIO0 | PCI_MSK_GPIO1)))
379*4882a593Smuzhiyun return 0;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun if (pci_status & PCI_MSK_GPIO0) {
382*4882a593Smuzhiyun port = &dev->ts1;
383*4882a593Smuzhiyun state = port->port_priv;
384*4882a593Smuzhiyun schedule_work(&state->work);
385*4882a593Smuzhiyun ci_dbg_print("%s: Wakeup CI0\n", __func__);
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (pci_status & PCI_MSK_GPIO1) {
389*4882a593Smuzhiyun port = &dev->ts2;
390*4882a593Smuzhiyun state = port->port_priv;
391*4882a593Smuzhiyun schedule_work(&state->work);
392*4882a593Smuzhiyun ci_dbg_print("%s: Wakeup CI1\n", __func__);
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun return 1;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
netup_poll_ci_slot_status(struct dvb_ca_en50221 * en50221,int slot,int open)398*4882a593Smuzhiyun int netup_poll_ci_slot_status(struct dvb_ca_en50221 *en50221,
399*4882a593Smuzhiyun int slot, int open)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct netup_ci_state *state = en50221->data;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun if (0 != slot)
404*4882a593Smuzhiyun return -EINVAL;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun netup_ci_set_irq(en50221, open ? (NETUP_IRQ_DETAM | ci_irq_flags())
407*4882a593Smuzhiyun : NETUP_IRQ_DETAM);
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun return state->status;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
netup_ci_init(struct cx23885_tsport * port)412*4882a593Smuzhiyun int netup_ci_init(struct cx23885_tsport *port)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun struct netup_ci_state *state;
415*4882a593Smuzhiyun u8 cimax_init[34] = {
416*4882a593Smuzhiyun 0x00, /* module A control*/
417*4882a593Smuzhiyun 0x00, /* auto select mask high A */
418*4882a593Smuzhiyun 0x00, /* auto select mask low A */
419*4882a593Smuzhiyun 0x00, /* auto select pattern high A */
420*4882a593Smuzhiyun 0x00, /* auto select pattern low A */
421*4882a593Smuzhiyun 0x44, /* memory access time A */
422*4882a593Smuzhiyun 0x00, /* invert input A */
423*4882a593Smuzhiyun 0x00, /* RFU */
424*4882a593Smuzhiyun 0x00, /* RFU */
425*4882a593Smuzhiyun 0x00, /* module B control*/
426*4882a593Smuzhiyun 0x00, /* auto select mask high B */
427*4882a593Smuzhiyun 0x00, /* auto select mask low B */
428*4882a593Smuzhiyun 0x00, /* auto select pattern high B */
429*4882a593Smuzhiyun 0x00, /* auto select pattern low B */
430*4882a593Smuzhiyun 0x44, /* memory access time B */
431*4882a593Smuzhiyun 0x00, /* invert input B */
432*4882a593Smuzhiyun 0x00, /* RFU */
433*4882a593Smuzhiyun 0x00, /* RFU */
434*4882a593Smuzhiyun 0x00, /* auto select mask high Ext */
435*4882a593Smuzhiyun 0x00, /* auto select mask low Ext */
436*4882a593Smuzhiyun 0x00, /* auto select pattern high Ext */
437*4882a593Smuzhiyun 0x00, /* auto select pattern low Ext */
438*4882a593Smuzhiyun 0x00, /* RFU */
439*4882a593Smuzhiyun 0x02, /* destination - module A */
440*4882a593Smuzhiyun 0x01, /* power on (use it like store place) */
441*4882a593Smuzhiyun 0x00, /* RFU */
442*4882a593Smuzhiyun 0x00, /* int status read only */
443*4882a593Smuzhiyun ci_irq_flags() | NETUP_IRQ_DETAM, /* DETAM, IRQAM unmasked */
444*4882a593Smuzhiyun 0x05, /* EXTINT=active-high, INT=push-pull */
445*4882a593Smuzhiyun 0x00, /* USCG1 */
446*4882a593Smuzhiyun 0x04, /* ack active low */
447*4882a593Smuzhiyun 0x00, /* LOCK = 0 */
448*4882a593Smuzhiyun 0x33, /* serial mode, rising in, rising out, MSB first*/
449*4882a593Smuzhiyun 0x31, /* synchronization */
450*4882a593Smuzhiyun };
451*4882a593Smuzhiyun int ret;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun ci_dbg_print("%s\n", __func__);
454*4882a593Smuzhiyun state = kzalloc(sizeof(struct netup_ci_state), GFP_KERNEL);
455*4882a593Smuzhiyun if (!state) {
456*4882a593Smuzhiyun ci_dbg_print("%s: Unable create CI structure!\n", __func__);
457*4882a593Smuzhiyun ret = -ENOMEM;
458*4882a593Smuzhiyun goto err;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun port->port_priv = state;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun switch (port->nr) {
464*4882a593Smuzhiyun case 1:
465*4882a593Smuzhiyun state->ci_i2c_addr = 0x40;
466*4882a593Smuzhiyun break;
467*4882a593Smuzhiyun case 2:
468*4882a593Smuzhiyun state->ci_i2c_addr = 0x41;
469*4882a593Smuzhiyun break;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun state->i2c_adap = &port->dev->i2c_bus[0].i2c_adap;
473*4882a593Smuzhiyun state->ca.owner = THIS_MODULE;
474*4882a593Smuzhiyun state->ca.read_attribute_mem = netup_ci_read_attribute_mem;
475*4882a593Smuzhiyun state->ca.write_attribute_mem = netup_ci_write_attribute_mem;
476*4882a593Smuzhiyun state->ca.read_cam_control = netup_ci_read_cam_ctl;
477*4882a593Smuzhiyun state->ca.write_cam_control = netup_ci_write_cam_ctl;
478*4882a593Smuzhiyun state->ca.slot_reset = netup_ci_slot_reset;
479*4882a593Smuzhiyun state->ca.slot_shutdown = netup_ci_slot_shutdown;
480*4882a593Smuzhiyun state->ca.slot_ts_enable = netup_ci_slot_ts_ctl;
481*4882a593Smuzhiyun state->ca.poll_slot_status = netup_poll_ci_slot_status;
482*4882a593Smuzhiyun state->ca.data = state;
483*4882a593Smuzhiyun state->priv = port;
484*4882a593Smuzhiyun state->current_irq_mode = ci_irq_flags() | NETUP_IRQ_DETAM;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun ret = netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
487*4882a593Smuzhiyun 0, &cimax_init[0], 34);
488*4882a593Smuzhiyun /* lock registers */
489*4882a593Smuzhiyun ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
490*4882a593Smuzhiyun 0x1f, &cimax_init[0x18], 1);
491*4882a593Smuzhiyun /* power on slots */
492*4882a593Smuzhiyun ret |= netup_write_i2c(state->i2c_adap, state->ci_i2c_addr,
493*4882a593Smuzhiyun 0x18, &cimax_init[0x18], 1);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun if (0 != ret)
496*4882a593Smuzhiyun goto err;
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun ret = dvb_ca_en50221_init(&port->frontends.adapter,
499*4882a593Smuzhiyun &state->ca,
500*4882a593Smuzhiyun /* flags */ 0,
501*4882a593Smuzhiyun /* n_slots */ 1);
502*4882a593Smuzhiyun if (0 != ret)
503*4882a593Smuzhiyun goto err;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun INIT_WORK(&state->work, netup_read_ci_status);
506*4882a593Smuzhiyun schedule_work(&state->work);
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun ci_dbg_print("%s: CI initialized!\n", __func__);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun return 0;
511*4882a593Smuzhiyun err:
512*4882a593Smuzhiyun ci_dbg_print("%s: Cannot initialize CI: Error %d.\n", __func__, ret);
513*4882a593Smuzhiyun kfree(state);
514*4882a593Smuzhiyun return ret;
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
netup_ci_exit(struct cx23885_tsport * port)517*4882a593Smuzhiyun void netup_ci_exit(struct cx23885_tsport *port)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun struct netup_ci_state *state;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun if (NULL == port)
522*4882a593Smuzhiyun return;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun state = (struct netup_ci_state *)port->port_priv;
525*4882a593Smuzhiyun if (NULL == state)
526*4882a593Smuzhiyun return;
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun if (NULL == state->ca.data)
529*4882a593Smuzhiyun return;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun dvb_ca_en50221_release(&state->ca);
532*4882a593Smuzhiyun kfree(state);
533*4882a593Smuzhiyun }
534