1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * cx18 header containing common defines. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef CX23418_H 9*4882a593Smuzhiyun #define CX23418_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <media/drv-intf/cx2341x.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define MGR_CMD_MASK 0x40000000 14*4882a593Smuzhiyun /* The MSB of the command code indicates that this is the completion of a 15*4882a593Smuzhiyun command */ 16*4882a593Smuzhiyun #define MGR_CMD_MASK_ACK (MGR_CMD_MASK | 0x80000000) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* Description: This command creates a new instance of a certain task 19*4882a593Smuzhiyun IN[0] - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is 20*4882a593Smuzhiyun the processor on which the task YYY will be created 21*4882a593Smuzhiyun OUT[0] - Task handle. This handle is passed along with commands to 22*4882a593Smuzhiyun dispatch to the right instance of the task 23*4882a593Smuzhiyun ReturnCode - One of the ERR_SYS_... */ 24*4882a593Smuzhiyun #define CX18_CREATE_TASK (MGR_CMD_MASK | 0x0001) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Description: This command destroys an instance of a task 27*4882a593Smuzhiyun IN[0] - Task handle. Hanlde of the task to destroy 28*4882a593Smuzhiyun ReturnCode - One of the ERR_SYS_... */ 29*4882a593Smuzhiyun #define CX18_DESTROY_TASK (MGR_CMD_MASK | 0x0002) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* All commands for CPU have the following mask set */ 32*4882a593Smuzhiyun #define CPU_CMD_MASK 0x20000000 33*4882a593Smuzhiyun #define CPU_CMD_MASK_DEBUG (CPU_CMD_MASK | 0x00000000) 34*4882a593Smuzhiyun #define CPU_CMD_MASK_ACK (CPU_CMD_MASK | 0x80000000) 35*4882a593Smuzhiyun #define CPU_CMD_MASK_CAPTURE (CPU_CMD_MASK | 0x00020000) 36*4882a593Smuzhiyun #define CPU_CMD_MASK_TS (CPU_CMD_MASK | 0x00040000) 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define EPU_CMD_MASK 0x02000000 39*4882a593Smuzhiyun #define EPU_CMD_MASK_DEBUG (EPU_CMD_MASK | 0x000000) 40*4882a593Smuzhiyun #define EPU_CMD_MASK_DE (EPU_CMD_MASK | 0x040000) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define APU_CMD_MASK 0x10000000 43*4882a593Smuzhiyun #define APU_CMD_MASK_ACK (APU_CMD_MASK | 0x80000000) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CX18_APU_ENCODING_METHOD_MPEG (0 << 28) 46*4882a593Smuzhiyun #define CX18_APU_ENCODING_METHOD_AC3 (1 << 28) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Description: Command APU to start audio 49*4882a593Smuzhiyun IN[0] - audio parameters (same as CX18_CPU_SET_AUDIO_PARAMETERS?) 50*4882a593Smuzhiyun IN[1] - caller buffer address, or 0 51*4882a593Smuzhiyun ReturnCode - ??? */ 52*4882a593Smuzhiyun #define CX18_APU_START (APU_CMD_MASK | 0x01) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Description: Command APU to stop audio 55*4882a593Smuzhiyun IN[0] - encoding method to stop 56*4882a593Smuzhiyun ReturnCode - ??? */ 57*4882a593Smuzhiyun #define CX18_APU_STOP (APU_CMD_MASK | 0x02) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Description: Command APU to reset the AI 60*4882a593Smuzhiyun ReturnCode - ??? */ 61*4882a593Smuzhiyun #define CX18_APU_RESETAI (APU_CMD_MASK | 0x05) 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* Description: This command indicates that a Memory Descriptor List has been 64*4882a593Smuzhiyun filled with the requested channel type 65*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task 66*4882a593Smuzhiyun IN[1] - Offset of the MDL_ACK from the beginning of the local DDR. 67*4882a593Smuzhiyun IN[2] - Number of CNXT_MDL_ACK structures in the array pointed to by IN[1] 68*4882a593Smuzhiyun ReturnCode - One of the ERR_DE_... */ 69*4882a593Smuzhiyun #define CX18_EPU_DMA_DONE (EPU_CMD_MASK_DE | 0x0001) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Something interesting happened 72*4882a593Smuzhiyun IN[0] - A value to log 73*4882a593Smuzhiyun IN[1] - An offset of a string in the MiniMe memory; 74*4882a593Smuzhiyun 0/zero/NULL means "I have nothing to say" */ 75*4882a593Smuzhiyun #define CX18_EPU_DEBUG (EPU_CMD_MASK_DEBUG | 0x0003) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Reads memory/registers (32-bit) 78*4882a593Smuzhiyun IN[0] - Address 79*4882a593Smuzhiyun OUT[1] - Value */ 80*4882a593Smuzhiyun #define CX18_CPU_DEBUG_PEEK32 (CPU_CMD_MASK_DEBUG | 0x0003) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Description: This command starts streaming with the set channel type 83*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to start 84*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 85*4882a593Smuzhiyun #define CX18_CPU_CAPTURE_START (CPU_CMD_MASK_CAPTURE | 0x0002) 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* Description: This command stops streaming with the set channel type 88*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to stop 89*4882a593Smuzhiyun IN[1] - 0 = stop at end of GOP, 1 = stop at end of frame (MPEG only) 90*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 91*4882a593Smuzhiyun #define CX18_CPU_CAPTURE_STOP (CPU_CMD_MASK_CAPTURE | 0x0003) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Description: This command pauses streaming with the set channel type 94*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to pause 95*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 96*4882a593Smuzhiyun #define CX18_CPU_CAPTURE_PAUSE (CPU_CMD_MASK_CAPTURE | 0x0007) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Description: This command resumes streaming with the set channel type 99*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to resume 100*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 101*4882a593Smuzhiyun #define CX18_CPU_CAPTURE_RESUME (CPU_CMD_MASK_CAPTURE | 0x0008) 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_NONE 0 104*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_MPEG 1 105*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_INDEX 2 106*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_YUV 3 107*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_PCM 4 108*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_VBI 5 109*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_SLICED_VBI 6 110*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_TS 7 111*4882a593Smuzhiyun #define CAPTURE_CHANNEL_TYPE_MAX 15 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* Description: This command sets the channel type. This can only be done 114*4882a593Smuzhiyun when stopped. 115*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to start 116*4882a593Smuzhiyun IN[1] - Channel Type. See Below. 117*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 118*4882a593Smuzhiyun #define CX18_CPU_SET_CHANNEL_TYPE (CPU_CMD_MASK_CAPTURE + 1) 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* Description: Set stream output type 121*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 122*4882a593Smuzhiyun IN[1] - type 123*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 124*4882a593Smuzhiyun #define CX18_CPU_SET_STREAM_OUTPUT_TYPE (CPU_CMD_MASK_CAPTURE | 0x0012) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* Description: Set video input resolution and frame rate 127*4882a593Smuzhiyun IN[0] - task handle 128*4882a593Smuzhiyun IN[1] - reserved 129*4882a593Smuzhiyun IN[2] - reserved 130*4882a593Smuzhiyun IN[3] - reserved 131*4882a593Smuzhiyun IN[4] - reserved 132*4882a593Smuzhiyun IN[5] - frame rate, 0 - 29.97f/s, 1 - 25f/s 133*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 134*4882a593Smuzhiyun #define CX18_CPU_SET_VIDEO_IN (CPU_CMD_MASK_CAPTURE | 0x0004) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Description: Set video frame rate 137*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 138*4882a593Smuzhiyun IN[1] - video bit rate mode 139*4882a593Smuzhiyun IN[2] - video average rate 140*4882a593Smuzhiyun IN[3] - video peak rate 141*4882a593Smuzhiyun IN[4] - system mux rate 142*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 143*4882a593Smuzhiyun #define CX18_CPU_SET_VIDEO_RATE (CPU_CMD_MASK_CAPTURE | 0x0005) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun /* Description: Set video output resolution 146*4882a593Smuzhiyun IN[0] - task handle 147*4882a593Smuzhiyun IN[1] - horizontal size 148*4882a593Smuzhiyun IN[2] - vertical size 149*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 150*4882a593Smuzhiyun #define CX18_CPU_SET_VIDEO_RESOLUTION (CPU_CMD_MASK_CAPTURE | 0x0006) 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* Description: This command set filter parameters 153*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task 154*4882a593Smuzhiyun IN[1] - type, 0 - temporal, 1 - spatial, 2 - median 155*4882a593Smuzhiyun IN[2] - mode, temporal/spatial: 0 - disable, 1 - static, 2 - dynamic 156*4882a593Smuzhiyun median: 0 = disable, 1 = horizontal, 2 = vertical, 157*4882a593Smuzhiyun 3 = horizontal/vertical, 4 = diagonal 158*4882a593Smuzhiyun IN[3] - strength, temporal 0 - 31, spatial 0 - 15 159*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 160*4882a593Smuzhiyun #define CX18_CPU_SET_FILTER_PARAM (CPU_CMD_MASK_CAPTURE | 0x0009) 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* Description: This command set spatial filter type 163*4882a593Smuzhiyun IN[0] - Task handle. 164*4882a593Smuzhiyun IN[1] - luma type: 0 = disable, 1 = 1D horizontal only, 2 = 1D vertical only, 165*4882a593Smuzhiyun 3 = 2D H/V separable, 4 = 2D symmetric non-separable 166*4882a593Smuzhiyun IN[2] - chroma type: 0 - disable, 1 = 1D horizontal 167*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 168*4882a593Smuzhiyun #define CX18_CPU_SET_SPATIAL_FILTER_TYPE (CPU_CMD_MASK_CAPTURE | 0x000C) 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* Description: This command set coring levels for median filter 171*4882a593Smuzhiyun IN[0] - Task handle. 172*4882a593Smuzhiyun IN[1] - luma_high 173*4882a593Smuzhiyun IN[2] - luma_low 174*4882a593Smuzhiyun IN[3] - chroma_high 175*4882a593Smuzhiyun IN[4] - chroma_low 176*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 177*4882a593Smuzhiyun #define CX18_CPU_SET_MEDIAN_CORING (CPU_CMD_MASK_CAPTURE | 0x000E) 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* Description: This command set the picture type mask for index file 180*4882a593Smuzhiyun IN[0] - Task handle (ignored by firmware) 181*4882a593Smuzhiyun IN[1] - 0 = disable index file output 182*4882a593Smuzhiyun 1 = output I picture 183*4882a593Smuzhiyun 2 = P picture 184*4882a593Smuzhiyun 4 = B picture 185*4882a593Smuzhiyun other = illegal */ 186*4882a593Smuzhiyun #define CX18_CPU_SET_INDEXTABLE (CPU_CMD_MASK_CAPTURE | 0x0010) 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* Description: Set audio parameters 189*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 190*4882a593Smuzhiyun IN[1] - audio parameter 191*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 192*4882a593Smuzhiyun #define CX18_CPU_SET_AUDIO_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0011) 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* Description: Set video mute 195*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 196*4882a593Smuzhiyun IN[1] - bit31-24: muteYvalue 197*4882a593Smuzhiyun bit23-16: muteUvalue 198*4882a593Smuzhiyun bit15-8: muteVvalue 199*4882a593Smuzhiyun bit0: 1:mute, 0: unmute 200*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 201*4882a593Smuzhiyun #define CX18_CPU_SET_VIDEO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0013) 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Description: Set audio mute 204*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 205*4882a593Smuzhiyun IN[1] - mute/unmute 206*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 207*4882a593Smuzhiyun #define CX18_CPU_SET_AUDIO_MUTE (CPU_CMD_MASK_CAPTURE | 0x0014) 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* Description: Set stream output type 210*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 211*4882a593Smuzhiyun IN[1] - subType 212*4882a593Smuzhiyun SET_INITIAL_SCR 1 213*4882a593Smuzhiyun SET_QUALITY_MODE 2 214*4882a593Smuzhiyun SET_VIM_PROTECT_MODE 3 215*4882a593Smuzhiyun SET_PTS_CORRECTION 4 216*4882a593Smuzhiyun SET_USB_FLUSH_MODE 5 217*4882a593Smuzhiyun SET_MERAQPAR_ENABLE 6 218*4882a593Smuzhiyun SET_NAV_PACK_INSERTION 7 219*4882a593Smuzhiyun SET_SCENE_CHANGE_ENABLE 8 220*4882a593Smuzhiyun IN[2] - parameter 1 221*4882a593Smuzhiyun IN[3] - parameter 2 222*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 223*4882a593Smuzhiyun #define CX18_CPU_SET_MISC_PARAMETERS (CPU_CMD_MASK_CAPTURE | 0x0015) 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun /* Description: Set raw VBI parameters 226*4882a593Smuzhiyun IN[0] - Task handle 227*4882a593Smuzhiyun IN[1] - No. of input lines per field: 228*4882a593Smuzhiyun bit[15:0]: field 1, 229*4882a593Smuzhiyun bit[31:16]: field 2 230*4882a593Smuzhiyun IN[2] - No. of input bytes per line 231*4882a593Smuzhiyun IN[3] - No. of output frames per transfer 232*4882a593Smuzhiyun IN[4] - start code 233*4882a593Smuzhiyun IN[5] - stop code 234*4882a593Smuzhiyun ReturnCode */ 235*4882a593Smuzhiyun #define CX18_CPU_SET_RAW_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0016) 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* Description: Set capture line No. 238*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 239*4882a593Smuzhiyun IN[1] - height1 240*4882a593Smuzhiyun IN[2] - height2 241*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 242*4882a593Smuzhiyun #define CX18_CPU_SET_CAPTURE_LINE_NO (CPU_CMD_MASK_CAPTURE | 0x0017) 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* Description: Set copyright 245*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 246*4882a593Smuzhiyun IN[1] - copyright 247*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 248*4882a593Smuzhiyun #define CX18_CPU_SET_COPYRIGHT (CPU_CMD_MASK_CAPTURE | 0x0018) 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun /* Description: Set audio PID 251*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 252*4882a593Smuzhiyun IN[1] - PID 253*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 254*4882a593Smuzhiyun #define CX18_CPU_SET_AUDIO_PID (CPU_CMD_MASK_CAPTURE | 0x0019) 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun /* Description: Set video PID 257*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 258*4882a593Smuzhiyun IN[1] - PID 259*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 260*4882a593Smuzhiyun #define CX18_CPU_SET_VIDEO_PID (CPU_CMD_MASK_CAPTURE | 0x001A) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun /* Description: Set Vertical Crop Line 263*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 264*4882a593Smuzhiyun IN[1] - Line 265*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 266*4882a593Smuzhiyun #define CX18_CPU_SET_VER_CROP_LINE (CPU_CMD_MASK_CAPTURE | 0x001B) 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* Description: Set COP structure 269*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 270*4882a593Smuzhiyun IN[1] - M 271*4882a593Smuzhiyun IN[2] - N 272*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 273*4882a593Smuzhiyun #define CX18_CPU_SET_GOP_STRUCTURE (CPU_CMD_MASK_CAPTURE | 0x001C) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* Description: Set Scene Change Detection 276*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 277*4882a593Smuzhiyun IN[1] - scene change 278*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 279*4882a593Smuzhiyun #define CX18_CPU_SET_SCENE_CHANGE_DETECTION (CPU_CMD_MASK_CAPTURE | 0x001D) 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* Description: Set Aspect Ratio 282*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 283*4882a593Smuzhiyun IN[1] - AspectRatio 284*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 285*4882a593Smuzhiyun #define CX18_CPU_SET_ASPECT_RATIO (CPU_CMD_MASK_CAPTURE | 0x001E) 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* Description: Set Skip Input Frame 288*4882a593Smuzhiyun IN[0] - task handle. Handle of the task to start 289*4882a593Smuzhiyun IN[1] - skip input frames 290*4882a593Smuzhiyun ReturnCode - One of the ERR_CAPTURE_... */ 291*4882a593Smuzhiyun #define CX18_CPU_SET_SKIP_INPUT_FRAME (CPU_CMD_MASK_CAPTURE | 0x001F) 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun /* Description: Set sliced VBI parameters - 294*4882a593Smuzhiyun Note This API will only apply to MPEG and Sliced VBI Channels 295*4882a593Smuzhiyun IN[0] - Task handle 296*4882a593Smuzhiyun IN[1] - output type, 0 - CC, 1 - Moji, 2 - Teletext 297*4882a593Smuzhiyun IN[2] - start / stop line 298*4882a593Smuzhiyun bit[15:0] start line number 299*4882a593Smuzhiyun bit[31:16] stop line number 300*4882a593Smuzhiyun IN[3] - number of output frames per interrupt 301*4882a593Smuzhiyun IN[4] - VBI insertion mode 302*4882a593Smuzhiyun bit 0: output user data, 1 - enable 303*4882a593Smuzhiyun bit 1: output private stream, 1 - enable 304*4882a593Smuzhiyun bit 2: mux option, 0 - in GOP, 1 - in picture 305*4882a593Smuzhiyun bit[7:0] private stream ID 306*4882a593Smuzhiyun IN[5] - insertion period while mux option is in picture 307*4882a593Smuzhiyun ReturnCode - VBI data offset */ 308*4882a593Smuzhiyun #define CX18_CPU_SET_SLICED_VBI_PARAM (CPU_CMD_MASK_CAPTURE | 0x0020) 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* Description: Set the user data place holder 311*4882a593Smuzhiyun IN[0] - type of data (0 for user) 312*4882a593Smuzhiyun IN[1] - Stuffing period 313*4882a593Smuzhiyun IN[2] - ID data size in word (less than 10) 314*4882a593Smuzhiyun IN[3] - Pointer to ID buffer */ 315*4882a593Smuzhiyun #define CX18_CPU_SET_USERDATA_PLACE_HOLDER (CPU_CMD_MASK_CAPTURE | 0x0021) 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun /* Description: 319*4882a593Smuzhiyun In[0] Task Handle 320*4882a593Smuzhiyun return parameter: 321*4882a593Smuzhiyun Out[0] Reserved 322*4882a593Smuzhiyun Out[1] Video PTS bit[32:2] of last output video frame. 323*4882a593Smuzhiyun Out[2] Video PTS bit[ 1:0] of last output video frame. 324*4882a593Smuzhiyun Out[3] Hardware Video PTS counter bit[31:0], 325*4882a593Smuzhiyun these bits get incremented on every 90kHz clock tick. 326*4882a593Smuzhiyun Out[4] Hardware Video PTS counter bit32, 327*4882a593Smuzhiyun these bits get incremented on every 90kHz clock tick. 328*4882a593Smuzhiyun ReturnCode */ 329*4882a593Smuzhiyun #define CX18_CPU_GET_ENC_PTS (CPU_CMD_MASK_CAPTURE | 0x0022) 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* Description: Set VFC parameters 332*4882a593Smuzhiyun IN[0] - task handle 333*4882a593Smuzhiyun IN[1] - VFC enable flag, 1 - enable, 0 - disable 334*4882a593Smuzhiyun */ 335*4882a593Smuzhiyun #define CX18_CPU_SET_VFC_PARAM (CPU_CMD_MASK_CAPTURE | 0x0023) 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun /* Below is the list of commands related to the data exchange */ 338*4882a593Smuzhiyun #define CPU_CMD_MASK_DE (CPU_CMD_MASK | 0x040000) 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* Description: This command provides the physical base address of the local 341*4882a593Smuzhiyun DDR as viewed by EPU 342*4882a593Smuzhiyun IN[0] - Physical offset where EPU has the local DDR mapped 343*4882a593Smuzhiyun ReturnCode - One of the ERR_DE_... */ 344*4882a593Smuzhiyun #define CPU_CMD_DE_SetBase (CPU_CMD_MASK_DE | 0x0001) 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun /* Description: This command provides the offsets in the device memory where 347*4882a593Smuzhiyun the 2 cx18_mdl_ack blocks reside 348*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to start 349*4882a593Smuzhiyun IN[1] - Offset of the first cx18_mdl_ack from the beginning of the 350*4882a593Smuzhiyun local DDR. 351*4882a593Smuzhiyun IN[2] - Offset of the second cx18_mdl_ack from the beginning of the 352*4882a593Smuzhiyun local DDR. 353*4882a593Smuzhiyun ReturnCode - One of the ERR_DE_... */ 354*4882a593Smuzhiyun #define CX18_CPU_DE_SET_MDL_ACK (CPU_CMD_MASK_DE | 0x0002) 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* Description: This command provides the offset to a Memory Descriptor List 357*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to start 358*4882a593Smuzhiyun IN[1] - Offset of the MDL from the beginning of the local DDR. 359*4882a593Smuzhiyun IN[2] - Number of cx18_mdl_ent structures in the array pointed to by IN[1] 360*4882a593Smuzhiyun IN[3] - Buffer ID 361*4882a593Smuzhiyun IN[4] - Total buffer length 362*4882a593Smuzhiyun ReturnCode - One of the ERR_DE_... */ 363*4882a593Smuzhiyun #define CX18_CPU_DE_SET_MDL (CPU_CMD_MASK_DE | 0x0005) 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun /* Description: This command requests return of all current Memory 366*4882a593Smuzhiyun Descriptor Lists to the driver 367*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task to start 368*4882a593Smuzhiyun ReturnCode - One of the ERR_DE_... */ 369*4882a593Smuzhiyun #define CX18_CPU_DE_RELEASE_MDL (CPU_CMD_MASK_DE | 0x0006) 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun /* Description: This command signals the cpu that the dat buffer has been 372*4882a593Smuzhiyun consumed and ready for re-use. 373*4882a593Smuzhiyun IN[0] - Task handle. Handle of the task 374*4882a593Smuzhiyun IN[1] - Offset of the data block from the beginning of the local DDR. 375*4882a593Smuzhiyun IN[2] - Number of bytes in the data block 376*4882a593Smuzhiyun ReturnCode - One of the ERR_DE_... */ 377*4882a593Smuzhiyun /* #define CX18_CPU_DE_RELEASE_BUFFER (CPU_CMD_MASK_DE | 0x0007) */ 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* No Error / Success */ 380*4882a593Smuzhiyun #define CNXT_OK 0x000000 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun /* Received unknown command */ 383*4882a593Smuzhiyun #define CXERR_UNK_CMD 0x000001 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun /* First parameter in the command is invalid */ 386*4882a593Smuzhiyun #define CXERR_INVALID_PARAM1 0x000002 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun /* Second parameter in the command is invalid */ 389*4882a593Smuzhiyun #define CXERR_INVALID_PARAM2 0x000003 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun /* Device interface is not open/found */ 392*4882a593Smuzhiyun #define CXERR_DEV_NOT_FOUND 0x000004 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun /* Requested function is not implemented/available */ 395*4882a593Smuzhiyun #define CXERR_NOTSUPPORTED 0x000005 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun /* Invalid pointer is provided */ 398*4882a593Smuzhiyun #define CXERR_BADPTR 0x000006 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun /* Unable to allocate memory */ 401*4882a593Smuzhiyun #define CXERR_NOMEM 0x000007 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun /* Object/Link not found */ 404*4882a593Smuzhiyun #define CXERR_LINK 0x000008 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun /* Device busy, command cannot be executed */ 407*4882a593Smuzhiyun #define CXERR_BUSY 0x000009 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun /* File/device/handle is not open. */ 410*4882a593Smuzhiyun #define CXERR_NOT_OPEN 0x00000A 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun /* Value is out of range */ 413*4882a593Smuzhiyun #define CXERR_OUTOFRANGE 0x00000B 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun /* Buffer overflow */ 416*4882a593Smuzhiyun #define CXERR_OVERFLOW 0x00000C 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun /* Version mismatch */ 419*4882a593Smuzhiyun #define CXERR_BADVER 0x00000D 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun /* Operation timed out */ 422*4882a593Smuzhiyun #define CXERR_TIMEOUT 0x00000E 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun /* Operation aborted */ 425*4882a593Smuzhiyun #define CXERR_ABORT 0x00000F 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun /* Specified I2C device not found for read/write */ 428*4882a593Smuzhiyun #define CXERR_I2CDEV_NOTFOUND 0x000010 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun /* Error in I2C data xfer (but I2C device is present) */ 431*4882a593Smuzhiyun #define CXERR_I2CDEV_XFERERR 0x000011 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun /* Channel changing component not ready */ 434*4882a593Smuzhiyun #define CXERR_CHANNELNOTREADY 0x000012 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun /* PPU (Presensation/Decoder) mail box is corrupted */ 437*4882a593Smuzhiyun #define CXERR_PPU_MB_CORRUPT 0x000013 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun /* CPU (Capture/Encoder) mail box is corrupted */ 440*4882a593Smuzhiyun #define CXERR_CPU_MB_CORRUPT 0x000014 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun /* APU (Audio) mail box is corrupted */ 443*4882a593Smuzhiyun #define CXERR_APU_MB_CORRUPT 0x000015 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun /* Unable to open file for reading */ 446*4882a593Smuzhiyun #define CXERR_FILE_OPEN_READ 0x000016 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun /* Unable to open file for writing */ 449*4882a593Smuzhiyun #define CXERR_FILE_OPEN_WRITE 0x000017 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun /* Unable to find the I2C section specified */ 452*4882a593Smuzhiyun #define CXERR_I2C_BADSECTION 0x000018 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun /* Error in I2C data xfer (but I2C device is present) */ 455*4882a593Smuzhiyun #define CXERR_I2CDEV_DATALOW 0x000019 456*4882a593Smuzhiyun 457*4882a593Smuzhiyun /* Error in I2C data xfer (but I2C device is present) */ 458*4882a593Smuzhiyun #define CXERR_I2CDEV_CLOCKLOW 0x00001A 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /* No Interrupt received from HW (for I2C access) */ 461*4882a593Smuzhiyun #define CXERR_NO_HW_I2C_INTR 0x00001B 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun /* RPU is not ready to accept commands! */ 464*4882a593Smuzhiyun #define CXERR_RPU_NOT_READY 0x00001C 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun /* RPU is not ready to accept commands! */ 467*4882a593Smuzhiyun #define CXERR_RPU_NO_ACK 0x00001D 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun /* The are no buffers ready. Try again soon! */ 470*4882a593Smuzhiyun #define CXERR_NODATA_AGAIN 0x00001E 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun /* The stream is stopping. Function not allowed now! */ 473*4882a593Smuzhiyun #define CXERR_STOPPING_STATUS 0x00001F 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun /* Trying to access hardware when the power is turned OFF */ 476*4882a593Smuzhiyun #define CXERR_DEVPOWER_OFF 0x000020 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun #endif /* CX23418_H */ 479