1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * cx18 System Control Block initialization
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6*4882a593Smuzhiyun * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "cx18-driver.h"
10*4882a593Smuzhiyun #include "cx18-io.h"
11*4882a593Smuzhiyun #include "cx18-scb.h"
12*4882a593Smuzhiyun
cx18_init_scb(struct cx18 * cx)13*4882a593Smuzhiyun void cx18_init_scb(struct cx18 *cx)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun cx18_setup_page(cx, SCB_OFFSET);
16*4882a593Smuzhiyun cx18_memset_io(cx, cx->scb, 0, 0x10000);
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_CPU, &cx->scb->apu2cpu_irq);
19*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_APU_ACK, &cx->scb->cpu2apu_irq_ack);
20*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_CPU, &cx->scb->hpu2cpu_irq);
21*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_HPU_ACK, &cx->scb->cpu2hpu_irq_ack);
22*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_CPU, &cx->scb->ppu2cpu_irq);
23*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_PPU_ACK, &cx->scb->cpu2ppu_irq_ack);
24*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_CPU, &cx->scb->epu2cpu_irq);
25*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_EPU_ACK, &cx->scb->cpu2epu_irq_ack);
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_APU, &cx->scb->cpu2apu_irq);
28*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_CPU_ACK, &cx->scb->apu2cpu_irq_ack);
29*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_APU, &cx->scb->hpu2apu_irq);
30*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_HPU_ACK, &cx->scb->apu2hpu_irq_ack);
31*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_APU, &cx->scb->ppu2apu_irq);
32*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_PPU_ACK, &cx->scb->apu2ppu_irq_ack);
33*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_APU, &cx->scb->epu2apu_irq);
34*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_EPU_ACK, &cx->scb->apu2epu_irq_ack);
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_HPU, &cx->scb->cpu2hpu_irq);
37*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_CPU_ACK, &cx->scb->hpu2cpu_irq_ack);
38*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_HPU, &cx->scb->apu2hpu_irq);
39*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_APU_ACK, &cx->scb->hpu2apu_irq_ack);
40*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_HPU, &cx->scb->ppu2hpu_irq);
41*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_PPU_ACK, &cx->scb->hpu2ppu_irq_ack);
42*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_HPU, &cx->scb->epu2hpu_irq);
43*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_EPU_ACK, &cx->scb->hpu2epu_irq_ack);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_PPU, &cx->scb->cpu2ppu_irq);
46*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_CPU_ACK, &cx->scb->ppu2cpu_irq_ack);
47*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_PPU, &cx->scb->apu2ppu_irq);
48*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_APU_ACK, &cx->scb->ppu2apu_irq_ack);
49*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_PPU, &cx->scb->hpu2ppu_irq);
50*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_HPU_ACK, &cx->scb->ppu2hpu_irq_ack);
51*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_PPU, &cx->scb->epu2ppu_irq);
52*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_EPU_ACK, &cx->scb->ppu2epu_irq_ack);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun cx18_writel(cx, IRQ_CPU_TO_EPU, &cx->scb->cpu2epu_irq);
55*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_CPU_ACK, &cx->scb->epu2cpu_irq_ack);
56*4882a593Smuzhiyun cx18_writel(cx, IRQ_APU_TO_EPU, &cx->scb->apu2epu_irq);
57*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_APU_ACK, &cx->scb->epu2apu_irq_ack);
58*4882a593Smuzhiyun cx18_writel(cx, IRQ_HPU_TO_EPU, &cx->scb->hpu2epu_irq);
59*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_HPU_ACK, &cx->scb->epu2hpu_irq_ack);
60*4882a593Smuzhiyun cx18_writel(cx, IRQ_PPU_TO_EPU, &cx->scb->ppu2epu_irq);
61*4882a593Smuzhiyun cx18_writel(cx, IRQ_EPU_TO_PPU_ACK, &cx->scb->epu2ppu_irq_ack);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2cpu_mb),
64*4882a593Smuzhiyun &cx->scb->apu2cpu_mb_offset);
65*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2cpu_mb),
66*4882a593Smuzhiyun &cx->scb->hpu2cpu_mb_offset);
67*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2cpu_mb),
68*4882a593Smuzhiyun &cx->scb->ppu2cpu_mb_offset);
69*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2cpu_mb),
70*4882a593Smuzhiyun &cx->scb->epu2cpu_mb_offset);
71*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2apu_mb),
72*4882a593Smuzhiyun &cx->scb->cpu2apu_mb_offset);
73*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2apu_mb),
74*4882a593Smuzhiyun &cx->scb->hpu2apu_mb_offset);
75*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2apu_mb),
76*4882a593Smuzhiyun &cx->scb->ppu2apu_mb_offset);
77*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2apu_mb),
78*4882a593Smuzhiyun &cx->scb->epu2apu_mb_offset);
79*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2hpu_mb),
80*4882a593Smuzhiyun &cx->scb->cpu2hpu_mb_offset);
81*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2hpu_mb),
82*4882a593Smuzhiyun &cx->scb->apu2hpu_mb_offset);
83*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2hpu_mb),
84*4882a593Smuzhiyun &cx->scb->ppu2hpu_mb_offset);
85*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2hpu_mb),
86*4882a593Smuzhiyun &cx->scb->epu2hpu_mb_offset);
87*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2ppu_mb),
88*4882a593Smuzhiyun &cx->scb->cpu2ppu_mb_offset);
89*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2ppu_mb),
90*4882a593Smuzhiyun &cx->scb->apu2ppu_mb_offset);
91*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2ppu_mb),
92*4882a593Smuzhiyun &cx->scb->hpu2ppu_mb_offset);
93*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, epu2ppu_mb),
94*4882a593Smuzhiyun &cx->scb->epu2ppu_mb_offset);
95*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu2epu_mb),
96*4882a593Smuzhiyun &cx->scb->cpu2epu_mb_offset);
97*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, apu2epu_mb),
98*4882a593Smuzhiyun &cx->scb->apu2epu_mb_offset);
99*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, hpu2epu_mb),
100*4882a593Smuzhiyun &cx->scb->hpu2epu_mb_offset);
101*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, ppu2epu_mb),
102*4882a593Smuzhiyun &cx->scb->ppu2epu_mb_offset);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun cx18_writel(cx, SCB_OFFSET + offsetof(struct cx18_scb, cpu_state),
105*4882a593Smuzhiyun &cx->scb->ipc_offset);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun cx18_writel(cx, 1, &cx->scb->epu_state);
108*4882a593Smuzhiyun }
109