1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * cx18 interrupt handling
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6*4882a593Smuzhiyun * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "cx18-driver.h"
10*4882a593Smuzhiyun #include "cx18-io.h"
11*4882a593Smuzhiyun #include "cx18-irq.h"
12*4882a593Smuzhiyun #include "cx18-mailbox.h"
13*4882a593Smuzhiyun #include "cx18-scb.h"
14*4882a593Smuzhiyun
xpu_ack(struct cx18 * cx,u32 sw2)15*4882a593Smuzhiyun static void xpu_ack(struct cx18 *cx, u32 sw2)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun if (sw2 & IRQ_CPU_TO_EPU_ACK)
18*4882a593Smuzhiyun wake_up(&cx->mb_cpu_waitq);
19*4882a593Smuzhiyun if (sw2 & IRQ_APU_TO_EPU_ACK)
20*4882a593Smuzhiyun wake_up(&cx->mb_apu_waitq);
21*4882a593Smuzhiyun }
22*4882a593Smuzhiyun
epu_cmd(struct cx18 * cx,u32 sw1)23*4882a593Smuzhiyun static void epu_cmd(struct cx18 *cx, u32 sw1)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun if (sw1 & IRQ_CPU_TO_EPU)
26*4882a593Smuzhiyun cx18_api_epu_cmd_irq(cx, CPU);
27*4882a593Smuzhiyun if (sw1 & IRQ_APU_TO_EPU)
28*4882a593Smuzhiyun cx18_api_epu_cmd_irq(cx, APU);
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
cx18_irq_handler(int irq,void * dev_id)31*4882a593Smuzhiyun irqreturn_t cx18_irq_handler(int irq, void *dev_id)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct cx18 *cx = (struct cx18 *)dev_id;
34*4882a593Smuzhiyun u32 sw1, sw2, hw2;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask;
37*4882a593Smuzhiyun sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask;
38*4882a593Smuzhiyun hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & cx->hw2_irq_mask;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun if (sw1)
41*4882a593Smuzhiyun cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
42*4882a593Smuzhiyun if (sw2)
43*4882a593Smuzhiyun cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
44*4882a593Smuzhiyun if (hw2)
45*4882a593Smuzhiyun cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun if (sw1 || sw2 || hw2)
48*4882a593Smuzhiyun CX18_DEBUG_HI_IRQ("received interrupts SW1: %x SW2: %x HW2: %x\n",
49*4882a593Smuzhiyun sw1, sw2, hw2);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * SW1 responses have to happen first. The sending XPU times out the
53*4882a593Smuzhiyun * incoming mailboxes on us rather rapidly.
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun if (sw1)
56*4882a593Smuzhiyun epu_cmd(cx, sw1);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* To do: interrupt-based I2C handling
59*4882a593Smuzhiyun if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (sw2)
64*4882a593Smuzhiyun xpu_ack(cx, sw2);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
67*4882a593Smuzhiyun }
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