1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * cx18 driver PCI memory mapped IO access routines
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
6*4882a593Smuzhiyun * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "cx18-driver.h"
10*4882a593Smuzhiyun #include "cx18-io.h"
11*4882a593Smuzhiyun #include "cx18-irq.h"
12*4882a593Smuzhiyun
cx18_memset_io(struct cx18 * cx,void __iomem * addr,int val,size_t count)13*4882a593Smuzhiyun void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun u8 __iomem *dst = addr;
16*4882a593Smuzhiyun u16 val2 = val | (val << 8);
17*4882a593Smuzhiyun u32 val4 = val2 | (val2 << 16);
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* Align writes on the CX23418's addresses */
20*4882a593Smuzhiyun if ((count > 0) && ((unsigned long)dst & 1)) {
21*4882a593Smuzhiyun cx18_writeb(cx, (u8) val, dst);
22*4882a593Smuzhiyun count--;
23*4882a593Smuzhiyun dst++;
24*4882a593Smuzhiyun }
25*4882a593Smuzhiyun if ((count > 1) && ((unsigned long)dst & 2)) {
26*4882a593Smuzhiyun cx18_writew(cx, val2, dst);
27*4882a593Smuzhiyun count -= 2;
28*4882a593Smuzhiyun dst += 2;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun while (count > 3) {
31*4882a593Smuzhiyun cx18_writel(cx, val4, dst);
32*4882a593Smuzhiyun count -= 4;
33*4882a593Smuzhiyun dst += 4;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun if (count > 1) {
36*4882a593Smuzhiyun cx18_writew(cx, val2, dst);
37*4882a593Smuzhiyun count -= 2;
38*4882a593Smuzhiyun dst += 2;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun if (count > 0)
41*4882a593Smuzhiyun cx18_writeb(cx, (u8) val, dst);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
cx18_sw1_irq_enable(struct cx18 * cx,u32 val)44*4882a593Smuzhiyun void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
47*4882a593Smuzhiyun cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
48*4882a593Smuzhiyun cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
cx18_sw1_irq_disable(struct cx18 * cx,u32 val)51*4882a593Smuzhiyun void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
54*4882a593Smuzhiyun cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
cx18_sw2_irq_enable(struct cx18 * cx,u32 val)57*4882a593Smuzhiyun void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
60*4882a593Smuzhiyun cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
61*4882a593Smuzhiyun cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
cx18_sw2_irq_disable(struct cx18 * cx,u32 val)64*4882a593Smuzhiyun void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
67*4882a593Smuzhiyun cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
cx18_sw2_irq_disable_cpu(struct cx18 * cx,u32 val)70*4882a593Smuzhiyun void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun u32 r;
73*4882a593Smuzhiyun r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
74*4882a593Smuzhiyun cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
cx18_setup_page(struct cx18 * cx,u32 addr)77*4882a593Smuzhiyun void cx18_setup_page(struct cx18 *cx, u32 addr)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun u32 val;
80*4882a593Smuzhiyun val = cx18_read_reg(cx, 0xD000F8);
81*4882a593Smuzhiyun val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
82*4882a593Smuzhiyun cx18_write_reg(cx, val, 0xD000F8);
83*4882a593Smuzhiyun }
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