1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * cx18 driver internal defines and structures
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Derived from ivtv-driver.h
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
8*4882a593Smuzhiyun * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef CX18_DRIVER_H
12*4882a593Smuzhiyun #define CX18_DRIVER_H
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/moduleparam.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/sched/signal.h>
19*4882a593Smuzhiyun #include <linux/fs.h>
20*4882a593Smuzhiyun #include <linux/pci.h>
21*4882a593Smuzhiyun #include <linux/interrupt.h>
22*4882a593Smuzhiyun #include <linux/spinlock.h>
23*4882a593Smuzhiyun #include <linux/i2c.h>
24*4882a593Smuzhiyun #include <linux/i2c-algo-bit.h>
25*4882a593Smuzhiyun #include <linux/list.h>
26*4882a593Smuzhiyun #include <linux/unistd.h>
27*4882a593Smuzhiyun #include <linux/pagemap.h>
28*4882a593Smuzhiyun #include <linux/workqueue.h>
29*4882a593Smuzhiyun #include <linux/mutex.h>
30*4882a593Smuzhiyun #include <linux/slab.h>
31*4882a593Smuzhiyun #include <asm/byteorder.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <media/v4l2-common.h>
34*4882a593Smuzhiyun #include <media/v4l2-ioctl.h>
35*4882a593Smuzhiyun #include <media/v4l2-device.h>
36*4882a593Smuzhiyun #include <media/v4l2-fh.h>
37*4882a593Smuzhiyun #include <media/tuner.h>
38*4882a593Smuzhiyun #include <media/i2c/ir-kbd-i2c.h>
39*4882a593Smuzhiyun #include "cx18-mailbox.h"
40*4882a593Smuzhiyun #include "cx18-av-core.h"
41*4882a593Smuzhiyun #include "cx23418.h"
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* DVB */
44*4882a593Smuzhiyun #include <media/demux.h>
45*4882a593Smuzhiyun #include <media/dmxdev.h>
46*4882a593Smuzhiyun #include <media/dvb_demux.h>
47*4882a593Smuzhiyun #include <media/dvb_frontend.h>
48*4882a593Smuzhiyun #include <media/dvb_net.h>
49*4882a593Smuzhiyun #include <media/dvbdev.h>
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Videobuf / YUV support */
52*4882a593Smuzhiyun #include <media/videobuf-core.h>
53*4882a593Smuzhiyun #include <media/videobuf-vmalloc.h>
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #ifndef CONFIG_PCI
56*4882a593Smuzhiyun # error "This driver requires kernel PCI support."
57*4882a593Smuzhiyun #endif
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define CX18_MEM_OFFSET 0x00000000
60*4882a593Smuzhiyun #define CX18_MEM_SIZE 0x04000000
61*4882a593Smuzhiyun #define CX18_REG_OFFSET 0x02000000
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Maximum cx18 driver instances. */
64*4882a593Smuzhiyun #define CX18_MAX_CARDS 32
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Supported cards */
67*4882a593Smuzhiyun #define CX18_CARD_HVR_1600_ESMT 0 /* Hauppauge HVR 1600 (ESMT memory) */
68*4882a593Smuzhiyun #define CX18_CARD_HVR_1600_SAMSUNG 1 /* Hauppauge HVR 1600 (Samsung memory) */
69*4882a593Smuzhiyun #define CX18_CARD_COMPRO_H900 2 /* Compro VideoMate H900 */
70*4882a593Smuzhiyun #define CX18_CARD_YUAN_MPC718 3 /* Yuan MPC718 */
71*4882a593Smuzhiyun #define CX18_CARD_CNXT_RAPTOR_PAL 4 /* Conexant Raptor PAL */
72*4882a593Smuzhiyun #define CX18_CARD_TOSHIBA_QOSMIO_DVBT 5 /* Toshiba Qosmio Interal DVB-T/Analog*/
73*4882a593Smuzhiyun #define CX18_CARD_LEADTEK_PVR2100 6 /* Leadtek WinFast PVR2100 */
74*4882a593Smuzhiyun #define CX18_CARD_LEADTEK_DVR3100H 7 /* Leadtek WinFast DVR3100 H */
75*4882a593Smuzhiyun #define CX18_CARD_GOTVIEW_PCI_DVD3 8 /* GoTView PCI DVD3 Hybrid */
76*4882a593Smuzhiyun #define CX18_CARD_HVR_1600_S5H1411 9 /* Hauppauge HVR 1600 s5h1411/tda18271*/
77*4882a593Smuzhiyun #define CX18_CARD_LAST 9
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define CX18_ENC_STREAM_TYPE_MPG 0
80*4882a593Smuzhiyun #define CX18_ENC_STREAM_TYPE_TS 1
81*4882a593Smuzhiyun #define CX18_ENC_STREAM_TYPE_YUV 2
82*4882a593Smuzhiyun #define CX18_ENC_STREAM_TYPE_VBI 3
83*4882a593Smuzhiyun #define CX18_ENC_STREAM_TYPE_PCM 4
84*4882a593Smuzhiyun #define CX18_ENC_STREAM_TYPE_IDX 5
85*4882a593Smuzhiyun #define CX18_ENC_STREAM_TYPE_RAD 6
86*4882a593Smuzhiyun #define CX18_MAX_STREAMS 7
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* system vendor and device IDs */
89*4882a593Smuzhiyun #define PCI_VENDOR_ID_CX 0x14f1
90*4882a593Smuzhiyun #define PCI_DEVICE_ID_CX23418 0x5b7a
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* subsystem vendor ID */
93*4882a593Smuzhiyun #define CX18_PCI_ID_HAUPPAUGE 0x0070
94*4882a593Smuzhiyun #define CX18_PCI_ID_COMPRO 0x185b
95*4882a593Smuzhiyun #define CX18_PCI_ID_YUAN 0x12ab
96*4882a593Smuzhiyun #define CX18_PCI_ID_CONEXANT 0x14f1
97*4882a593Smuzhiyun #define CX18_PCI_ID_TOSHIBA 0x1179
98*4882a593Smuzhiyun #define CX18_PCI_ID_LEADTEK 0x107D
99*4882a593Smuzhiyun #define CX18_PCI_ID_GOTVIEW 0x5854
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* ======================================================================== */
102*4882a593Smuzhiyun /* ========================== START USER SETTABLE DMA VARIABLES =========== */
103*4882a593Smuzhiyun /* ======================================================================== */
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* DMA Buffers, Default size in MB allocated */
106*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_TS_BUFFERS 1
107*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_MPG_BUFFERS 2
108*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_IDX_BUFFERS 1
109*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_YUV_BUFFERS 2
110*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_VBI_BUFFERS 1
111*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_PCM_BUFFERS 1
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* Maximum firmware DMA buffers per stream */
114*4882a593Smuzhiyun #define CX18_MAX_FW_MDLS_PER_STREAM 63
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* YUV buffer sizes in bytes to ensure integer # of frames per buffer */
117*4882a593Smuzhiyun #define CX18_UNIT_ENC_YUV_BUFSIZE (720 * 32 * 3 / 2) /* bytes */
118*4882a593Smuzhiyun #define CX18_625_LINE_ENC_YUV_BUFSIZE (CX18_UNIT_ENC_YUV_BUFSIZE * 576/32)
119*4882a593Smuzhiyun #define CX18_525_LINE_ENC_YUV_BUFSIZE (CX18_UNIT_ENC_YUV_BUFSIZE * 480/32)
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* IDX buffer size should be a multiple of the index entry size from the chip */
122*4882a593Smuzhiyun struct cx18_enc_idx_entry {
123*4882a593Smuzhiyun __le32 length;
124*4882a593Smuzhiyun __le32 offset_low;
125*4882a593Smuzhiyun __le32 offset_high;
126*4882a593Smuzhiyun __le32 flags;
127*4882a593Smuzhiyun __le32 pts_low;
128*4882a593Smuzhiyun __le32 pts_high;
129*4882a593Smuzhiyun } __attribute__ ((packed));
130*4882a593Smuzhiyun #define CX18_UNIT_ENC_IDX_BUFSIZE \
131*4882a593Smuzhiyun (sizeof(struct cx18_enc_idx_entry) * V4L2_ENC_IDX_ENTRIES)
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun /* DMA buffer, default size in kB allocated */
134*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_TS_BUFSIZE 32
135*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_MPG_BUFSIZE 32
136*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_IDX_BUFSIZE (CX18_UNIT_ENC_IDX_BUFSIZE * 1 / 1024 + 1)
137*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_YUV_BUFSIZE (CX18_UNIT_ENC_YUV_BUFSIZE * 3 / 1024 + 1)
138*4882a593Smuzhiyun #define CX18_DEFAULT_ENC_PCM_BUFSIZE 4
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* i2c stuff */
141*4882a593Smuzhiyun #define I2C_CLIENTS_MAX 16
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* debugging */
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* Flag to turn on high volume debugging */
146*4882a593Smuzhiyun #define CX18_DBGFLG_WARN (1 << 0)
147*4882a593Smuzhiyun #define CX18_DBGFLG_INFO (1 << 1)
148*4882a593Smuzhiyun #define CX18_DBGFLG_API (1 << 2)
149*4882a593Smuzhiyun #define CX18_DBGFLG_DMA (1 << 3)
150*4882a593Smuzhiyun #define CX18_DBGFLG_IOCTL (1 << 4)
151*4882a593Smuzhiyun #define CX18_DBGFLG_FILE (1 << 5)
152*4882a593Smuzhiyun #define CX18_DBGFLG_I2C (1 << 6)
153*4882a593Smuzhiyun #define CX18_DBGFLG_IRQ (1 << 7)
154*4882a593Smuzhiyun /* Flag to turn on high volume debugging */
155*4882a593Smuzhiyun #define CX18_DBGFLG_HIGHVOL (1 << 8)
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /* NOTE: extra space before comma in 'fmt , ## args' is required for
158*4882a593Smuzhiyun gcc-2.95, otherwise it won't compile. */
159*4882a593Smuzhiyun #define CX18_DEBUG(x, type, fmt, args...) \
160*4882a593Smuzhiyun do { \
161*4882a593Smuzhiyun if ((x) & cx18_debug) \
162*4882a593Smuzhiyun v4l2_info(&cx->v4l2_dev, " " type ": " fmt , ## args); \
163*4882a593Smuzhiyun } while (0)
164*4882a593Smuzhiyun #define CX18_DEBUG_WARN(fmt, args...) CX18_DEBUG(CX18_DBGFLG_WARN, "warning", fmt , ## args)
165*4882a593Smuzhiyun #define CX18_DEBUG_INFO(fmt, args...) CX18_DEBUG(CX18_DBGFLG_INFO, "info", fmt , ## args)
166*4882a593Smuzhiyun #define CX18_DEBUG_API(fmt, args...) CX18_DEBUG(CX18_DBGFLG_API, "api", fmt , ## args)
167*4882a593Smuzhiyun #define CX18_DEBUG_DMA(fmt, args...) CX18_DEBUG(CX18_DBGFLG_DMA, "dma", fmt , ## args)
168*4882a593Smuzhiyun #define CX18_DEBUG_IOCTL(fmt, args...) CX18_DEBUG(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
169*4882a593Smuzhiyun #define CX18_DEBUG_FILE(fmt, args...) CX18_DEBUG(CX18_DBGFLG_FILE, "file", fmt , ## args)
170*4882a593Smuzhiyun #define CX18_DEBUG_I2C(fmt, args...) CX18_DEBUG(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
171*4882a593Smuzhiyun #define CX18_DEBUG_IRQ(fmt, args...) CX18_DEBUG(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun #define CX18_DEBUG_HIGH_VOL(x, type, fmt, args...) \
174*4882a593Smuzhiyun do { \
175*4882a593Smuzhiyun if (((x) & cx18_debug) && (cx18_debug & CX18_DBGFLG_HIGHVOL)) \
176*4882a593Smuzhiyun v4l2_info(&cx->v4l2_dev, " " type ": " fmt , ## args); \
177*4882a593Smuzhiyun } while (0)
178*4882a593Smuzhiyun #define CX18_DEBUG_HI_WARN(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_WARN, "warning", fmt , ## args)
179*4882a593Smuzhiyun #define CX18_DEBUG_HI_INFO(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_INFO, "info", fmt , ## args)
180*4882a593Smuzhiyun #define CX18_DEBUG_HI_API(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_API, "api", fmt , ## args)
181*4882a593Smuzhiyun #define CX18_DEBUG_HI_DMA(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_DMA, "dma", fmt , ## args)
182*4882a593Smuzhiyun #define CX18_DEBUG_HI_IOCTL(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IOCTL, "ioctl", fmt , ## args)
183*4882a593Smuzhiyun #define CX18_DEBUG_HI_FILE(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_FILE, "file", fmt , ## args)
184*4882a593Smuzhiyun #define CX18_DEBUG_HI_I2C(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_I2C, "i2c", fmt , ## args)
185*4882a593Smuzhiyun #define CX18_DEBUG_HI_IRQ(fmt, args...) CX18_DEBUG_HIGH_VOL(CX18_DBGFLG_IRQ, "irq", fmt , ## args)
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* Standard kernel messages */
188*4882a593Smuzhiyun #define CX18_ERR(fmt, args...) v4l2_err(&cx->v4l2_dev, fmt , ## args)
189*4882a593Smuzhiyun #define CX18_WARN(fmt, args...) v4l2_warn(&cx->v4l2_dev, fmt , ## args)
190*4882a593Smuzhiyun #define CX18_INFO(fmt, args...) v4l2_info(&cx->v4l2_dev, fmt , ## args)
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun /* Messages for internal subdevs to use */
193*4882a593Smuzhiyun #define CX18_DEBUG_DEV(x, dev, type, fmt, args...) \
194*4882a593Smuzhiyun do { \
195*4882a593Smuzhiyun if ((x) & cx18_debug) \
196*4882a593Smuzhiyun v4l2_info(dev, " " type ": " fmt , ## args); \
197*4882a593Smuzhiyun } while (0)
198*4882a593Smuzhiyun #define CX18_DEBUG_WARN_DEV(dev, fmt, args...) \
199*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_WARN, dev, "warning", fmt , ## args)
200*4882a593Smuzhiyun #define CX18_DEBUG_INFO_DEV(dev, fmt, args...) \
201*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_INFO, dev, "info", fmt , ## args)
202*4882a593Smuzhiyun #define CX18_DEBUG_API_DEV(dev, fmt, args...) \
203*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_API, dev, "api", fmt , ## args)
204*4882a593Smuzhiyun #define CX18_DEBUG_DMA_DEV(dev, fmt, args...) \
205*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_DMA, dev, "dma", fmt , ## args)
206*4882a593Smuzhiyun #define CX18_DEBUG_IOCTL_DEV(dev, fmt, args...) \
207*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_IOCTL, dev, "ioctl", fmt , ## args)
208*4882a593Smuzhiyun #define CX18_DEBUG_FILE_DEV(dev, fmt, args...) \
209*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_FILE, dev, "file", fmt , ## args)
210*4882a593Smuzhiyun #define CX18_DEBUG_I2C_DEV(dev, fmt, args...) \
211*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_I2C, dev, "i2c", fmt , ## args)
212*4882a593Smuzhiyun #define CX18_DEBUG_IRQ_DEV(dev, fmt, args...) \
213*4882a593Smuzhiyun CX18_DEBUG_DEV(CX18_DBGFLG_IRQ, dev, "irq", fmt , ## args)
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun #define CX18_DEBUG_HIGH_VOL_DEV(x, dev, type, fmt, args...) \
216*4882a593Smuzhiyun do { \
217*4882a593Smuzhiyun if (((x) & cx18_debug) && (cx18_debug & CX18_DBGFLG_HIGHVOL)) \
218*4882a593Smuzhiyun v4l2_info(dev, " " type ": " fmt , ## args); \
219*4882a593Smuzhiyun } while (0)
220*4882a593Smuzhiyun #define CX18_DEBUG_HI_WARN_DEV(dev, fmt, args...) \
221*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_WARN, dev, "warning", fmt , ## args)
222*4882a593Smuzhiyun #define CX18_DEBUG_HI_INFO_DEV(dev, fmt, args...) \
223*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_INFO, dev, "info", fmt , ## args)
224*4882a593Smuzhiyun #define CX18_DEBUG_HI_API_DEV(dev, fmt, args...) \
225*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_API, dev, "api", fmt , ## args)
226*4882a593Smuzhiyun #define CX18_DEBUG_HI_DMA_DEV(dev, fmt, args...) \
227*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_DMA, dev, "dma", fmt , ## args)
228*4882a593Smuzhiyun #define CX18_DEBUG_HI_IOCTL_DEV(dev, fmt, args...) \
229*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_IOCTL, dev, "ioctl", fmt , ## args)
230*4882a593Smuzhiyun #define CX18_DEBUG_HI_FILE_DEV(dev, fmt, args...) \
231*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_FILE, dev, "file", fmt , ## args)
232*4882a593Smuzhiyun #define CX18_DEBUG_HI_I2C_DEV(dev, fmt, args...) \
233*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_I2C, dev, "i2c", fmt , ## args)
234*4882a593Smuzhiyun #define CX18_DEBUG_HI_IRQ_DEV(dev, fmt, args...) \
235*4882a593Smuzhiyun CX18_DEBUG_HIGH_VOL_DEV(CX18_DBGFLG_IRQ, dev, "irq", fmt , ## args)
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun #define CX18_ERR_DEV(dev, fmt, args...) v4l2_err(dev, fmt , ## args)
238*4882a593Smuzhiyun #define CX18_WARN_DEV(dev, fmt, args...) v4l2_warn(dev, fmt , ## args)
239*4882a593Smuzhiyun #define CX18_INFO_DEV(dev, fmt, args...) v4l2_info(dev, fmt , ## args)
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun extern int cx18_debug;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun struct cx18_options {
244*4882a593Smuzhiyun int megabytes[CX18_MAX_STREAMS]; /* Size in megabytes of each stream */
245*4882a593Smuzhiyun int cardtype; /* force card type on load */
246*4882a593Smuzhiyun int tuner; /* set tuner on load */
247*4882a593Smuzhiyun int radio; /* enable/disable radio */
248*4882a593Smuzhiyun };
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* per-mdl bit flags */
251*4882a593Smuzhiyun #define CX18_F_M_NEED_SWAP 0 /* mdl buffer data must be endianness swapped */
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun /* per-stream, s_flags */
254*4882a593Smuzhiyun #define CX18_F_S_CLAIMED 3 /* this stream is claimed */
255*4882a593Smuzhiyun #define CX18_F_S_STREAMING 4 /* the fw is decoding/encoding this stream */
256*4882a593Smuzhiyun #define CX18_F_S_INTERNAL_USE 5 /* this stream is used internally (sliced VBI processing) */
257*4882a593Smuzhiyun #define CX18_F_S_STREAMOFF 7 /* signal end of stream EOS */
258*4882a593Smuzhiyun #define CX18_F_S_APPL_IO 8 /* this stream is used read/written by an application */
259*4882a593Smuzhiyun #define CX18_F_S_STOPPING 9 /* telling the fw to stop capturing */
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* per-cx18, i_flags */
262*4882a593Smuzhiyun #define CX18_F_I_LOADED_FW 0 /* Loaded firmware 1st time */
263*4882a593Smuzhiyun #define CX18_F_I_EOS 4 /* End of encoder stream */
264*4882a593Smuzhiyun #define CX18_F_I_RADIO_USER 5 /* radio tuner is selected */
265*4882a593Smuzhiyun #define CX18_F_I_ENC_PAUSED 13 /* the encoder is paused */
266*4882a593Smuzhiyun #define CX18_F_I_INITED 21 /* set after first open */
267*4882a593Smuzhiyun #define CX18_F_I_FAILED 22 /* set if first open failed */
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* These are the VBI types as they appear in the embedded VBI private packets. */
270*4882a593Smuzhiyun #define CX18_SLICED_TYPE_TELETEXT_B (1)
271*4882a593Smuzhiyun #define CX18_SLICED_TYPE_CAPTION_525 (4)
272*4882a593Smuzhiyun #define CX18_SLICED_TYPE_WSS_625 (5)
273*4882a593Smuzhiyun #define CX18_SLICED_TYPE_VPS (7)
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /**
276*4882a593Smuzhiyun * list_entry_is_past_end - check if a previous loop cursor is off list end
277*4882a593Smuzhiyun * @pos: the type * previously used as a loop cursor.
278*4882a593Smuzhiyun * @head: the head for your list.
279*4882a593Smuzhiyun * @member: the name of the list_head within the struct.
280*4882a593Smuzhiyun *
281*4882a593Smuzhiyun * Check if the entry's list_head is the head of the list, thus it's not a
282*4882a593Smuzhiyun * real entry but was the loop cursor that walked past the end
283*4882a593Smuzhiyun */
284*4882a593Smuzhiyun #define list_entry_is_past_end(pos, head, member) \
285*4882a593Smuzhiyun (&pos->member == (head))
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun struct cx18_buffer {
288*4882a593Smuzhiyun struct list_head list;
289*4882a593Smuzhiyun dma_addr_t dma_handle;
290*4882a593Smuzhiyun char *buf;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun u32 bytesused;
293*4882a593Smuzhiyun u32 readpos;
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun struct cx18_mdl {
297*4882a593Smuzhiyun struct list_head list;
298*4882a593Smuzhiyun u32 id; /* index into cx->scb->cpu_mdl[] of 1st cx18_mdl_ent */
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun unsigned int skipped;
301*4882a593Smuzhiyun unsigned long m_flags;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun struct list_head buf_list;
304*4882a593Smuzhiyun struct cx18_buffer *curr_buf; /* current buffer in list for reading */
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun u32 bytesused;
307*4882a593Smuzhiyun u32 readpos;
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun struct cx18_queue {
311*4882a593Smuzhiyun struct list_head list;
312*4882a593Smuzhiyun atomic_t depth;
313*4882a593Smuzhiyun u32 bytesused;
314*4882a593Smuzhiyun spinlock_t lock;
315*4882a593Smuzhiyun };
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun struct cx18_stream; /* forward reference */
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun struct cx18_dvb {
320*4882a593Smuzhiyun struct cx18_stream *stream;
321*4882a593Smuzhiyun struct dmx_frontend hw_frontend;
322*4882a593Smuzhiyun struct dmx_frontend mem_frontend;
323*4882a593Smuzhiyun struct dmxdev dmxdev;
324*4882a593Smuzhiyun struct dvb_adapter dvb_adapter;
325*4882a593Smuzhiyun struct dvb_demux demux;
326*4882a593Smuzhiyun struct dvb_frontend *fe;
327*4882a593Smuzhiyun struct dvb_net dvbnet;
328*4882a593Smuzhiyun int enabled;
329*4882a593Smuzhiyun int feeding;
330*4882a593Smuzhiyun struct mutex feedlock;
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun struct cx18; /* forward reference */
334*4882a593Smuzhiyun struct cx18_scb; /* forward reference */
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun #define CX18_MAX_MDL_ACKS 2
338*4882a593Smuzhiyun #define CX18_MAX_IN_WORK_ORDERS (CX18_MAX_FW_MDLS_PER_STREAM + 7)
339*4882a593Smuzhiyun /* CPU_DE_RELEASE_MDL can burst CX18_MAX_FW_MDLS_PER_STREAM orders in a group */
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun #define CX18_F_EWO_MB_STALE_UPON_RECEIPT 0x1
342*4882a593Smuzhiyun #define CX18_F_EWO_MB_STALE_WHILE_PROC 0x2
343*4882a593Smuzhiyun #define CX18_F_EWO_MB_STALE \
344*4882a593Smuzhiyun (CX18_F_EWO_MB_STALE_UPON_RECEIPT | CX18_F_EWO_MB_STALE_WHILE_PROC)
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun struct cx18_in_work_order {
347*4882a593Smuzhiyun struct work_struct work;
348*4882a593Smuzhiyun atomic_t pending;
349*4882a593Smuzhiyun struct cx18 *cx;
350*4882a593Smuzhiyun unsigned long flags;
351*4882a593Smuzhiyun int rpu;
352*4882a593Smuzhiyun struct cx18_mailbox mb;
353*4882a593Smuzhiyun struct cx18_mdl_ack mdl_ack[CX18_MAX_MDL_ACKS];
354*4882a593Smuzhiyun char *str;
355*4882a593Smuzhiyun };
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun #define CX18_INVALID_TASK_HANDLE 0xffffffff
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun struct cx18_stream {
360*4882a593Smuzhiyun /* These first five fields are always set, even if the stream
361*4882a593Smuzhiyun is not actually created. */
362*4882a593Smuzhiyun struct video_device video_dev; /* v4l2_dev is NULL when stream not created */
363*4882a593Smuzhiyun struct cx18_dvb *dvb; /* DVB / Digital Transport */
364*4882a593Smuzhiyun struct cx18 *cx; /* for ease of use */
365*4882a593Smuzhiyun const char *name; /* name of the stream */
366*4882a593Smuzhiyun int type; /* stream type */
367*4882a593Smuzhiyun u32 handle; /* task handle */
368*4882a593Smuzhiyun u32 v4l2_dev_caps; /* device capabilities */
369*4882a593Smuzhiyun unsigned int mdl_base_idx;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun u32 id;
372*4882a593Smuzhiyun unsigned long s_flags; /* status flags, see above */
373*4882a593Smuzhiyun int dma; /* can be PCI_DMA_TODEVICE,
374*4882a593Smuzhiyun PCI_DMA_FROMDEVICE or
375*4882a593Smuzhiyun PCI_DMA_NONE */
376*4882a593Smuzhiyun wait_queue_head_t waitq;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun /* Buffers */
379*4882a593Smuzhiyun struct list_head buf_pool; /* buffers not attached to an MDL */
380*4882a593Smuzhiyun u32 buffers; /* total buffers owned by this stream */
381*4882a593Smuzhiyun u32 buf_size; /* size in bytes of a single buffer */
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* MDL sizes - all stream MDLs are the same size */
384*4882a593Smuzhiyun u32 bufs_per_mdl;
385*4882a593Smuzhiyun u32 mdl_size; /* total bytes in all buffers in a mdl */
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /* MDL Queues */
388*4882a593Smuzhiyun struct cx18_queue q_free; /* free - in rotation, not committed */
389*4882a593Smuzhiyun struct cx18_queue q_busy; /* busy - in use by firmware */
390*4882a593Smuzhiyun struct cx18_queue q_full; /* full - data for user apps */
391*4882a593Smuzhiyun struct cx18_queue q_idle; /* idle - not in rotation */
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun struct work_struct out_work_order;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun /* Videobuf for YUV video */
396*4882a593Smuzhiyun u32 pixelformat;
397*4882a593Smuzhiyun u32 vb_bytes_per_frame;
398*4882a593Smuzhiyun u32 vb_bytes_per_line;
399*4882a593Smuzhiyun struct list_head vb_capture; /* video capture queue */
400*4882a593Smuzhiyun spinlock_t vb_lock;
401*4882a593Smuzhiyun struct timer_list vb_timeout;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun struct videobuf_queue vbuf_q;
404*4882a593Smuzhiyun spinlock_t vbuf_q_lock; /* Protect vbuf_q */
405*4882a593Smuzhiyun enum v4l2_buf_type vb_type;
406*4882a593Smuzhiyun };
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun struct cx18_videobuf_buffer {
409*4882a593Smuzhiyun /* Common video buffer sub-system struct */
410*4882a593Smuzhiyun struct videobuf_buffer vb;
411*4882a593Smuzhiyun v4l2_std_id tvnorm; /* selected tv norm */
412*4882a593Smuzhiyun u32 bytes_used;
413*4882a593Smuzhiyun };
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun struct cx18_open_id {
416*4882a593Smuzhiyun struct v4l2_fh fh;
417*4882a593Smuzhiyun u32 open_id;
418*4882a593Smuzhiyun int type;
419*4882a593Smuzhiyun struct cx18 *cx;
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun
fh2id(struct v4l2_fh * fh)422*4882a593Smuzhiyun static inline struct cx18_open_id *fh2id(struct v4l2_fh *fh)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun return container_of(fh, struct cx18_open_id, fh);
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
file2id(struct file * file)427*4882a593Smuzhiyun static inline struct cx18_open_id *file2id(struct file *file)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun return fh2id(file->private_data);
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /* forward declaration of struct defined in cx18-cards.h */
433*4882a593Smuzhiyun struct cx18_card;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun /*
436*4882a593Smuzhiyun * A note about "sliced" VBI data as implemented in this driver:
437*4882a593Smuzhiyun *
438*4882a593Smuzhiyun * Currently we collect the sliced VBI in the form of Ancillary Data
439*4882a593Smuzhiyun * packets, inserted by the AV core decoder/digitizer/slicer in the
440*4882a593Smuzhiyun * horizontal blanking region of the VBI lines, in "raw" mode as far as
441*4882a593Smuzhiyun * the Encoder is concerned. We don't ever tell the Encoder itself
442*4882a593Smuzhiyun * to provide sliced VBI. (AV Core: sliced mode - Encoder: raw mode)
443*4882a593Smuzhiyun *
444*4882a593Smuzhiyun * We then process the ancillary data ourselves to send the sliced data
445*4882a593Smuzhiyun * to the user application directly or build up MPEG-2 private stream 1
446*4882a593Smuzhiyun * packets to splice into (only!) MPEG-2 PS streams for the user app.
447*4882a593Smuzhiyun *
448*4882a593Smuzhiyun * (That's how ivtv essentially does it.)
449*4882a593Smuzhiyun *
450*4882a593Smuzhiyun * The Encoder should be able to extract certain sliced VBI data for
451*4882a593Smuzhiyun * us and provide it in a separate stream or splice it into any type of
452*4882a593Smuzhiyun * MPEG PS or TS stream, but this isn't implemented yet.
453*4882a593Smuzhiyun */
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun /*
456*4882a593Smuzhiyun * Number of "raw" VBI samples per horizontal line we tell the Encoder to
457*4882a593Smuzhiyun * grab from the decoder/digitizer/slicer output for raw or sliced VBI.
458*4882a593Smuzhiyun * It depends on the pixel clock and the horiz rate:
459*4882a593Smuzhiyun *
460*4882a593Smuzhiyun * (1/Fh)*(2*Fp) = Samples/line
461*4882a593Smuzhiyun * = 4 bytes EAV + Anc data in hblank + 4 bytes SAV + active samples
462*4882a593Smuzhiyun *
463*4882a593Smuzhiyun * Sliced VBI data is sent as ancillary data during horizontal blanking
464*4882a593Smuzhiyun * Raw VBI is sent as active video samples during vertcal blanking
465*4882a593Smuzhiyun *
466*4882a593Smuzhiyun * We use a BT.656 pxiel clock of 13.5 MHz and a BT.656 active line
467*4882a593Smuzhiyun * length of 720 pixels @ 4:2:2 sampling. Thus...
468*4882a593Smuzhiyun *
469*4882a593Smuzhiyun * For systems that use a 15.734 kHz horizontal rate, such as
470*4882a593Smuzhiyun * NTSC-M, PAL-M, PAL-60, and other 60 Hz/525 line systems, we have:
471*4882a593Smuzhiyun *
472*4882a593Smuzhiyun * (1/15.734 kHz) * 2 * 13.5 MHz = 1716 samples/line =
473*4882a593Smuzhiyun * 4 bytes SAV + 268 bytes anc data + 4 bytes SAV + 1440 active samples
474*4882a593Smuzhiyun *
475*4882a593Smuzhiyun * For systems that use a 15.625 kHz horizontal rate, such as
476*4882a593Smuzhiyun * PAL-B/G/H, PAL-I, SECAM-L and other 50 Hz/625 line systems, we have:
477*4882a593Smuzhiyun *
478*4882a593Smuzhiyun * (1/15.625 kHz) * 2 * 13.5 MHz = 1728 samples/line =
479*4882a593Smuzhiyun * 4 bytes SAV + 280 bytes anc data + 4 bytes SAV + 1440 active samples
480*4882a593Smuzhiyun */
481*4882a593Smuzhiyun #define VBI_ACTIVE_SAMPLES 1444 /* 4 byte SAV + 720 Y + 720 U/V */
482*4882a593Smuzhiyun #define VBI_HBLANK_SAMPLES_60HZ 272 /* 4 byte EAV + 268 anc/fill */
483*4882a593Smuzhiyun #define VBI_HBLANK_SAMPLES_50HZ 284 /* 4 byte EAV + 280 anc/fill */
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun #define CX18_VBI_FRAMES 32
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun struct vbi_info {
488*4882a593Smuzhiyun /* Current state of v4l2 VBI settings for this device */
489*4882a593Smuzhiyun struct v4l2_format in;
490*4882a593Smuzhiyun struct v4l2_sliced_vbi_format *sliced_in; /* pointer to in.fmt.sliced */
491*4882a593Smuzhiyun u32 count; /* Count of VBI data lines: 60 Hz: 12 or 50 Hz: 18 */
492*4882a593Smuzhiyun u32 start[2]; /* First VBI data line per field: 10 & 273 or 6 & 318 */
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun u32 frame; /* Count of VBI buffers/frames received from Encoder */
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun /*
497*4882a593Smuzhiyun * Vars for creation and insertion of MPEG Private Stream 1 packets
498*4882a593Smuzhiyun * of sliced VBI data into an MPEG PS
499*4882a593Smuzhiyun */
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun /* Boolean: create and insert Private Stream 1 packets into the PS */
502*4882a593Smuzhiyun int insert_mpeg;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun /*
505*4882a593Smuzhiyun * Buffer for the maximum of 2 * 18 * packet_size sliced VBI lines.
506*4882a593Smuzhiyun * Used in cx18-vbi.c only for collecting sliced data, and as a source
507*4882a593Smuzhiyun * during conversion of sliced VBI data into MPEG Priv Stream 1 packets.
508*4882a593Smuzhiyun * We don't need to save state here, but the array may have been a bit
509*4882a593Smuzhiyun * too big (2304 bytes) to alloc from the stack.
510*4882a593Smuzhiyun */
511*4882a593Smuzhiyun struct v4l2_sliced_vbi_data sliced_data[36];
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun /*
514*4882a593Smuzhiyun * A ring buffer of driver-generated MPEG-2 PS
515*4882a593Smuzhiyun * Program Pack/Private Stream 1 packets for sliced VBI data insertion
516*4882a593Smuzhiyun * into the MPEG PS stream.
517*4882a593Smuzhiyun *
518*4882a593Smuzhiyun * In each sliced_mpeg_data[] buffer is:
519*4882a593Smuzhiyun * 16 byte MPEG-2 PS Program Pack Header
520*4882a593Smuzhiyun * 16 byte MPEG-2 Private Stream 1 PES Header
521*4882a593Smuzhiyun * 4 byte magic number: "itv0" or "ITV0"
522*4882a593Smuzhiyun * 4 byte first field line mask, if "itv0"
523*4882a593Smuzhiyun * 4 byte second field line mask, if "itv0"
524*4882a593Smuzhiyun * 36 lines, if "ITV0"; or <36 lines, if "itv0"; of sliced VBI data
525*4882a593Smuzhiyun *
526*4882a593Smuzhiyun * Each line in the payload is
527*4882a593Smuzhiyun * 1 byte line header derived from the SDID (WSS, CC, VPS, etc.)
528*4882a593Smuzhiyun * 42 bytes of line data
529*4882a593Smuzhiyun *
530*4882a593Smuzhiyun * That's a maximum 1552 bytes of payload in the Private Stream 1 packet
531*4882a593Smuzhiyun * which is the payload size a PVR-350 (CX23415) MPEG decoder will
532*4882a593Smuzhiyun * accept for VBI data. So, including the headers, it's a maximum 1584
533*4882a593Smuzhiyun * bytes total.
534*4882a593Smuzhiyun */
535*4882a593Smuzhiyun #define CX18_SLICED_MPEG_DATA_MAXSZ 1584
536*4882a593Smuzhiyun /* copy_vbi_buf() needs 8 temp bytes on the end for the worst case */
537*4882a593Smuzhiyun #define CX18_SLICED_MPEG_DATA_BUFSZ (CX18_SLICED_MPEG_DATA_MAXSZ+8)
538*4882a593Smuzhiyun u8 *sliced_mpeg_data[CX18_VBI_FRAMES];
539*4882a593Smuzhiyun u32 sliced_mpeg_size[CX18_VBI_FRAMES];
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun /* Count of Program Pack/Program Stream 1 packets inserted into PS */
542*4882a593Smuzhiyun u32 inserted_frame;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun /*
545*4882a593Smuzhiyun * A dummy driver stream transfer mdl & buffer with a copy of the next
546*4882a593Smuzhiyun * sliced_mpeg_data[] buffer for output to userland apps.
547*4882a593Smuzhiyun * Only used in cx18-fileops.c, but its state needs to persist at times.
548*4882a593Smuzhiyun */
549*4882a593Smuzhiyun struct cx18_mdl sliced_mpeg_mdl;
550*4882a593Smuzhiyun struct cx18_buffer sliced_mpeg_buf;
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun /* Per cx23418, per I2C bus private algo callback data */
554*4882a593Smuzhiyun struct cx18_i2c_algo_callback_data {
555*4882a593Smuzhiyun struct cx18 *cx;
556*4882a593Smuzhiyun int bus_index; /* 0 or 1 for the cx23418's 1st or 2nd I2C bus */
557*4882a593Smuzhiyun };
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun #define CX18_MAX_MMIO_WR_RETRIES 10
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun /* Struct to hold info about cx18 cards */
562*4882a593Smuzhiyun struct cx18 {
563*4882a593Smuzhiyun int instance;
564*4882a593Smuzhiyun struct pci_dev *pci_dev;
565*4882a593Smuzhiyun struct v4l2_device v4l2_dev;
566*4882a593Smuzhiyun struct v4l2_subdev *sd_av; /* A/V decoder/digitizer sub-device */
567*4882a593Smuzhiyun struct v4l2_subdev *sd_extmux; /* External multiplexer sub-dev */
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun const struct cx18_card *card; /* card information */
570*4882a593Smuzhiyun const char *card_name; /* full name of the card */
571*4882a593Smuzhiyun const struct cx18_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */
572*4882a593Smuzhiyun u8 is_50hz;
573*4882a593Smuzhiyun u8 is_60hz;
574*4882a593Smuzhiyun u8 nof_inputs; /* number of video inputs */
575*4882a593Smuzhiyun u8 nof_audio_inputs; /* number of audio inputs */
576*4882a593Smuzhiyun u32 v4l2_cap; /* V4L2 capabilities of card */
577*4882a593Smuzhiyun u32 hw_flags; /* Hardware description of the board */
578*4882a593Smuzhiyun unsigned int free_mdl_idx;
579*4882a593Smuzhiyun struct cx18_scb __iomem *scb; /* pointer to SCB */
580*4882a593Smuzhiyun struct mutex epu2apu_mb_lock; /* protect driver to chip mailbox in SCB*/
581*4882a593Smuzhiyun struct mutex epu2cpu_mb_lock; /* protect driver to chip mailbox in SCB*/
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun struct cx18_av_state av_state;
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun /* codec settings */
586*4882a593Smuzhiyun struct cx2341x_handler cxhdl;
587*4882a593Smuzhiyun u32 filter_mode;
588*4882a593Smuzhiyun u32 temporal_strength;
589*4882a593Smuzhiyun u32 spatial_strength;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun /* dualwatch */
592*4882a593Smuzhiyun unsigned long dualwatch_jiffies;
593*4882a593Smuzhiyun u32 dualwatch_stereo_mode;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun struct mutex serialize_lock; /* mutex used to serialize open/close/start/stop/ioctl operations */
596*4882a593Smuzhiyun struct cx18_options options; /* User options */
597*4882a593Smuzhiyun int stream_buffers[CX18_MAX_STREAMS]; /* # of buffers for each stream */
598*4882a593Smuzhiyun int stream_buf_size[CX18_MAX_STREAMS]; /* Stream buffer size */
599*4882a593Smuzhiyun struct cx18_stream streams[CX18_MAX_STREAMS]; /* Stream data */
600*4882a593Smuzhiyun struct snd_cx18_card *alsa; /* ALSA interface for PCM capture stream */
601*4882a593Smuzhiyun void (*pcm_announce_callback)(struct snd_cx18_card *card, u8 *pcm_data,
602*4882a593Smuzhiyun size_t num_bytes);
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun unsigned long i_flags; /* global cx18 flags */
605*4882a593Smuzhiyun atomic_t ana_capturing; /* count number of active analog capture streams */
606*4882a593Smuzhiyun atomic_t tot_capturing; /* total count number of active capture streams */
607*4882a593Smuzhiyun int search_pack_header;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun int open_id; /* incremented each time an open occurs, used as
610*4882a593Smuzhiyun unique ID. Starts at 1, so 0 can be used as
611*4882a593Smuzhiyun uninitialized value in the stream->id. */
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun resource_size_t base_addr;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun u8 card_rev;
616*4882a593Smuzhiyun void __iomem *enc_mem, *reg_mem;
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun struct vbi_info vbi;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun u64 mpg_data_received;
621*4882a593Smuzhiyun u64 vbi_data_inserted;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun wait_queue_head_t mb_apu_waitq;
624*4882a593Smuzhiyun wait_queue_head_t mb_cpu_waitq;
625*4882a593Smuzhiyun wait_queue_head_t cap_w;
626*4882a593Smuzhiyun /* when the current DMA is finished this queue is woken up */
627*4882a593Smuzhiyun wait_queue_head_t dma_waitq;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun u32 sw1_irq_mask;
630*4882a593Smuzhiyun u32 sw2_irq_mask;
631*4882a593Smuzhiyun u32 hw2_irq_mask;
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun struct workqueue_struct *in_work_queue;
634*4882a593Smuzhiyun char in_workq_name[11]; /* "cx18-NN-in" */
635*4882a593Smuzhiyun struct cx18_in_work_order in_work_order[CX18_MAX_IN_WORK_ORDERS];
636*4882a593Smuzhiyun char epu_debug_str[256]; /* CX18_EPU_DEBUG is rare: use shared space */
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun /* i2c */
639*4882a593Smuzhiyun struct i2c_adapter i2c_adap[2];
640*4882a593Smuzhiyun struct i2c_algo_bit_data i2c_algo[2];
641*4882a593Smuzhiyun struct cx18_i2c_algo_callback_data i2c_algo_cb_data[2];
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun struct IR_i2c_init_data ir_i2c_init_data;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun /* gpio */
646*4882a593Smuzhiyun u32 gpio_dir;
647*4882a593Smuzhiyun u32 gpio_val;
648*4882a593Smuzhiyun struct mutex gpio_lock;
649*4882a593Smuzhiyun struct v4l2_subdev sd_gpiomux;
650*4882a593Smuzhiyun struct v4l2_subdev sd_resetctrl;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /* v4l2 and User settings */
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun /* codec settings */
655*4882a593Smuzhiyun u32 audio_input;
656*4882a593Smuzhiyun u32 active_input;
657*4882a593Smuzhiyun v4l2_std_id std;
658*4882a593Smuzhiyun v4l2_std_id tuner_std; /* The norm of the tuner (fixed) */
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun /* Used for cx18-alsa module loading */
661*4882a593Smuzhiyun struct work_struct request_module_wk;
662*4882a593Smuzhiyun };
663*4882a593Smuzhiyun
to_cx18(struct v4l2_device * v4l2_dev)664*4882a593Smuzhiyun static inline struct cx18 *to_cx18(struct v4l2_device *v4l2_dev)
665*4882a593Smuzhiyun {
666*4882a593Smuzhiyun return container_of(v4l2_dev, struct cx18, v4l2_dev);
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun /* cx18 extensions to be loaded */
670*4882a593Smuzhiyun extern int (*cx18_ext_init)(struct cx18 *);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun /* Globals */
673*4882a593Smuzhiyun extern int cx18_first_minor;
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun /*==============Prototypes==================*/
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun /* Return non-zero if a signal is pending */
678*4882a593Smuzhiyun int cx18_msleep_timeout(unsigned int msecs, int intr);
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun /* Read Hauppauge eeprom */
681*4882a593Smuzhiyun struct tveeprom; /* forward reference */
682*4882a593Smuzhiyun void cx18_read_eeprom(struct cx18 *cx, struct tveeprom *tv);
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun /* First-open initialization: load firmware, etc. */
685*4882a593Smuzhiyun int cx18_init_on_first_open(struct cx18 *cx);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun /* Test if the current VBI mode is raw (1) or sliced (0) */
cx18_raw_vbi(const struct cx18 * cx)688*4882a593Smuzhiyun static inline int cx18_raw_vbi(const struct cx18 *cx)
689*4882a593Smuzhiyun {
690*4882a593Smuzhiyun return cx->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun /* Call the specified callback for all subdevs with a grp_id bit matching the
694*4882a593Smuzhiyun * mask in hw (if 0, then match them all). Ignore any errors. */
695*4882a593Smuzhiyun #define cx18_call_hw(cx, hw, o, f, args...) \
696*4882a593Smuzhiyun v4l2_device_mask_call_all(&(cx)->v4l2_dev, hw, o, f, ##args)
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun #define cx18_call_all(cx, o, f, args...) cx18_call_hw(cx, 0, o, f , ##args)
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun /* Call the specified callback for all subdevs with a grp_id bit matching the
701*4882a593Smuzhiyun * mask in hw (if 0, then match them all). If the callback returns an error
702*4882a593Smuzhiyun * other than 0 or -ENOIOCTLCMD, then return with that error code. */
703*4882a593Smuzhiyun #define cx18_call_hw_err(cx, hw, o, f, args...) \
704*4882a593Smuzhiyun v4l2_device_mask_call_until_err(&(cx)->v4l2_dev, hw, o, f, ##args)
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun #define cx18_call_all_err(cx, o, f, args...) \
707*4882a593Smuzhiyun cx18_call_hw_err(cx, 0, o, f , ##args)
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun #endif /* CX18_DRIVER_H */
710