1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * cobalt driver initialization and card probing
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Derived from cx18-driver.c
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright 2012-2015 Cisco Systems, Inc. and/or its affiliates.
8*4882a593Smuzhiyun * All rights reserved.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <media/i2c/adv7604.h>
13*4882a593Smuzhiyun #include <media/i2c/adv7842.h>
14*4882a593Smuzhiyun #include <media/i2c/adv7511.h>
15*4882a593Smuzhiyun #include <media/v4l2-event.h>
16*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "cobalt-driver.h"
19*4882a593Smuzhiyun #include "cobalt-irq.h"
20*4882a593Smuzhiyun #include "cobalt-i2c.h"
21*4882a593Smuzhiyun #include "cobalt-v4l2.h"
22*4882a593Smuzhiyun #include "cobalt-flash.h"
23*4882a593Smuzhiyun #include "cobalt-alsa.h"
24*4882a593Smuzhiyun #include "cobalt-omnitek.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* add your revision and whatnot here */
27*4882a593Smuzhiyun static const struct pci_device_id cobalt_pci_tbl[] = {
28*4882a593Smuzhiyun {PCI_VENDOR_ID_CISCO, PCI_DEVICE_ID_COBALT,
29*4882a593Smuzhiyun PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
30*4882a593Smuzhiyun {0,}
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, cobalt_pci_tbl);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static atomic_t cobalt_instance = ATOMIC_INIT(0);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun int cobalt_debug;
38*4882a593Smuzhiyun module_param_named(debug, cobalt_debug, int, 0644);
39*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level. Default: 0\n");
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun int cobalt_ignore_err;
42*4882a593Smuzhiyun module_param_named(ignore_err, cobalt_ignore_err, int, 0644);
43*4882a593Smuzhiyun MODULE_PARM_DESC(ignore_err,
44*4882a593Smuzhiyun "If set then ignore missing i2c adapters/receivers. Default: 0\n");
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com> & Morten Hestnes");
47*4882a593Smuzhiyun MODULE_DESCRIPTION("cobalt driver");
48*4882a593Smuzhiyun MODULE_LICENSE("GPL");
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static u8 edid[256] = {
51*4882a593Smuzhiyun 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
52*4882a593Smuzhiyun 0x50, 0x21, 0x32, 0x27, 0x00, 0x00, 0x00, 0x00,
53*4882a593Smuzhiyun 0x22, 0x1a, 0x01, 0x03, 0x80, 0x30, 0x1b, 0x78,
54*4882a593Smuzhiyun 0x0f, 0xee, 0x91, 0xa3, 0x54, 0x4c, 0x99, 0x26,
55*4882a593Smuzhiyun 0x0f, 0x50, 0x54, 0x2f, 0xcf, 0x00, 0x31, 0x59,
56*4882a593Smuzhiyun 0x45, 0x59, 0x61, 0x59, 0x81, 0x99, 0x01, 0x01,
57*4882a593Smuzhiyun 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a,
58*4882a593Smuzhiyun 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
59*4882a593Smuzhiyun 0x46, 0x00, 0xe0, 0x0e, 0x11, 0x00, 0x00, 0x1e,
60*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x55, 0x18,
61*4882a593Smuzhiyun 0x5e, 0x11, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20,
62*4882a593Smuzhiyun 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x63,
63*4882a593Smuzhiyun 0x6f, 0x62, 0x61, 0x6c, 0x74, 0x0a, 0x20, 0x20,
64*4882a593Smuzhiyun 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x10,
65*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
66*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x9c,
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun 0x02, 0x03, 0x1f, 0xf0, 0x4a, 0x90, 0x1f, 0x04,
69*4882a593Smuzhiyun 0x13, 0x22, 0x21, 0x20, 0x02, 0x11, 0x01, 0x23,
70*4882a593Smuzhiyun 0x09, 0x07, 0x07, 0x68, 0x03, 0x0c, 0x00, 0x10,
71*4882a593Smuzhiyun 0x00, 0x00, 0x22, 0x0f, 0xe2, 0x00, 0xea, 0x00,
72*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
73*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
74*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
76*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
78*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
80*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
81*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
82*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
83*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
cobalt_set_interrupt(struct cobalt * cobalt,bool enable)86*4882a593Smuzhiyun static void cobalt_set_interrupt(struct cobalt *cobalt, bool enable)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun if (enable) {
89*4882a593Smuzhiyun unsigned irqs = COBALT_SYSSTAT_VI0_INT1_MSK |
90*4882a593Smuzhiyun COBALT_SYSSTAT_VI1_INT1_MSK |
91*4882a593Smuzhiyun COBALT_SYSSTAT_VI2_INT1_MSK |
92*4882a593Smuzhiyun COBALT_SYSSTAT_VI3_INT1_MSK |
93*4882a593Smuzhiyun COBALT_SYSSTAT_VI0_INT2_MSK |
94*4882a593Smuzhiyun COBALT_SYSSTAT_VI1_INT2_MSK |
95*4882a593Smuzhiyun COBALT_SYSSTAT_VI2_INT2_MSK |
96*4882a593Smuzhiyun COBALT_SYSSTAT_VI3_INT2_MSK |
97*4882a593Smuzhiyun COBALT_SYSSTAT_VI0_LOST_DATA_MSK |
98*4882a593Smuzhiyun COBALT_SYSSTAT_VI1_LOST_DATA_MSK |
99*4882a593Smuzhiyun COBALT_SYSSTAT_VI2_LOST_DATA_MSK |
100*4882a593Smuzhiyun COBALT_SYSSTAT_VI3_LOST_DATA_MSK |
101*4882a593Smuzhiyun COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (cobalt->have_hsma_rx)
104*4882a593Smuzhiyun irqs |= COBALT_SYSSTAT_VIHSMA_INT1_MSK |
105*4882a593Smuzhiyun COBALT_SYSSTAT_VIHSMA_INT2_MSK |
106*4882a593Smuzhiyun COBALT_SYSSTAT_VIHSMA_LOST_DATA_MSK;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (cobalt->have_hsma_tx)
109*4882a593Smuzhiyun irqs |= COBALT_SYSSTAT_VOHSMA_INT1_MSK |
110*4882a593Smuzhiyun COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK |
111*4882a593Smuzhiyun COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK;
112*4882a593Smuzhiyun /* Clear any existing interrupts */
113*4882a593Smuzhiyun cobalt_write_bar1(cobalt, COBALT_SYS_STAT_EDGE, 0xffffffff);
114*4882a593Smuzhiyun /* PIO Core interrupt mask register.
115*4882a593Smuzhiyun Enable ADV7604 INT1 interrupts */
116*4882a593Smuzhiyun cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, irqs);
117*4882a593Smuzhiyun } else {
118*4882a593Smuzhiyun /* Disable all ADV7604 interrupts */
119*4882a593Smuzhiyun cobalt_write_bar1(cobalt, COBALT_SYS_STAT_MASK, 0);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
cobalt_get_sd_nr(struct v4l2_subdev * sd)123*4882a593Smuzhiyun static unsigned cobalt_get_sd_nr(struct v4l2_subdev *sd)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct cobalt *cobalt = to_cobalt(sd->v4l2_dev);
126*4882a593Smuzhiyun unsigned i;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun for (i = 0; i < COBALT_NUM_NODES; i++)
129*4882a593Smuzhiyun if (sd == cobalt->streams[i].sd)
130*4882a593Smuzhiyun return i;
131*4882a593Smuzhiyun cobalt_err("Invalid adv7604 subdev pointer!\n");
132*4882a593Smuzhiyun return 0;
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
cobalt_notify(struct v4l2_subdev * sd,unsigned int notification,void * arg)135*4882a593Smuzhiyun static void cobalt_notify(struct v4l2_subdev *sd,
136*4882a593Smuzhiyun unsigned int notification, void *arg)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct cobalt *cobalt = to_cobalt(sd->v4l2_dev);
139*4882a593Smuzhiyun unsigned sd_nr = cobalt_get_sd_nr(sd);
140*4882a593Smuzhiyun struct cobalt_stream *s = &cobalt->streams[sd_nr];
141*4882a593Smuzhiyun bool hotplug = arg ? *((int *)arg) : false;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun if (s->is_output)
144*4882a593Smuzhiyun return;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun switch (notification) {
147*4882a593Smuzhiyun case ADV76XX_HOTPLUG:
148*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
149*4882a593Smuzhiyun COBALT_SYS_CTRL_HPD_TO_CONNECTOR_BIT(sd_nr), hotplug);
150*4882a593Smuzhiyun cobalt_dbg(1, "Set hotplug for adv %d to %d\n", sd_nr, hotplug);
151*4882a593Smuzhiyun break;
152*4882a593Smuzhiyun case V4L2_DEVICE_NOTIFY_EVENT:
153*4882a593Smuzhiyun cobalt_dbg(1, "Format changed for adv %d\n", sd_nr);
154*4882a593Smuzhiyun v4l2_event_queue(&s->vdev, arg);
155*4882a593Smuzhiyun break;
156*4882a593Smuzhiyun default:
157*4882a593Smuzhiyun break;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
get_payload_size(u16 code)161*4882a593Smuzhiyun static int get_payload_size(u16 code)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun switch (code) {
164*4882a593Smuzhiyun case 0: return 128;
165*4882a593Smuzhiyun case 1: return 256;
166*4882a593Smuzhiyun case 2: return 512;
167*4882a593Smuzhiyun case 3: return 1024;
168*4882a593Smuzhiyun case 4: return 2048;
169*4882a593Smuzhiyun case 5: return 4096;
170*4882a593Smuzhiyun default: return 0;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun return 0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
get_link_speed(u16 stat)175*4882a593Smuzhiyun static const char *get_link_speed(u16 stat)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun switch (stat & PCI_EXP_LNKSTA_CLS) {
178*4882a593Smuzhiyun case 1: return "2.5 Gbit/s";
179*4882a593Smuzhiyun case 2: return "5 Gbit/s";
180*4882a593Smuzhiyun case 3: return "10 Gbit/s";
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun return "Unknown speed";
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
cobalt_pcie_status_show(struct cobalt * cobalt)185*4882a593Smuzhiyun void cobalt_pcie_status_show(struct cobalt *cobalt)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun struct pci_dev *pci_dev = cobalt->pci_dev;
188*4882a593Smuzhiyun struct pci_dev *pci_bus_dev = cobalt->pci_dev->bus->self;
189*4882a593Smuzhiyun u32 capa;
190*4882a593Smuzhiyun u16 stat, ctrl;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun if (!pci_is_pcie(pci_dev) || !pci_is_pcie(pci_bus_dev))
193*4882a593Smuzhiyun return;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* Device */
196*4882a593Smuzhiyun pcie_capability_read_dword(pci_dev, PCI_EXP_DEVCAP, &capa);
197*4882a593Smuzhiyun pcie_capability_read_word(pci_dev, PCI_EXP_DEVCTL, &ctrl);
198*4882a593Smuzhiyun pcie_capability_read_word(pci_dev, PCI_EXP_DEVSTA, &stat);
199*4882a593Smuzhiyun cobalt_info("PCIe device capability 0x%08x: Max payload %d\n",
200*4882a593Smuzhiyun capa, get_payload_size(capa & PCI_EXP_DEVCAP_PAYLOAD));
201*4882a593Smuzhiyun cobalt_info("PCIe device control 0x%04x: Max payload %d. Max read request %d\n",
202*4882a593Smuzhiyun ctrl,
203*4882a593Smuzhiyun get_payload_size((ctrl & PCI_EXP_DEVCTL_PAYLOAD) >> 5),
204*4882a593Smuzhiyun get_payload_size((ctrl & PCI_EXP_DEVCTL_READRQ) >> 12));
205*4882a593Smuzhiyun cobalt_info("PCIe device status 0x%04x\n", stat);
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* Link */
208*4882a593Smuzhiyun pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &capa);
209*4882a593Smuzhiyun pcie_capability_read_word(pci_dev, PCI_EXP_LNKCTL, &ctrl);
210*4882a593Smuzhiyun pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &stat);
211*4882a593Smuzhiyun cobalt_info("PCIe link capability 0x%08x: %s per lane and %u lanes\n",
212*4882a593Smuzhiyun capa, get_link_speed(capa),
213*4882a593Smuzhiyun (capa & PCI_EXP_LNKCAP_MLW) >> 4);
214*4882a593Smuzhiyun cobalt_info("PCIe link control 0x%04x\n", ctrl);
215*4882a593Smuzhiyun cobalt_info("PCIe link status 0x%04x: %s per lane and %u lanes\n",
216*4882a593Smuzhiyun stat, get_link_speed(stat),
217*4882a593Smuzhiyun (stat & PCI_EXP_LNKSTA_NLW) >> 4);
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /* Bus */
220*4882a593Smuzhiyun pcie_capability_read_dword(pci_bus_dev, PCI_EXP_LNKCAP, &capa);
221*4882a593Smuzhiyun cobalt_info("PCIe bus link capability 0x%08x: %s per lane and %u lanes\n",
222*4882a593Smuzhiyun capa, get_link_speed(capa),
223*4882a593Smuzhiyun (capa & PCI_EXP_LNKCAP_MLW) >> 4);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* Slot */
226*4882a593Smuzhiyun pcie_capability_read_dword(pci_dev, PCI_EXP_SLTCAP, &capa);
227*4882a593Smuzhiyun pcie_capability_read_word(pci_dev, PCI_EXP_SLTCTL, &ctrl);
228*4882a593Smuzhiyun pcie_capability_read_word(pci_dev, PCI_EXP_SLTSTA, &stat);
229*4882a593Smuzhiyun cobalt_info("PCIe slot capability 0x%08x\n", capa);
230*4882a593Smuzhiyun cobalt_info("PCIe slot control 0x%04x\n", ctrl);
231*4882a593Smuzhiyun cobalt_info("PCIe slot status 0x%04x\n", stat);
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
pcie_link_get_lanes(struct cobalt * cobalt)234*4882a593Smuzhiyun static unsigned pcie_link_get_lanes(struct cobalt *cobalt)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun struct pci_dev *pci_dev = cobalt->pci_dev;
237*4882a593Smuzhiyun u16 link;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun if (!pci_is_pcie(pci_dev))
240*4882a593Smuzhiyun return 0;
241*4882a593Smuzhiyun pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &link);
242*4882a593Smuzhiyun return (link & PCI_EXP_LNKSTA_NLW) >> 4;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
pcie_bus_link_get_lanes(struct cobalt * cobalt)245*4882a593Smuzhiyun static unsigned pcie_bus_link_get_lanes(struct cobalt *cobalt)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun struct pci_dev *pci_dev = cobalt->pci_dev->bus->self;
248*4882a593Smuzhiyun u32 link;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun if (!pci_is_pcie(pci_dev))
251*4882a593Smuzhiyun return 0;
252*4882a593Smuzhiyun pcie_capability_read_dword(pci_dev, PCI_EXP_LNKCAP, &link);
253*4882a593Smuzhiyun return (link & PCI_EXP_LNKCAP_MLW) >> 4;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
msi_config_show(struct cobalt * cobalt,struct pci_dev * pci_dev)256*4882a593Smuzhiyun static void msi_config_show(struct cobalt *cobalt, struct pci_dev *pci_dev)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun u16 ctrl, data;
259*4882a593Smuzhiyun u32 adrs_l, adrs_h;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun pci_read_config_word(pci_dev, 0x52, &ctrl);
262*4882a593Smuzhiyun cobalt_info("MSI %s\n", ctrl & 1 ? "enable" : "disable");
263*4882a593Smuzhiyun cobalt_info("MSI multiple message: Capable %u. Enable %u\n",
264*4882a593Smuzhiyun (1 << ((ctrl >> 1) & 7)), (1 << ((ctrl >> 4) & 7)));
265*4882a593Smuzhiyun if (ctrl & 0x80)
266*4882a593Smuzhiyun cobalt_info("MSI: 64-bit address capable\n");
267*4882a593Smuzhiyun pci_read_config_dword(pci_dev, 0x54, &adrs_l);
268*4882a593Smuzhiyun pci_read_config_dword(pci_dev, 0x58, &adrs_h);
269*4882a593Smuzhiyun pci_read_config_word(pci_dev, 0x5c, &data);
270*4882a593Smuzhiyun if (ctrl & 0x80)
271*4882a593Smuzhiyun cobalt_info("MSI: Address 0x%08x%08x. Data 0x%04x\n",
272*4882a593Smuzhiyun adrs_h, adrs_l, data);
273*4882a593Smuzhiyun else
274*4882a593Smuzhiyun cobalt_info("MSI: Address 0x%08x. Data 0x%04x\n",
275*4882a593Smuzhiyun adrs_l, data);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
cobalt_pci_iounmap(struct cobalt * cobalt,struct pci_dev * pci_dev)278*4882a593Smuzhiyun static void cobalt_pci_iounmap(struct cobalt *cobalt, struct pci_dev *pci_dev)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun if (cobalt->bar0) {
281*4882a593Smuzhiyun pci_iounmap(pci_dev, cobalt->bar0);
282*4882a593Smuzhiyun cobalt->bar0 = NULL;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun if (cobalt->bar1) {
285*4882a593Smuzhiyun pci_iounmap(pci_dev, cobalt->bar1);
286*4882a593Smuzhiyun cobalt->bar1 = NULL;
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
cobalt_free_msi(struct cobalt * cobalt,struct pci_dev * pci_dev)290*4882a593Smuzhiyun static void cobalt_free_msi(struct cobalt *cobalt, struct pci_dev *pci_dev)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun free_irq(pci_dev->irq, (void *)cobalt);
293*4882a593Smuzhiyun pci_free_irq_vectors(pci_dev);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
cobalt_setup_pci(struct cobalt * cobalt,struct pci_dev * pci_dev,const struct pci_device_id * pci_id)296*4882a593Smuzhiyun static int cobalt_setup_pci(struct cobalt *cobalt, struct pci_dev *pci_dev,
297*4882a593Smuzhiyun const struct pci_device_id *pci_id)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun u32 ctrl;
300*4882a593Smuzhiyun int ret;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun cobalt_dbg(1, "enabling pci device\n");
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun ret = pci_enable_device(pci_dev);
305*4882a593Smuzhiyun if (ret) {
306*4882a593Smuzhiyun cobalt_err("can't enable device\n");
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun pci_set_master(pci_dev);
310*4882a593Smuzhiyun pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &cobalt->card_rev);
311*4882a593Smuzhiyun pci_read_config_word(pci_dev, PCI_DEVICE_ID, &cobalt->device_id);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun switch (cobalt->device_id) {
314*4882a593Smuzhiyun case PCI_DEVICE_ID_COBALT:
315*4882a593Smuzhiyun cobalt_info("PCI Express interface from Omnitek\n");
316*4882a593Smuzhiyun break;
317*4882a593Smuzhiyun default:
318*4882a593Smuzhiyun cobalt_info("PCI Express interface provider is unknown!\n");
319*4882a593Smuzhiyun break;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun if (pcie_link_get_lanes(cobalt) != 8) {
323*4882a593Smuzhiyun cobalt_warn("PCI Express link width is %d lanes.\n",
324*4882a593Smuzhiyun pcie_link_get_lanes(cobalt));
325*4882a593Smuzhiyun if (pcie_bus_link_get_lanes(cobalt) < 8)
326*4882a593Smuzhiyun cobalt_warn("The current slot only supports %d lanes, for best performance 8 are needed\n",
327*4882a593Smuzhiyun pcie_bus_link_get_lanes(cobalt));
328*4882a593Smuzhiyun if (pcie_link_get_lanes(cobalt) != pcie_bus_link_get_lanes(cobalt)) {
329*4882a593Smuzhiyun cobalt_err("The card is most likely not seated correctly in the PCIe slot\n");
330*4882a593Smuzhiyun ret = -EIO;
331*4882a593Smuzhiyun goto err_disable;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) {
336*4882a593Smuzhiyun ret = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
337*4882a593Smuzhiyun if (ret) {
338*4882a593Smuzhiyun cobalt_err("no suitable DMA available\n");
339*4882a593Smuzhiyun goto err_disable;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun ret = pci_request_regions(pci_dev, "cobalt");
344*4882a593Smuzhiyun if (ret) {
345*4882a593Smuzhiyun cobalt_err("error requesting regions\n");
346*4882a593Smuzhiyun goto err_disable;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun cobalt_pcie_status_show(cobalt);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun cobalt->bar0 = pci_iomap(pci_dev, 0, 0);
352*4882a593Smuzhiyun cobalt->bar1 = pci_iomap(pci_dev, 1, 0);
353*4882a593Smuzhiyun if (cobalt->bar1 == NULL) {
354*4882a593Smuzhiyun cobalt->bar1 = pci_iomap(pci_dev, 2, 0);
355*4882a593Smuzhiyun cobalt_info("64-bit BAR\n");
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun if (!cobalt->bar0 || !cobalt->bar1) {
358*4882a593Smuzhiyun ret = -EIO;
359*4882a593Smuzhiyun goto err_release;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /* Reset the video inputs before enabling any interrupts */
363*4882a593Smuzhiyun ctrl = cobalt_read_bar1(cobalt, COBALT_SYS_CTRL_BASE);
364*4882a593Smuzhiyun cobalt_write_bar1(cobalt, COBALT_SYS_CTRL_BASE, ctrl & ~0xf00);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /* Disable interrupts to prevent any spurious interrupts
367*4882a593Smuzhiyun from being generated. */
368*4882a593Smuzhiyun cobalt_set_interrupt(cobalt, false);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (pci_alloc_irq_vectors(pci_dev, 1, 1, PCI_IRQ_MSI) < 1) {
371*4882a593Smuzhiyun cobalt_err("Could not enable MSI\n");
372*4882a593Smuzhiyun ret = -EIO;
373*4882a593Smuzhiyun goto err_release;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun msi_config_show(cobalt, pci_dev);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /* Register IRQ */
378*4882a593Smuzhiyun if (request_irq(pci_dev->irq, cobalt_irq_handler, IRQF_SHARED,
379*4882a593Smuzhiyun cobalt->v4l2_dev.name, (void *)cobalt)) {
380*4882a593Smuzhiyun cobalt_err("Failed to register irq %d\n", pci_dev->irq);
381*4882a593Smuzhiyun ret = -EIO;
382*4882a593Smuzhiyun goto err_msi;
383*4882a593Smuzhiyun }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun omni_sg_dma_init(cobalt);
386*4882a593Smuzhiyun return 0;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun err_msi:
389*4882a593Smuzhiyun pci_disable_msi(pci_dev);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun err_release:
392*4882a593Smuzhiyun cobalt_pci_iounmap(cobalt, pci_dev);
393*4882a593Smuzhiyun pci_release_regions(pci_dev);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun err_disable:
396*4882a593Smuzhiyun pci_disable_device(cobalt->pci_dev);
397*4882a593Smuzhiyun return ret;
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
cobalt_hdl_info_get(struct cobalt * cobalt)400*4882a593Smuzhiyun static int cobalt_hdl_info_get(struct cobalt *cobalt)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun int i;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun for (i = 0; i < COBALT_HDL_INFO_SIZE; i++)
405*4882a593Smuzhiyun cobalt->hdl_info[i] =
406*4882a593Smuzhiyun ioread8(cobalt->bar1 + COBALT_HDL_INFO_BASE + i);
407*4882a593Smuzhiyun cobalt->hdl_info[COBALT_HDL_INFO_SIZE - 1] = '\0';
408*4882a593Smuzhiyun if (strstr(cobalt->hdl_info, COBALT_HDL_SEARCH_STR))
409*4882a593Smuzhiyun return 0;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun return 1;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
cobalt_stream_struct_init(struct cobalt * cobalt)414*4882a593Smuzhiyun static void cobalt_stream_struct_init(struct cobalt *cobalt)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun int i;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun for (i = 0; i < COBALT_NUM_STREAMS; i++) {
419*4882a593Smuzhiyun struct cobalt_stream *s = &cobalt->streams[i];
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun s->cobalt = cobalt;
422*4882a593Smuzhiyun s->flags = 0;
423*4882a593Smuzhiyun s->is_audio = false;
424*4882a593Smuzhiyun s->is_output = false;
425*4882a593Smuzhiyun s->is_dummy = true;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun /* The Memory DMA channels will always get a lower channel
428*4882a593Smuzhiyun * number than the FIFO DMA. Video input should map to the
429*4882a593Smuzhiyun * stream 0-3. The other can use stream struct from 4 and
430*4882a593Smuzhiyun * higher */
431*4882a593Smuzhiyun if (i <= COBALT_HSMA_IN_NODE) {
432*4882a593Smuzhiyun s->dma_channel = i + cobalt->first_fifo_channel;
433*4882a593Smuzhiyun s->video_channel = i;
434*4882a593Smuzhiyun s->dma_fifo_mask =
435*4882a593Smuzhiyun COBALT_SYSSTAT_VI0_LOST_DATA_MSK << (4 * i);
436*4882a593Smuzhiyun s->adv_irq_mask =
437*4882a593Smuzhiyun COBALT_SYSSTAT_VI0_INT1_MSK << (4 * i);
438*4882a593Smuzhiyun } else if (i >= COBALT_AUDIO_IN_STREAM &&
439*4882a593Smuzhiyun i <= COBALT_AUDIO_IN_STREAM + 4) {
440*4882a593Smuzhiyun unsigned idx = i - COBALT_AUDIO_IN_STREAM;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun s->dma_channel = 6 + idx;
443*4882a593Smuzhiyun s->is_audio = true;
444*4882a593Smuzhiyun s->video_channel = idx;
445*4882a593Smuzhiyun s->dma_fifo_mask = COBALT_SYSSTAT_AUD_IN_LOST_DATA_MSK;
446*4882a593Smuzhiyun } else if (i == COBALT_HSMA_OUT_NODE) {
447*4882a593Smuzhiyun s->dma_channel = 11;
448*4882a593Smuzhiyun s->is_output = true;
449*4882a593Smuzhiyun s->video_channel = 5;
450*4882a593Smuzhiyun s->dma_fifo_mask = COBALT_SYSSTAT_VOHSMA_LOST_DATA_MSK;
451*4882a593Smuzhiyun s->adv_irq_mask = COBALT_SYSSTAT_VOHSMA_INT1_MSK;
452*4882a593Smuzhiyun } else if (i == COBALT_AUDIO_OUT_STREAM) {
453*4882a593Smuzhiyun s->dma_channel = 12;
454*4882a593Smuzhiyun s->is_audio = true;
455*4882a593Smuzhiyun s->is_output = true;
456*4882a593Smuzhiyun s->video_channel = 5;
457*4882a593Smuzhiyun s->dma_fifo_mask = COBALT_SYSSTAT_AUD_OUT_LOST_DATA_MSK;
458*4882a593Smuzhiyun } else {
459*4882a593Smuzhiyun /* FIXME: Memory DMA for debug purpose */
460*4882a593Smuzhiyun s->dma_channel = i - COBALT_NUM_NODES;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun cobalt_info("stream #%d -> dma channel #%d <- video channel %d\n",
463*4882a593Smuzhiyun i, s->dma_channel, s->video_channel);
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
cobalt_subdevs_init(struct cobalt * cobalt)467*4882a593Smuzhiyun static int cobalt_subdevs_init(struct cobalt *cobalt)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun static struct adv76xx_platform_data adv7604_pdata = {
470*4882a593Smuzhiyun .disable_pwrdnb = 1,
471*4882a593Smuzhiyun .ain_sel = ADV7604_AIN7_8_9_NC_SYNC_3_1,
472*4882a593Smuzhiyun .bus_order = ADV7604_BUS_ORDER_BRG,
473*4882a593Smuzhiyun .blank_data = 1,
474*4882a593Smuzhiyun .op_format_mode_sel = ADV7604_OP_FORMAT_MODE0,
475*4882a593Smuzhiyun .int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH,
476*4882a593Smuzhiyun .dr_str_data = ADV76XX_DR_STR_HIGH,
477*4882a593Smuzhiyun .dr_str_clk = ADV76XX_DR_STR_HIGH,
478*4882a593Smuzhiyun .dr_str_sync = ADV76XX_DR_STR_HIGH,
479*4882a593Smuzhiyun .hdmi_free_run_mode = 1,
480*4882a593Smuzhiyun .inv_vs_pol = 1,
481*4882a593Smuzhiyun .inv_hs_pol = 1,
482*4882a593Smuzhiyun };
483*4882a593Smuzhiyun static struct i2c_board_info adv7604_info = {
484*4882a593Smuzhiyun .type = "adv7604",
485*4882a593Smuzhiyun .addr = 0x20,
486*4882a593Smuzhiyun .platform_data = &adv7604_pdata,
487*4882a593Smuzhiyun };
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun struct cobalt_stream *s = cobalt->streams;
490*4882a593Smuzhiyun int i;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun for (i = 0; i < COBALT_NUM_INPUTS; i++) {
493*4882a593Smuzhiyun struct v4l2_subdev_format sd_fmt = {
494*4882a593Smuzhiyun .pad = ADV7604_PAD_SOURCE,
495*4882a593Smuzhiyun .which = V4L2_SUBDEV_FORMAT_ACTIVE,
496*4882a593Smuzhiyun .format.code = MEDIA_BUS_FMT_YUYV8_1X16,
497*4882a593Smuzhiyun };
498*4882a593Smuzhiyun struct v4l2_subdev_edid cobalt_edid = {
499*4882a593Smuzhiyun .pad = ADV76XX_PAD_HDMI_PORT_A,
500*4882a593Smuzhiyun .start_block = 0,
501*4882a593Smuzhiyun .blocks = 2,
502*4882a593Smuzhiyun .edid = edid,
503*4882a593Smuzhiyun };
504*4882a593Smuzhiyun int err;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun s[i].pad_source = ADV7604_PAD_SOURCE;
507*4882a593Smuzhiyun s[i].i2c_adap = &cobalt->i2c_adap[i];
508*4882a593Smuzhiyun if (s[i].i2c_adap->dev.parent == NULL)
509*4882a593Smuzhiyun continue;
510*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
511*4882a593Smuzhiyun COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(i), 1);
512*4882a593Smuzhiyun s[i].sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
513*4882a593Smuzhiyun s[i].i2c_adap, &adv7604_info, NULL);
514*4882a593Smuzhiyun if (!s[i].sd) {
515*4882a593Smuzhiyun if (cobalt_ignore_err)
516*4882a593Smuzhiyun continue;
517*4882a593Smuzhiyun return -ENODEV;
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun err = v4l2_subdev_call(s[i].sd, video, s_routing,
520*4882a593Smuzhiyun ADV76XX_PAD_HDMI_PORT_A, 0, 0);
521*4882a593Smuzhiyun if (err)
522*4882a593Smuzhiyun return err;
523*4882a593Smuzhiyun err = v4l2_subdev_call(s[i].sd, pad, set_edid,
524*4882a593Smuzhiyun &cobalt_edid);
525*4882a593Smuzhiyun if (err)
526*4882a593Smuzhiyun return err;
527*4882a593Smuzhiyun err = v4l2_subdev_call(s[i].sd, pad, set_fmt, NULL,
528*4882a593Smuzhiyun &sd_fmt);
529*4882a593Smuzhiyun if (err)
530*4882a593Smuzhiyun return err;
531*4882a593Smuzhiyun /* Reset channel video module */
532*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
533*4882a593Smuzhiyun COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(i), 0);
534*4882a593Smuzhiyun mdelay(2);
535*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
536*4882a593Smuzhiyun COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(i), 1);
537*4882a593Smuzhiyun mdelay(1);
538*4882a593Smuzhiyun s[i].is_dummy = false;
539*4882a593Smuzhiyun cobalt->streams[i + COBALT_AUDIO_IN_STREAM].is_dummy = false;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun return 0;
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
cobalt_subdevs_hsma_init(struct cobalt * cobalt)544*4882a593Smuzhiyun static int cobalt_subdevs_hsma_init(struct cobalt *cobalt)
545*4882a593Smuzhiyun {
546*4882a593Smuzhiyun static struct adv7842_platform_data adv7842_pdata = {
547*4882a593Smuzhiyun .disable_pwrdnb = 1,
548*4882a593Smuzhiyun .ain_sel = ADV7842_AIN1_2_3_NC_SYNC_1_2,
549*4882a593Smuzhiyun .bus_order = ADV7842_BUS_ORDER_RBG,
550*4882a593Smuzhiyun .op_format_mode_sel = ADV7842_OP_FORMAT_MODE0,
551*4882a593Smuzhiyun .blank_data = 1,
552*4882a593Smuzhiyun .dr_str_data = 3,
553*4882a593Smuzhiyun .dr_str_clk = 3,
554*4882a593Smuzhiyun .dr_str_sync = 3,
555*4882a593Smuzhiyun .mode = ADV7842_MODE_HDMI,
556*4882a593Smuzhiyun .hdmi_free_run_enable = 1,
557*4882a593Smuzhiyun .vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P,
558*4882a593Smuzhiyun .i2c_sdp_io = 0x4a,
559*4882a593Smuzhiyun .i2c_sdp = 0x48,
560*4882a593Smuzhiyun .i2c_cp = 0x22,
561*4882a593Smuzhiyun .i2c_vdp = 0x24,
562*4882a593Smuzhiyun .i2c_afe = 0x26,
563*4882a593Smuzhiyun .i2c_hdmi = 0x34,
564*4882a593Smuzhiyun .i2c_repeater = 0x32,
565*4882a593Smuzhiyun .i2c_edid = 0x36,
566*4882a593Smuzhiyun .i2c_infoframe = 0x3e,
567*4882a593Smuzhiyun .i2c_cec = 0x40,
568*4882a593Smuzhiyun .i2c_avlink = 0x42,
569*4882a593Smuzhiyun };
570*4882a593Smuzhiyun static struct i2c_board_info adv7842_info = {
571*4882a593Smuzhiyun .type = "adv7842",
572*4882a593Smuzhiyun .addr = 0x20,
573*4882a593Smuzhiyun .platform_data = &adv7842_pdata,
574*4882a593Smuzhiyun };
575*4882a593Smuzhiyun static struct v4l2_subdev_format sd_fmt = {
576*4882a593Smuzhiyun .pad = ADV7842_PAD_SOURCE,
577*4882a593Smuzhiyun .which = V4L2_SUBDEV_FORMAT_ACTIVE,
578*4882a593Smuzhiyun .format.code = MEDIA_BUS_FMT_YUYV8_1X16,
579*4882a593Smuzhiyun };
580*4882a593Smuzhiyun static struct adv7511_platform_data adv7511_pdata = {
581*4882a593Smuzhiyun .i2c_edid = 0x7e >> 1,
582*4882a593Smuzhiyun .i2c_cec = 0x7c >> 1,
583*4882a593Smuzhiyun .i2c_pktmem = 0x70 >> 1,
584*4882a593Smuzhiyun .cec_clk = 12000000,
585*4882a593Smuzhiyun };
586*4882a593Smuzhiyun static struct i2c_board_info adv7511_info = {
587*4882a593Smuzhiyun .type = "adv7511-v4l2",
588*4882a593Smuzhiyun .addr = 0x39, /* 0x39 or 0x3d */
589*4882a593Smuzhiyun .platform_data = &adv7511_pdata,
590*4882a593Smuzhiyun };
591*4882a593Smuzhiyun struct v4l2_subdev_edid cobalt_edid = {
592*4882a593Smuzhiyun .pad = ADV7842_EDID_PORT_A,
593*4882a593Smuzhiyun .start_block = 0,
594*4882a593Smuzhiyun .blocks = 2,
595*4882a593Smuzhiyun .edid = edid,
596*4882a593Smuzhiyun };
597*4882a593Smuzhiyun struct cobalt_stream *s = &cobalt->streams[COBALT_HSMA_IN_NODE];
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun s->i2c_adap = &cobalt->i2c_adap[COBALT_NUM_ADAPTERS - 1];
600*4882a593Smuzhiyun if (s->i2c_adap->dev.parent == NULL)
601*4882a593Smuzhiyun return 0;
602*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(4), 1);
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun s->sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
605*4882a593Smuzhiyun s->i2c_adap, &adv7842_info, NULL);
606*4882a593Smuzhiyun if (s->sd) {
607*4882a593Smuzhiyun int err = v4l2_subdev_call(s->sd, pad, set_edid, &cobalt_edid);
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun if (err)
610*4882a593Smuzhiyun return err;
611*4882a593Smuzhiyun err = v4l2_subdev_call(s->sd, pad, set_fmt, NULL,
612*4882a593Smuzhiyun &sd_fmt);
613*4882a593Smuzhiyun if (err)
614*4882a593Smuzhiyun return err;
615*4882a593Smuzhiyun cobalt->have_hsma_rx = true;
616*4882a593Smuzhiyun s->pad_source = ADV7842_PAD_SOURCE;
617*4882a593Smuzhiyun s->is_dummy = false;
618*4882a593Smuzhiyun cobalt->streams[4 + COBALT_AUDIO_IN_STREAM].is_dummy = false;
619*4882a593Smuzhiyun /* Reset channel video module */
620*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
621*4882a593Smuzhiyun COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 0);
622*4882a593Smuzhiyun mdelay(2);
623*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
624*4882a593Smuzhiyun COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 1);
625*4882a593Smuzhiyun mdelay(1);
626*4882a593Smuzhiyun return err;
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_NRESET_TO_HDMI_BIT(4), 0);
629*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_PWRDN0_TO_HSMA_TX_BIT, 0);
630*4882a593Smuzhiyun s++;
631*4882a593Smuzhiyun s->i2c_adap = &cobalt->i2c_adap[COBALT_NUM_ADAPTERS - 1];
632*4882a593Smuzhiyun s->sd = v4l2_i2c_new_subdev_board(&cobalt->v4l2_dev,
633*4882a593Smuzhiyun s->i2c_adap, &adv7511_info, NULL);
634*4882a593Smuzhiyun if (s->sd) {
635*4882a593Smuzhiyun /* A transmitter is hooked up, so we can set this bit */
636*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
637*4882a593Smuzhiyun COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 1);
638*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
639*4882a593Smuzhiyun COBALT_SYS_CTRL_VIDEO_RX_RESETN_BIT(4), 0);
640*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt,
641*4882a593Smuzhiyun COBALT_SYS_CTRL_VIDEO_TX_RESETN_BIT, 1);
642*4882a593Smuzhiyun cobalt->have_hsma_tx = true;
643*4882a593Smuzhiyun v4l2_subdev_call(s->sd, core, s_power, 1);
644*4882a593Smuzhiyun v4l2_subdev_call(s->sd, video, s_stream, 1);
645*4882a593Smuzhiyun v4l2_subdev_call(s->sd, audio, s_stream, 1);
646*4882a593Smuzhiyun v4l2_ctrl_s_ctrl(v4l2_ctrl_find(s->sd->ctrl_handler,
647*4882a593Smuzhiyun V4L2_CID_DV_TX_MODE), V4L2_DV_TX_MODE_HDMI);
648*4882a593Smuzhiyun s->is_dummy = false;
649*4882a593Smuzhiyun cobalt->streams[COBALT_AUDIO_OUT_STREAM].is_dummy = false;
650*4882a593Smuzhiyun return 0;
651*4882a593Smuzhiyun }
652*4882a593Smuzhiyun return -ENODEV;
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun
cobalt_probe(struct pci_dev * pci_dev,const struct pci_device_id * pci_id)655*4882a593Smuzhiyun static int cobalt_probe(struct pci_dev *pci_dev,
656*4882a593Smuzhiyun const struct pci_device_id *pci_id)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun struct cobalt *cobalt;
659*4882a593Smuzhiyun int retval = 0;
660*4882a593Smuzhiyun int i;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun /* FIXME - module parameter arrays constrain max instances */
663*4882a593Smuzhiyun i = atomic_inc_return(&cobalt_instance) - 1;
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun cobalt = kzalloc(sizeof(struct cobalt), GFP_KERNEL);
666*4882a593Smuzhiyun if (cobalt == NULL)
667*4882a593Smuzhiyun return -ENOMEM;
668*4882a593Smuzhiyun cobalt->pci_dev = pci_dev;
669*4882a593Smuzhiyun cobalt->instance = i;
670*4882a593Smuzhiyun mutex_init(&cobalt->pci_lock);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun retval = v4l2_device_register(&pci_dev->dev, &cobalt->v4l2_dev);
673*4882a593Smuzhiyun if (retval) {
674*4882a593Smuzhiyun pr_err("cobalt: v4l2_device_register of card %d failed\n",
675*4882a593Smuzhiyun cobalt->instance);
676*4882a593Smuzhiyun kfree(cobalt);
677*4882a593Smuzhiyun return retval;
678*4882a593Smuzhiyun }
679*4882a593Smuzhiyun snprintf(cobalt->v4l2_dev.name, sizeof(cobalt->v4l2_dev.name),
680*4882a593Smuzhiyun "cobalt-%d", cobalt->instance);
681*4882a593Smuzhiyun cobalt->v4l2_dev.notify = cobalt_notify;
682*4882a593Smuzhiyun cobalt_info("Initializing card %d\n", cobalt->instance);
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun cobalt->irq_work_queues =
685*4882a593Smuzhiyun create_singlethread_workqueue(cobalt->v4l2_dev.name);
686*4882a593Smuzhiyun if (cobalt->irq_work_queues == NULL) {
687*4882a593Smuzhiyun cobalt_err("Could not create workqueue\n");
688*4882a593Smuzhiyun retval = -ENOMEM;
689*4882a593Smuzhiyun goto err;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun INIT_WORK(&cobalt->irq_work_queue, cobalt_irq_work_handler);
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun /* PCI Device Setup */
695*4882a593Smuzhiyun retval = cobalt_setup_pci(cobalt, pci_dev, pci_id);
696*4882a593Smuzhiyun if (retval != 0)
697*4882a593Smuzhiyun goto err_wq;
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun /* Show HDL version info */
700*4882a593Smuzhiyun if (cobalt_hdl_info_get(cobalt))
701*4882a593Smuzhiyun cobalt_info("Not able to read the HDL info\n");
702*4882a593Smuzhiyun else
703*4882a593Smuzhiyun cobalt_info("%s", cobalt->hdl_info);
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun retval = cobalt_i2c_init(cobalt);
706*4882a593Smuzhiyun if (retval)
707*4882a593Smuzhiyun goto err_pci;
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun cobalt_stream_struct_init(cobalt);
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun retval = cobalt_subdevs_init(cobalt);
712*4882a593Smuzhiyun if (retval)
713*4882a593Smuzhiyun goto err_i2c;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun if (!(cobalt_read_bar1(cobalt, COBALT_SYS_STAT_BASE) &
716*4882a593Smuzhiyun COBALT_SYSSTAT_HSMA_PRSNTN_MSK)) {
717*4882a593Smuzhiyun retval = cobalt_subdevs_hsma_init(cobalt);
718*4882a593Smuzhiyun if (retval)
719*4882a593Smuzhiyun goto err_i2c;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun retval = cobalt_nodes_register(cobalt);
723*4882a593Smuzhiyun if (retval) {
724*4882a593Smuzhiyun cobalt_err("Error %d registering device nodes\n", retval);
725*4882a593Smuzhiyun goto err_i2c;
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun cobalt_set_interrupt(cobalt, true);
728*4882a593Smuzhiyun v4l2_device_call_all(&cobalt->v4l2_dev, 0, core,
729*4882a593Smuzhiyun interrupt_service_routine, 0, NULL);
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun cobalt_info("Initialized cobalt card\n");
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun cobalt_flash_probe(cobalt);
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun return 0;
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun err_i2c:
738*4882a593Smuzhiyun cobalt_i2c_exit(cobalt);
739*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 0);
740*4882a593Smuzhiyun err_pci:
741*4882a593Smuzhiyun cobalt_free_msi(cobalt, pci_dev);
742*4882a593Smuzhiyun cobalt_pci_iounmap(cobalt, pci_dev);
743*4882a593Smuzhiyun pci_release_regions(cobalt->pci_dev);
744*4882a593Smuzhiyun pci_disable_device(cobalt->pci_dev);
745*4882a593Smuzhiyun err_wq:
746*4882a593Smuzhiyun destroy_workqueue(cobalt->irq_work_queues);
747*4882a593Smuzhiyun err:
748*4882a593Smuzhiyun cobalt_err("error %d on initialization\n", retval);
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun v4l2_device_unregister(&cobalt->v4l2_dev);
751*4882a593Smuzhiyun kfree(cobalt);
752*4882a593Smuzhiyun return retval;
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun
cobalt_remove(struct pci_dev * pci_dev)755*4882a593Smuzhiyun static void cobalt_remove(struct pci_dev *pci_dev)
756*4882a593Smuzhiyun {
757*4882a593Smuzhiyun struct v4l2_device *v4l2_dev = pci_get_drvdata(pci_dev);
758*4882a593Smuzhiyun struct cobalt *cobalt = to_cobalt(v4l2_dev);
759*4882a593Smuzhiyun int i;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun cobalt_flash_remove(cobalt);
762*4882a593Smuzhiyun cobalt_set_interrupt(cobalt, false);
763*4882a593Smuzhiyun flush_workqueue(cobalt->irq_work_queues);
764*4882a593Smuzhiyun cobalt_nodes_unregister(cobalt);
765*4882a593Smuzhiyun for (i = 0; i < COBALT_NUM_ADAPTERS; i++) {
766*4882a593Smuzhiyun struct v4l2_subdev *sd = cobalt->streams[i].sd;
767*4882a593Smuzhiyun struct i2c_client *client;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun if (sd == NULL)
770*4882a593Smuzhiyun continue;
771*4882a593Smuzhiyun client = v4l2_get_subdevdata(sd);
772*4882a593Smuzhiyun v4l2_device_unregister_subdev(sd);
773*4882a593Smuzhiyun i2c_unregister_device(client);
774*4882a593Smuzhiyun }
775*4882a593Smuzhiyun cobalt_i2c_exit(cobalt);
776*4882a593Smuzhiyun cobalt_free_msi(cobalt, pci_dev);
777*4882a593Smuzhiyun cobalt_s_bit_sysctrl(cobalt, COBALT_SYS_CTRL_HSMA_TX_ENABLE_BIT, 0);
778*4882a593Smuzhiyun cobalt_pci_iounmap(cobalt, pci_dev);
779*4882a593Smuzhiyun pci_release_regions(cobalt->pci_dev);
780*4882a593Smuzhiyun pci_disable_device(cobalt->pci_dev);
781*4882a593Smuzhiyun destroy_workqueue(cobalt->irq_work_queues);
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun cobalt_info("removed cobalt card\n");
784*4882a593Smuzhiyun
785*4882a593Smuzhiyun v4l2_device_unregister(v4l2_dev);
786*4882a593Smuzhiyun kfree(cobalt);
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun /* define a pci_driver for card detection */
790*4882a593Smuzhiyun static struct pci_driver cobalt_pci_driver = {
791*4882a593Smuzhiyun .name = "cobalt",
792*4882a593Smuzhiyun .id_table = cobalt_pci_tbl,
793*4882a593Smuzhiyun .probe = cobalt_probe,
794*4882a593Smuzhiyun .remove = cobalt_remove,
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun module_pci_driver(cobalt_pci_driver);
798