1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * wm8739
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2005 T. Adachi <tadachi@tadachi-net.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2005 Hans Verkuil <hverkuil@xs4all.nl>
8*4882a593Smuzhiyun * - Cleanup
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/types.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/ioctl.h>
15*4882a593Smuzhiyun #include <linux/uaccess.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/videodev2.h>
18*4882a593Smuzhiyun #include <media/v4l2-device.h>
19*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun MODULE_DESCRIPTION("wm8739 driver");
22*4882a593Smuzhiyun MODULE_AUTHOR("T. Adachi, Hans Verkuil");
23*4882a593Smuzhiyun MODULE_LICENSE("GPL");
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static int debug;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun module_param(debug, int, 0644);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level (0-1)");
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun enum {
35*4882a593Smuzhiyun R0 = 0, R1,
36*4882a593Smuzhiyun R5 = 5, R6, R7, R8, R9, R15 = 15,
37*4882a593Smuzhiyun TOT_REGS
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct wm8739_state {
41*4882a593Smuzhiyun struct v4l2_subdev sd;
42*4882a593Smuzhiyun struct v4l2_ctrl_handler hdl;
43*4882a593Smuzhiyun struct {
44*4882a593Smuzhiyun /* audio cluster */
45*4882a593Smuzhiyun struct v4l2_ctrl *volume;
46*4882a593Smuzhiyun struct v4l2_ctrl *mute;
47*4882a593Smuzhiyun struct v4l2_ctrl *balance;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun u32 clock_freq;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
to_state(struct v4l2_subdev * sd)52*4882a593Smuzhiyun static inline struct wm8739_state *to_state(struct v4l2_subdev *sd)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun return container_of(sd, struct wm8739_state, sd);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
to_sd(struct v4l2_ctrl * ctrl)57*4882a593Smuzhiyun static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun return &container_of(ctrl->handler, struct wm8739_state, hdl)->sd;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
63*4882a593Smuzhiyun
wm8739_write(struct v4l2_subdev * sd,int reg,u16 val)64*4882a593Smuzhiyun static int wm8739_write(struct v4l2_subdev *sd, int reg, u16 val)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
67*4882a593Smuzhiyun int i;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (reg < 0 || reg >= TOT_REGS) {
70*4882a593Smuzhiyun v4l2_err(sd, "Invalid register R%d\n", reg);
71*4882a593Smuzhiyun return -1;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "write: %02x %02x\n", reg, val);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun for (i = 0; i < 3; i++)
77*4882a593Smuzhiyun if (i2c_smbus_write_byte_data(client,
78*4882a593Smuzhiyun (reg << 1) | (val >> 8), val & 0xff) == 0)
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun v4l2_err(sd, "I2C: cannot write %03x to register R%d\n", val, reg);
81*4882a593Smuzhiyun return -1;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
wm8739_s_ctrl(struct v4l2_ctrl * ctrl)84*4882a593Smuzhiyun static int wm8739_s_ctrl(struct v4l2_ctrl *ctrl)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct v4l2_subdev *sd = to_sd(ctrl);
87*4882a593Smuzhiyun struct wm8739_state *state = to_state(sd);
88*4882a593Smuzhiyun unsigned int work_l, work_r;
89*4882a593Smuzhiyun u8 vol_l; /* +12dB to -34.5dB 1.5dB step (5bit) def:0dB */
90*4882a593Smuzhiyun u8 vol_r; /* +12dB to -34.5dB 1.5dB step (5bit) def:0dB */
91*4882a593Smuzhiyun u16 mute;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun switch (ctrl->id) {
94*4882a593Smuzhiyun case V4L2_CID_AUDIO_VOLUME:
95*4882a593Smuzhiyun break;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun default:
98*4882a593Smuzhiyun return -EINVAL;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /* normalize ( 65535 to 0 -> 31 to 0 (12dB to -34.5dB) ) */
102*4882a593Smuzhiyun work_l = (min(65536 - state->balance->val, 32768) * state->volume->val) / 32768;
103*4882a593Smuzhiyun work_r = (min(state->balance->val, 32768) * state->volume->val) / 32768;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun vol_l = (long)work_l * 31 / 65535;
106*4882a593Smuzhiyun vol_r = (long)work_r * 31 / 65535;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* set audio volume etc. */
109*4882a593Smuzhiyun mute = state->mute->val ? 0x80 : 0;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* Volume setting: bits 0-4, 0x1f = 12 dB, 0x00 = -34.5 dB
112*4882a593Smuzhiyun * Default setting: 0x17 = 0 dB
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun wm8739_write(sd, R0, (vol_l & 0x1f) | mute);
115*4882a593Smuzhiyun wm8739_write(sd, R1, (vol_r & 0x1f) | mute);
116*4882a593Smuzhiyun return 0;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
120*4882a593Smuzhiyun
wm8739_s_clock_freq(struct v4l2_subdev * sd,u32 audiofreq)121*4882a593Smuzhiyun static int wm8739_s_clock_freq(struct v4l2_subdev *sd, u32 audiofreq)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct wm8739_state *state = to_state(sd);
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun state->clock_freq = audiofreq;
126*4882a593Smuzhiyun /* de-activate */
127*4882a593Smuzhiyun wm8739_write(sd, R9, 0x000);
128*4882a593Smuzhiyun switch (audiofreq) {
129*4882a593Smuzhiyun case 44100:
130*4882a593Smuzhiyun /* 256fps, fs=44.1k */
131*4882a593Smuzhiyun wm8739_write(sd, R8, 0x020);
132*4882a593Smuzhiyun break;
133*4882a593Smuzhiyun case 48000:
134*4882a593Smuzhiyun /* 256fps, fs=48k */
135*4882a593Smuzhiyun wm8739_write(sd, R8, 0x000);
136*4882a593Smuzhiyun break;
137*4882a593Smuzhiyun case 32000:
138*4882a593Smuzhiyun /* 256fps, fs=32k */
139*4882a593Smuzhiyun wm8739_write(sd, R8, 0x018);
140*4882a593Smuzhiyun break;
141*4882a593Smuzhiyun default:
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun /* activate */
145*4882a593Smuzhiyun wm8739_write(sd, R9, 0x001);
146*4882a593Smuzhiyun return 0;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
wm8739_log_status(struct v4l2_subdev * sd)149*4882a593Smuzhiyun static int wm8739_log_status(struct v4l2_subdev *sd)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun struct wm8739_state *state = to_state(sd);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun v4l2_info(sd, "Frequency: %u Hz\n", state->clock_freq);
154*4882a593Smuzhiyun v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
155*4882a593Smuzhiyun return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static const struct v4l2_ctrl_ops wm8739_ctrl_ops = {
161*4882a593Smuzhiyun .s_ctrl = wm8739_s_ctrl,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops wm8739_core_ops = {
165*4882a593Smuzhiyun .log_status = wm8739_log_status,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun static const struct v4l2_subdev_audio_ops wm8739_audio_ops = {
169*4882a593Smuzhiyun .s_clock_freq = wm8739_s_clock_freq,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun static const struct v4l2_subdev_ops wm8739_ops = {
173*4882a593Smuzhiyun .core = &wm8739_core_ops,
174*4882a593Smuzhiyun .audio = &wm8739_audio_ops,
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /* i2c implementation */
180*4882a593Smuzhiyun
wm8739_probe(struct i2c_client * client,const struct i2c_device_id * id)181*4882a593Smuzhiyun static int wm8739_probe(struct i2c_client *client,
182*4882a593Smuzhiyun const struct i2c_device_id *id)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun struct wm8739_state *state;
185*4882a593Smuzhiyun struct v4l2_subdev *sd;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* Check if the adapter supports the needed features */
188*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
189*4882a593Smuzhiyun return -EIO;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun v4l_info(client, "chip found @ 0x%x (%s)\n",
192*4882a593Smuzhiyun client->addr << 1, client->adapter->name);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
195*4882a593Smuzhiyun if (state == NULL)
196*4882a593Smuzhiyun return -ENOMEM;
197*4882a593Smuzhiyun sd = &state->sd;
198*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &wm8739_ops);
199*4882a593Smuzhiyun v4l2_ctrl_handler_init(&state->hdl, 2);
200*4882a593Smuzhiyun state->volume = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops,
201*4882a593Smuzhiyun V4L2_CID_AUDIO_VOLUME, 0, 65535, 65535 / 100, 50736);
202*4882a593Smuzhiyun state->mute = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops,
203*4882a593Smuzhiyun V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
204*4882a593Smuzhiyun state->balance = v4l2_ctrl_new_std(&state->hdl, &wm8739_ctrl_ops,
205*4882a593Smuzhiyun V4L2_CID_AUDIO_BALANCE, 0, 65535, 65535 / 100, 32768);
206*4882a593Smuzhiyun sd->ctrl_handler = &state->hdl;
207*4882a593Smuzhiyun if (state->hdl.error) {
208*4882a593Smuzhiyun int err = state->hdl.error;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun v4l2_ctrl_handler_free(&state->hdl);
211*4882a593Smuzhiyun return err;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun v4l2_ctrl_cluster(3, &state->volume);
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun state->clock_freq = 48000;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* Initialize wm8739 */
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /* reset */
220*4882a593Smuzhiyun wm8739_write(sd, R15, 0x00);
221*4882a593Smuzhiyun /* filter setting, high path, offet clear */
222*4882a593Smuzhiyun wm8739_write(sd, R5, 0x000);
223*4882a593Smuzhiyun /* ADC, OSC, Power Off mode Disable */
224*4882a593Smuzhiyun wm8739_write(sd, R6, 0x000);
225*4882a593Smuzhiyun /* Digital Audio interface format:
226*4882a593Smuzhiyun Enable Master mode, 24 bit, MSB first/left justified */
227*4882a593Smuzhiyun wm8739_write(sd, R7, 0x049);
228*4882a593Smuzhiyun /* sampling control: normal, 256fs, 48KHz sampling rate */
229*4882a593Smuzhiyun wm8739_write(sd, R8, 0x000);
230*4882a593Smuzhiyun /* activate */
231*4882a593Smuzhiyun wm8739_write(sd, R9, 0x001);
232*4882a593Smuzhiyun /* set volume/mute */
233*4882a593Smuzhiyun v4l2_ctrl_handler_setup(&state->hdl);
234*4882a593Smuzhiyun return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
wm8739_remove(struct i2c_client * client)237*4882a593Smuzhiyun static int wm8739_remove(struct i2c_client *client)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
240*4882a593Smuzhiyun struct wm8739_state *state = to_state(sd);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun v4l2_device_unregister_subdev(sd);
243*4882a593Smuzhiyun v4l2_ctrl_handler_free(&state->hdl);
244*4882a593Smuzhiyun return 0;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun static const struct i2c_device_id wm8739_id[] = {
248*4882a593Smuzhiyun { "wm8739", 0 },
249*4882a593Smuzhiyun { }
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, wm8739_id);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun static struct i2c_driver wm8739_driver = {
254*4882a593Smuzhiyun .driver = {
255*4882a593Smuzhiyun .name = "wm8739",
256*4882a593Smuzhiyun },
257*4882a593Smuzhiyun .probe = wm8739_probe,
258*4882a593Smuzhiyun .remove = wm8739_remove,
259*4882a593Smuzhiyun .id_table = wm8739_id,
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun module_i2c_driver(wm8739_driver);
263