xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/upd64031a.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * upd64031A - NEC Electronics Ghost Reduction for NTSC in Japan
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * 2003 by T.Adachi <tadachi@tadachi-net.com>
6*4882a593Smuzhiyun  * 2003 by Takeru KOMORIYA <komoriya@paken.org>
7*4882a593Smuzhiyun  * 2006 by Hans Verkuil <hverkuil@xs4all.nl>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/videodev2.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <media/v4l2-device.h>
17*4882a593Smuzhiyun #include <media/i2c/upd64031a.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /* --------------------- read registers functions define -------------------- */
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun /* bit masks */
22*4882a593Smuzhiyun #define GR_MODE_MASK              0xc0
23*4882a593Smuzhiyun #define DIRECT_3DYCS_CONNECT_MASK 0xc0
24*4882a593Smuzhiyun #define SYNC_CIRCUIT_MASK         0xa0
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /* -------------------------------------------------------------------------- */
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun MODULE_DESCRIPTION("uPD64031A driver");
29*4882a593Smuzhiyun MODULE_AUTHOR("T. Adachi, Takeru KOMORIYA, Hans Verkuil");
30*4882a593Smuzhiyun MODULE_LICENSE("GPL");
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static int debug;
33*4882a593Smuzhiyun module_param(debug, int, 0644);
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level (0-1)");
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun enum {
39*4882a593Smuzhiyun 	R00 = 0, R01, R02, R03, R04,
40*4882a593Smuzhiyun 	R05, R06, R07, R08, R09,
41*4882a593Smuzhiyun 	R0A, R0B, R0C, R0D, R0E, R0F,
42*4882a593Smuzhiyun 	/* unused registers
43*4882a593Smuzhiyun 	 R10, R11, R12, R13, R14,
44*4882a593Smuzhiyun 	 R15, R16, R17,
45*4882a593Smuzhiyun 	 */
46*4882a593Smuzhiyun 	TOT_REGS
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun struct upd64031a_state {
50*4882a593Smuzhiyun 	struct v4l2_subdev sd;
51*4882a593Smuzhiyun 	u8 regs[TOT_REGS];
52*4882a593Smuzhiyun 	u8 gr_mode;
53*4882a593Smuzhiyun 	u8 direct_3dycs_connect;
54*4882a593Smuzhiyun 	u8 ext_comp_sync;
55*4882a593Smuzhiyun 	u8 ext_vert_sync;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
to_state(struct v4l2_subdev * sd)58*4882a593Smuzhiyun static inline struct upd64031a_state *to_state(struct v4l2_subdev *sd)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	return container_of(sd, struct upd64031a_state, sd);
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun static u8 upd64031a_init[] = {
64*4882a593Smuzhiyun 	0x00, 0xb8, 0x48, 0xd2, 0xe6,
65*4882a593Smuzhiyun 	0x03, 0x10, 0x0b, 0xaf, 0x7f,
66*4882a593Smuzhiyun 	0x00, 0x00, 0x1d, 0x5e, 0x00,
67*4882a593Smuzhiyun 	0xd0
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
71*4882a593Smuzhiyun 
upd64031a_read(struct v4l2_subdev * sd,u8 reg)72*4882a593Smuzhiyun static u8 upd64031a_read(struct v4l2_subdev *sd, u8 reg)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
75*4882a593Smuzhiyun 	u8 buf[2];
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	if (reg >= sizeof(buf))
78*4882a593Smuzhiyun 		return 0xff;
79*4882a593Smuzhiyun 	i2c_master_recv(client, buf, 2);
80*4882a593Smuzhiyun 	return buf[reg];
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
84*4882a593Smuzhiyun 
upd64031a_write(struct v4l2_subdev * sd,u8 reg,u8 val)85*4882a593Smuzhiyun static void upd64031a_write(struct v4l2_subdev *sd, u8 reg, u8 val)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
88*4882a593Smuzhiyun 	u8 buf[2];
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	buf[0] = reg;
91*4882a593Smuzhiyun 	buf[1] = val;
92*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "write reg: %02X val: %02X\n", reg, val);
93*4882a593Smuzhiyun 	if (i2c_master_send(client, buf, 2) != 2)
94*4882a593Smuzhiyun 		v4l2_err(sd, "I/O error write 0x%02x/0x%02x\n", reg, val);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun /* The input changed due to new input or channel changed */
upd64031a_s_frequency(struct v4l2_subdev * sd,const struct v4l2_frequency * freq)100*4882a593Smuzhiyun static int upd64031a_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *freq)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	struct upd64031a_state *state = to_state(sd);
103*4882a593Smuzhiyun 	u8 reg = state->regs[R00];
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "changed input or channel\n");
106*4882a593Smuzhiyun 	upd64031a_write(sd, R00, reg | 0x10);
107*4882a593Smuzhiyun 	upd64031a_write(sd, R00, reg & ~0x10);
108*4882a593Smuzhiyun 	return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
112*4882a593Smuzhiyun 
upd64031a_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)113*4882a593Smuzhiyun static int upd64031a_s_routing(struct v4l2_subdev *sd,
114*4882a593Smuzhiyun 			       u32 input, u32 output, u32 config)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun 	struct upd64031a_state *state = to_state(sd);
117*4882a593Smuzhiyun 	u8 r00, r05, r08;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	state->gr_mode = (input & 3) << 6;
120*4882a593Smuzhiyun 	state->direct_3dycs_connect = (input & 0xc) << 4;
121*4882a593Smuzhiyun 	state->ext_comp_sync =
122*4882a593Smuzhiyun 		(input & UPD64031A_COMPOSITE_EXTERNAL) << 1;
123*4882a593Smuzhiyun 	state->ext_vert_sync =
124*4882a593Smuzhiyun 		(input & UPD64031A_VERTICAL_EXTERNAL) << 2;
125*4882a593Smuzhiyun 	r00 = (state->regs[R00] & ~GR_MODE_MASK) | state->gr_mode;
126*4882a593Smuzhiyun 	r05 = (state->regs[R00] & ~SYNC_CIRCUIT_MASK) |
127*4882a593Smuzhiyun 		state->ext_comp_sync | state->ext_vert_sync;
128*4882a593Smuzhiyun 	r08 = (state->regs[R08] & ~DIRECT_3DYCS_CONNECT_MASK) |
129*4882a593Smuzhiyun 		state->direct_3dycs_connect;
130*4882a593Smuzhiyun 	upd64031a_write(sd, R00, r00);
131*4882a593Smuzhiyun 	upd64031a_write(sd, R05, r05);
132*4882a593Smuzhiyun 	upd64031a_write(sd, R08, r08);
133*4882a593Smuzhiyun 	return upd64031a_s_frequency(sd, NULL);
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
upd64031a_log_status(struct v4l2_subdev * sd)136*4882a593Smuzhiyun static int upd64031a_log_status(struct v4l2_subdev *sd)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	v4l2_info(sd, "Status: SA00=0x%02x SA01=0x%02x\n",
139*4882a593Smuzhiyun 			upd64031a_read(sd, 0), upd64031a_read(sd, 1));
140*4882a593Smuzhiyun 	return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
upd64031a_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)144*4882a593Smuzhiyun static int upd64031a_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	reg->val = upd64031a_read(sd, reg->reg & 0xff);
147*4882a593Smuzhiyun 	reg->size = 1;
148*4882a593Smuzhiyun 	return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun 
upd64031a_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)151*4882a593Smuzhiyun static int upd64031a_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	upd64031a_write(sd, reg->reg & 0xff, reg->val & 0xff);
154*4882a593Smuzhiyun 	return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun #endif
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops upd64031a_core_ops = {
161*4882a593Smuzhiyun 	.log_status = upd64031a_log_status,
162*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
163*4882a593Smuzhiyun 	.g_register = upd64031a_g_register,
164*4882a593Smuzhiyun 	.s_register = upd64031a_s_register,
165*4882a593Smuzhiyun #endif
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun static const struct v4l2_subdev_tuner_ops upd64031a_tuner_ops = {
169*4882a593Smuzhiyun 	.s_frequency = upd64031a_s_frequency,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops upd64031a_video_ops = {
173*4882a593Smuzhiyun 	.s_routing = upd64031a_s_routing,
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun static const struct v4l2_subdev_ops upd64031a_ops = {
177*4882a593Smuzhiyun 	.core = &upd64031a_core_ops,
178*4882a593Smuzhiyun 	.tuner = &upd64031a_tuner_ops,
179*4882a593Smuzhiyun 	.video = &upd64031a_video_ops,
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun /* ------------------------------------------------------------------------ */
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /* i2c implementation */
185*4882a593Smuzhiyun 
upd64031a_probe(struct i2c_client * client,const struct i2c_device_id * id)186*4882a593Smuzhiyun static int upd64031a_probe(struct i2c_client *client,
187*4882a593Smuzhiyun 			   const struct i2c_device_id *id)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	struct upd64031a_state *state;
190*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
191*4882a593Smuzhiyun 	int i;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
194*4882a593Smuzhiyun 		return -EIO;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	v4l_info(client, "chip found @ 0x%x (%s)\n",
197*4882a593Smuzhiyun 			client->addr << 1, client->adapter->name);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
200*4882a593Smuzhiyun 	if (state == NULL)
201*4882a593Smuzhiyun 		return -ENOMEM;
202*4882a593Smuzhiyun 	sd = &state->sd;
203*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &upd64031a_ops);
204*4882a593Smuzhiyun 	memcpy(state->regs, upd64031a_init, sizeof(state->regs));
205*4882a593Smuzhiyun 	state->gr_mode = UPD64031A_GR_ON << 6;
206*4882a593Smuzhiyun 	state->direct_3dycs_connect = UPD64031A_3DYCS_COMPOSITE << 4;
207*4882a593Smuzhiyun 	state->ext_comp_sync = state->ext_vert_sync = 0;
208*4882a593Smuzhiyun 	for (i = 0; i < TOT_REGS; i++)
209*4882a593Smuzhiyun 		upd64031a_write(sd, i, state->regs[i]);
210*4882a593Smuzhiyun 	return 0;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun 
upd64031a_remove(struct i2c_client * client)213*4882a593Smuzhiyun static int upd64031a_remove(struct i2c_client *client)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
218*4882a593Smuzhiyun 	return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun static const struct i2c_device_id upd64031a_id[] = {
224*4882a593Smuzhiyun 	{ "upd64031a", 0 },
225*4882a593Smuzhiyun 	{ }
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, upd64031a_id);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun static struct i2c_driver upd64031a_driver = {
230*4882a593Smuzhiyun 	.driver = {
231*4882a593Smuzhiyun 		.name	= "upd64031a",
232*4882a593Smuzhiyun 	},
233*4882a593Smuzhiyun 	.probe		= upd64031a_probe,
234*4882a593Smuzhiyun 	.remove		= upd64031a_remove,
235*4882a593Smuzhiyun 	.id_table	= upd64031a_id,
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun module_i2c_driver(upd64031a_driver);
239