1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics 3*4882a593Smuzhiyun * Digitizer with Horizontal PLL registers 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Texas Instruments Inc 6*4882a593Smuzhiyun * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This code is partially based upon the TVP5150 driver 9*4882a593Smuzhiyun * written by Mauro Carvalho Chehab <mchehab@kernel.org>, 10*4882a593Smuzhiyun * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> 11*4882a593Smuzhiyun * and the TVP7002 driver in the TI LSP 2.10.00.14 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Naming conventions 15*4882a593Smuzhiyun * ------------------ 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * FDBK: Feedback 18*4882a593Smuzhiyun * DIV: Divider 19*4882a593Smuzhiyun * CTL: Control 20*4882a593Smuzhiyun * SEL: Select 21*4882a593Smuzhiyun * IN: Input 22*4882a593Smuzhiyun * OUT: Output 23*4882a593Smuzhiyun * R: Red 24*4882a593Smuzhiyun * G: Green 25*4882a593Smuzhiyun * B: Blue 26*4882a593Smuzhiyun * OFF: Offset 27*4882a593Smuzhiyun * THRS: Threshold 28*4882a593Smuzhiyun * DGTL: Digital 29*4882a593Smuzhiyun * LVL: Level 30*4882a593Smuzhiyun * PWR: Power 31*4882a593Smuzhiyun * MVIS: Macrovision 32*4882a593Smuzhiyun * W: Width 33*4882a593Smuzhiyun * H: Height 34*4882a593Smuzhiyun * ALGN: Alignment 35*4882a593Smuzhiyun * CLK: Clocks 36*4882a593Smuzhiyun * TOL: Tolerance 37*4882a593Smuzhiyun * BWTH: Bandwidth 38*4882a593Smuzhiyun * COEF: Coefficient 39*4882a593Smuzhiyun * STAT: Status 40*4882a593Smuzhiyun * AUTO: Automatic 41*4882a593Smuzhiyun * FLD: Field 42*4882a593Smuzhiyun * L: Line 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define TVP7002_CHIP_REV 0x00 46*4882a593Smuzhiyun #define TVP7002_HPLL_FDBK_DIV_MSBS 0x01 47*4882a593Smuzhiyun #define TVP7002_HPLL_FDBK_DIV_LSBS 0x02 48*4882a593Smuzhiyun #define TVP7002_HPLL_CRTL 0x03 49*4882a593Smuzhiyun #define TVP7002_HPLL_PHASE_SEL 0x04 50*4882a593Smuzhiyun #define TVP7002_CLAMP_START 0x05 51*4882a593Smuzhiyun #define TVP7002_CLAMP_W 0x06 52*4882a593Smuzhiyun #define TVP7002_HSYNC_OUT_W 0x07 53*4882a593Smuzhiyun #define TVP7002_B_FINE_GAIN 0x08 54*4882a593Smuzhiyun #define TVP7002_G_FINE_GAIN 0x09 55*4882a593Smuzhiyun #define TVP7002_R_FINE_GAIN 0x0a 56*4882a593Smuzhiyun #define TVP7002_B_FINE_OFF_MSBS 0x0b 57*4882a593Smuzhiyun #define TVP7002_G_FINE_OFF_MSBS 0x0c 58*4882a593Smuzhiyun #define TVP7002_R_FINE_OFF_MSBS 0x0d 59*4882a593Smuzhiyun #define TVP7002_SYNC_CTL_1 0x0e 60*4882a593Smuzhiyun #define TVP7002_HPLL_AND_CLAMP_CTL 0x0f 61*4882a593Smuzhiyun #define TVP7002_SYNC_ON_G_THRS 0x10 62*4882a593Smuzhiyun #define TVP7002_SYNC_SEPARATOR_THRS 0x11 63*4882a593Smuzhiyun #define TVP7002_HPLL_PRE_COAST 0x12 64*4882a593Smuzhiyun #define TVP7002_HPLL_POST_COAST 0x13 65*4882a593Smuzhiyun #define TVP7002_SYNC_DETECT_STAT 0x14 66*4882a593Smuzhiyun #define TVP7002_OUT_FORMATTER 0x15 67*4882a593Smuzhiyun #define TVP7002_MISC_CTL_1 0x16 68*4882a593Smuzhiyun #define TVP7002_MISC_CTL_2 0x17 69*4882a593Smuzhiyun #define TVP7002_MISC_CTL_3 0x18 70*4882a593Smuzhiyun #define TVP7002_IN_MUX_SEL_1 0x19 71*4882a593Smuzhiyun #define TVP7002_IN_MUX_SEL_2 0x1a 72*4882a593Smuzhiyun #define TVP7002_B_AND_G_COARSE_GAIN 0x1b 73*4882a593Smuzhiyun #define TVP7002_R_COARSE_GAIN 0x1c 74*4882a593Smuzhiyun #define TVP7002_FINE_OFF_LSBS 0x1d 75*4882a593Smuzhiyun #define TVP7002_B_COARSE_OFF 0x1e 76*4882a593Smuzhiyun #define TVP7002_G_COARSE_OFF 0x1f 77*4882a593Smuzhiyun #define TVP7002_R_COARSE_OFF 0x20 78*4882a593Smuzhiyun #define TVP7002_HSOUT_OUT_START 0x21 79*4882a593Smuzhiyun #define TVP7002_MISC_CTL_4 0x22 80*4882a593Smuzhiyun #define TVP7002_B_DGTL_ALC_OUT_LSBS 0x23 81*4882a593Smuzhiyun #define TVP7002_G_DGTL_ALC_OUT_LSBS 0x24 82*4882a593Smuzhiyun #define TVP7002_R_DGTL_ALC_OUT_LSBS 0x25 83*4882a593Smuzhiyun #define TVP7002_AUTO_LVL_CTL_ENABLE 0x26 84*4882a593Smuzhiyun #define TVP7002_DGTL_ALC_OUT_MSBS 0x27 85*4882a593Smuzhiyun #define TVP7002_AUTO_LVL_CTL_FILTER 0x28 86*4882a593Smuzhiyun /* Reserved 0x29*/ 87*4882a593Smuzhiyun #define TVP7002_FINE_CLAMP_CTL 0x2a 88*4882a593Smuzhiyun #define TVP7002_PWR_CTL 0x2b 89*4882a593Smuzhiyun #define TVP7002_ADC_SETUP 0x2c 90*4882a593Smuzhiyun #define TVP7002_COARSE_CLAMP_CTL 0x2d 91*4882a593Smuzhiyun #define TVP7002_SOG_CLAMP 0x2e 92*4882a593Smuzhiyun #define TVP7002_RGB_COARSE_CLAMP_CTL 0x2f 93*4882a593Smuzhiyun #define TVP7002_SOG_COARSE_CLAMP_CTL 0x30 94*4882a593Smuzhiyun #define TVP7002_ALC_PLACEMENT 0x31 95*4882a593Smuzhiyun /* Reserved 0x32 */ 96*4882a593Smuzhiyun /* Reserved 0x33 */ 97*4882a593Smuzhiyun #define TVP7002_MVIS_STRIPPER_W 0x34 98*4882a593Smuzhiyun #define TVP7002_VSYNC_ALGN 0x35 99*4882a593Smuzhiyun #define TVP7002_SYNC_BYPASS 0x36 100*4882a593Smuzhiyun #define TVP7002_L_FRAME_STAT_LSBS 0x37 101*4882a593Smuzhiyun #define TVP7002_L_FRAME_STAT_MSBS 0x38 102*4882a593Smuzhiyun #define TVP7002_CLK_L_STAT_LSBS 0x39 103*4882a593Smuzhiyun #define TVP7002_CLK_L_STAT_MSBS 0x3a 104*4882a593Smuzhiyun #define TVP7002_HSYNC_W 0x3b 105*4882a593Smuzhiyun #define TVP7002_VSYNC_W 0x3c 106*4882a593Smuzhiyun #define TVP7002_L_LENGTH_TOL 0x3d 107*4882a593Smuzhiyun /* Reserved 0x3e */ 108*4882a593Smuzhiyun #define TVP7002_VIDEO_BWTH_CTL 0x3f 109*4882a593Smuzhiyun #define TVP7002_AVID_START_PIXEL_LSBS 0x40 110*4882a593Smuzhiyun #define TVP7002_AVID_START_PIXEL_MSBS 0x41 111*4882a593Smuzhiyun #define TVP7002_AVID_STOP_PIXEL_LSBS 0x42 112*4882a593Smuzhiyun #define TVP7002_AVID_STOP_PIXEL_MSBS 0x43 113*4882a593Smuzhiyun #define TVP7002_VBLK_F_0_START_L_OFF 0x44 114*4882a593Smuzhiyun #define TVP7002_VBLK_F_1_START_L_OFF 0x45 115*4882a593Smuzhiyun #define TVP7002_VBLK_F_0_DURATION 0x46 116*4882a593Smuzhiyun #define TVP7002_VBLK_F_1_DURATION 0x47 117*4882a593Smuzhiyun #define TVP7002_FBIT_F_0_START_L_OFF 0x48 118*4882a593Smuzhiyun #define TVP7002_FBIT_F_1_START_L_OFF 0x49 119*4882a593Smuzhiyun #define TVP7002_YUV_Y_G_COEF_LSBS 0x4a 120*4882a593Smuzhiyun #define TVP7002_YUV_Y_G_COEF_MSBS 0x4b 121*4882a593Smuzhiyun #define TVP7002_YUV_Y_B_COEF_LSBS 0x4c 122*4882a593Smuzhiyun #define TVP7002_YUV_Y_B_COEF_MSBS 0x4d 123*4882a593Smuzhiyun #define TVP7002_YUV_Y_R_COEF_LSBS 0x4e 124*4882a593Smuzhiyun #define TVP7002_YUV_Y_R_COEF_MSBS 0x4f 125*4882a593Smuzhiyun #define TVP7002_YUV_U_G_COEF_LSBS 0x50 126*4882a593Smuzhiyun #define TVP7002_YUV_U_G_COEF_MSBS 0x51 127*4882a593Smuzhiyun #define TVP7002_YUV_U_B_COEF_LSBS 0x52 128*4882a593Smuzhiyun #define TVP7002_YUV_U_B_COEF_MSBS 0x53 129*4882a593Smuzhiyun #define TVP7002_YUV_U_R_COEF_LSBS 0x54 130*4882a593Smuzhiyun #define TVP7002_YUV_U_R_COEF_MSBS 0x55 131*4882a593Smuzhiyun #define TVP7002_YUV_V_G_COEF_LSBS 0x56 132*4882a593Smuzhiyun #define TVP7002_YUV_V_G_COEF_MSBS 0x57 133*4882a593Smuzhiyun #define TVP7002_YUV_V_B_COEF_LSBS 0x58 134*4882a593Smuzhiyun #define TVP7002_YUV_V_B_COEF_MSBS 0x59 135*4882a593Smuzhiyun #define TVP7002_YUV_V_R_COEF_LSBS 0x5a 136*4882a593Smuzhiyun #define TVP7002_YUV_V_R_COEF_MSBS 0x5b 137*4882a593Smuzhiyun 138