1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * drivers/media/i2c/tvp514x.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * TI TVP5146/47 decoder driver
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2008 Texas Instruments Inc
8*4882a593Smuzhiyun * Author: Vaibhav Hiremath <hvaibhav@ti.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Contributors:
11*4882a593Smuzhiyun * Sivaraj R <sivaraj@ti.com>
12*4882a593Smuzhiyun * Brijesh R Jadav <brijesh.j@ti.com>
13*4882a593Smuzhiyun * Hardik Shah <hardik.shah@ti.com>
14*4882a593Smuzhiyun * Manjunath Hadli <mrh@ti.com>
15*4882a593Smuzhiyun * Karicheri Muralidharan <m-karicheri2@ti.com>
16*4882a593Smuzhiyun * Prabhakar Lad <prabhakar.lad@ti.com>
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/i2c.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/videodev2.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/v4l2-mediabus.h>
25*4882a593Smuzhiyun #include <linux/of.h>
26*4882a593Smuzhiyun #include <linux/of_graph.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include <media/v4l2-async.h>
29*4882a593Smuzhiyun #include <media/v4l2-device.h>
30*4882a593Smuzhiyun #include <media/v4l2-common.h>
31*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
32*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
33*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
34*4882a593Smuzhiyun #include <media/i2c/tvp514x.h>
35*4882a593Smuzhiyun #include <media/media-entity.h>
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include "tvp514x_regs.h"
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Private macros for TVP */
40*4882a593Smuzhiyun #define I2C_RETRY_COUNT (5)
41*4882a593Smuzhiyun #define LOCK_RETRY_COUNT (5)
42*4882a593Smuzhiyun #define LOCK_RETRY_DELAY (200)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* Debug functions */
45*4882a593Smuzhiyun static bool debug;
46*4882a593Smuzhiyun module_param(debug, bool, 0644);
47*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level (0-1)");
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun MODULE_AUTHOR("Texas Instruments");
50*4882a593Smuzhiyun MODULE_DESCRIPTION("TVP514X linux decoder driver");
51*4882a593Smuzhiyun MODULE_LICENSE("GPL");
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* enum tvp514x_std - enum for supported standards */
54*4882a593Smuzhiyun enum tvp514x_std {
55*4882a593Smuzhiyun STD_NTSC_MJ = 0,
56*4882a593Smuzhiyun STD_PAL_BDGHIN,
57*4882a593Smuzhiyun STD_INVALID
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /**
61*4882a593Smuzhiyun * struct tvp514x_std_info - Structure to store standard information
62*4882a593Smuzhiyun * @width: Line width in pixels
63*4882a593Smuzhiyun * @height:Number of active lines
64*4882a593Smuzhiyun * @video_std: Value to write in REG_VIDEO_STD register
65*4882a593Smuzhiyun * @standard: v4l2 standard structure information
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun struct tvp514x_std_info {
68*4882a593Smuzhiyun unsigned long width;
69*4882a593Smuzhiyun unsigned long height;
70*4882a593Smuzhiyun u8 video_std;
71*4882a593Smuzhiyun struct v4l2_standard standard;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static struct tvp514x_reg tvp514x_reg_list_default[0x40];
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable);
77*4882a593Smuzhiyun /**
78*4882a593Smuzhiyun * struct tvp514x_decoder - TVP5146/47 decoder object
79*4882a593Smuzhiyun * @sd: Subdevice Slave handle
80*4882a593Smuzhiyun * @hdl: embedded &struct v4l2_ctrl_handler
81*4882a593Smuzhiyun * @tvp514x_regs: copy of hw's regs with preset values.
82*4882a593Smuzhiyun * @pdata: Board specific
83*4882a593Smuzhiyun * @ver: Chip version
84*4882a593Smuzhiyun * @streaming: TVP5146/47 decoder streaming - enabled or disabled.
85*4882a593Smuzhiyun * @pix: Current pixel format
86*4882a593Smuzhiyun * @num_fmts: Number of formats
87*4882a593Smuzhiyun * @fmt_list: Format list
88*4882a593Smuzhiyun * @current_std: Current standard
89*4882a593Smuzhiyun * @num_stds: Number of standards
90*4882a593Smuzhiyun * @std_list: Standards list
91*4882a593Smuzhiyun * @input: Input routing at chip level
92*4882a593Smuzhiyun * @output: Output routing at chip level
93*4882a593Smuzhiyun * @pad: subdev media pad associated with the decoder
94*4882a593Smuzhiyun * @format: media bus frame format
95*4882a593Smuzhiyun * @int_seq: driver's register init sequence
96*4882a593Smuzhiyun */
97*4882a593Smuzhiyun struct tvp514x_decoder {
98*4882a593Smuzhiyun struct v4l2_subdev sd;
99*4882a593Smuzhiyun struct v4l2_ctrl_handler hdl;
100*4882a593Smuzhiyun struct tvp514x_reg tvp514x_regs[ARRAY_SIZE(tvp514x_reg_list_default)];
101*4882a593Smuzhiyun const struct tvp514x_platform_data *pdata;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun int ver;
104*4882a593Smuzhiyun int streaming;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun struct v4l2_pix_format pix;
107*4882a593Smuzhiyun int num_fmts;
108*4882a593Smuzhiyun const struct v4l2_fmtdesc *fmt_list;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun enum tvp514x_std current_std;
111*4882a593Smuzhiyun int num_stds;
112*4882a593Smuzhiyun const struct tvp514x_std_info *std_list;
113*4882a593Smuzhiyun /* Input and Output Routing parameters */
114*4882a593Smuzhiyun u32 input;
115*4882a593Smuzhiyun u32 output;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* mc related members */
118*4882a593Smuzhiyun struct media_pad pad;
119*4882a593Smuzhiyun struct v4l2_mbus_framefmt format;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun struct tvp514x_reg *int_seq;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* TVP514x default register values */
125*4882a593Smuzhiyun static struct tvp514x_reg tvp514x_reg_list_default[] = {
126*4882a593Smuzhiyun /* Composite selected */
127*4882a593Smuzhiyun {TOK_WRITE, REG_INPUT_SEL, 0x05},
128*4882a593Smuzhiyun {TOK_WRITE, REG_AFE_GAIN_CTRL, 0x0F},
129*4882a593Smuzhiyun /* Auto mode */
130*4882a593Smuzhiyun {TOK_WRITE, REG_VIDEO_STD, 0x00},
131*4882a593Smuzhiyun {TOK_WRITE, REG_OPERATION_MODE, 0x00},
132*4882a593Smuzhiyun {TOK_SKIP, REG_AUTOSWITCH_MASK, 0x3F},
133*4882a593Smuzhiyun {TOK_WRITE, REG_COLOR_KILLER, 0x10},
134*4882a593Smuzhiyun {TOK_WRITE, REG_LUMA_CONTROL1, 0x00},
135*4882a593Smuzhiyun {TOK_WRITE, REG_LUMA_CONTROL2, 0x00},
136*4882a593Smuzhiyun {TOK_WRITE, REG_LUMA_CONTROL3, 0x02},
137*4882a593Smuzhiyun {TOK_WRITE, REG_BRIGHTNESS, 0x80},
138*4882a593Smuzhiyun {TOK_WRITE, REG_CONTRAST, 0x80},
139*4882a593Smuzhiyun {TOK_WRITE, REG_SATURATION, 0x80},
140*4882a593Smuzhiyun {TOK_WRITE, REG_HUE, 0x00},
141*4882a593Smuzhiyun {TOK_WRITE, REG_CHROMA_CONTROL1, 0x00},
142*4882a593Smuzhiyun {TOK_WRITE, REG_CHROMA_CONTROL2, 0x0E},
143*4882a593Smuzhiyun /* Reserved */
144*4882a593Smuzhiyun {TOK_SKIP, 0x0F, 0x00},
145*4882a593Smuzhiyun {TOK_WRITE, REG_COMP_PR_SATURATION, 0x80},
146*4882a593Smuzhiyun {TOK_WRITE, REG_COMP_Y_CONTRAST, 0x80},
147*4882a593Smuzhiyun {TOK_WRITE, REG_COMP_PB_SATURATION, 0x80},
148*4882a593Smuzhiyun /* Reserved */
149*4882a593Smuzhiyun {TOK_SKIP, 0x13, 0x00},
150*4882a593Smuzhiyun {TOK_WRITE, REG_COMP_Y_BRIGHTNESS, 0x80},
151*4882a593Smuzhiyun /* Reserved */
152*4882a593Smuzhiyun {TOK_SKIP, 0x15, 0x00},
153*4882a593Smuzhiyun /* NTSC timing */
154*4882a593Smuzhiyun {TOK_SKIP, REG_AVID_START_PIXEL_LSB, 0x55},
155*4882a593Smuzhiyun {TOK_SKIP, REG_AVID_START_PIXEL_MSB, 0x00},
156*4882a593Smuzhiyun {TOK_SKIP, REG_AVID_STOP_PIXEL_LSB, 0x25},
157*4882a593Smuzhiyun {TOK_SKIP, REG_AVID_STOP_PIXEL_MSB, 0x03},
158*4882a593Smuzhiyun /* NTSC timing */
159*4882a593Smuzhiyun {TOK_SKIP, REG_HSYNC_START_PIXEL_LSB, 0x00},
160*4882a593Smuzhiyun {TOK_SKIP, REG_HSYNC_START_PIXEL_MSB, 0x00},
161*4882a593Smuzhiyun {TOK_SKIP, REG_HSYNC_STOP_PIXEL_LSB, 0x40},
162*4882a593Smuzhiyun {TOK_SKIP, REG_HSYNC_STOP_PIXEL_MSB, 0x00},
163*4882a593Smuzhiyun /* NTSC timing */
164*4882a593Smuzhiyun {TOK_SKIP, REG_VSYNC_START_LINE_LSB, 0x04},
165*4882a593Smuzhiyun {TOK_SKIP, REG_VSYNC_START_LINE_MSB, 0x00},
166*4882a593Smuzhiyun {TOK_SKIP, REG_VSYNC_STOP_LINE_LSB, 0x07},
167*4882a593Smuzhiyun {TOK_SKIP, REG_VSYNC_STOP_LINE_MSB, 0x00},
168*4882a593Smuzhiyun /* NTSC timing */
169*4882a593Smuzhiyun {TOK_SKIP, REG_VBLK_START_LINE_LSB, 0x01},
170*4882a593Smuzhiyun {TOK_SKIP, REG_VBLK_START_LINE_MSB, 0x00},
171*4882a593Smuzhiyun {TOK_SKIP, REG_VBLK_STOP_LINE_LSB, 0x15},
172*4882a593Smuzhiyun {TOK_SKIP, REG_VBLK_STOP_LINE_MSB, 0x00},
173*4882a593Smuzhiyun /* Reserved */
174*4882a593Smuzhiyun {TOK_SKIP, 0x26, 0x00},
175*4882a593Smuzhiyun /* Reserved */
176*4882a593Smuzhiyun {TOK_SKIP, 0x27, 0x00},
177*4882a593Smuzhiyun {TOK_SKIP, REG_FAST_SWTICH_CONTROL, 0xCC},
178*4882a593Smuzhiyun /* Reserved */
179*4882a593Smuzhiyun {TOK_SKIP, 0x29, 0x00},
180*4882a593Smuzhiyun {TOK_SKIP, REG_FAST_SWTICH_SCART_DELAY, 0x00},
181*4882a593Smuzhiyun /* Reserved */
182*4882a593Smuzhiyun {TOK_SKIP, 0x2B, 0x00},
183*4882a593Smuzhiyun {TOK_SKIP, REG_SCART_DELAY, 0x00},
184*4882a593Smuzhiyun {TOK_SKIP, REG_CTI_DELAY, 0x00},
185*4882a593Smuzhiyun {TOK_SKIP, REG_CTI_CONTROL, 0x00},
186*4882a593Smuzhiyun /* Reserved */
187*4882a593Smuzhiyun {TOK_SKIP, 0x2F, 0x00},
188*4882a593Smuzhiyun /* Reserved */
189*4882a593Smuzhiyun {TOK_SKIP, 0x30, 0x00},
190*4882a593Smuzhiyun /* Reserved */
191*4882a593Smuzhiyun {TOK_SKIP, 0x31, 0x00},
192*4882a593Smuzhiyun /* HS, VS active high */
193*4882a593Smuzhiyun {TOK_WRITE, REG_SYNC_CONTROL, 0x00},
194*4882a593Smuzhiyun /* 10-bit BT.656 */
195*4882a593Smuzhiyun {TOK_WRITE, REG_OUTPUT_FORMATTER1, 0x00},
196*4882a593Smuzhiyun /* Enable clk & data */
197*4882a593Smuzhiyun {TOK_WRITE, REG_OUTPUT_FORMATTER2, 0x11},
198*4882a593Smuzhiyun /* Enable AVID & FLD */
199*4882a593Smuzhiyun {TOK_WRITE, REG_OUTPUT_FORMATTER3, 0xEE},
200*4882a593Smuzhiyun /* Enable VS & HS */
201*4882a593Smuzhiyun {TOK_WRITE, REG_OUTPUT_FORMATTER4, 0xAF},
202*4882a593Smuzhiyun {TOK_WRITE, REG_OUTPUT_FORMATTER5, 0xFF},
203*4882a593Smuzhiyun {TOK_WRITE, REG_OUTPUT_FORMATTER6, 0xFF},
204*4882a593Smuzhiyun /* Clear status */
205*4882a593Smuzhiyun {TOK_WRITE, REG_CLEAR_LOST_LOCK, 0x01},
206*4882a593Smuzhiyun {TOK_TERM, 0, 0},
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /*
210*4882a593Smuzhiyun * List of image formats supported by TVP5146/47 decoder
211*4882a593Smuzhiyun * Currently we are using 8 bit mode only, but can be
212*4882a593Smuzhiyun * extended to 10/20 bit mode.
213*4882a593Smuzhiyun */
214*4882a593Smuzhiyun static const struct v4l2_fmtdesc tvp514x_fmt_list[] = {
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun .index = 0,
217*4882a593Smuzhiyun .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
218*4882a593Smuzhiyun .flags = 0,
219*4882a593Smuzhiyun .description = "8-bit UYVY 4:2:2 Format",
220*4882a593Smuzhiyun .pixelformat = V4L2_PIX_FMT_UYVY,
221*4882a593Smuzhiyun },
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /*
225*4882a593Smuzhiyun * Supported standards -
226*4882a593Smuzhiyun *
227*4882a593Smuzhiyun * Currently supports two standards only, need to add support for rest of the
228*4882a593Smuzhiyun * modes, like SECAM, etc...
229*4882a593Smuzhiyun */
230*4882a593Smuzhiyun static const struct tvp514x_std_info tvp514x_std_list[] = {
231*4882a593Smuzhiyun /* Standard: STD_NTSC_MJ */
232*4882a593Smuzhiyun [STD_NTSC_MJ] = {
233*4882a593Smuzhiyun .width = NTSC_NUM_ACTIVE_PIXELS,
234*4882a593Smuzhiyun .height = NTSC_NUM_ACTIVE_LINES,
235*4882a593Smuzhiyun .video_std = VIDEO_STD_NTSC_MJ_BIT,
236*4882a593Smuzhiyun .standard = {
237*4882a593Smuzhiyun .index = 0,
238*4882a593Smuzhiyun .id = V4L2_STD_NTSC,
239*4882a593Smuzhiyun .name = "NTSC",
240*4882a593Smuzhiyun .frameperiod = {1001, 30000},
241*4882a593Smuzhiyun .framelines = 525
242*4882a593Smuzhiyun },
243*4882a593Smuzhiyun /* Standard: STD_PAL_BDGHIN */
244*4882a593Smuzhiyun },
245*4882a593Smuzhiyun [STD_PAL_BDGHIN] = {
246*4882a593Smuzhiyun .width = PAL_NUM_ACTIVE_PIXELS,
247*4882a593Smuzhiyun .height = PAL_NUM_ACTIVE_LINES,
248*4882a593Smuzhiyun .video_std = VIDEO_STD_PAL_BDGHIN_BIT,
249*4882a593Smuzhiyun .standard = {
250*4882a593Smuzhiyun .index = 1,
251*4882a593Smuzhiyun .id = V4L2_STD_PAL,
252*4882a593Smuzhiyun .name = "PAL",
253*4882a593Smuzhiyun .frameperiod = {1, 25},
254*4882a593Smuzhiyun .framelines = 625
255*4882a593Smuzhiyun },
256*4882a593Smuzhiyun },
257*4882a593Smuzhiyun /* Standard: need to add for additional standard */
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun
to_decoder(struct v4l2_subdev * sd)261*4882a593Smuzhiyun static inline struct tvp514x_decoder *to_decoder(struct v4l2_subdev *sd)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun return container_of(sd, struct tvp514x_decoder, sd);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
to_sd(struct v4l2_ctrl * ctrl)266*4882a593Smuzhiyun static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun return &container_of(ctrl->handler, struct tvp514x_decoder, hdl)->sd;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /**
273*4882a593Smuzhiyun * tvp514x_read_reg() - Read a value from a register in an TVP5146/47.
274*4882a593Smuzhiyun * @sd: ptr to v4l2_subdev struct
275*4882a593Smuzhiyun * @reg: TVP5146/47 register address
276*4882a593Smuzhiyun *
277*4882a593Smuzhiyun * Returns value read if successful, or non-zero (-1) otherwise.
278*4882a593Smuzhiyun */
tvp514x_read_reg(struct v4l2_subdev * sd,u8 reg)279*4882a593Smuzhiyun static int tvp514x_read_reg(struct v4l2_subdev *sd, u8 reg)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun int err, retry = 0;
282*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun read_again:
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun err = i2c_smbus_read_byte_data(client, reg);
287*4882a593Smuzhiyun if (err < 0) {
288*4882a593Smuzhiyun if (retry <= I2C_RETRY_COUNT) {
289*4882a593Smuzhiyun v4l2_warn(sd, "Read: retry ... %d\n", retry);
290*4882a593Smuzhiyun retry++;
291*4882a593Smuzhiyun msleep_interruptible(10);
292*4882a593Smuzhiyun goto read_again;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun return err;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /**
300*4882a593Smuzhiyun * dump_reg() - dump the register content of TVP5146/47.
301*4882a593Smuzhiyun * @sd: ptr to v4l2_subdev struct
302*4882a593Smuzhiyun * @reg: TVP5146/47 register address
303*4882a593Smuzhiyun */
dump_reg(struct v4l2_subdev * sd,u8 reg)304*4882a593Smuzhiyun static void dump_reg(struct v4l2_subdev *sd, u8 reg)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun u32 val;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun val = tvp514x_read_reg(sd, reg);
309*4882a593Smuzhiyun v4l2_info(sd, "Reg(0x%.2X): 0x%.2X\n", reg, val);
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /**
313*4882a593Smuzhiyun * tvp514x_write_reg() - Write a value to a register in TVP5146/47
314*4882a593Smuzhiyun * @sd: ptr to v4l2_subdev struct
315*4882a593Smuzhiyun * @reg: TVP5146/47 register address
316*4882a593Smuzhiyun * @val: value to be written to the register
317*4882a593Smuzhiyun *
318*4882a593Smuzhiyun * Write a value to a register in an TVP5146/47 decoder device.
319*4882a593Smuzhiyun * Returns zero if successful, or non-zero otherwise.
320*4882a593Smuzhiyun */
tvp514x_write_reg(struct v4l2_subdev * sd,u8 reg,u8 val)321*4882a593Smuzhiyun static int tvp514x_write_reg(struct v4l2_subdev *sd, u8 reg, u8 val)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun int err, retry = 0;
324*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun write_again:
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun err = i2c_smbus_write_byte_data(client, reg, val);
329*4882a593Smuzhiyun if (err) {
330*4882a593Smuzhiyun if (retry <= I2C_RETRY_COUNT) {
331*4882a593Smuzhiyun v4l2_warn(sd, "Write: retry ... %d\n", retry);
332*4882a593Smuzhiyun retry++;
333*4882a593Smuzhiyun msleep_interruptible(10);
334*4882a593Smuzhiyun goto write_again;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun return err;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /**
342*4882a593Smuzhiyun * tvp514x_write_regs() : Initializes a list of TVP5146/47 registers
343*4882a593Smuzhiyun * @sd: ptr to v4l2_subdev struct
344*4882a593Smuzhiyun * @reglist: list of TVP5146/47 registers and values
345*4882a593Smuzhiyun *
346*4882a593Smuzhiyun * Initializes a list of TVP5146/47 registers:-
347*4882a593Smuzhiyun * if token is TOK_TERM, then entire write operation terminates
348*4882a593Smuzhiyun * if token is TOK_DELAY, then a delay of 'val' msec is introduced
349*4882a593Smuzhiyun * if token is TOK_SKIP, then the register write is skipped
350*4882a593Smuzhiyun * if token is TOK_WRITE, then the register write is performed
351*4882a593Smuzhiyun * Returns zero if successful, or non-zero otherwise.
352*4882a593Smuzhiyun */
tvp514x_write_regs(struct v4l2_subdev * sd,const struct tvp514x_reg reglist[])353*4882a593Smuzhiyun static int tvp514x_write_regs(struct v4l2_subdev *sd,
354*4882a593Smuzhiyun const struct tvp514x_reg reglist[])
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun int err;
357*4882a593Smuzhiyun const struct tvp514x_reg *next = reglist;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun for (; next->token != TOK_TERM; next++) {
360*4882a593Smuzhiyun if (next->token == TOK_DELAY) {
361*4882a593Smuzhiyun msleep(next->val);
362*4882a593Smuzhiyun continue;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun if (next->token == TOK_SKIP)
366*4882a593Smuzhiyun continue;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun err = tvp514x_write_reg(sd, next->reg, (u8) next->val);
369*4882a593Smuzhiyun if (err) {
370*4882a593Smuzhiyun v4l2_err(sd, "Write failed. Err[%d]\n", err);
371*4882a593Smuzhiyun return err;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun return 0;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun /**
378*4882a593Smuzhiyun * tvp514x_query_current_std() : Query the current standard detected by TVP5146/47
379*4882a593Smuzhiyun * @sd: ptr to v4l2_subdev struct
380*4882a593Smuzhiyun *
381*4882a593Smuzhiyun * Returns the current standard detected by TVP5146/47, STD_INVALID if there is no
382*4882a593Smuzhiyun * standard detected.
383*4882a593Smuzhiyun */
tvp514x_query_current_std(struct v4l2_subdev * sd)384*4882a593Smuzhiyun static enum tvp514x_std tvp514x_query_current_std(struct v4l2_subdev *sd)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun u8 std, std_status;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun std = tvp514x_read_reg(sd, REG_VIDEO_STD);
389*4882a593Smuzhiyun if ((std & VIDEO_STD_MASK) == VIDEO_STD_AUTO_SWITCH_BIT)
390*4882a593Smuzhiyun /* use the standard status register */
391*4882a593Smuzhiyun std_status = tvp514x_read_reg(sd, REG_VIDEO_STD_STATUS);
392*4882a593Smuzhiyun else
393*4882a593Smuzhiyun /* use the standard register itself */
394*4882a593Smuzhiyun std_status = std;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun switch (std_status & VIDEO_STD_MASK) {
397*4882a593Smuzhiyun case VIDEO_STD_NTSC_MJ_BIT:
398*4882a593Smuzhiyun return STD_NTSC_MJ;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun case VIDEO_STD_PAL_BDGHIN_BIT:
401*4882a593Smuzhiyun return STD_PAL_BDGHIN;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun default:
404*4882a593Smuzhiyun return STD_INVALID;
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun return STD_INVALID;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun /* TVP5146/47 register dump function */
tvp514x_reg_dump(struct v4l2_subdev * sd)411*4882a593Smuzhiyun static void tvp514x_reg_dump(struct v4l2_subdev *sd)
412*4882a593Smuzhiyun {
413*4882a593Smuzhiyun dump_reg(sd, REG_INPUT_SEL);
414*4882a593Smuzhiyun dump_reg(sd, REG_AFE_GAIN_CTRL);
415*4882a593Smuzhiyun dump_reg(sd, REG_VIDEO_STD);
416*4882a593Smuzhiyun dump_reg(sd, REG_OPERATION_MODE);
417*4882a593Smuzhiyun dump_reg(sd, REG_COLOR_KILLER);
418*4882a593Smuzhiyun dump_reg(sd, REG_LUMA_CONTROL1);
419*4882a593Smuzhiyun dump_reg(sd, REG_LUMA_CONTROL2);
420*4882a593Smuzhiyun dump_reg(sd, REG_LUMA_CONTROL3);
421*4882a593Smuzhiyun dump_reg(sd, REG_BRIGHTNESS);
422*4882a593Smuzhiyun dump_reg(sd, REG_CONTRAST);
423*4882a593Smuzhiyun dump_reg(sd, REG_SATURATION);
424*4882a593Smuzhiyun dump_reg(sd, REG_HUE);
425*4882a593Smuzhiyun dump_reg(sd, REG_CHROMA_CONTROL1);
426*4882a593Smuzhiyun dump_reg(sd, REG_CHROMA_CONTROL2);
427*4882a593Smuzhiyun dump_reg(sd, REG_COMP_PR_SATURATION);
428*4882a593Smuzhiyun dump_reg(sd, REG_COMP_Y_CONTRAST);
429*4882a593Smuzhiyun dump_reg(sd, REG_COMP_PB_SATURATION);
430*4882a593Smuzhiyun dump_reg(sd, REG_COMP_Y_BRIGHTNESS);
431*4882a593Smuzhiyun dump_reg(sd, REG_AVID_START_PIXEL_LSB);
432*4882a593Smuzhiyun dump_reg(sd, REG_AVID_START_PIXEL_MSB);
433*4882a593Smuzhiyun dump_reg(sd, REG_AVID_STOP_PIXEL_LSB);
434*4882a593Smuzhiyun dump_reg(sd, REG_AVID_STOP_PIXEL_MSB);
435*4882a593Smuzhiyun dump_reg(sd, REG_HSYNC_START_PIXEL_LSB);
436*4882a593Smuzhiyun dump_reg(sd, REG_HSYNC_START_PIXEL_MSB);
437*4882a593Smuzhiyun dump_reg(sd, REG_HSYNC_STOP_PIXEL_LSB);
438*4882a593Smuzhiyun dump_reg(sd, REG_HSYNC_STOP_PIXEL_MSB);
439*4882a593Smuzhiyun dump_reg(sd, REG_VSYNC_START_LINE_LSB);
440*4882a593Smuzhiyun dump_reg(sd, REG_VSYNC_START_LINE_MSB);
441*4882a593Smuzhiyun dump_reg(sd, REG_VSYNC_STOP_LINE_LSB);
442*4882a593Smuzhiyun dump_reg(sd, REG_VSYNC_STOP_LINE_MSB);
443*4882a593Smuzhiyun dump_reg(sd, REG_VBLK_START_LINE_LSB);
444*4882a593Smuzhiyun dump_reg(sd, REG_VBLK_START_LINE_MSB);
445*4882a593Smuzhiyun dump_reg(sd, REG_VBLK_STOP_LINE_LSB);
446*4882a593Smuzhiyun dump_reg(sd, REG_VBLK_STOP_LINE_MSB);
447*4882a593Smuzhiyun dump_reg(sd, REG_SYNC_CONTROL);
448*4882a593Smuzhiyun dump_reg(sd, REG_OUTPUT_FORMATTER1);
449*4882a593Smuzhiyun dump_reg(sd, REG_OUTPUT_FORMATTER2);
450*4882a593Smuzhiyun dump_reg(sd, REG_OUTPUT_FORMATTER3);
451*4882a593Smuzhiyun dump_reg(sd, REG_OUTPUT_FORMATTER4);
452*4882a593Smuzhiyun dump_reg(sd, REG_OUTPUT_FORMATTER5);
453*4882a593Smuzhiyun dump_reg(sd, REG_OUTPUT_FORMATTER6);
454*4882a593Smuzhiyun dump_reg(sd, REG_CLEAR_LOST_LOCK);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /**
458*4882a593Smuzhiyun * tvp514x_configure() - Configure the TVP5146/47 registers
459*4882a593Smuzhiyun * @sd: ptr to v4l2_subdev struct
460*4882a593Smuzhiyun * @decoder: ptr to tvp514x_decoder structure
461*4882a593Smuzhiyun *
462*4882a593Smuzhiyun * Returns zero if successful, or non-zero otherwise.
463*4882a593Smuzhiyun */
tvp514x_configure(struct v4l2_subdev * sd,struct tvp514x_decoder * decoder)464*4882a593Smuzhiyun static int tvp514x_configure(struct v4l2_subdev *sd,
465*4882a593Smuzhiyun struct tvp514x_decoder *decoder)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun int err;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /* common register initialization */
470*4882a593Smuzhiyun err =
471*4882a593Smuzhiyun tvp514x_write_regs(sd, decoder->tvp514x_regs);
472*4882a593Smuzhiyun if (err)
473*4882a593Smuzhiyun return err;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun if (debug)
476*4882a593Smuzhiyun tvp514x_reg_dump(sd);
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun return 0;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun /**
482*4882a593Smuzhiyun * tvp514x_detect() - Detect if an tvp514x is present, and if so which revision.
483*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
484*4882a593Smuzhiyun * @decoder: pointer to tvp514x_decoder structure
485*4882a593Smuzhiyun *
486*4882a593Smuzhiyun * A device is considered to be detected if the chip ID (LSB and MSB)
487*4882a593Smuzhiyun * registers match the expected values.
488*4882a593Smuzhiyun * Any value of the rom version register is accepted.
489*4882a593Smuzhiyun * Returns ENODEV error number if no device is detected, or zero
490*4882a593Smuzhiyun * if a device is detected.
491*4882a593Smuzhiyun */
tvp514x_detect(struct v4l2_subdev * sd,struct tvp514x_decoder * decoder)492*4882a593Smuzhiyun static int tvp514x_detect(struct v4l2_subdev *sd,
493*4882a593Smuzhiyun struct tvp514x_decoder *decoder)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun u8 chip_id_msb, chip_id_lsb, rom_ver;
496*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun chip_id_msb = tvp514x_read_reg(sd, REG_CHIP_ID_MSB);
499*4882a593Smuzhiyun chip_id_lsb = tvp514x_read_reg(sd, REG_CHIP_ID_LSB);
500*4882a593Smuzhiyun rom_ver = tvp514x_read_reg(sd, REG_ROM_VERSION);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun v4l2_dbg(1, debug, sd,
503*4882a593Smuzhiyun "chip id detected msb:0x%x lsb:0x%x rom version:0x%x\n",
504*4882a593Smuzhiyun chip_id_msb, chip_id_lsb, rom_ver);
505*4882a593Smuzhiyun if ((chip_id_msb != TVP514X_CHIP_ID_MSB)
506*4882a593Smuzhiyun || ((chip_id_lsb != TVP5146_CHIP_ID_LSB)
507*4882a593Smuzhiyun && (chip_id_lsb != TVP5147_CHIP_ID_LSB))) {
508*4882a593Smuzhiyun /* We didn't read the values we expected, so this must not be
509*4882a593Smuzhiyun * an TVP5146/47.
510*4882a593Smuzhiyun */
511*4882a593Smuzhiyun v4l2_err(sd, "chip id mismatch msb:0x%x lsb:0x%x\n",
512*4882a593Smuzhiyun chip_id_msb, chip_id_lsb);
513*4882a593Smuzhiyun return -ENODEV;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun decoder->ver = rom_ver;
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun v4l2_info(sd, "%s (Version - 0x%.2x) found at 0x%x (%s)\n",
519*4882a593Smuzhiyun client->name, decoder->ver,
520*4882a593Smuzhiyun client->addr << 1, client->adapter->name);
521*4882a593Smuzhiyun return 0;
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun /**
525*4882a593Smuzhiyun * tvp514x_querystd() - V4L2 decoder interface handler for querystd
526*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
527*4882a593Smuzhiyun * @std_id: standard V4L2 std_id ioctl enum
528*4882a593Smuzhiyun *
529*4882a593Smuzhiyun * Returns the current standard detected by TVP5146/47. If no active input is
530*4882a593Smuzhiyun * detected then *std_id is set to 0 and the function returns 0.
531*4882a593Smuzhiyun */
tvp514x_querystd(struct v4l2_subdev * sd,v4l2_std_id * std_id)532*4882a593Smuzhiyun static int tvp514x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std_id)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
535*4882a593Smuzhiyun enum tvp514x_std current_std;
536*4882a593Smuzhiyun enum tvp514x_input input_sel;
537*4882a593Smuzhiyun u8 sync_lock_status, lock_mask;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun if (std_id == NULL)
540*4882a593Smuzhiyun return -EINVAL;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun /* To query the standard the TVP514x must power on the ADCs. */
543*4882a593Smuzhiyun if (!decoder->streaming) {
544*4882a593Smuzhiyun tvp514x_s_stream(sd, 1);
545*4882a593Smuzhiyun msleep(LOCK_RETRY_DELAY);
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun /* query the current standard */
549*4882a593Smuzhiyun current_std = tvp514x_query_current_std(sd);
550*4882a593Smuzhiyun if (current_std == STD_INVALID) {
551*4882a593Smuzhiyun *std_id = V4L2_STD_UNKNOWN;
552*4882a593Smuzhiyun return 0;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun input_sel = decoder->input;
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun switch (input_sel) {
558*4882a593Smuzhiyun case INPUT_CVBS_VI1A:
559*4882a593Smuzhiyun case INPUT_CVBS_VI1B:
560*4882a593Smuzhiyun case INPUT_CVBS_VI1C:
561*4882a593Smuzhiyun case INPUT_CVBS_VI2A:
562*4882a593Smuzhiyun case INPUT_CVBS_VI2B:
563*4882a593Smuzhiyun case INPUT_CVBS_VI2C:
564*4882a593Smuzhiyun case INPUT_CVBS_VI3A:
565*4882a593Smuzhiyun case INPUT_CVBS_VI3B:
566*4882a593Smuzhiyun case INPUT_CVBS_VI3C:
567*4882a593Smuzhiyun case INPUT_CVBS_VI4A:
568*4882a593Smuzhiyun lock_mask = STATUS_CLR_SUBCAR_LOCK_BIT |
569*4882a593Smuzhiyun STATUS_HORZ_SYNC_LOCK_BIT |
570*4882a593Smuzhiyun STATUS_VIRT_SYNC_LOCK_BIT;
571*4882a593Smuzhiyun break;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun case INPUT_SVIDEO_VI2A_VI1A:
574*4882a593Smuzhiyun case INPUT_SVIDEO_VI2B_VI1B:
575*4882a593Smuzhiyun case INPUT_SVIDEO_VI2C_VI1C:
576*4882a593Smuzhiyun case INPUT_SVIDEO_VI2A_VI3A:
577*4882a593Smuzhiyun case INPUT_SVIDEO_VI2B_VI3B:
578*4882a593Smuzhiyun case INPUT_SVIDEO_VI2C_VI3C:
579*4882a593Smuzhiyun case INPUT_SVIDEO_VI4A_VI1A:
580*4882a593Smuzhiyun case INPUT_SVIDEO_VI4A_VI1B:
581*4882a593Smuzhiyun case INPUT_SVIDEO_VI4A_VI1C:
582*4882a593Smuzhiyun case INPUT_SVIDEO_VI4A_VI3A:
583*4882a593Smuzhiyun case INPUT_SVIDEO_VI4A_VI3B:
584*4882a593Smuzhiyun case INPUT_SVIDEO_VI4A_VI3C:
585*4882a593Smuzhiyun lock_mask = STATUS_HORZ_SYNC_LOCK_BIT |
586*4882a593Smuzhiyun STATUS_VIRT_SYNC_LOCK_BIT;
587*4882a593Smuzhiyun break;
588*4882a593Smuzhiyun /*Need to add other interfaces*/
589*4882a593Smuzhiyun default:
590*4882a593Smuzhiyun return -EINVAL;
591*4882a593Smuzhiyun }
592*4882a593Smuzhiyun /* check whether signal is locked */
593*4882a593Smuzhiyun sync_lock_status = tvp514x_read_reg(sd, REG_STATUS1);
594*4882a593Smuzhiyun if (lock_mask != (sync_lock_status & lock_mask)) {
595*4882a593Smuzhiyun *std_id = V4L2_STD_UNKNOWN;
596*4882a593Smuzhiyun return 0; /* No input detected */
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun *std_id &= decoder->std_list[current_std].standard.id;
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "Current STD: %s\n",
602*4882a593Smuzhiyun decoder->std_list[current_std].standard.name);
603*4882a593Smuzhiyun return 0;
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun /**
607*4882a593Smuzhiyun * tvp514x_s_std() - V4L2 decoder interface handler for s_std
608*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
609*4882a593Smuzhiyun * @std_id: standard V4L2 v4l2_std_id ioctl enum
610*4882a593Smuzhiyun *
611*4882a593Smuzhiyun * If std_id is supported, sets the requested standard. Otherwise, returns
612*4882a593Smuzhiyun * -EINVAL
613*4882a593Smuzhiyun */
tvp514x_s_std(struct v4l2_subdev * sd,v4l2_std_id std_id)614*4882a593Smuzhiyun static int tvp514x_s_std(struct v4l2_subdev *sd, v4l2_std_id std_id)
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
617*4882a593Smuzhiyun int err, i;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun for (i = 0; i < decoder->num_stds; i++)
620*4882a593Smuzhiyun if (std_id & decoder->std_list[i].standard.id)
621*4882a593Smuzhiyun break;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun if ((i == decoder->num_stds) || (i == STD_INVALID))
624*4882a593Smuzhiyun return -EINVAL;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_VIDEO_STD,
627*4882a593Smuzhiyun decoder->std_list[i].video_std);
628*4882a593Smuzhiyun if (err)
629*4882a593Smuzhiyun return err;
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun decoder->current_std = i;
632*4882a593Smuzhiyun decoder->tvp514x_regs[REG_VIDEO_STD].val =
633*4882a593Smuzhiyun decoder->std_list[i].video_std;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "Standard set to: %s\n",
636*4882a593Smuzhiyun decoder->std_list[i].standard.name);
637*4882a593Smuzhiyun return 0;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun /**
641*4882a593Smuzhiyun * tvp514x_s_routing() - V4L2 decoder interface handler for s_routing
642*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
643*4882a593Smuzhiyun * @input: input selector for routing the signal
644*4882a593Smuzhiyun * @output: output selector for routing the signal
645*4882a593Smuzhiyun * @config: config value. Not used
646*4882a593Smuzhiyun *
647*4882a593Smuzhiyun * If index is valid, selects the requested input. Otherwise, returns -EINVAL if
648*4882a593Smuzhiyun * the input is not supported or there is no active signal present in the
649*4882a593Smuzhiyun * selected input.
650*4882a593Smuzhiyun */
tvp514x_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)651*4882a593Smuzhiyun static int tvp514x_s_routing(struct v4l2_subdev *sd,
652*4882a593Smuzhiyun u32 input, u32 output, u32 config)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
655*4882a593Smuzhiyun int err;
656*4882a593Smuzhiyun enum tvp514x_input input_sel;
657*4882a593Smuzhiyun enum tvp514x_output output_sel;
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun if ((input >= INPUT_INVALID) ||
660*4882a593Smuzhiyun (output >= OUTPUT_INVALID))
661*4882a593Smuzhiyun /* Index out of bound */
662*4882a593Smuzhiyun return -EINVAL;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun input_sel = input;
665*4882a593Smuzhiyun output_sel = output;
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_INPUT_SEL, input_sel);
668*4882a593Smuzhiyun if (err)
669*4882a593Smuzhiyun return err;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun output_sel |= tvp514x_read_reg(sd,
672*4882a593Smuzhiyun REG_OUTPUT_FORMATTER1) & 0x7;
673*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_OUTPUT_FORMATTER1,
674*4882a593Smuzhiyun output_sel);
675*4882a593Smuzhiyun if (err)
676*4882a593Smuzhiyun return err;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun decoder->tvp514x_regs[REG_INPUT_SEL].val = input_sel;
679*4882a593Smuzhiyun decoder->tvp514x_regs[REG_OUTPUT_FORMATTER1].val = output_sel;
680*4882a593Smuzhiyun decoder->input = input;
681*4882a593Smuzhiyun decoder->output = output;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "Input set to: %d\n", input_sel);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun return 0;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun /**
689*4882a593Smuzhiyun * tvp514x_s_ctrl() - V4L2 decoder interface handler for s_ctrl
690*4882a593Smuzhiyun * @ctrl: pointer to v4l2_ctrl structure
691*4882a593Smuzhiyun *
692*4882a593Smuzhiyun * If the requested control is supported, sets the control's current
693*4882a593Smuzhiyun * value in HW. Otherwise, returns -EINVAL if the control is not supported.
694*4882a593Smuzhiyun */
tvp514x_s_ctrl(struct v4l2_ctrl * ctrl)695*4882a593Smuzhiyun static int tvp514x_s_ctrl(struct v4l2_ctrl *ctrl)
696*4882a593Smuzhiyun {
697*4882a593Smuzhiyun struct v4l2_subdev *sd = to_sd(ctrl);
698*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
699*4882a593Smuzhiyun int err = -EINVAL, value;
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun value = ctrl->val;
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun switch (ctrl->id) {
704*4882a593Smuzhiyun case V4L2_CID_BRIGHTNESS:
705*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_BRIGHTNESS, value);
706*4882a593Smuzhiyun if (!err)
707*4882a593Smuzhiyun decoder->tvp514x_regs[REG_BRIGHTNESS].val = value;
708*4882a593Smuzhiyun break;
709*4882a593Smuzhiyun case V4L2_CID_CONTRAST:
710*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_CONTRAST, value);
711*4882a593Smuzhiyun if (!err)
712*4882a593Smuzhiyun decoder->tvp514x_regs[REG_CONTRAST].val = value;
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun case V4L2_CID_SATURATION:
715*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_SATURATION, value);
716*4882a593Smuzhiyun if (!err)
717*4882a593Smuzhiyun decoder->tvp514x_regs[REG_SATURATION].val = value;
718*4882a593Smuzhiyun break;
719*4882a593Smuzhiyun case V4L2_CID_HUE:
720*4882a593Smuzhiyun if (value == 180)
721*4882a593Smuzhiyun value = 0x7F;
722*4882a593Smuzhiyun else if (value == -180)
723*4882a593Smuzhiyun value = 0x80;
724*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_HUE, value);
725*4882a593Smuzhiyun if (!err)
726*4882a593Smuzhiyun decoder->tvp514x_regs[REG_HUE].val = value;
727*4882a593Smuzhiyun break;
728*4882a593Smuzhiyun case V4L2_CID_AUTOGAIN:
729*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_AFE_GAIN_CTRL, value ? 0x0f : 0x0c);
730*4882a593Smuzhiyun if (!err)
731*4882a593Smuzhiyun decoder->tvp514x_regs[REG_AFE_GAIN_CTRL].val = value;
732*4882a593Smuzhiyun break;
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun v4l2_dbg(1, debug, sd, "Set Control: ID - %d - %d\n",
736*4882a593Smuzhiyun ctrl->id, ctrl->val);
737*4882a593Smuzhiyun return err;
738*4882a593Smuzhiyun }
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun /**
741*4882a593Smuzhiyun * tvp514x_g_frame_interval() - V4L2 decoder interface handler
742*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
743*4882a593Smuzhiyun * @ival: pointer to a v4l2_subdev_frame_interval structure
744*4882a593Smuzhiyun *
745*4882a593Smuzhiyun * Returns the decoder's video CAPTURE parameters.
746*4882a593Smuzhiyun */
747*4882a593Smuzhiyun static int
tvp514x_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * ival)748*4882a593Smuzhiyun tvp514x_g_frame_interval(struct v4l2_subdev *sd,
749*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *ival)
750*4882a593Smuzhiyun {
751*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
752*4882a593Smuzhiyun enum tvp514x_std current_std;
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun /* get the current standard */
756*4882a593Smuzhiyun current_std = decoder->current_std;
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun ival->interval =
759*4882a593Smuzhiyun decoder->std_list[current_std].standard.frameperiod;
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun return 0;
762*4882a593Smuzhiyun }
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun /**
765*4882a593Smuzhiyun * tvp514x_s_frame_interval() - V4L2 decoder interface handler
766*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
767*4882a593Smuzhiyun * @ival: pointer to a v4l2_subdev_frame_interval structure
768*4882a593Smuzhiyun *
769*4882a593Smuzhiyun * Configures the decoder to use the input parameters, if possible. If
770*4882a593Smuzhiyun * not possible, returns the appropriate error code.
771*4882a593Smuzhiyun */
772*4882a593Smuzhiyun static int
tvp514x_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * ival)773*4882a593Smuzhiyun tvp514x_s_frame_interval(struct v4l2_subdev *sd,
774*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *ival)
775*4882a593Smuzhiyun {
776*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
777*4882a593Smuzhiyun struct v4l2_fract *timeperframe;
778*4882a593Smuzhiyun enum tvp514x_std current_std;
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun timeperframe = &ival->interval;
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun /* get the current standard */
784*4882a593Smuzhiyun current_std = decoder->current_std;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun *timeperframe =
787*4882a593Smuzhiyun decoder->std_list[current_std].standard.frameperiod;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun return 0;
790*4882a593Smuzhiyun }
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun /**
793*4882a593Smuzhiyun * tvp514x_s_stream() - V4L2 decoder i/f handler for s_stream
794*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
795*4882a593Smuzhiyun * @enable: streaming enable or disable
796*4882a593Smuzhiyun *
797*4882a593Smuzhiyun * Sets streaming to enable or disable, if possible.
798*4882a593Smuzhiyun */
tvp514x_s_stream(struct v4l2_subdev * sd,int enable)799*4882a593Smuzhiyun static int tvp514x_s_stream(struct v4l2_subdev *sd, int enable)
800*4882a593Smuzhiyun {
801*4882a593Smuzhiyun int err = 0;
802*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun if (decoder->streaming == enable)
805*4882a593Smuzhiyun return 0;
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun switch (enable) {
808*4882a593Smuzhiyun case 0:
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun /* Power Down Sequence */
811*4882a593Smuzhiyun err = tvp514x_write_reg(sd, REG_OPERATION_MODE, 0x01);
812*4882a593Smuzhiyun if (err) {
813*4882a593Smuzhiyun v4l2_err(sd, "Unable to turn off decoder\n");
814*4882a593Smuzhiyun return err;
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun decoder->streaming = enable;
817*4882a593Smuzhiyun break;
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun case 1:
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun /* Power Up Sequence */
822*4882a593Smuzhiyun err = tvp514x_write_regs(sd, decoder->int_seq);
823*4882a593Smuzhiyun if (err) {
824*4882a593Smuzhiyun v4l2_err(sd, "Unable to turn on decoder\n");
825*4882a593Smuzhiyun return err;
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun /* Detect if not already detected */
828*4882a593Smuzhiyun err = tvp514x_detect(sd, decoder);
829*4882a593Smuzhiyun if (err) {
830*4882a593Smuzhiyun v4l2_err(sd, "Unable to detect decoder\n");
831*4882a593Smuzhiyun return err;
832*4882a593Smuzhiyun }
833*4882a593Smuzhiyun err = tvp514x_configure(sd, decoder);
834*4882a593Smuzhiyun if (err) {
835*4882a593Smuzhiyun v4l2_err(sd, "Unable to configure decoder\n");
836*4882a593Smuzhiyun return err;
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun decoder->streaming = enable;
839*4882a593Smuzhiyun break;
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun default:
842*4882a593Smuzhiyun err = -ENODEV;
843*4882a593Smuzhiyun break;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun return err;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun static const struct v4l2_ctrl_ops tvp514x_ctrl_ops = {
850*4882a593Smuzhiyun .s_ctrl = tvp514x_s_ctrl,
851*4882a593Smuzhiyun };
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun /**
854*4882a593Smuzhiyun * tvp514x_enum_mbus_code() - V4L2 decoder interface handler for enum_mbus_code
855*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
856*4882a593Smuzhiyun * @cfg: pad configuration
857*4882a593Smuzhiyun * @code: pointer to v4l2_subdev_mbus_code_enum structure
858*4882a593Smuzhiyun *
859*4882a593Smuzhiyun * Enumertaes mbus codes supported
860*4882a593Smuzhiyun */
tvp514x_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)861*4882a593Smuzhiyun static int tvp514x_enum_mbus_code(struct v4l2_subdev *sd,
862*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
863*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
864*4882a593Smuzhiyun {
865*4882a593Smuzhiyun u32 pad = code->pad;
866*4882a593Smuzhiyun u32 index = code->index;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun memset(code, 0, sizeof(*code));
869*4882a593Smuzhiyun code->index = index;
870*4882a593Smuzhiyun code->pad = pad;
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun if (index != 0)
873*4882a593Smuzhiyun return -EINVAL;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun code->code = MEDIA_BUS_FMT_UYVY8_2X8;
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun return 0;
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun /**
881*4882a593Smuzhiyun * tvp514x_get_pad_format() - V4L2 decoder interface handler for get pad format
882*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
883*4882a593Smuzhiyun * @cfg: pad configuration
884*4882a593Smuzhiyun * @format: pointer to v4l2_subdev_format structure
885*4882a593Smuzhiyun *
886*4882a593Smuzhiyun * Retrieves pad format which is active or tried based on requirement
887*4882a593Smuzhiyun */
tvp514x_get_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)888*4882a593Smuzhiyun static int tvp514x_get_pad_format(struct v4l2_subdev *sd,
889*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
890*4882a593Smuzhiyun struct v4l2_subdev_format *format)
891*4882a593Smuzhiyun {
892*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
893*4882a593Smuzhiyun __u32 which = format->which;
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun if (format->pad)
896*4882a593Smuzhiyun return -EINVAL;
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
899*4882a593Smuzhiyun format->format = decoder->format;
900*4882a593Smuzhiyun return 0;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun format->format.code = MEDIA_BUS_FMT_UYVY8_2X8;
904*4882a593Smuzhiyun format->format.width = tvp514x_std_list[decoder->current_std].width;
905*4882a593Smuzhiyun format->format.height = tvp514x_std_list[decoder->current_std].height;
906*4882a593Smuzhiyun format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
907*4882a593Smuzhiyun format->format.field = V4L2_FIELD_INTERLACED;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun return 0;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun /**
913*4882a593Smuzhiyun * tvp514x_set_pad_format() - V4L2 decoder interface handler for set pad format
914*4882a593Smuzhiyun * @sd: pointer to standard V4L2 sub-device structure
915*4882a593Smuzhiyun * @cfg: pad configuration
916*4882a593Smuzhiyun * @fmt: pointer to v4l2_subdev_format structure
917*4882a593Smuzhiyun *
918*4882a593Smuzhiyun * Set pad format for the output pad
919*4882a593Smuzhiyun */
tvp514x_set_pad_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)920*4882a593Smuzhiyun static int tvp514x_set_pad_format(struct v4l2_subdev *sd,
921*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
922*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
923*4882a593Smuzhiyun {
924*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun if (fmt->format.field != V4L2_FIELD_INTERLACED ||
927*4882a593Smuzhiyun fmt->format.code != MEDIA_BUS_FMT_UYVY8_2X8 ||
928*4882a593Smuzhiyun fmt->format.colorspace != V4L2_COLORSPACE_SMPTE170M ||
929*4882a593Smuzhiyun fmt->format.width != tvp514x_std_list[decoder->current_std].width ||
930*4882a593Smuzhiyun fmt->format.height != tvp514x_std_list[decoder->current_std].height)
931*4882a593Smuzhiyun return -EINVAL;
932*4882a593Smuzhiyun
933*4882a593Smuzhiyun decoder->format = fmt->format;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun return 0;
936*4882a593Smuzhiyun }
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops tvp514x_video_ops = {
939*4882a593Smuzhiyun .s_std = tvp514x_s_std,
940*4882a593Smuzhiyun .s_routing = tvp514x_s_routing,
941*4882a593Smuzhiyun .querystd = tvp514x_querystd,
942*4882a593Smuzhiyun .g_frame_interval = tvp514x_g_frame_interval,
943*4882a593Smuzhiyun .s_frame_interval = tvp514x_s_frame_interval,
944*4882a593Smuzhiyun .s_stream = tvp514x_s_stream,
945*4882a593Smuzhiyun };
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops tvp514x_pad_ops = {
948*4882a593Smuzhiyun .enum_mbus_code = tvp514x_enum_mbus_code,
949*4882a593Smuzhiyun .get_fmt = tvp514x_get_pad_format,
950*4882a593Smuzhiyun .set_fmt = tvp514x_set_pad_format,
951*4882a593Smuzhiyun };
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun static const struct v4l2_subdev_ops tvp514x_ops = {
954*4882a593Smuzhiyun .video = &tvp514x_video_ops,
955*4882a593Smuzhiyun .pad = &tvp514x_pad_ops,
956*4882a593Smuzhiyun };
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun static const struct tvp514x_decoder tvp514x_dev = {
959*4882a593Smuzhiyun .streaming = 0,
960*4882a593Smuzhiyun .fmt_list = tvp514x_fmt_list,
961*4882a593Smuzhiyun .num_fmts = ARRAY_SIZE(tvp514x_fmt_list),
962*4882a593Smuzhiyun .pix = {
963*4882a593Smuzhiyun /* Default to NTSC 8-bit YUV 422 */
964*4882a593Smuzhiyun .width = NTSC_NUM_ACTIVE_PIXELS,
965*4882a593Smuzhiyun .height = NTSC_NUM_ACTIVE_LINES,
966*4882a593Smuzhiyun .pixelformat = V4L2_PIX_FMT_UYVY,
967*4882a593Smuzhiyun .field = V4L2_FIELD_INTERLACED,
968*4882a593Smuzhiyun .bytesperline = NTSC_NUM_ACTIVE_PIXELS * 2,
969*4882a593Smuzhiyun .sizeimage = NTSC_NUM_ACTIVE_PIXELS * 2 *
970*4882a593Smuzhiyun NTSC_NUM_ACTIVE_LINES,
971*4882a593Smuzhiyun .colorspace = V4L2_COLORSPACE_SMPTE170M,
972*4882a593Smuzhiyun },
973*4882a593Smuzhiyun .current_std = STD_NTSC_MJ,
974*4882a593Smuzhiyun .std_list = tvp514x_std_list,
975*4882a593Smuzhiyun .num_stds = ARRAY_SIZE(tvp514x_std_list),
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun };
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun static struct tvp514x_platform_data *
tvp514x_get_pdata(struct i2c_client * client)980*4882a593Smuzhiyun tvp514x_get_pdata(struct i2c_client *client)
981*4882a593Smuzhiyun {
982*4882a593Smuzhiyun struct tvp514x_platform_data *pdata = NULL;
983*4882a593Smuzhiyun struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
984*4882a593Smuzhiyun struct device_node *endpoint;
985*4882a593Smuzhiyun unsigned int flags;
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
988*4882a593Smuzhiyun return client->dev.platform_data;
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun endpoint = of_graph_get_next_endpoint(client->dev.of_node, NULL);
991*4882a593Smuzhiyun if (!endpoint)
992*4882a593Smuzhiyun return NULL;
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg))
995*4882a593Smuzhiyun goto done;
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
998*4882a593Smuzhiyun if (!pdata)
999*4882a593Smuzhiyun goto done;
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun flags = bus_cfg.bus.parallel.flags;
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1004*4882a593Smuzhiyun pdata->hs_polarity = 1;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1007*4882a593Smuzhiyun pdata->vs_polarity = 1;
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1010*4882a593Smuzhiyun pdata->clk_polarity = 1;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun done:
1013*4882a593Smuzhiyun of_node_put(endpoint);
1014*4882a593Smuzhiyun return pdata;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun
1017*4882a593Smuzhiyun /**
1018*4882a593Smuzhiyun * tvp514x_probe() - decoder driver i2c probe handler
1019*4882a593Smuzhiyun * @client: i2c driver client device structure
1020*4882a593Smuzhiyun * @id: i2c driver id table
1021*4882a593Smuzhiyun *
1022*4882a593Smuzhiyun * Register decoder as an i2c client device and V4L2
1023*4882a593Smuzhiyun * device.
1024*4882a593Smuzhiyun */
1025*4882a593Smuzhiyun static int
tvp514x_probe(struct i2c_client * client,const struct i2c_device_id * id)1026*4882a593Smuzhiyun tvp514x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun struct tvp514x_platform_data *pdata = tvp514x_get_pdata(client);
1029*4882a593Smuzhiyun struct tvp514x_decoder *decoder;
1030*4882a593Smuzhiyun struct v4l2_subdev *sd;
1031*4882a593Smuzhiyun int ret;
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun if (pdata == NULL) {
1034*4882a593Smuzhiyun dev_err(&client->dev, "No platform data\n");
1035*4882a593Smuzhiyun return -EINVAL;
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun /* Check if the adapter supports the needed features */
1039*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1040*4882a593Smuzhiyun return -EIO;
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
1043*4882a593Smuzhiyun if (!decoder)
1044*4882a593Smuzhiyun return -ENOMEM;
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun /* Initialize the tvp514x_decoder with default configuration */
1047*4882a593Smuzhiyun *decoder = tvp514x_dev;
1048*4882a593Smuzhiyun /* Copy default register configuration */
1049*4882a593Smuzhiyun memcpy(decoder->tvp514x_regs, tvp514x_reg_list_default,
1050*4882a593Smuzhiyun sizeof(tvp514x_reg_list_default));
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun decoder->int_seq = (struct tvp514x_reg *)id->driver_data;
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun /* Copy board specific information here */
1055*4882a593Smuzhiyun decoder->pdata = pdata;
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun /**
1058*4882a593Smuzhiyun * Fetch platform specific data, and configure the
1059*4882a593Smuzhiyun * tvp514x_reg_list[] accordingly. Since this is one
1060*4882a593Smuzhiyun * time configuration, no need to preserve.
1061*4882a593Smuzhiyun */
1062*4882a593Smuzhiyun decoder->tvp514x_regs[REG_OUTPUT_FORMATTER2].val |=
1063*4882a593Smuzhiyun (decoder->pdata->clk_polarity << 1);
1064*4882a593Smuzhiyun decoder->tvp514x_regs[REG_SYNC_CONTROL].val |=
1065*4882a593Smuzhiyun ((decoder->pdata->hs_polarity << 2) |
1066*4882a593Smuzhiyun (decoder->pdata->vs_polarity << 3));
1067*4882a593Smuzhiyun /* Set default standard to auto */
1068*4882a593Smuzhiyun decoder->tvp514x_regs[REG_VIDEO_STD].val =
1069*4882a593Smuzhiyun VIDEO_STD_AUTO_SWITCH_BIT;
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun /* Register with V4L2 layer as slave device */
1072*4882a593Smuzhiyun sd = &decoder->sd;
1073*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &tvp514x_ops);
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1076*4882a593Smuzhiyun decoder->pad.flags = MEDIA_PAD_FL_SOURCE;
1077*4882a593Smuzhiyun decoder->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1078*4882a593Smuzhiyun decoder->sd.entity.function = MEDIA_ENT_F_ATV_DECODER;
1079*4882a593Smuzhiyun
1080*4882a593Smuzhiyun ret = media_entity_pads_init(&decoder->sd.entity, 1, &decoder->pad);
1081*4882a593Smuzhiyun if (ret < 0) {
1082*4882a593Smuzhiyun v4l2_err(sd, "%s decoder driver failed to register !!\n",
1083*4882a593Smuzhiyun sd->name);
1084*4882a593Smuzhiyun return ret;
1085*4882a593Smuzhiyun }
1086*4882a593Smuzhiyun #endif
1087*4882a593Smuzhiyun v4l2_ctrl_handler_init(&decoder->hdl, 5);
1088*4882a593Smuzhiyun v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1089*4882a593Smuzhiyun V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1090*4882a593Smuzhiyun v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1091*4882a593Smuzhiyun V4L2_CID_CONTRAST, 0, 255, 1, 128);
1092*4882a593Smuzhiyun v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1093*4882a593Smuzhiyun V4L2_CID_SATURATION, 0, 255, 1, 128);
1094*4882a593Smuzhiyun v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1095*4882a593Smuzhiyun V4L2_CID_HUE, -180, 180, 180, 0);
1096*4882a593Smuzhiyun v4l2_ctrl_new_std(&decoder->hdl, &tvp514x_ctrl_ops,
1097*4882a593Smuzhiyun V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1098*4882a593Smuzhiyun sd->ctrl_handler = &decoder->hdl;
1099*4882a593Smuzhiyun if (decoder->hdl.error) {
1100*4882a593Smuzhiyun ret = decoder->hdl.error;
1101*4882a593Smuzhiyun goto done;
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun v4l2_ctrl_handler_setup(&decoder->hdl);
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun ret = v4l2_async_register_subdev(&decoder->sd);
1106*4882a593Smuzhiyun if (!ret)
1107*4882a593Smuzhiyun v4l2_info(sd, "%s decoder driver registered !!\n", sd->name);
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun done:
1110*4882a593Smuzhiyun if (ret < 0) {
1111*4882a593Smuzhiyun v4l2_ctrl_handler_free(&decoder->hdl);
1112*4882a593Smuzhiyun media_entity_cleanup(&decoder->sd.entity);
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun return ret;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun /**
1118*4882a593Smuzhiyun * tvp514x_remove() - decoder driver i2c remove handler
1119*4882a593Smuzhiyun * @client: i2c driver client device structure
1120*4882a593Smuzhiyun *
1121*4882a593Smuzhiyun * Unregister decoder as an i2c client device and V4L2
1122*4882a593Smuzhiyun * device. Complement of tvp514x_probe().
1123*4882a593Smuzhiyun */
tvp514x_remove(struct i2c_client * client)1124*4882a593Smuzhiyun static int tvp514x_remove(struct i2c_client *client)
1125*4882a593Smuzhiyun {
1126*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1127*4882a593Smuzhiyun struct tvp514x_decoder *decoder = to_decoder(sd);
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun v4l2_async_unregister_subdev(&decoder->sd);
1130*4882a593Smuzhiyun media_entity_cleanup(&decoder->sd.entity);
1131*4882a593Smuzhiyun v4l2_ctrl_handler_free(&decoder->hdl);
1132*4882a593Smuzhiyun return 0;
1133*4882a593Smuzhiyun }
1134*4882a593Smuzhiyun /* TVP5146 Init/Power on Sequence */
1135*4882a593Smuzhiyun static const struct tvp514x_reg tvp5146_init_reg_seq[] = {
1136*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1137*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1138*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1139*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1140*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1141*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1142*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1143*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1144*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1145*4882a593Smuzhiyun {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1146*4882a593Smuzhiyun {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1147*4882a593Smuzhiyun {TOK_TERM, 0, 0},
1148*4882a593Smuzhiyun };
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun /* TVP5147 Init/Power on Sequence */
1151*4882a593Smuzhiyun static const struct tvp514x_reg tvp5147_init_reg_seq[] = {
1152*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x02},
1153*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1154*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0x80},
1155*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1156*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1157*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1158*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1159*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x01},
1160*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x16},
1161*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1162*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xA0},
1163*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x16},
1164*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS1, 0x60},
1165*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS2, 0x00},
1166*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_ADDRESS_ACCESS3, 0xB0},
1167*4882a593Smuzhiyun {TOK_WRITE, REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR, 0x00},
1168*4882a593Smuzhiyun {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1169*4882a593Smuzhiyun {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1170*4882a593Smuzhiyun {TOK_TERM, 0, 0},
1171*4882a593Smuzhiyun };
1172*4882a593Smuzhiyun
1173*4882a593Smuzhiyun /* TVP5146M2/TVP5147M1 Init/Power on Sequence */
1174*4882a593Smuzhiyun static const struct tvp514x_reg tvp514xm_init_reg_seq[] = {
1175*4882a593Smuzhiyun {TOK_WRITE, REG_OPERATION_MODE, 0x01},
1176*4882a593Smuzhiyun {TOK_WRITE, REG_OPERATION_MODE, 0x00},
1177*4882a593Smuzhiyun {TOK_TERM, 0, 0},
1178*4882a593Smuzhiyun };
1179*4882a593Smuzhiyun
1180*4882a593Smuzhiyun /*
1181*4882a593Smuzhiyun * I2C Device Table -
1182*4882a593Smuzhiyun *
1183*4882a593Smuzhiyun * name - Name of the actual device/chip.
1184*4882a593Smuzhiyun * driver_data - Driver data
1185*4882a593Smuzhiyun */
1186*4882a593Smuzhiyun static const struct i2c_device_id tvp514x_id[] = {
1187*4882a593Smuzhiyun {"tvp5146", (unsigned long)tvp5146_init_reg_seq},
1188*4882a593Smuzhiyun {"tvp5146m2", (unsigned long)tvp514xm_init_reg_seq},
1189*4882a593Smuzhiyun {"tvp5147", (unsigned long)tvp5147_init_reg_seq},
1190*4882a593Smuzhiyun {"tvp5147m1", (unsigned long)tvp514xm_init_reg_seq},
1191*4882a593Smuzhiyun {},
1192*4882a593Smuzhiyun };
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, tvp514x_id);
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1197*4882a593Smuzhiyun static const struct of_device_id tvp514x_of_match[] = {
1198*4882a593Smuzhiyun { .compatible = "ti,tvp5146", },
1199*4882a593Smuzhiyun { .compatible = "ti,tvp5146m2", },
1200*4882a593Smuzhiyun { .compatible = "ti,tvp5147", },
1201*4882a593Smuzhiyun { .compatible = "ti,tvp5147m1", },
1202*4882a593Smuzhiyun { /* sentinel */ },
1203*4882a593Smuzhiyun };
1204*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tvp514x_of_match);
1205*4882a593Smuzhiyun #endif
1206*4882a593Smuzhiyun
1207*4882a593Smuzhiyun static struct i2c_driver tvp514x_driver = {
1208*4882a593Smuzhiyun .driver = {
1209*4882a593Smuzhiyun .of_match_table = of_match_ptr(tvp514x_of_match),
1210*4882a593Smuzhiyun .name = TVP514X_MODULE_NAME,
1211*4882a593Smuzhiyun },
1212*4882a593Smuzhiyun .probe = tvp514x_probe,
1213*4882a593Smuzhiyun .remove = tvp514x_remove,
1214*4882a593Smuzhiyun .id_table = tvp514x_id,
1215*4882a593Smuzhiyun };
1216*4882a593Smuzhiyun
1217*4882a593Smuzhiyun module_i2c_driver(tvp514x_driver);
1218