xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/ths7303.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * ths7303/53- THS7303/53 Video Amplifier driver
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5*4882a593Smuzhiyun  * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Author: Chaithrika U S <chaithrika@ti.com>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Contributors:
10*4882a593Smuzhiyun  *     Hans Verkuil <hans.verkuil@cisco.com>
11*4882a593Smuzhiyun  *     Lad, Prabhakar <prabhakar.lad@ti.com>
12*4882a593Smuzhiyun  *     Martin Bugge <marbugge@cisco.com>
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or
15*4882a593Smuzhiyun  * modify it under the terms of the GNU General Public License as
16*4882a593Smuzhiyun  * published by the Free Software Foundation version 2.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
19*4882a593Smuzhiyun  * kind, whether express or implied; without even the implied warranty
20*4882a593Smuzhiyun  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21*4882a593Smuzhiyun  * GNU General Public License for more details.
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include <linux/i2c.h>
25*4882a593Smuzhiyun #include <linux/module.h>
26*4882a593Smuzhiyun #include <linux/slab.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include <media/i2c/ths7303.h>
29*4882a593Smuzhiyun #include <media/v4l2-device.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define THS7303_CHANNEL_1	1
32*4882a593Smuzhiyun #define THS7303_CHANNEL_2	2
33*4882a593Smuzhiyun #define THS7303_CHANNEL_3	3
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun struct ths7303_state {
36*4882a593Smuzhiyun 	struct v4l2_subdev		sd;
37*4882a593Smuzhiyun 	const struct ths7303_platform_data *pdata;
38*4882a593Smuzhiyun 	struct v4l2_bt_timings		bt;
39*4882a593Smuzhiyun 	int std_id;
40*4882a593Smuzhiyun 	int stream_on;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun enum ths7303_filter_mode {
44*4882a593Smuzhiyun 	THS7303_FILTER_MODE_480I_576I,
45*4882a593Smuzhiyun 	THS7303_FILTER_MODE_480P_576P,
46*4882a593Smuzhiyun 	THS7303_FILTER_MODE_720P_1080I,
47*4882a593Smuzhiyun 	THS7303_FILTER_MODE_1080P,
48*4882a593Smuzhiyun 	THS7303_FILTER_MODE_DISABLE
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
52*4882a593Smuzhiyun MODULE_AUTHOR("Chaithrika U S");
53*4882a593Smuzhiyun MODULE_LICENSE("GPL");
54*4882a593Smuzhiyun 
to_state(struct v4l2_subdev * sd)55*4882a593Smuzhiyun static inline struct ths7303_state *to_state(struct v4l2_subdev *sd)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun 	return container_of(sd, struct ths7303_state, sd);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
ths7303_read(struct v4l2_subdev * sd,u8 reg)60*4882a593Smuzhiyun static int ths7303_read(struct v4l2_subdev *sd, u8 reg)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	return i2c_smbus_read_byte_data(client, reg);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun 
ths7303_write(struct v4l2_subdev * sd,u8 reg,u8 val)67*4882a593Smuzhiyun static int ths7303_write(struct v4l2_subdev *sd, u8 reg, u8 val)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
70*4882a593Smuzhiyun 	int ret;
71*4882a593Smuzhiyun 	int i;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	for (i = 0; i < 3; i++) {
74*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(client, reg, val);
75*4882a593Smuzhiyun 		if (ret == 0)
76*4882a593Smuzhiyun 			return 0;
77*4882a593Smuzhiyun 	}
78*4882a593Smuzhiyun 	return ret;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /* following function is used to set ths7303 */
ths7303_setval(struct v4l2_subdev * sd,enum ths7303_filter_mode mode)82*4882a593Smuzhiyun static int ths7303_setval(struct v4l2_subdev *sd,
83*4882a593Smuzhiyun 			  enum ths7303_filter_mode mode)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
86*4882a593Smuzhiyun 	struct ths7303_state *state = to_state(sd);
87*4882a593Smuzhiyun 	const struct ths7303_platform_data *pdata = state->pdata;
88*4882a593Smuzhiyun 	u8 val, sel = 0;
89*4882a593Smuzhiyun 	int err, disable = 0;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	if (!client)
92*4882a593Smuzhiyun 		return -EINVAL;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	switch (mode) {
95*4882a593Smuzhiyun 	case THS7303_FILTER_MODE_1080P:
96*4882a593Smuzhiyun 		sel = 0x3;	/*1080p and SXGA/UXGA */
97*4882a593Smuzhiyun 		break;
98*4882a593Smuzhiyun 	case THS7303_FILTER_MODE_720P_1080I:
99*4882a593Smuzhiyun 		sel = 0x2;	/*720p, 1080i and SVGA/XGA */
100*4882a593Smuzhiyun 		break;
101*4882a593Smuzhiyun 	case THS7303_FILTER_MODE_480P_576P:
102*4882a593Smuzhiyun 		sel = 0x1;	/* EDTV 480p/576p and VGA */
103*4882a593Smuzhiyun 		break;
104*4882a593Smuzhiyun 	case THS7303_FILTER_MODE_480I_576I:
105*4882a593Smuzhiyun 		sel = 0x0;	/* SDTV, S-Video, 480i/576i */
106*4882a593Smuzhiyun 		break;
107*4882a593Smuzhiyun 	default:
108*4882a593Smuzhiyun 		/* disable all channels */
109*4882a593Smuzhiyun 		disable = 1;
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	val = (sel << 6) | (sel << 3);
113*4882a593Smuzhiyun 	if (!disable)
114*4882a593Smuzhiyun 		val |= (pdata->ch_1 & 0x27);
115*4882a593Smuzhiyun 	err = ths7303_write(sd, THS7303_CHANNEL_1, val);
116*4882a593Smuzhiyun 	if (err)
117*4882a593Smuzhiyun 		goto out;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	val = (sel << 6) | (sel << 3);
120*4882a593Smuzhiyun 	if (!disable)
121*4882a593Smuzhiyun 		val |= (pdata->ch_2 & 0x27);
122*4882a593Smuzhiyun 	err = ths7303_write(sd, THS7303_CHANNEL_2, val);
123*4882a593Smuzhiyun 	if (err)
124*4882a593Smuzhiyun 		goto out;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	val = (sel << 6) | (sel << 3);
127*4882a593Smuzhiyun 	if (!disable)
128*4882a593Smuzhiyun 		val |= (pdata->ch_3 & 0x27);
129*4882a593Smuzhiyun 	err = ths7303_write(sd, THS7303_CHANNEL_3, val);
130*4882a593Smuzhiyun 	if (err)
131*4882a593Smuzhiyun 		goto out;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	return 0;
134*4882a593Smuzhiyun out:
135*4882a593Smuzhiyun 	pr_info("write byte data failed\n");
136*4882a593Smuzhiyun 	return err;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
ths7303_s_std_output(struct v4l2_subdev * sd,v4l2_std_id norm)139*4882a593Smuzhiyun static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	struct ths7303_state *state = to_state(sd);
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	if (norm & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
144*4882a593Smuzhiyun 		state->std_id = 1;
145*4882a593Smuzhiyun 		state->bt.pixelclock = 0;
146*4882a593Smuzhiyun 		return ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
147*4882a593Smuzhiyun 	}
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	return ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun 
ths7303_config(struct v4l2_subdev * sd)152*4882a593Smuzhiyun static int ths7303_config(struct v4l2_subdev *sd)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	struct ths7303_state *state = to_state(sd);
155*4882a593Smuzhiyun 	int res;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	if (!state->stream_on) {
158*4882a593Smuzhiyun 		ths7303_write(sd, THS7303_CHANNEL_1,
159*4882a593Smuzhiyun 			      (ths7303_read(sd, THS7303_CHANNEL_1) & 0xf8) |
160*4882a593Smuzhiyun 			      0x00);
161*4882a593Smuzhiyun 		ths7303_write(sd, THS7303_CHANNEL_2,
162*4882a593Smuzhiyun 			      (ths7303_read(sd, THS7303_CHANNEL_2) & 0xf8) |
163*4882a593Smuzhiyun 			      0x00);
164*4882a593Smuzhiyun 		ths7303_write(sd, THS7303_CHANNEL_3,
165*4882a593Smuzhiyun 			      (ths7303_read(sd, THS7303_CHANNEL_3) & 0xf8) |
166*4882a593Smuzhiyun 			      0x00);
167*4882a593Smuzhiyun 		return 0;
168*4882a593Smuzhiyun 	}
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	if (state->bt.pixelclock > 120000000)
171*4882a593Smuzhiyun 		res = ths7303_setval(sd, THS7303_FILTER_MODE_1080P);
172*4882a593Smuzhiyun 	else if (state->bt.pixelclock > 70000000)
173*4882a593Smuzhiyun 		res = ths7303_setval(sd, THS7303_FILTER_MODE_720P_1080I);
174*4882a593Smuzhiyun 	else if (state->bt.pixelclock > 20000000)
175*4882a593Smuzhiyun 		res = ths7303_setval(sd, THS7303_FILTER_MODE_480P_576P);
176*4882a593Smuzhiyun 	else if (state->std_id)
177*4882a593Smuzhiyun 		res = ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
178*4882a593Smuzhiyun 	else
179*4882a593Smuzhiyun 		/* disable all channels */
180*4882a593Smuzhiyun 		res = ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	return res;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun 
ths7303_s_stream(struct v4l2_subdev * sd,int enable)186*4882a593Smuzhiyun static int ths7303_s_stream(struct v4l2_subdev *sd, int enable)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	struct ths7303_state *state = to_state(sd);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	state->stream_on = enable;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	return ths7303_config(sd);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun /* for setting filter for HD output */
ths7303_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * dv_timings)196*4882a593Smuzhiyun static int ths7303_s_dv_timings(struct v4l2_subdev *sd,
197*4882a593Smuzhiyun 			       struct v4l2_dv_timings *dv_timings)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun 	struct ths7303_state *state = to_state(sd);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	if (!dv_timings || dv_timings->type != V4L2_DV_BT_656_1120)
202*4882a593Smuzhiyun 		return -EINVAL;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	state->bt = dv_timings->bt;
205*4882a593Smuzhiyun 	state->std_id = 0;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	return ths7303_config(sd);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops ths7303_video_ops = {
211*4882a593Smuzhiyun 	.s_stream	= ths7303_s_stream,
212*4882a593Smuzhiyun 	.s_std_output	= ths7303_s_std_output,
213*4882a593Smuzhiyun 	.s_dv_timings   = ths7303_s_dv_timings,
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
217*4882a593Smuzhiyun 
ths7303_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)218*4882a593Smuzhiyun static int ths7303_g_register(struct v4l2_subdev *sd,
219*4882a593Smuzhiyun 			      struct v4l2_dbg_register *reg)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun 	reg->size = 1;
222*4882a593Smuzhiyun 	reg->val = ths7303_read(sd, reg->reg);
223*4882a593Smuzhiyun 	return 0;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
ths7303_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)226*4882a593Smuzhiyun static int ths7303_s_register(struct v4l2_subdev *sd,
227*4882a593Smuzhiyun 			      const struct v4l2_dbg_register *reg)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	ths7303_write(sd, reg->reg, reg->val);
230*4882a593Smuzhiyun 	return 0;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun #endif
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun static const char * const stc_lpf_sel_txt[4] = {
235*4882a593Smuzhiyun 	"500-kHz Filter",
236*4882a593Smuzhiyun 	"2.5-MHz Filter",
237*4882a593Smuzhiyun 	"5-MHz Filter",
238*4882a593Smuzhiyun 	"5-MHz Filter",
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static const char * const in_mux_sel_txt[2] = {
242*4882a593Smuzhiyun 	"Input A Select",
243*4882a593Smuzhiyun 	"Input B Select",
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun static const char * const lpf_freq_sel_txt[4] = {
247*4882a593Smuzhiyun 	"9-MHz LPF",
248*4882a593Smuzhiyun 	"16-MHz LPF",
249*4882a593Smuzhiyun 	"35-MHz LPF",
250*4882a593Smuzhiyun 	"Bypass LPF",
251*4882a593Smuzhiyun };
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun static const char * const in_bias_sel_dis_cont_txt[8] = {
254*4882a593Smuzhiyun 	"Disable Channel",
255*4882a593Smuzhiyun 	"Mute Function - No Output",
256*4882a593Smuzhiyun 	"DC Bias Select",
257*4882a593Smuzhiyun 	"DC Bias + 250 mV Offset Select",
258*4882a593Smuzhiyun 	"AC Bias Select",
259*4882a593Smuzhiyun 	"Sync Tip Clamp with low bias",
260*4882a593Smuzhiyun 	"Sync Tip Clamp with mid bias",
261*4882a593Smuzhiyun 	"Sync Tip Clamp with high bias",
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun 
ths7303_log_channel_status(struct v4l2_subdev * sd,u8 reg)264*4882a593Smuzhiyun static void ths7303_log_channel_status(struct v4l2_subdev *sd, u8 reg)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	u8 val = ths7303_read(sd, reg);
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	if ((val & 0x7) == 0) {
269*4882a593Smuzhiyun 		v4l2_info(sd, "Channel %d Off\n", reg);
270*4882a593Smuzhiyun 		return;
271*4882a593Smuzhiyun 	}
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	v4l2_info(sd, "Channel %d On\n", reg);
274*4882a593Smuzhiyun 	v4l2_info(sd, "  value 0x%x\n", val);
275*4882a593Smuzhiyun 	v4l2_info(sd, "  %s\n", stc_lpf_sel_txt[(val >> 6) & 0x3]);
276*4882a593Smuzhiyun 	v4l2_info(sd, "  %s\n", in_mux_sel_txt[(val >> 5) & 0x1]);
277*4882a593Smuzhiyun 	v4l2_info(sd, "  %s\n", lpf_freq_sel_txt[(val >> 3) & 0x3]);
278*4882a593Smuzhiyun 	v4l2_info(sd, "  %s\n", in_bias_sel_dis_cont_txt[(val >> 0) & 0x7]);
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun 
ths7303_log_status(struct v4l2_subdev * sd)281*4882a593Smuzhiyun static int ths7303_log_status(struct v4l2_subdev *sd)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun 	struct ths7303_state *state = to_state(sd);
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	v4l2_info(sd, "stream %s\n", state->stream_on ? "On" : "Off");
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	if (state->bt.pixelclock) {
288*4882a593Smuzhiyun 		struct v4l2_bt_timings *bt = &state->bt;
289*4882a593Smuzhiyun 		u32 frame_width, frame_height;
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 		frame_width = V4L2_DV_BT_FRAME_WIDTH(bt);
292*4882a593Smuzhiyun 		frame_height = V4L2_DV_BT_FRAME_HEIGHT(bt);
293*4882a593Smuzhiyun 		v4l2_info(sd,
294*4882a593Smuzhiyun 			  "timings: %dx%d%s%d (%dx%d). Pix freq. = %d Hz. Polarities = 0x%x\n",
295*4882a593Smuzhiyun 			  bt->width, bt->height, bt->interlaced ? "i" : "p",
296*4882a593Smuzhiyun 			  (frame_height * frame_width) > 0 ?
297*4882a593Smuzhiyun 			  (int)bt->pixelclock /
298*4882a593Smuzhiyun 			  (frame_height * frame_width) : 0,
299*4882a593Smuzhiyun 			  frame_width, frame_height,
300*4882a593Smuzhiyun 			  (int)bt->pixelclock, bt->polarities);
301*4882a593Smuzhiyun 	} else {
302*4882a593Smuzhiyun 		v4l2_info(sd, "no timings set\n");
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	ths7303_log_channel_status(sd, THS7303_CHANNEL_1);
306*4882a593Smuzhiyun 	ths7303_log_channel_status(sd, THS7303_CHANNEL_2);
307*4882a593Smuzhiyun 	ths7303_log_channel_status(sd, THS7303_CHANNEL_3);
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	return 0;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops ths7303_core_ops = {
313*4882a593Smuzhiyun 	.log_status = ths7303_log_status,
314*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
315*4882a593Smuzhiyun 	.g_register = ths7303_g_register,
316*4882a593Smuzhiyun 	.s_register = ths7303_s_register,
317*4882a593Smuzhiyun #endif
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun static const struct v4l2_subdev_ops ths7303_ops = {
321*4882a593Smuzhiyun 	.core	= &ths7303_core_ops,
322*4882a593Smuzhiyun 	.video	= &ths7303_video_ops,
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun 
ths7303_probe(struct i2c_client * client,const struct i2c_device_id * id)325*4882a593Smuzhiyun static int ths7303_probe(struct i2c_client *client,
326*4882a593Smuzhiyun 			const struct i2c_device_id *id)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun 	struct ths7303_platform_data *pdata = client->dev.platform_data;
329*4882a593Smuzhiyun 	struct ths7303_state *state;
330*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	if (pdata == NULL) {
333*4882a593Smuzhiyun 		dev_err(&client->dev, "No platform data\n");
334*4882a593Smuzhiyun 		return -EINVAL;
335*4882a593Smuzhiyun 	}
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
338*4882a593Smuzhiyun 		return -ENODEV;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	v4l_info(client, "chip found @ 0x%x (%s)\n",
341*4882a593Smuzhiyun 			client->addr << 1, client->adapter->name);
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	state = devm_kzalloc(&client->dev, sizeof(struct ths7303_state),
344*4882a593Smuzhiyun 			     GFP_KERNEL);
345*4882a593Smuzhiyun 	if (!state)
346*4882a593Smuzhiyun 		return -ENOMEM;
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	state->pdata = pdata;
349*4882a593Smuzhiyun 	sd = &state->sd;
350*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	/* set to default 480I_576I filter mode */
353*4882a593Smuzhiyun 	if (ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I) < 0) {
354*4882a593Smuzhiyun 		v4l_err(client, "Setting to 480I_576I filter mode failed!\n");
355*4882a593Smuzhiyun 		return -EINVAL;
356*4882a593Smuzhiyun 	}
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	return 0;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun 
ths7303_remove(struct i2c_client * client)361*4882a593Smuzhiyun static int ths7303_remove(struct i2c_client *client)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	return 0;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun static const struct i2c_device_id ths7303_id[] = {
371*4882a593Smuzhiyun 	{"ths7303", 0},
372*4882a593Smuzhiyun 	{"ths7353", 0},
373*4882a593Smuzhiyun 	{},
374*4882a593Smuzhiyun };
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ths7303_id);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun static struct i2c_driver ths7303_driver = {
379*4882a593Smuzhiyun 	.driver = {
380*4882a593Smuzhiyun 		.name	= "ths73x3",
381*4882a593Smuzhiyun 	},
382*4882a593Smuzhiyun 	.probe		= ths7303_probe,
383*4882a593Smuzhiyun 	.remove		= ths7303_remove,
384*4882a593Smuzhiyun 	.id_table	= ths7303_id,
385*4882a593Smuzhiyun };
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun module_i2c_driver(ths7303_driver);
388