1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * thcv241 to thcv244 serdes driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 *
9 */
10
11 // #define DEBUG
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <linux/slab.h>
22 #include <linux/version.h>
23 #include <linux/compat.h>
24 #include <linux/rk-camera-module.h>
25 #include <media/media-entity.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-ctrls.h>
28 #include <media/v4l2-subdev.h>
29 #include <media/v4l2-fwnode.h>
30 #include <media/v4l2-mediabus.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/of_graph.h>
33
34 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
35
36 #ifndef V4L2_CID_DIGITAL_GAIN
37 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
38 #endif
39
40 #define THCV244_LINK_FREQ_742MHZ 742500000UL
41 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
42 #define THCV244_PIXEL_RATE (THCV244_LINK_FREQ_742MHZ * 2LL * 4LL / 8LL)
43 #define THCV244_XVCLK_FREQ 24000000
44
45 #define THCV244_REG_CTRL_MODE 0x1600
46 #define THCV244_MODE_SW_STANDBY 0x0
47 #define THCV244_MODE_STREAMING 0x1a
48
49 #define THCV244_ADDR 0x0b
50 #define THCV241_ADDR 0x34
51
52 #define REG_NULL 0xFFFF
53
54 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
55 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
56
57 #define THCV244_REG_VALUE_08BIT 1
58 #define THCV244_REG_VALUE_16BIT 2
59 #define THCV244_REG_VALUE_24BIT 3
60
61 #define THCV244_NAME "thcv244"
62 #define THCV244_MEDIA_BUS_FMT MEDIA_BUS_FMT_UYVY8_2X8
63
64 static const char * const thcv244_supply_names[] = {
65 "avdd", /* Analog power */
66 "dovdd", /* Digital I/O power */
67 "dvdd", /* Digital core power */
68 };
69
70 #define THCV244_NUM_SUPPLIES ARRAY_SIZE(thcv244_supply_names)
71
72 struct regval {
73 u16 i2c_addr;
74 u16 addr;
75 u8 val;
76 u16 delay;
77 };
78
79 struct thcv244_mode {
80 u32 width;
81 u32 height;
82 struct v4l2_fract max_fps;
83 u32 hts_def;
84 u32 vts_def;
85 u32 exp_def;
86 u32 link_freq_idx;
87 u32 bpp;
88 const struct regval *reg_list;
89 };
90
91 struct thcv244 {
92 struct i2c_client *client;
93 struct clk *xvclk;
94 struct gpio_desc *power_gpio;
95 struct gpio_desc *reset_gpio;
96 struct gpio_desc *pwdn_gpio;
97 struct regulator_bulk_data supplies[THCV244_NUM_SUPPLIES];
98
99 struct pinctrl *pinctrl;
100 struct pinctrl_state *pins_default;
101 struct pinctrl_state *pins_sleep;
102
103 struct v4l2_subdev subdev;
104 struct media_pad pad;
105 struct v4l2_ctrl_handler ctrl_handler;
106 struct v4l2_ctrl *exposure;
107 struct v4l2_ctrl *anal_gain;
108 struct v4l2_ctrl *digi_gain;
109 struct v4l2_ctrl *hblank;
110 struct v4l2_ctrl *vblank;
111 struct v4l2_ctrl *pixel_rate;
112 struct v4l2_ctrl *link_freq;
113 struct v4l2_ctrl *test_pattern;
114 struct mutex mutex;
115 struct v4l2_fwnode_endpoint bus_cfg;
116 bool streaming;
117 bool power_on;
118 bool hot_plug;
119 u8 is_reset;
120 const struct thcv244_mode *cur_mode;
121 u32 module_index;
122 const char *module_facing;
123 const char *module_name;
124 const char *len_name;
125 };
126
127 #define to_thcv244(sd) container_of(sd, struct thcv244, subdev)
128
129 static const struct regval thcv244_global_init_table[] = {
130 {0x0b, 0x0050, 0x34, 0x00},
131 {0x0b, 0x0070, 0x34, 0x00},
132 {0x0b, 0x0090, 0x34, 0x00},
133 {0x0b, 0x00B0, 0x34, 0x00},
134 {0x0b, 0x0004, 0x03, 0x00},
135 {0x0b, 0x0010, 0xF0, 0x00},
136 {0x0b, 0x1704, 0x0F, 0x00},
137 {0x0b, 0x0102, 0xAA, 0x00},
138 {0x0b, 0x0103, 0xAA, 0x00},
139 {0x0b, 0x0104, 0x00, 0x00},
140 {0x0b, 0x0105, 0x00, 0x00},
141 {0x0b, 0x0100, 0x03, 0x00},
142 {0x0b, 0x010F, 0x25, 0x00},
143 {0x0b, 0x010A, 0x15, 0x00},
144 {0x0b, 0x0031, 0x02, 0x00},
145 {0x0b, 0x0032, 0x10, 0x00},
146 {0x0b, REG_NULL, 0x00, 0x00},
147 };
148
149 static const struct regval thcv244_1080p30_init_table[] = {
150 {0x0b, 0x0010, 0xFF, 0x00},
151 {0x0b, 0x1010, 0xA1, 0x00},
152 {0x0b, 0x1011, 0x06, 0x00},
153 {0x0b, 0x1014, 0xA1, 0x00},
154 {0x0b, 0x1015, 0x06, 0x00},
155 {0x0b, 0x1018, 0xA1, 0x00},
156 {0x0b, 0x1019, 0x06, 0x00},
157 {0x0b, 0x101C, 0xA1, 0x00},
158 {0x0b, 0x101D, 0x06, 0x00},
159 {0x0b, 0x1012, 0x00, 0x00},
160 {0x0b, 0x1013, 0x01, 0x00},
161 {0x0b, 0x1021, 0x28, 0x00},
162 {0x0b, 0x1022, 0x02, 0x00},
163 {0x0b, 0x1023, 0x11, 0x00},
164 {0x0b, 0x1024, 0x00, 0x00},
165 {0x0b, 0x1025, 0x00, 0x00},
166 {0x0b, 0x1026, 0x00, 0x00},
167 {0x0b, 0x1027, 0x07, 0x00},
168 {0x0b, 0x1028, 0x00, 0x00},
169 {0x0b, 0x1030, 0x18, 0x00},
170 {0x0b, 0x1100, 0x01, 0x00},
171 {0x0b, 0x1101, 0x01, 0x00},
172 {0x0b, 0x1102, 0x01, 0x00},
173 {0x0b, 0x1108, 0x01, 0x00},
174 {0x0b, 0x1200, 0x01, 0x00},
175 {0x0b, 0x1201, 0x01, 0x00},
176 {0x0b, 0x1202, 0x01, 0x00},
177 {0x0b, 0x1208, 0x01, 0x00},
178 {0x0b, 0x1300, 0x01, 0x00},
179 {0x0b, 0x1301, 0x01, 0x00},
180 {0x0b, 0x1302, 0x01, 0x00},
181 {0x0b, 0x1308, 0x01, 0x00},
182 {0x0b, 0x1400, 0x01, 0x00},
183 {0x0b, 0x1401, 0x01, 0x00},
184 {0x0b, 0x1402, 0x01, 0x00},
185 {0x0b, 0x1408, 0x01, 0x00},
186 {0x0b, 0x1500, 0x01, 0x00},
187 {0x0b, 0x1501, 0x0B, 0x00},
188 {0x0b, 0x1502, 0x64, 0x00},
189 {0x0b, 0x1504, 0x64, 0x00},
190 {0x0b, 0x1506, 0x64, 0x00},
191 {0x0b, 0x1508, 0x64, 0x00},
192 {0x0b, 0x150B, 0xE4, 0x00},
193 {0x0b, 0x150C, 0xE5, 0x00},
194 {0x0b, 0x150D, 0xE6, 0x00},
195 {0x0b, 0x150E, 0xE7, 0x00},
196 // {0x0b, 0x1600, 0x1A, 0x00},
197 {0x0b, 0x1601, 0x3B, 0x00},
198 {0x0b, 0x1605, 0x2B, 0x00},
199 {0x0b, 0x1606, 0x44, 0x00},
200 {0x0b, 0x1609, 0x0E, 0x00},
201 {0x0b, 0x160A, 0x17, 0x00},
202 {0x0b, 0x160B, 0x0C, 0x00},
203 {0x0b, 0x160D, 0x10, 0x00},
204 {0x0b, 0x160E, 0x06, 0x00},
205 {0x0b, 0x160F, 0x09, 0x00},
206 {0x0b, 0x1610, 0x05, 0x00},
207 {0x0b, 0x1611, 0x19, 0x00},
208 {0x0b, 0x1612, 0x0D, 0x00},
209 {0x0b, 0x1703, 0x01, 0x00},
210 {0x0b, 0x1704, 0xFF, 0x00},
211 {0x0b, 0x0032, 0x00, 0x00},
212 {0x0b, 0x1003, 0x00, 0x00},
213 {0x0b, 0x1004, 0x00, 0x00},
214 {0x0b, 0x001B, 0x18, 0x00},
215 {0x0b, 0x0032, 0x10, 0x00},
216 {0x0b, 0x1005, 0x22, 0x00},
217 {0x0b, 0x100C, 0x30, 0x00},
218 {0x0b, 0x100D, 0x34, 0x00},
219 {0x0b, REG_NULL, 0x00, 0x00},
220 };
221
222 static const struct regval thcv241_init_table[] = {
223 {0x34, 0xF3, 0x00, 0x00},
224 {0x34, 0xF2, 0x22, 0x00},
225 {0x34, 0xF0, 0x03, 0x00},
226 {0x34, 0xFF, 0x19, 0x00},
227 {0x34, 0xF6, 0x15, 0x00},
228 {0x34, 0xC9, 0x05, 0x00},
229 {0x34, 0xCA, 0x05, 0x00},
230 {0x34, 0xFE, 0x21, 0x00},
231 {0x34, 0x76, 0x10, 0x00},
232 {0x34, 0x0F, 0x01, 0x00},
233 {0x34, 0x11, 0x2C, 0x00},
234 {0x34, 0x12, 0x00, 0x00},
235 {0x34, 0x13, 0x00, 0x00},
236 {0x34, 0x14, 0x00, 0x00},
237 {0x34, 0x15, 0x44, 0x00},
238 {0x34, 0x16, 0x01, 0x00},
239 {0x34, 0x00, 0x00, 0x00},
240 {0x34, 0x01, 0x00, 0x00},
241 {0x34, 0x02, 0x00, 0x00},
242 {0x34, 0x55, 0x00, 0x00},
243 {0x34, 0x04, 0x00, 0x00},
244 {0x34, 0x2B, 0x05, 0x00},
245 {0x34, 0x2F, 0x00, 0x00},
246 {0x34, 0x2D, 0x13, 0x00},
247 {0x34, 0x2C, 0x01, 0x00},
248 {0x34, 0x05, 0x01, 0x00},
249 {0x34, 0x06, 0x01, 0x00},
250 {0x34, 0x27, 0x00, 0x00},
251 {0x34, 0x1D, 0x00, 0x00},
252 {0x34, 0x1E, 0x00, 0x00},
253 {0x34, 0x3D, 0x00, 0x00},
254 {0x34, 0x3E, 0x0c, 0x00},
255 {0x34, 0x3F, 0x02, 0x00},
256 {0x34, REG_NULL, 0x00, 0x00},
257 };
258
259 static const struct regval thcv244_reset_init_table[] = {
260 {0x0b, 0x1702, 0x01, 0x00},
261 {0x0b, 0x1600, 0x00, 0x00},
262 {0x0b, 0x1703, 0x00, 0x00},
263 {0x0b, 0x1704, 0x00, 0x00},
264 {0x0b, 0x1701, 0xFD, 0x00},
265 {0x0b, 0x0001, 0x01, 0x50},
266 {0x0b, 0x0050, 0x34, 0x00},
267 {0x0b, 0x0070, 0x34, 0x00},
268 {0x0b, 0x0090, 0x34, 0x00},
269 {0x0b, 0x00B0, 0x34, 0x00},
270 {0x0b, 0x0004, 0x03, 0x00},
271 {0x0b, 0x0010, 0xF0, 0x00},
272 {0x0b, 0x1704, 0x0F, 0x00},
273 {0x0b, 0x0102, 0xAA, 0x00},
274 {0x0b, 0x0103, 0xAA, 0x00},
275 {0x0b, 0x0104, 0x00, 0x00},
276 {0x0b, 0x0105, 0x00, 0x00},
277 {0x0b, 0x0100, 0x03, 0x00},
278 {0x0b, 0x010F, 0x25, 0x00},
279 {0x0b, 0x010A, 0x15, 0x00},
280 {0x0b, 0x0031, 0x02, 0x00},
281 {0x0b, 0x0032, 0x00, 0x00},
282 {0x0b, REG_NULL, 0x00, 0x00},
283 };
284
285 static const struct regval thcv241_reset_init_table0[] = {
286 {0x34, 0xFE, 0x21, 0x00},
287 {0x34, 0x06, 0x00, 0x00},
288 {0x34, 0x05, 0x00, 0x00},
289 {0x34, 0x21, 0x00, 0x00},
290 {0x34, 0x22, 0x00, 0x00},
291 {0x34, 0x23, 0x00, 0x00},
292 {0x34, 0xFF, 0xAA, 0x00},
293 {0x0b, REG_NULL, 0x00, 0x00},
294 };
295
296 static const struct regval thcv241_reset_init_table1[] = {
297 {0x34, 0xF3, 0x00, 0x00},
298 {0x34, 0xF2, 0x22, 0x00},
299 {0x34, 0xF0, 0x03, 0x00},
300 {0x34, 0xFF, 0x19, 0x00},
301 {0x34, 0xF6, 0x15, 0x00},
302 {0x34, 0xFE, 0x21, 0x00},
303 {0x34, 0x2D, 0x03, 0x00},
304 {0x34, 0x2C, 0x00, 0x00},
305 {0x34, 0x21, 0x01, 0x00},
306 {0x34, 0x22, 0x01, 0x00},
307 {0x34, 0x23, 0x01, 0x00},
308 {0x34, 0xFE, 0x00, 0x00},
309 {0x0b, REG_NULL, 0x00, 0x00},
310 };
311
312 static const struct thcv244_mode supported_modes[] = {
313 {
314 .width = 1920,
315 .height = 1080,
316 .max_fps = {
317 .numerator = 10000,
318 .denominator = 300000,
319 },
320 .link_freq_idx = 0,
321 },
322 };
323
324 static const s64 link_freq_items[] = {
325 THCV244_LINK_FREQ_742MHZ,
326 };
327
328 /* Write registers up to 4 at a time */
thine_write_reg(struct i2c_client * client,u16 client_addr,u16 reg,u32 reg_len,u32 val_len,u32 val)329 static int thine_write_reg(struct i2c_client *client, u16 client_addr, u16 reg,
330 u32 reg_len, u32 val_len, u32 val)
331 {
332 u32 buf_i, val_i;
333 u8 buf[6];
334 u8 *val_p;
335 __be32 val_be;
336
337 if (val_len > 4)
338 return -EINVAL;
339 if (reg_len == 2) {
340 buf[0] = reg >> 8;
341 buf[1] = reg & 0xff;
342 } else {
343 buf[0] = reg & 0xff;
344 }
345 val_be = cpu_to_be32(val);
346 val_p = (u8 *)&val_be;
347 if (reg_len == 2) {
348 buf_i = 2;
349 val_i = 4 - val_len;
350 } else {
351 buf_i = 1;
352 val_i = 4 - val_len;
353 }
354 while (val_i < 4)
355 buf[buf_i++] = val_p[val_i++];
356 client->addr = client_addr;
357
358 if (i2c_master_send(client, buf, val_len + reg_len) != val_len + reg_len) {
359 dev_err(&client->dev,
360 "%s, i2c_master_send err, client->addr = 0x%x, reg = 0x%x, val = 0x%x\n",
361 __func__, client->addr, reg, val);
362 return -EIO;
363 }
364
365 dev_dbg(&client->dev,
366 "%s, i2c_master_send ok, client->addr = 0x%x, reg = 0x%x, val = 0x%x\n",
367 __func__, client->addr, reg, val);
368
369 return 0;
370 }
371
thcv244_write_array(struct i2c_client * client,const struct regval * regs)372 static int thcv244_write_array(struct i2c_client *client,
373 const struct regval *regs)
374 {
375 u32 i;
376 int ret = 0;
377
378 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
379 ret = thine_write_reg(client, THCV244_ADDR, regs[i].addr, 2,
380 THCV244_REG_VALUE_08BIT,
381 regs[i].val);
382 msleep(regs[i].delay);
383 }
384
385 return ret;
386 }
387
thcv241_write_array(struct i2c_client * client,const struct regval * regs)388 static int thcv241_write_array(struct i2c_client *client,
389 const struct regval *regs)
390 {
391 u32 i;
392 int ret = 0;
393
394 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
395 ret = thine_write_reg(client, THCV241_ADDR, regs[i].addr, 1,
396 THCV244_REG_VALUE_08BIT,
397 regs[i].val);
398 msleep(regs[i].delay);
399 }
400
401 return ret;
402 }
403
404 /* Read registers up to 4 at a time */
thcv244_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)405 static int __maybe_unused thcv244_read_reg(struct i2c_client *client, u16 reg,
406 unsigned int len, u32 *val)
407 {
408 struct i2c_msg msgs[2];
409 u8 *data_be_p;
410 __be32 data_be = 0;
411 __be16 reg_addr_be = cpu_to_be16(reg);
412 int ret;
413
414 if (len > 4 || !len)
415 return -EINVAL;
416
417 data_be_p = (u8 *)&data_be;
418 /* Write register address */
419 msgs[0].addr = client->addr;
420 msgs[0].flags = 0;
421 msgs[0].len = 2;
422 msgs[0].buf = (u8 *)®_addr_be;
423
424 /* Read data from register */
425 msgs[1].addr = client->addr;
426 msgs[1].flags = I2C_M_RD;
427 msgs[1].len = len;
428 msgs[1].buf = &data_be_p[4 - len];
429
430 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
431 if (ret != ARRAY_SIZE(msgs))
432 return -EIO;
433
434 *val = be32_to_cpu(data_be);
435
436 return 0;
437 }
438
thcv244_get_reso_dist(const struct thcv244_mode * mode,struct v4l2_mbus_framefmt * framefmt)439 static int thcv244_get_reso_dist(const struct thcv244_mode *mode,
440 struct v4l2_mbus_framefmt *framefmt)
441 {
442 return abs(mode->width - framefmt->width) +
443 abs(mode->height - framefmt->height);
444 }
445
446 static const struct thcv244_mode *
thcv244_find_best_fit(struct v4l2_subdev_format * fmt)447 thcv244_find_best_fit(struct v4l2_subdev_format *fmt)
448 {
449 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
450 int dist;
451 int cur_best_fit = 0;
452 int cur_best_fit_dist = -1;
453 unsigned int i;
454
455 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
456 dist = thcv244_get_reso_dist(&supported_modes[i], framefmt);
457 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
458 cur_best_fit_dist = dist;
459 cur_best_fit = i;
460 }
461 }
462
463 return &supported_modes[cur_best_fit];
464 }
465
thcv244_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)466 static int thcv244_set_fmt(struct v4l2_subdev *sd,
467 struct v4l2_subdev_pad_config *cfg,
468 struct v4l2_subdev_format *fmt)
469 {
470 struct thcv244 *thcv244 = to_thcv244(sd);
471 const struct thcv244_mode *mode;
472
473 mutex_lock(&thcv244->mutex);
474
475 mode = thcv244_find_best_fit(fmt);
476 fmt->format.code = THCV244_MEDIA_BUS_FMT;
477 fmt->format.width = mode->width;
478 fmt->format.height = mode->height;
479 fmt->format.field = V4L2_FIELD_NONE;
480 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
481 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
482 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
483 #else
484 mutex_unlock(&thcv244->mutex);
485 return -ENOTTY;
486 #endif
487 } else {
488 if (thcv244->streaming) {
489 mutex_unlock(&thcv244->mutex);
490 return -EBUSY;
491 }
492 }
493
494 mutex_unlock(&thcv244->mutex);
495
496 return 0;
497 }
498
thcv244_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)499 static int thcv244_get_fmt(struct v4l2_subdev *sd,
500 struct v4l2_subdev_pad_config *cfg,
501 struct v4l2_subdev_format *fmt)
502 {
503 struct thcv244 *thcv244 = to_thcv244(sd);
504 const struct thcv244_mode *mode = thcv244->cur_mode;
505
506 mutex_lock(&thcv244->mutex);
507 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
508 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
509 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
510 #else
511 mutex_unlock(&thcv244->mutex);
512 return -ENOTTY;
513 #endif
514 } else {
515 fmt->format.width = mode->width;
516 fmt->format.height = mode->height;
517 fmt->format.code = THCV244_MEDIA_BUS_FMT;
518 fmt->format.field = V4L2_FIELD_NONE;
519 }
520 mutex_unlock(&thcv244->mutex);
521
522 return 0;
523 }
524
thcv244_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)525 static int thcv244_enum_mbus_code(struct v4l2_subdev *sd,
526 struct v4l2_subdev_pad_config *cfg,
527 struct v4l2_subdev_mbus_code_enum *code)
528 {
529 if (code->index != 0)
530 return -EINVAL;
531 code->code = THCV244_MEDIA_BUS_FMT;
532
533 return 0;
534 }
535
thcv244_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)536 static int thcv244_enum_frame_sizes(struct v4l2_subdev *sd,
537 struct v4l2_subdev_pad_config *cfg,
538 struct v4l2_subdev_frame_size_enum *fse)
539 {
540 if (fse->index >= ARRAY_SIZE(supported_modes))
541 return -EINVAL;
542
543 if (fse->code != THCV244_MEDIA_BUS_FMT)
544 return -EINVAL;
545
546 fse->min_width = supported_modes[fse->index].width;
547 fse->max_width = supported_modes[fse->index].width;
548 fse->max_height = supported_modes[fse->index].height;
549 fse->min_height = supported_modes[fse->index].height;
550
551 return 0;
552 }
553
thcv244_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)554 static int thcv244_g_frame_interval(struct v4l2_subdev *sd,
555 struct v4l2_subdev_frame_interval *fi)
556 {
557 struct thcv244 *thcv244 = to_thcv244(sd);
558 const struct thcv244_mode *mode = thcv244->cur_mode;
559
560 mutex_lock(&thcv244->mutex);
561 fi->interval = mode->max_fps;
562 mutex_unlock(&thcv244->mutex);
563
564 return 0;
565 }
566
thcv244_get_module_inf(struct thcv244 * thcv244,struct rkmodule_inf * inf)567 static void thcv244_get_module_inf(struct thcv244 *thcv244,
568 struct rkmodule_inf *inf)
569 {
570 memset(inf, 0, sizeof(*inf));
571 strscpy(inf->base.sensor, THCV244_NAME, sizeof(inf->base.sensor));
572 strscpy(inf->base.module, thcv244->module_name,
573 sizeof(inf->base.module));
574 strscpy(inf->base.lens, thcv244->len_name, sizeof(inf->base.lens));
575 }
576
thcv244_get_vicap_rst_inf(struct thcv244 * thcv244,struct rkmodule_vicap_reset_info * rst_info)577 static void thcv244_get_vicap_rst_inf(struct thcv244 *thcv244,
578 struct rkmodule_vicap_reset_info *rst_info)
579 {
580 struct i2c_client *client = thcv244->client;
581
582 rst_info->is_reset = thcv244->hot_plug;
583 thcv244->hot_plug = false;
584 rst_info->src = RKCIF_RESET_SRC_ERR_HOTPLUG;
585 if (rst_info->is_reset)
586 dev_info(&client->dev, "%s: rst_info->is_reset:%d.\n",
587 __func__, rst_info->is_reset);
588 }
589
thcv244_set_vicap_rst_inf(struct thcv244 * thcv244,struct rkmodule_vicap_reset_info rst_info)590 static void thcv244_set_vicap_rst_inf(struct thcv244 *thcv244,
591 struct rkmodule_vicap_reset_info rst_info)
592 {
593 thcv244->is_reset = rst_info.is_reset;
594 }
595
thcv244_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)596 static long thcv244_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
597 {
598 struct thcv244 *thcv244 = to_thcv244(sd);
599 long ret = 0;
600 u32 stream = 0;
601
602 switch (cmd) {
603 case RKMODULE_GET_MODULE_INFO:
604 thcv244_get_module_inf(thcv244, (struct rkmodule_inf *)arg);
605 break;
606 case RKMODULE_SET_QUICK_STREAM:
607
608 stream = *((u32 *)arg);
609
610 if (stream)
611 ret = thine_write_reg(thcv244->client, THCV244_ADDR,
612 THCV244_REG_CTRL_MODE, 2,
613 THCV244_REG_VALUE_08BIT,
614 THCV244_MODE_STREAMING);
615 else
616 ret = thine_write_reg(thcv244->client, THCV244_ADDR,
617 THCV244_REG_CTRL_MODE, 2,
618 THCV244_REG_VALUE_08BIT,
619 THCV244_MODE_SW_STANDBY);
620 break;
621 case RKMODULE_GET_VICAP_RST_INFO:
622 thcv244_get_vicap_rst_inf(thcv244,
623 (struct rkmodule_vicap_reset_info *)arg);
624 break;
625 case RKMODULE_SET_VICAP_RST_INFO:
626 thcv244_set_vicap_rst_inf(thcv244,
627 *(struct rkmodule_vicap_reset_info *)arg);
628 break;
629 default:
630 ret = -ENOIOCTLCMD;
631 break;
632 }
633
634 return ret;
635 }
636
637 #ifdef CONFIG_COMPAT
thcv244_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)638 static long thcv244_compat_ioctl32(struct v4l2_subdev *sd,
639 unsigned int cmd, unsigned long arg)
640 {
641 void __user *up = compat_ptr(arg);
642 struct rkmodule_inf *inf;
643 struct rkmodule_awb_cfg *cfg;
644 struct rkmodule_vicap_reset_info *vicap_rst_inf;
645 long ret = 0;
646 u32 stream = 0;
647
648 switch (cmd) {
649 case RKMODULE_GET_MODULE_INFO:
650 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
651 if (!inf) {
652 ret = -ENOMEM;
653 return ret;
654 }
655
656 ret = thcv244_ioctl(sd, cmd, inf);
657 if (!ret) {
658 ret = copy_to_user(up, inf, sizeof(*inf));
659 if (ret)
660 ret = -EFAULT;
661 }
662 kfree(inf);
663 break;
664 case RKMODULE_AWB_CFG:
665 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
666 if (!cfg) {
667 ret = -ENOMEM;
668 return ret;
669 }
670
671 ret = copy_from_user(cfg, up, sizeof(*cfg));
672 if (!ret)
673 ret = thcv244_ioctl(sd, cmd, cfg);
674 else
675 ret = -EFAULT;
676 kfree(cfg);
677 break;
678 case RKMODULE_GET_VICAP_RST_INFO:
679 vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
680 if (!vicap_rst_inf) {
681 ret = -ENOMEM;
682 return ret;
683 }
684
685 ret = thcv244_ioctl(sd, cmd, vicap_rst_inf);
686 if (!ret) {
687 ret = copy_to_user(up, vicap_rst_inf, sizeof(*vicap_rst_inf));
688 if (ret)
689 ret = -EFAULT;
690 }
691 kfree(vicap_rst_inf);
692 break;
693 case RKMODULE_SET_VICAP_RST_INFO:
694 vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
695 if (!vicap_rst_inf) {
696 ret = -ENOMEM;
697 return ret;
698 }
699
700 ret = copy_from_user(vicap_rst_inf, up, sizeof(*vicap_rst_inf));
701 if (!ret)
702 ret = thcv244_ioctl(sd, cmd, vicap_rst_inf);
703 else
704 ret = -EFAULT;
705 kfree(vicap_rst_inf);
706 break;
707 case RKMODULE_SET_QUICK_STREAM:
708 ret = copy_from_user(&stream, up, sizeof(u32));
709 if (!ret)
710 ret = thcv244_ioctl(sd, cmd, &stream);
711 else
712 ret = -EFAULT;
713 break;
714 default:
715 ret = -ENOIOCTLCMD;
716 break;
717 }
718
719 return ret;
720 }
721 #endif
722
thcv244_thcv241_init(struct thcv244 * thcv244)723 static int thcv244_thcv241_init(struct thcv244 *thcv244)
724 {
725 struct device *dev = &thcv244->client->dev;
726 int ret;
727
728 ret = thcv244_write_array(thcv244->client, thcv244_global_init_table);
729 ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x00fe,
730 2, THCV244_REG_VALUE_08BIT, 0x11);
731 ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,
732 2, THCV244_REG_VALUE_08BIT, 0x00);
733 ret |= thcv241_write_array(thcv244->client, thcv241_init_table);
734 ret |= thcv244_write_array(thcv244->client, thcv244_1080p30_init_table);
735 ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,
736 2, THCV244_REG_VALUE_08BIT, 0x00);
737 ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0xfe,
738 1, THCV244_REG_VALUE_08BIT, 0x21);
739 ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x3e,
740 1, THCV244_REG_VALUE_08BIT, 0x0c);
741 usleep_range(1000, 2000);
742 ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x3e,
743 1, THCV244_REG_VALUE_08BIT, 0x3c);
744 usleep_range(1000, 2000);
745 ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x1600,
746 2, THCV244_REG_VALUE_08BIT, 0x00);
747 if (ret)
748 dev_err(dev, "fail to init thcv244 and thcv 241!\n");
749
750 return ret;
751 }
752
thcv244_thcv241_reset_initial(struct thcv244 * thcv244)753 static int thcv244_thcv241_reset_initial(struct thcv244 *thcv244)
754 {
755 struct device *dev = &thcv244->client->dev;
756 int ret;
757
758 ret = thcv244_write_array(thcv244->client, thcv244_reset_init_table);
759
760 ret |= thcv241_write_array(thcv244->client, thcv241_reset_init_table0);
761 ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,
762 2, THCV244_REG_VALUE_08BIT, 0x10);
763 ret |= thine_write_reg(thcv244->client, THCV241_ADDR, 0x00fe,
764 1, THCV244_REG_VALUE_08BIT, 0x11);
765 ret |= thine_write_reg(thcv244->client, THCV244_ADDR, 0x0032,
766 2, THCV244_REG_VALUE_08BIT, 0x00);
767 ret |= thcv241_write_array(thcv244->client, thcv241_reset_init_table1);
768
769 if (ret)
770 dev_err(dev, "fail to reset thcv244 and thcv 241!\n");
771
772 return ret;
773 }
774
__thcv244_start_stream(struct thcv244 * thcv244)775 static int __thcv244_start_stream(struct thcv244 *thcv244)
776 {
777 int ret;
778
779 ret = thcv244_thcv241_reset_initial(thcv244);
780
781 ret |= thcv244_thcv241_init(thcv244);
782 if (ret)
783 return ret;
784
785 /* In case these controls are set before streaming */
786 mutex_unlock(&thcv244->mutex);
787 ret = v4l2_ctrl_handler_setup(&thcv244->ctrl_handler);
788 mutex_lock(&thcv244->mutex);
789 if (ret)
790 return ret;
791
792 return thine_write_reg(thcv244->client, THCV244_ADDR,
793 THCV244_REG_CTRL_MODE, 2,
794 THCV244_REG_VALUE_08BIT,
795 THCV244_MODE_STREAMING);
796 }
797
__thcv244_stop_stream(struct thcv244 * thcv244)798 static int __thcv244_stop_stream(struct thcv244 *thcv244)
799 {
800 return thine_write_reg(thcv244->client, THCV244_ADDR,
801 THCV244_REG_CTRL_MODE, 2,
802 THCV244_REG_VALUE_08BIT,
803 THCV244_MODE_SW_STANDBY);
804 }
805
thcv244_s_stream(struct v4l2_subdev * sd,int on)806 static int thcv244_s_stream(struct v4l2_subdev *sd, int on)
807 {
808 struct thcv244 *thcv244 = to_thcv244(sd);
809 struct i2c_client *client = thcv244->client;
810 int ret = 0;
811
812 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
813 thcv244->cur_mode->width,
814 thcv244->cur_mode->height,
815 DIV_ROUND_CLOSEST(thcv244->cur_mode->max_fps.denominator,
816 thcv244->cur_mode->max_fps.numerator));
817
818 mutex_lock(&thcv244->mutex);
819 on = !!on;
820 if (on == thcv244->streaming)
821 goto unlock_and_return;
822
823 if (on) {
824 ret = pm_runtime_get_sync(&client->dev);
825 if (ret < 0) {
826 pm_runtime_put_noidle(&client->dev);
827 goto unlock_and_return;
828 }
829
830 ret = __thcv244_start_stream(thcv244);
831 if (ret) {
832 v4l2_err(sd, "start stream failed while write regs\n");
833 pm_runtime_put(&client->dev);
834 goto unlock_and_return;
835 }
836 } else {
837 __thcv244_stop_stream(thcv244);
838 pm_runtime_put(&client->dev);
839 }
840
841 thcv244->streaming = on;
842
843 unlock_and_return:
844 mutex_unlock(&thcv244->mutex);
845
846 return ret;
847 }
848
thcv244_s_power(struct v4l2_subdev * sd,int on)849 static int thcv244_s_power(struct v4l2_subdev *sd, int on)
850 {
851 struct thcv244 *thcv244 = to_thcv244(sd);
852 struct i2c_client *client = thcv244->client;
853 int ret = 0;
854
855 mutex_lock(&thcv244->mutex);
856
857 /* If the power state is not modified - no work to do. */
858 if (thcv244->power_on == !!on)
859 goto unlock_and_return;
860
861 if (on) {
862 ret = pm_runtime_get_sync(&client->dev);
863 if (ret < 0) {
864 pm_runtime_put_noidle(&client->dev);
865 goto unlock_and_return;
866 }
867
868 thcv244->power_on = true;
869 } else {
870 pm_runtime_put(&client->dev);
871 thcv244->power_on = false;
872 }
873
874 unlock_and_return:
875 mutex_unlock(&thcv244->mutex);
876
877 return ret;
878 }
879
880 /* Calculate the delay in us by clock rate and clock cycles */
thcv244_cal_delay(u32 cycles)881 static inline u32 thcv244_cal_delay(u32 cycles)
882 {
883 return DIV_ROUND_UP(cycles, THCV244_XVCLK_FREQ / 1000 / 1000);
884 }
885
__thcv244_power_on(struct thcv244 * thcv244)886 static int __thcv244_power_on(struct thcv244 *thcv244)
887 {
888 int ret;
889 u32 delay_us;
890 struct device *dev = &thcv244->client->dev;
891
892 if (!IS_ERR(thcv244->power_gpio))
893 gpiod_set_value_cansleep(thcv244->power_gpio, 1);
894
895 usleep_range(1000, 2000);
896
897 if (!IS_ERR_OR_NULL(thcv244->pins_default)) {
898 ret = pinctrl_select_state(thcv244->pinctrl,
899 thcv244->pins_default);
900 if (ret < 0)
901 dev_err(dev, "could not set pins\n");
902 }
903
904 if (!IS_ERR(thcv244->reset_gpio))
905 gpiod_set_value_cansleep(thcv244->reset_gpio, 0);
906
907 ret = regulator_bulk_enable(THCV244_NUM_SUPPLIES, thcv244->supplies);
908 if (ret < 0) {
909 dev_err(dev, "Failed to enable regulators\n");
910 goto disable_clk;
911 }
912
913 if (!IS_ERR(thcv244->reset_gpio))
914 gpiod_set_value_cansleep(thcv244->reset_gpio, 1);
915
916 usleep_range(500, 1000);
917 if (!IS_ERR(thcv244->pwdn_gpio))
918 gpiod_set_value_cansleep(thcv244->pwdn_gpio, 1);
919
920 /* 8192 cycles prior to first SCCB transaction */
921 delay_us = thcv244_cal_delay(8192);
922 usleep_range(delay_us, delay_us * 2);
923
924 return 0;
925
926 disable_clk:
927 clk_disable_unprepare(thcv244->xvclk);
928
929 return ret;
930 }
931
__thcv244_power_off(struct thcv244 * thcv244)932 static void __thcv244_power_off(struct thcv244 *thcv244)
933 {
934 int ret;
935 struct device *dev = &thcv244->client->dev;
936
937 if (!IS_ERR(thcv244->pwdn_gpio))
938 gpiod_set_value_cansleep(thcv244->pwdn_gpio, 0);
939 clk_disable_unprepare(thcv244->xvclk);
940 if (!IS_ERR(thcv244->reset_gpio))
941 gpiod_set_value_cansleep(thcv244->reset_gpio, 0);
942
943 if (!IS_ERR_OR_NULL(thcv244->pins_sleep)) {
944 ret = pinctrl_select_state(thcv244->pinctrl,
945 thcv244->pins_sleep);
946 if (ret < 0)
947 dev_dbg(dev, "could not set pins\n");
948 }
949 if (!IS_ERR(thcv244->power_gpio))
950 gpiod_set_value_cansleep(thcv244->power_gpio, 0);
951
952 regulator_bulk_disable(THCV244_NUM_SUPPLIES, thcv244->supplies);
953 }
954
thcv244_runtime_resume(struct device * dev)955 static int __maybe_unused thcv244_runtime_resume(struct device *dev)
956 {
957 struct i2c_client *client = to_i2c_client(dev);
958 struct v4l2_subdev *sd = i2c_get_clientdata(client);
959 struct thcv244 *thcv244 = to_thcv244(sd);
960
961 return __thcv244_power_on(thcv244);
962 }
963
thcv244_runtime_suspend(struct device * dev)964 static int __maybe_unused thcv244_runtime_suspend(struct device *dev)
965 {
966 struct i2c_client *client = to_i2c_client(dev);
967 struct v4l2_subdev *sd = i2c_get_clientdata(client);
968 struct thcv244 *thcv244 = to_thcv244(sd);
969
970 __thcv244_power_off(thcv244);
971
972 return 0;
973 }
974
975 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
thcv244_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)976 static int thcv244_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
977 {
978 struct thcv244 *thcv244 = to_thcv244(sd);
979 struct v4l2_mbus_framefmt *try_fmt =
980 v4l2_subdev_get_try_format(sd, fh->pad, 0);
981 const struct thcv244_mode *def_mode = &supported_modes[0];
982
983 mutex_lock(&thcv244->mutex);
984 /* Initialize try_fmt */
985 try_fmt->width = def_mode->width;
986 try_fmt->height = def_mode->height;
987 try_fmt->code = THCV244_MEDIA_BUS_FMT;
988 try_fmt->field = V4L2_FIELD_NONE;
989
990 mutex_unlock(&thcv244->mutex);
991 /* No crop or compose */
992
993 return 0;
994 }
995 #endif
996
thcv244_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)997 static int thcv244_enum_frame_interval(struct v4l2_subdev *sd,
998 struct v4l2_subdev_pad_config *cfg,
999 struct v4l2_subdev_frame_interval_enum *fie)
1000 {
1001 if (fie->index >= ARRAY_SIZE(supported_modes))
1002 return -EINVAL;
1003
1004 fie->code = THCV244_MEDIA_BUS_FMT;
1005
1006 fie->width = supported_modes[fie->index].width;
1007 fie->height = supported_modes[fie->index].height;
1008 fie->interval = supported_modes[fie->index].max_fps;
1009
1010 return 0;
1011 }
1012
thcv244_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1013 static int thcv244_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1014 struct v4l2_mbus_config *config)
1015 {
1016 struct thcv244 *thcv244 = to_thcv244(sd);
1017 u32 lane_num = thcv244->bus_cfg.bus.mipi_csi2.num_data_lanes;
1018
1019 config->type = V4L2_MBUS_CSI2_DPHY;
1020 config->flags = 1 << (lane_num - 1) |
1021 V4L2_MBUS_CSI2_CHANNELS |
1022 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1023
1024 return 0;
1025 }
1026
thcv244_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1027 static int thcv244_get_selection(struct v4l2_subdev *sd,
1028 struct v4l2_subdev_pad_config *cfg,
1029 struct v4l2_subdev_selection *sel)
1030 {
1031 struct thcv244 *thcv244 = to_thcv244(sd);
1032
1033 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1034 sel->r.left = 0;
1035 sel->r.width = thcv244->cur_mode->width;
1036 sel->r.top = 0;
1037 sel->r.height = thcv244->cur_mode->height;
1038 return 0;
1039 }
1040
1041 return -EINVAL;
1042 }
1043
1044 static const struct dev_pm_ops thcv244_pm_ops = {
1045 SET_RUNTIME_PM_OPS(thcv244_runtime_suspend,
1046 thcv244_runtime_resume, NULL)
1047 };
1048
1049 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1050 static const struct v4l2_subdev_internal_ops thcv244_internal_ops = {
1051 .open = thcv244_open,
1052 };
1053 #endif
1054
1055 static const struct v4l2_subdev_core_ops thcv244_core_ops = {
1056 .s_power = thcv244_s_power,
1057 .ioctl = thcv244_ioctl,
1058 #ifdef CONFIG_COMPAT
1059 .compat_ioctl32 = thcv244_compat_ioctl32,
1060 #endif
1061 };
1062
1063 static const struct v4l2_subdev_video_ops thcv244_video_ops = {
1064 .s_stream = thcv244_s_stream,
1065 .g_frame_interval = thcv244_g_frame_interval,
1066 };
1067
1068 static const struct v4l2_subdev_pad_ops thcv244_pad_ops = {
1069 .enum_mbus_code = thcv244_enum_mbus_code,
1070 .enum_frame_size = thcv244_enum_frame_sizes,
1071 .enum_frame_interval = thcv244_enum_frame_interval,
1072 .get_fmt = thcv244_get_fmt,
1073 .set_fmt = thcv244_set_fmt,
1074 .get_selection = thcv244_get_selection,
1075 .get_mbus_config = thcv244_g_mbus_config,
1076 };
1077
1078 static const struct v4l2_subdev_ops thcv244_subdev_ops = {
1079 .core = &thcv244_core_ops,
1080 .video = &thcv244_video_ops,
1081 .pad = &thcv244_pad_ops,
1082 };
1083
thcv244_initialize_controls(struct thcv244 * thcv244)1084 static int thcv244_initialize_controls(struct thcv244 *thcv244)
1085 {
1086 const struct thcv244_mode *mode;
1087 struct v4l2_ctrl_handler *handler;
1088 int ret;
1089
1090 handler = &thcv244->ctrl_handler;
1091 mode = thcv244->cur_mode;
1092 ret = v4l2_ctrl_handler_init(handler, 2);
1093 if (ret)
1094 return ret;
1095 handler->lock = &thcv244->mutex;
1096
1097 thcv244->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1098 V4L2_CID_LINK_FREQ,
1099 1, 0, link_freq_items);
1100
1101 thcv244->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1102 V4L2_CID_PIXEL_RATE,
1103 0, THCV244_PIXEL_RATE,
1104 1, THCV244_PIXEL_RATE);
1105
1106 __v4l2_ctrl_s_ctrl(thcv244->link_freq,
1107 mode->link_freq_idx);
1108
1109 if (handler->error) {
1110 ret = handler->error;
1111 dev_err(&thcv244->client->dev,
1112 "Failed to init controls(%d)\n", ret);
1113 goto err_free_handler;
1114 }
1115
1116 thcv244->subdev.ctrl_handler = handler;
1117
1118 return 0;
1119
1120 err_free_handler:
1121 v4l2_ctrl_handler_free(handler);
1122
1123 return ret;
1124 }
1125
thcv244_check_sensor_id(struct thcv244 * thcv244,struct i2c_client * client)1126 static int thcv244_check_sensor_id(struct thcv244 *thcv244,
1127 struct i2c_client *client)
1128 {
1129 return 0;
1130 }
1131
thcv244_configure_regulators(struct thcv244 * thcv244)1132 static int thcv244_configure_regulators(struct thcv244 *thcv244)
1133 {
1134 unsigned int i;
1135
1136 for (i = 0; i < THCV244_NUM_SUPPLIES; i++)
1137 thcv244->supplies[i].supply = thcv244_supply_names[i];
1138
1139 return devm_regulator_bulk_get(&thcv244->client->dev,
1140 THCV244_NUM_SUPPLIES,
1141 thcv244->supplies);
1142 }
1143
thcv244_probe(struct i2c_client * client,const struct i2c_device_id * id)1144 static int thcv244_probe(struct i2c_client *client,
1145 const struct i2c_device_id *id)
1146 {
1147 struct device *dev = &client->dev;
1148 struct device_node *node = dev->of_node;
1149 struct thcv244 *thcv244;
1150 struct v4l2_subdev *sd;
1151 struct device_node *endpoint;
1152 char facing[2];
1153 int ret;
1154
1155 dev_info(dev, "driver version: %02x.%02x.%02x",
1156 DRIVER_VERSION >> 16,
1157 (DRIVER_VERSION & 0xff00) >> 8,
1158 DRIVER_VERSION & 0x00ff);
1159
1160 thcv244 = devm_kzalloc(dev, sizeof(*thcv244), GFP_KERNEL);
1161 if (!thcv244)
1162 return -ENOMEM;
1163
1164 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1165 &thcv244->module_index);
1166 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1167 &thcv244->module_facing);
1168 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1169 &thcv244->module_name);
1170 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1171 &thcv244->len_name);
1172 if (ret) {
1173 dev_err(dev, "could not get module information!\n");
1174 return -EINVAL;
1175 }
1176
1177 thcv244->client = client;
1178 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1179 if (!endpoint) {
1180 dev_err(dev, "Failed to get endpoint\n");
1181 return -EINVAL;
1182 }
1183 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1184 &thcv244->bus_cfg);
1185 if (ret) {
1186 dev_err(dev, "Failed to get bus cfg\n");
1187 return ret;
1188 }
1189
1190 thcv244->cur_mode = &supported_modes[0];
1191
1192 thcv244->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1193 if (IS_ERR(thcv244->power_gpio))
1194 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1195
1196 thcv244->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1197 if (IS_ERR(thcv244->reset_gpio))
1198 dev_warn(dev, "Failed to get reset-gpios\n");
1199
1200 thcv244->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1201 if (IS_ERR(thcv244->pwdn_gpio))
1202 dev_warn(dev, "Failed to get pwdn-gpios\n");
1203
1204 ret = thcv244_configure_regulators(thcv244);
1205 if (ret) {
1206 dev_err(dev, "Failed to get power regulators\n");
1207 return ret;
1208 }
1209
1210 thcv244->pinctrl = devm_pinctrl_get(dev);
1211 if (!IS_ERR(thcv244->pinctrl)) {
1212 thcv244->pins_default =
1213 pinctrl_lookup_state(thcv244->pinctrl,
1214 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1215 if (IS_ERR(thcv244->pins_default))
1216 dev_err(dev, "could not get default pinstate\n");
1217
1218 thcv244->pins_sleep =
1219 pinctrl_lookup_state(thcv244->pinctrl,
1220 OF_CAMERA_PINCTRL_STATE_SLEEP);
1221 if (IS_ERR(thcv244->pins_sleep))
1222 dev_err(dev, "could not get sleep pinstate\n");
1223 }
1224
1225 mutex_init(&thcv244->mutex);
1226
1227 sd = &thcv244->subdev;
1228 v4l2_i2c_subdev_init(sd, client, &thcv244_subdev_ops);
1229 ret = thcv244_initialize_controls(thcv244);
1230 if (ret)
1231 goto err_destroy_mutex;
1232
1233 ret = __thcv244_power_on(thcv244);
1234 if (ret)
1235 goto err_free_handler;
1236
1237 ret = thcv244_check_sensor_id(thcv244, client);
1238 if (ret)
1239 goto err_power_off;
1240
1241 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1242 sd->internal_ops = &thcv244_internal_ops;
1243 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1244 #endif
1245 #if defined(CONFIG_MEDIA_CONTROLLER)
1246 thcv244->pad.flags = MEDIA_PAD_FL_SOURCE;
1247 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1248 ret = media_entity_pads_init(&sd->entity, 1, &thcv244->pad);
1249 if (ret < 0)
1250 goto err_power_off;
1251 #endif
1252
1253 memset(facing, 0, sizeof(facing));
1254 if (strcmp(thcv244->module_facing, "back") == 0)
1255 facing[0] = 'b';
1256 else
1257 facing[0] = 'f';
1258
1259 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1260 thcv244->module_index, facing,
1261 THCV244_NAME, dev_name(sd->dev));
1262 ret = v4l2_async_register_subdev_sensor_common(sd);
1263 if (ret) {
1264 dev_err(dev, "v4l2 async register subdev failed\n");
1265 goto err_clean_entity;
1266 }
1267
1268 pm_runtime_set_active(dev);
1269 pm_runtime_enable(dev);
1270 pm_runtime_idle(dev);
1271
1272 return 0;
1273
1274 err_clean_entity:
1275 #if defined(CONFIG_MEDIA_CONTROLLER)
1276 media_entity_cleanup(&sd->entity);
1277 #endif
1278 err_power_off:
1279 __thcv244_power_off(thcv244);
1280 err_free_handler:
1281 v4l2_ctrl_handler_free(&thcv244->ctrl_handler);
1282 err_destroy_mutex:
1283 mutex_destroy(&thcv244->mutex);
1284
1285 return ret;
1286 }
1287
thcv244_remove(struct i2c_client * client)1288 static int thcv244_remove(struct i2c_client *client)
1289 {
1290 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1291 struct thcv244 *thcv244 = to_thcv244(sd);
1292
1293 v4l2_async_unregister_subdev(sd);
1294 #if defined(CONFIG_MEDIA_CONTROLLER)
1295 media_entity_cleanup(&sd->entity);
1296 #endif
1297 v4l2_ctrl_handler_free(&thcv244->ctrl_handler);
1298 mutex_destroy(&thcv244->mutex);
1299
1300 pm_runtime_disable(&client->dev);
1301 if (!pm_runtime_status_suspended(&client->dev))
1302 __thcv244_power_off(thcv244);
1303 pm_runtime_set_suspended(&client->dev);
1304
1305 return 0;
1306 }
1307
1308 #if IS_ENABLED(CONFIG_OF)
1309 static const struct of_device_id thcv244_of_match[] = {
1310 { .compatible = "thine,thcv244" },
1311 {},
1312 };
1313 MODULE_DEVICE_TABLE(of, thcv244_of_match);
1314 #endif
1315
1316 static const struct i2c_device_id thcv244_match_id[] = {
1317 { "thine,thcv244", 0 },
1318 {},
1319 };
1320
1321 static struct i2c_driver thcv244_i2c_driver = {
1322 .driver = {
1323 .name = THCV244_NAME,
1324 .pm = &thcv244_pm_ops,
1325 .of_match_table = of_match_ptr(thcv244_of_match),
1326 },
1327 .probe = &thcv244_probe,
1328 .remove = &thcv244_remove,
1329 .id_table = thcv244_match_id,
1330 };
1331
sensor_mod_init(void)1332 static int __init sensor_mod_init(void)
1333 {
1334 return i2c_add_driver(&thcv244_i2c_driver);
1335 }
1336
sensor_mod_exit(void)1337 static void __exit sensor_mod_exit(void)
1338 {
1339 i2c_del_driver(&thcv244_i2c_driver);
1340 }
1341
1342 device_initcall_sync(sensor_mod_init);
1343 module_exit(sensor_mod_exit);
1344
1345 MODULE_DESCRIPTION("Thine thcv244 sensor driver");
1346 MODULE_LICENSE("GPL");
1347