1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __INCLUDED_TEA6415C__ 3*4882a593Smuzhiyun #define __INCLUDED_TEA6415C__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* the tea6415c's design is quite brain-dead. although there are 6*4882a593Smuzhiyun 8 inputs and 6 outputs, these aren't enumerated in any way. because 7*4882a593Smuzhiyun I don't want to say "connect input pin 20 to output pin 17", I define 8*4882a593Smuzhiyun a "virtual" pin-order. */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* input pins */ 11*4882a593Smuzhiyun #define TEA6415C_OUTPUT1 18 12*4882a593Smuzhiyun #define TEA6415C_OUTPUT2 14 13*4882a593Smuzhiyun #define TEA6415C_OUTPUT3 16 14*4882a593Smuzhiyun #define TEA6415C_OUTPUT4 17 15*4882a593Smuzhiyun #define TEA6415C_OUTPUT5 13 16*4882a593Smuzhiyun #define TEA6415C_OUTPUT6 15 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* output pins */ 19*4882a593Smuzhiyun #define TEA6415C_INPUT1 5 20*4882a593Smuzhiyun #define TEA6415C_INPUT2 8 21*4882a593Smuzhiyun #define TEA6415C_INPUT3 3 22*4882a593Smuzhiyun #define TEA6415C_INPUT4 20 23*4882a593Smuzhiyun #define TEA6415C_INPUT5 6 24*4882a593Smuzhiyun #define TEA6415C_INPUT6 10 25*4882a593Smuzhiyun #define TEA6415C_INPUT7 1 26*4882a593Smuzhiyun #define TEA6415C_INPUT8 11 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun #endif 29