1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 Gateworks Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun /* Page 0x00 - General Control */ 7*4882a593Smuzhiyun #define REG_VERSION 0x0000 8*4882a593Smuzhiyun #define REG_INPUT_SEL 0x0001 9*4882a593Smuzhiyun #define REG_SVC_MODE 0x0002 10*4882a593Smuzhiyun #define REG_HPD_MAN_CTRL 0x0003 11*4882a593Smuzhiyun #define REG_RT_MAN_CTRL 0x0004 12*4882a593Smuzhiyun #define REG_STANDBY_SOFT_RST 0x000A 13*4882a593Smuzhiyun #define REG_HDMI_SOFT_RST 0x000B 14*4882a593Smuzhiyun #define REG_HDMI_INFO_RST 0x000C 15*4882a593Smuzhiyun #define REG_INT_FLG_CLR_TOP 0x000E 16*4882a593Smuzhiyun #define REG_INT_FLG_CLR_SUS 0x000F 17*4882a593Smuzhiyun #define REG_INT_FLG_CLR_DDC 0x0010 18*4882a593Smuzhiyun #define REG_INT_FLG_CLR_RATE 0x0011 19*4882a593Smuzhiyun #define REG_INT_FLG_CLR_MODE 0x0012 20*4882a593Smuzhiyun #define REG_INT_FLG_CLR_INFO 0x0013 21*4882a593Smuzhiyun #define REG_INT_FLG_CLR_AUDIO 0x0014 22*4882a593Smuzhiyun #define REG_INT_FLG_CLR_HDCP 0x0015 23*4882a593Smuzhiyun #define REG_INT_FLG_CLR_AFE 0x0016 24*4882a593Smuzhiyun #define REG_INT_MASK_TOP 0x0017 25*4882a593Smuzhiyun #define REG_INT_MASK_SUS 0x0018 26*4882a593Smuzhiyun #define REG_INT_MASK_DDC 0x0019 27*4882a593Smuzhiyun #define REG_INT_MASK_RATE 0x001A 28*4882a593Smuzhiyun #define REG_INT_MASK_MODE 0x001B 29*4882a593Smuzhiyun #define REG_INT_MASK_INFO 0x001C 30*4882a593Smuzhiyun #define REG_INT_MASK_AUDIO 0x001D 31*4882a593Smuzhiyun #define REG_INT_MASK_HDCP 0x001E 32*4882a593Smuzhiyun #define REG_INT_MASK_AFE 0x001F 33*4882a593Smuzhiyun #define REG_DETECT_5V 0x0020 34*4882a593Smuzhiyun #define REG_SUS_STATUS 0x0021 35*4882a593Smuzhiyun #define REG_V_PER 0x0022 36*4882a593Smuzhiyun #define REG_H_PER 0x0025 37*4882a593Smuzhiyun #define REG_HS_WIDTH 0x0027 38*4882a593Smuzhiyun #define REG_FMT_H_TOT 0x0029 39*4882a593Smuzhiyun #define REG_FMT_H_ACT 0x002b 40*4882a593Smuzhiyun #define REG_FMT_H_FRONT 0x002d 41*4882a593Smuzhiyun #define REG_FMT_H_SYNC 0x002f 42*4882a593Smuzhiyun #define REG_FMT_H_BACK 0x0031 43*4882a593Smuzhiyun #define REG_FMT_V_TOT 0x0033 44*4882a593Smuzhiyun #define REG_FMT_V_ACT 0x0035 45*4882a593Smuzhiyun #define REG_FMT_V_FRONT_F1 0x0037 46*4882a593Smuzhiyun #define REG_FMT_V_FRONT_F2 0x0038 47*4882a593Smuzhiyun #define REG_FMT_V_SYNC 0x0039 48*4882a593Smuzhiyun #define REG_FMT_V_BACK_F1 0x003a 49*4882a593Smuzhiyun #define REG_FMT_V_BACK_F2 0x003b 50*4882a593Smuzhiyun #define REG_FMT_DE_ACT 0x003c 51*4882a593Smuzhiyun #define REG_RATE_CTRL 0x0040 52*4882a593Smuzhiyun #define REG_CLK_MIN_RATE 0x0043 53*4882a593Smuzhiyun #define REG_CLK_MAX_RATE 0x0046 54*4882a593Smuzhiyun #define REG_CLK_A_STATUS 0x0049 55*4882a593Smuzhiyun #define REG_CLK_A_RATE 0x004A 56*4882a593Smuzhiyun #define REG_DRIFT_CLK_A_REG 0x004D 57*4882a593Smuzhiyun #define REG_CLK_B_STATUS 0x004E 58*4882a593Smuzhiyun #define REG_CLK_B_RATE 0x004F 59*4882a593Smuzhiyun #define REG_DRIFT_CLK_B_REG 0x0052 60*4882a593Smuzhiyun #define REG_HDCP_CTRL 0x0060 61*4882a593Smuzhiyun #define REG_HDCP_KDS 0x0061 62*4882a593Smuzhiyun #define REG_HDCP_BCAPS 0x0063 63*4882a593Smuzhiyun #define REG_HDCP_KEY_CTRL 0x0064 64*4882a593Smuzhiyun #define REG_INFO_CTRL 0x0076 65*4882a593Smuzhiyun #define REG_INFO_EXCEED 0x0077 66*4882a593Smuzhiyun #define REG_PIX_REPEAT 0x007B 67*4882a593Smuzhiyun #define REG_AUDIO_PATH 0x007C 68*4882a593Smuzhiyun #define REG_AUDCFG 0x007D 69*4882a593Smuzhiyun #define REG_AUDIO_OUT_ENABLE 0x007E 70*4882a593Smuzhiyun #define REG_AUDIO_OUT_HIZ 0x007F 71*4882a593Smuzhiyun #define REG_VDP_CTRL 0x0080 72*4882a593Smuzhiyun #define REG_VDP_MATRIX 0x0081 73*4882a593Smuzhiyun #define REG_VHREF_CTRL 0x00A0 74*4882a593Smuzhiyun #define REG_PXCNT_PR 0x00A2 75*4882a593Smuzhiyun #define REG_PXCNT_NPIX 0x00A4 76*4882a593Smuzhiyun #define REG_LCNT_PR 0x00A6 77*4882a593Smuzhiyun #define REG_LCNT_NLIN 0x00A8 78*4882a593Smuzhiyun #define REG_HREF_S 0x00AA 79*4882a593Smuzhiyun #define REG_HREF_E 0x00AC 80*4882a593Smuzhiyun #define REG_HS_S 0x00AE 81*4882a593Smuzhiyun #define REG_HS_E 0x00B0 82*4882a593Smuzhiyun #define REG_VREF_F1_S 0x00B2 83*4882a593Smuzhiyun #define REG_VREF_F1_WIDTH 0x00B4 84*4882a593Smuzhiyun #define REG_VREF_F2_S 0x00B5 85*4882a593Smuzhiyun #define REG_VREF_F2_WIDTH 0x00B7 86*4882a593Smuzhiyun #define REG_VS_F1_LINE_S 0x00B8 87*4882a593Smuzhiyun #define REG_VS_F1_LINE_WIDTH 0x00BA 88*4882a593Smuzhiyun #define REG_VS_F2_LINE_S 0x00BB 89*4882a593Smuzhiyun #define REG_VS_F2_LINE_WIDTH 0x00BD 90*4882a593Smuzhiyun #define REG_VS_F1_PIX_S 0x00BE 91*4882a593Smuzhiyun #define REG_VS_F1_PIX_E 0x00C0 92*4882a593Smuzhiyun #define REG_VS_F2_PIX_S 0x00C2 93*4882a593Smuzhiyun #define REG_VS_F2_PIX_E 0x00C4 94*4882a593Smuzhiyun #define REG_FREF_F1_S 0x00C6 95*4882a593Smuzhiyun #define REG_FREF_F2_S 0x00C8 96*4882a593Smuzhiyun #define REG_FDW_S 0x00ca 97*4882a593Smuzhiyun #define REG_FDW_E 0x00cc 98*4882a593Smuzhiyun #define REG_BLK_GY 0x00da 99*4882a593Smuzhiyun #define REG_BLK_BU 0x00dc 100*4882a593Smuzhiyun #define REG_BLK_RV 0x00de 101*4882a593Smuzhiyun #define REG_FILTERS_CTRL 0x00e0 102*4882a593Smuzhiyun #define REG_DITHERING_CTRL 0x00E9 103*4882a593Smuzhiyun #define REG_OF 0x00EA 104*4882a593Smuzhiyun #define REG_PCLK 0x00EB 105*4882a593Smuzhiyun #define REG_HS_HREF 0x00EC 106*4882a593Smuzhiyun #define REG_VS_VREF 0x00ED 107*4882a593Smuzhiyun #define REG_DE_FREF 0x00EE 108*4882a593Smuzhiyun #define REG_VP35_32_CTRL 0x00EF 109*4882a593Smuzhiyun #define REG_VP31_28_CTRL 0x00F0 110*4882a593Smuzhiyun #define REG_VP27_24_CTRL 0x00F1 111*4882a593Smuzhiyun #define REG_VP23_20_CTRL 0x00F2 112*4882a593Smuzhiyun #define REG_VP19_16_CTRL 0x00F3 113*4882a593Smuzhiyun #define REG_VP15_12_CTRL 0x00F4 114*4882a593Smuzhiyun #define REG_VP11_08_CTRL 0x00F5 115*4882a593Smuzhiyun #define REG_VP07_04_CTRL 0x00F6 116*4882a593Smuzhiyun #define REG_VP03_00_CTRL 0x00F7 117*4882a593Smuzhiyun #define REG_CURPAGE_00H 0xFF 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define MASK_VPER 0x3fffff 120*4882a593Smuzhiyun #define MASK_VHREF 0x3fff 121*4882a593Smuzhiyun #define MASK_HPER 0x0fff 122*4882a593Smuzhiyun #define MASK_HSWIDTH 0x03ff 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* HPD Detection */ 125*4882a593Smuzhiyun #define DETECT_UTIL BIT(7) /* utility of HDMI level */ 126*4882a593Smuzhiyun #define DETECT_HPD BIT(6) /* HPD of HDMI level */ 127*4882a593Smuzhiyun #define DETECT_5V_SEL BIT(2) /* 5V present on selected input */ 128*4882a593Smuzhiyun #define DETECT_5V_B BIT(1) /* 5V present on input B */ 129*4882a593Smuzhiyun #define DETECT_5V_A BIT(0) /* 5V present on input A */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Input Select */ 132*4882a593Smuzhiyun #define INPUT_SEL_RST_FMT BIT(7) /* 1=reset format measurement */ 133*4882a593Smuzhiyun #define INPUT_SEL_RST_VDP BIT(2) /* 1=reset video data path */ 134*4882a593Smuzhiyun #define INPUT_SEL_OUT_MODE BIT(1) /* 0=loop 1=bypass */ 135*4882a593Smuzhiyun #define INPUT_SEL_B BIT(0) /* 0=inputA 1=inputB */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* Service Mode */ 138*4882a593Smuzhiyun #define SVC_MODE_CLK2_MASK 0xc0 139*4882a593Smuzhiyun #define SVC_MODE_CLK2_SHIFT 6 140*4882a593Smuzhiyun #define SVC_MODE_CLK2_XTL 0L 141*4882a593Smuzhiyun #define SVC_MODE_CLK2_XTLDIV2 1L 142*4882a593Smuzhiyun #define SVC_MODE_CLK2_HDMIX2 3L 143*4882a593Smuzhiyun #define SVC_MODE_CLK1_MASK 0x30 144*4882a593Smuzhiyun #define SVC_MODE_CLK1_SHIFT 4 145*4882a593Smuzhiyun #define SVC_MODE_CLK1_XTAL 0L 146*4882a593Smuzhiyun #define SVC_MODE_CLK1_XTLDIV2 1L 147*4882a593Smuzhiyun #define SVC_MODE_CLK1_HDMI 3L 148*4882a593Smuzhiyun #define SVC_MODE_RAMP BIT(3) /* 0=colorbar 1=ramp */ 149*4882a593Smuzhiyun #define SVC_MODE_PAL BIT(2) /* 0=NTSC(480i/p) 1=PAL(576i/p) */ 150*4882a593Smuzhiyun #define SVC_MODE_INT_PROG BIT(1) /* 0=interlaced 1=progressive */ 151*4882a593Smuzhiyun #define SVC_MODE_SM_ON BIT(0) /* Enable color bars and tone gen */ 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* HDP Manual Control */ 154*4882a593Smuzhiyun #define HPD_MAN_CTRL_HPD_PULSE BIT(7) /* HPD Pulse low 110ms */ 155*4882a593Smuzhiyun #define HPD_MAN_CTRL_5VEN BIT(2) /* Output 5V */ 156*4882a593Smuzhiyun #define HPD_MAN_CTRL_HPD_B BIT(1) /* Assert HPD High for Input A */ 157*4882a593Smuzhiyun #define HPD_MAN_CTRL_HPD_A BIT(0) /* Assert HPD High for Input A */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* RT_MAN_CTRL */ 160*4882a593Smuzhiyun #define RT_MAN_CTRL_RT_AUTO BIT(7) 161*4882a593Smuzhiyun #define RT_MAN_CTRL_RT BIT(6) 162*4882a593Smuzhiyun #define RT_MAN_CTRL_RT_B BIT(1) /* enable TMDS pull-up on Input B */ 163*4882a593Smuzhiyun #define RT_MAN_CTRL_RT_A BIT(0) /* enable TMDS pull-up on Input A */ 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* VDP_CTRL */ 166*4882a593Smuzhiyun #define VDP_CTRL_COMPDEL_BP BIT(5) /* bypass compdel */ 167*4882a593Smuzhiyun #define VDP_CTRL_FORMATTER_BP BIT(4) /* bypass formatter */ 168*4882a593Smuzhiyun #define VDP_CTRL_PREFILTER_BP BIT(1) /* bypass prefilter */ 169*4882a593Smuzhiyun #define VDP_CTRL_MATRIX_BP BIT(0) /* bypass matrix conversion */ 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* REG_VHREF_CTRL */ 172*4882a593Smuzhiyun #define VHREF_INT_DET BIT(7) /* interlace detect: 1=alt 0=frame */ 173*4882a593Smuzhiyun #define VHREF_VSYNC_MASK 0x60 174*4882a593Smuzhiyun #define VHREF_VSYNC_SHIFT 6 175*4882a593Smuzhiyun #define VHREF_VSYNC_AUTO 0L 176*4882a593Smuzhiyun #define VHREF_VSYNC_FDW 1L 177*4882a593Smuzhiyun #define VHREF_VSYNC_EVEN 2L 178*4882a593Smuzhiyun #define VHREF_VSYNC_ODD 3L 179*4882a593Smuzhiyun #define VHREF_STD_DET_MASK 0x18 180*4882a593Smuzhiyun #define VHREF_STD_DET_SHIFT 3 181*4882a593Smuzhiyun #define VHREF_STD_DET_PAL 0L 182*4882a593Smuzhiyun #define VHREF_STD_DET_NTSC 1L 183*4882a593Smuzhiyun #define VHREF_STD_DET_AUTO 2L 184*4882a593Smuzhiyun #define VHREF_STD_DET_OFF 3L 185*4882a593Smuzhiyun #define VHREF_VREF_SRC_STD BIT(2) /* 1=from standard 0=manual */ 186*4882a593Smuzhiyun #define VHREF_HREF_SRC_STD BIT(1) /* 1=from standard 0=manual */ 187*4882a593Smuzhiyun #define VHREF_HSYNC_SEL_HS BIT(0) /* 1=HS 0=VS */ 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* AUDIO_OUT_ENABLE */ 190*4882a593Smuzhiyun #define AUDIO_OUT_ENABLE_ACLK BIT(5) 191*4882a593Smuzhiyun #define AUDIO_OUT_ENABLE_WS BIT(4) 192*4882a593Smuzhiyun #define AUDIO_OUT_ENABLE_AP3 BIT(3) 193*4882a593Smuzhiyun #define AUDIO_OUT_ENABLE_AP2 BIT(2) 194*4882a593Smuzhiyun #define AUDIO_OUT_ENABLE_AP1 BIT(1) 195*4882a593Smuzhiyun #define AUDIO_OUT_ENABLE_AP0 BIT(0) 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun /* Prefilter Control */ 198*4882a593Smuzhiyun #define FILTERS_CTRL_BU_MASK 0x0c 199*4882a593Smuzhiyun #define FILTERS_CTRL_BU_SHIFT 2 200*4882a593Smuzhiyun #define FILTERS_CTRL_RV_MASK 0x03 201*4882a593Smuzhiyun #define FILTERS_CTRL_RV_SHIFT 0 202*4882a593Smuzhiyun #define FILTERS_CTRL_OFF 0L /* off */ 203*4882a593Smuzhiyun #define FILTERS_CTRL_2TAP 1L /* 2 Taps */ 204*4882a593Smuzhiyun #define FILTERS_CTRL_7TAP 2L /* 7 Taps */ 205*4882a593Smuzhiyun #define FILTERS_CTRL_2_7TAP 3L /* 2/7 Taps */ 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* PCLK Configuration */ 208*4882a593Smuzhiyun #define PCLK_DELAY_MASK 0x70 209*4882a593Smuzhiyun #define PCLK_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 210*4882a593Smuzhiyun #define PCLK_INV_SHIFT 2 211*4882a593Smuzhiyun #define PCLK_SEL_MASK 0x03 /* clock scaler */ 212*4882a593Smuzhiyun #define PCLK_SEL_SHIFT 0 213*4882a593Smuzhiyun #define PCLK_SEL_X1 0L 214*4882a593Smuzhiyun #define PCLK_SEL_X2 1L 215*4882a593Smuzhiyun #define PCLK_SEL_DIV2 2L 216*4882a593Smuzhiyun #define PCLK_SEL_DIV4 3L 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* Pixel Repeater */ 219*4882a593Smuzhiyun #define PIX_REPEAT_MASK_UP_SEL 0x30 220*4882a593Smuzhiyun #define PIX_REPEAT_MASK_REP 0x0f 221*4882a593Smuzhiyun #define PIX_REPEAT_SHIFT 4 222*4882a593Smuzhiyun #define PIX_REPEAT_CHROMA 1 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* Page 0x01 - HDMI info and packets */ 225*4882a593Smuzhiyun #define REG_HDMI_FLAGS 0x0100 226*4882a593Smuzhiyun #define REG_DEEP_COLOR_MODE 0x0101 227*4882a593Smuzhiyun #define REG_AUDIO_FLAGS 0x0108 228*4882a593Smuzhiyun #define REG_AUDIO_FREQ 0x0109 229*4882a593Smuzhiyun #define REG_ACP_PACKET_TYPE 0x0141 230*4882a593Smuzhiyun #define REG_ISRC1_PACKET_TYPE 0x0161 231*4882a593Smuzhiyun #define REG_ISRC2_PACKET_TYPE 0x0181 232*4882a593Smuzhiyun #define REG_GBD_PACKET_TYPE 0x01a1 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* HDMI_FLAGS */ 235*4882a593Smuzhiyun #define HDMI_FLAGS_AUDIO BIT(7) /* Audio packet in last videoframe */ 236*4882a593Smuzhiyun #define HDMI_FLAGS_HDMI BIT(6) /* HDMI detected */ 237*4882a593Smuzhiyun #define HDMI_FLAGS_EESS BIT(5) /* EESS detected */ 238*4882a593Smuzhiyun #define HDMI_FLAGS_HDCP BIT(4) /* HDCP detected */ 239*4882a593Smuzhiyun #define HDMI_FLAGS_AVMUTE BIT(3) /* AVMUTE */ 240*4882a593Smuzhiyun #define HDMI_FLAGS_AUD_LAYOUT BIT(2) /* Layout status Audio sample packet */ 241*4882a593Smuzhiyun #define HDMI_FLAGS_AUD_FIFO_OF BIT(1) /* FIFO read/write pointers crossed */ 242*4882a593Smuzhiyun #define HDMI_FLAGS_AUD_FIFO_LOW BIT(0) /* FIFO read ptr within 2 of write */ 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun /* Page 0x12 - HDMI Extra control and debug */ 245*4882a593Smuzhiyun #define REG_CLK_CFG 0x1200 246*4882a593Smuzhiyun #define REG_CLK_OUT_CFG 0x1201 247*4882a593Smuzhiyun #define REG_CFG1 0x1202 248*4882a593Smuzhiyun #define REG_CFG2 0x1203 249*4882a593Smuzhiyun #define REG_WDL_CFG 0x1210 250*4882a593Smuzhiyun #define REG_DELOCK_DELAY 0x1212 251*4882a593Smuzhiyun #define REG_PON_OVR_EN 0x12A0 252*4882a593Smuzhiyun #define REG_PON_CBIAS 0x12A1 253*4882a593Smuzhiyun #define REG_PON_RESCAL 0x12A2 254*4882a593Smuzhiyun #define REG_PON_RES 0x12A3 255*4882a593Smuzhiyun #define REG_PON_CLK 0x12A4 256*4882a593Smuzhiyun #define REG_PON_PLL 0x12A5 257*4882a593Smuzhiyun #define REG_PON_EQ 0x12A6 258*4882a593Smuzhiyun #define REG_PON_DES 0x12A7 259*4882a593Smuzhiyun #define REG_PON_OUT 0x12A8 260*4882a593Smuzhiyun #define REG_PON_MUX 0x12A9 261*4882a593Smuzhiyun #define REG_MODE_REC_CFG1 0x12F8 262*4882a593Smuzhiyun #define REG_MODE_REC_CFG2 0x12F9 263*4882a593Smuzhiyun #define REG_MODE_REC_STS 0x12FA 264*4882a593Smuzhiyun #define REG_AUDIO_LAYOUT 0x12D0 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #define PON_EN 1 267*4882a593Smuzhiyun #define PON_DIS 0 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* CLK CFG */ 270*4882a593Smuzhiyun #define CLK_CFG_INV_OUT_CLK BIT(7) 271*4882a593Smuzhiyun #define CLK_CFG_INV_BUS_CLK BIT(6) 272*4882a593Smuzhiyun #define CLK_CFG_SEL_ACLK_EN BIT(1) 273*4882a593Smuzhiyun #define CLK_CFG_SEL_ACLK BIT(0) 274*4882a593Smuzhiyun #define CLK_CFG_DIS 0 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun /* Page 0x13 - HDMI Extra control and debug */ 277*4882a593Smuzhiyun #define REG_DEEP_COLOR_CTRL 0x1300 278*4882a593Smuzhiyun #define REG_CGU_DBG_SEL 0x1305 279*4882a593Smuzhiyun #define REG_HDCP_DDC_ADDR 0x1310 280*4882a593Smuzhiyun #define REG_HDCP_KIDX 0x1316 281*4882a593Smuzhiyun #define REG_DEEP_PLL7_BYP 0x1347 282*4882a593Smuzhiyun #define REG_HDCP_DE_CTRL 0x1370 283*4882a593Smuzhiyun #define REG_HDCP_EP_FILT_CTRL 0x1371 284*4882a593Smuzhiyun #define REG_HDMI_CTRL 0x1377 285*4882a593Smuzhiyun #define REG_HMTP_CTRL 0x137a 286*4882a593Smuzhiyun #define REG_TIMER_D 0x13CF 287*4882a593Smuzhiyun #define REG_SUS_SET_RGB0 0x13E1 288*4882a593Smuzhiyun #define REG_SUS_SET_RGB1 0x13E2 289*4882a593Smuzhiyun #define REG_SUS_SET_RGB2 0x13E3 290*4882a593Smuzhiyun #define REG_SUS_SET_RGB3 0x13E4 291*4882a593Smuzhiyun #define REG_SUS_SET_RGB4 0x13E5 292*4882a593Smuzhiyun #define REG_MAN_SUS_HDMI_SEL 0x13E8 293*4882a593Smuzhiyun #define REG_MAN_HDMI_SET 0x13E9 294*4882a593Smuzhiyun #define REG_SUS_CLOCK_GOOD 0x13EF 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun /* HDCP DE Control */ 297*4882a593Smuzhiyun #define HDCP_DE_MODE_MASK 0xc0 /* DE Measurement mode */ 298*4882a593Smuzhiyun #define HDCP_DE_MODE_SHIFT 6 299*4882a593Smuzhiyun #define HDCP_DE_REGEN_EN BIT(5) /* enable regen mode */ 300*4882a593Smuzhiyun #define HDCP_DE_FILTER_MASK 0x18 /* DE filter sensitivity */ 301*4882a593Smuzhiyun #define HDCP_DE_FILTER_SHIFT 3 302*4882a593Smuzhiyun #define HDCP_DE_COMP_MASK 0x07 /* DE Composition mode */ 303*4882a593Smuzhiyun #define HDCP_DE_COMP_MIXED 6L 304*4882a593Smuzhiyun #define HDCP_DE_COMP_OR 5L 305*4882a593Smuzhiyun #define HDCP_DE_COMP_AND 4L 306*4882a593Smuzhiyun #define HDCP_DE_COMP_CH3 3L 307*4882a593Smuzhiyun #define HDCP_DE_COMP_CH2 2L 308*4882a593Smuzhiyun #define HDCP_DE_COMP_CH1 1L 309*4882a593Smuzhiyun #define HDCP_DE_COMP_CH0 0L 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun /* HDCP EP Filter Control */ 312*4882a593Smuzhiyun #define HDCP_EP_FIL_CTL_MASK 0x30 313*4882a593Smuzhiyun #define HDCP_EP_FIL_CTL_SHIFT 4 314*4882a593Smuzhiyun #define HDCP_EP_FIL_VS_MASK 0x0c 315*4882a593Smuzhiyun #define HDCP_EP_FIL_VS_SHIFT 2 316*4882a593Smuzhiyun #define HDCP_EP_FIL_HS_MASK 0x03 317*4882a593Smuzhiyun #define HDCP_EP_FIL_HS_SHIFT 0 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* HDMI_CTRL */ 320*4882a593Smuzhiyun #define HDMI_CTRL_MUTE_MASK 0x0c 321*4882a593Smuzhiyun #define HDMI_CTRL_MUTE_SHIFT 2 322*4882a593Smuzhiyun #define HDMI_CTRL_MUTE_AUTO 0L 323*4882a593Smuzhiyun #define HDMI_CTRL_MUTE_OFF 1L 324*4882a593Smuzhiyun #define HDMI_CTRL_MUTE_ON 2L 325*4882a593Smuzhiyun #define HDMI_CTRL_HDCP_MASK 0x03 326*4882a593Smuzhiyun #define HDMI_CTRL_HDCP_SHIFT 0 327*4882a593Smuzhiyun #define HDMI_CTRL_HDCP_EESS 2L 328*4882a593Smuzhiyun #define HDMI_CTRL_HDCP_OESS 1L 329*4882a593Smuzhiyun #define HDMI_CTRL_HDCP_AUTO 0L 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* CGU_DBG_SEL bits */ 332*4882a593Smuzhiyun #define CGU_DBG_CLK_SEL_MASK 0x18 333*4882a593Smuzhiyun #define CGU_DBG_CLK_SEL_SHIFT 3 334*4882a593Smuzhiyun #define CGU_DBG_XO_FRO_SEL BIT(2) 335*4882a593Smuzhiyun #define CGU_DBG_VDP_CLK_SEL BIT(1) 336*4882a593Smuzhiyun #define CGU_DBG_PIX_CLK_SEL BIT(0) 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun /* REG_MAN_SUS_HDMI_SEL / REG_MAN_HDMI_SET bits */ 339*4882a593Smuzhiyun #define MAN_DIS_OUT_BUF BIT(7) 340*4882a593Smuzhiyun #define MAN_DIS_ANA_PATH BIT(6) 341*4882a593Smuzhiyun #define MAN_DIS_HDCP BIT(5) 342*4882a593Smuzhiyun #define MAN_DIS_TMDS_ENC BIT(4) 343*4882a593Smuzhiyun #define MAN_DIS_TMDS_FLOW BIT(3) 344*4882a593Smuzhiyun #define MAN_RST_HDCP BIT(2) 345*4882a593Smuzhiyun #define MAN_RST_TMDS_ENC BIT(1) 346*4882a593Smuzhiyun #define MAN_RST_TMDS_FLOW BIT(0) 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun /* Page 0x14 - Audio Extra control and debug */ 349*4882a593Smuzhiyun #define REG_FIFO_LATENCY_VAL 0x1403 350*4882a593Smuzhiyun #define REG_AUDIO_CLOCK 0x1411 351*4882a593Smuzhiyun #define REG_TEST_NCTS_CTRL 0x1415 352*4882a593Smuzhiyun #define REG_TEST_AUDIO_FREQ 0x1426 353*4882a593Smuzhiyun #define REG_TEST_MODE 0x1437 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun /* Audio Clock Configuration */ 356*4882a593Smuzhiyun #define AUDIO_CLOCK_PLL_PD BIT(7) /* powerdown PLL */ 357*4882a593Smuzhiyun #define AUDIO_CLOCK_SEL_MASK 0x7f 358*4882a593Smuzhiyun #define AUDIO_CLOCK_SEL_16FS 0L /* 16*fs */ 359*4882a593Smuzhiyun #define AUDIO_CLOCK_SEL_32FS 1L /* 32*fs */ 360*4882a593Smuzhiyun #define AUDIO_CLOCK_SEL_64FS 2L /* 64*fs */ 361*4882a593Smuzhiyun #define AUDIO_CLOCK_SEL_128FS 3L /* 128*fs */ 362*4882a593Smuzhiyun #define AUDIO_CLOCK_SEL_256FS 4L /* 256*fs */ 363*4882a593Smuzhiyun #define AUDIO_CLOCK_SEL_512FS 5L /* 512*fs */ 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun /* Page 0x20: EDID and Hotplug Detect */ 366*4882a593Smuzhiyun #define REG_EDID_IN_BYTE0 0x2000 /* EDID base */ 367*4882a593Smuzhiyun #define REG_EDID_IN_VERSION 0x2080 368*4882a593Smuzhiyun #define REG_EDID_ENABLE 0x2081 369*4882a593Smuzhiyun #define REG_HPD_POWER 0x2084 370*4882a593Smuzhiyun #define REG_HPD_AUTO_CTRL 0x2085 371*4882a593Smuzhiyun #define REG_HPD_DURATION 0x2086 372*4882a593Smuzhiyun #define REG_RX_HPD_HEAC 0x2087 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun /* EDID_ENABLE */ 375*4882a593Smuzhiyun #define EDID_ENABLE_NACK_OFF BIT(7) 376*4882a593Smuzhiyun #define EDID_ENABLE_EDID_ONLY BIT(6) 377*4882a593Smuzhiyun #define EDID_ENABLE_B_EN BIT(1) 378*4882a593Smuzhiyun #define EDID_ENABLE_A_EN BIT(0) 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun /* HPD Power */ 381*4882a593Smuzhiyun #define HPD_POWER_BP_MASK 0x0c 382*4882a593Smuzhiyun #define HPD_POWER_BP_SHIFT 2 383*4882a593Smuzhiyun #define HPD_POWER_BP_LOW 0L 384*4882a593Smuzhiyun #define HPD_POWER_BP_HIGH 1L 385*4882a593Smuzhiyun #define HPD_POWER_EDID_ONLY BIT(1) 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun /* HPD Auto control */ 388*4882a593Smuzhiyun #define HPD_AUTO_READ_EDID BIT(7) 389*4882a593Smuzhiyun #define HPD_AUTO_HPD_F3TECH BIT(5) 390*4882a593Smuzhiyun #define HPD_AUTO_HP_OTHER BIT(4) 391*4882a593Smuzhiyun #define HPD_AUTO_HPD_UNSEL BIT(3) 392*4882a593Smuzhiyun #define HPD_AUTO_HPD_ALL_CH BIT(2) 393*4882a593Smuzhiyun #define HPD_AUTO_HPD_PRV_CH BIT(1) 394*4882a593Smuzhiyun #define HPD_AUTO_HPD_NEW_CH BIT(0) 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun /* Page 0x21 - EDID content */ 397*4882a593Smuzhiyun #define REG_EDID_IN_BYTE128 0x2100 /* CEA Extension block */ 398*4882a593Smuzhiyun #define REG_EDID_IN_SPA_SUB 0x2180 399*4882a593Smuzhiyun #define REG_EDID_IN_SPA_AB_A 0x2181 400*4882a593Smuzhiyun #define REG_EDID_IN_SPA_CD_A 0x2182 401*4882a593Smuzhiyun #define REG_EDID_IN_CKSUM_A 0x2183 402*4882a593Smuzhiyun #define REG_EDID_IN_SPA_AB_B 0x2184 403*4882a593Smuzhiyun #define REG_EDID_IN_SPA_CD_B 0x2185 404*4882a593Smuzhiyun #define REG_EDID_IN_CKSUM_B 0x2186 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun /* Page 0x30 - NV Configuration */ 407*4882a593Smuzhiyun #define REG_RT_AUTO_CTRL 0x3000 408*4882a593Smuzhiyun #define REG_EQ_MAN_CTRL0 0x3001 409*4882a593Smuzhiyun #define REG_EQ_MAN_CTRL1 0x3002 410*4882a593Smuzhiyun #define REG_OUTPUT_CFG 0x3003 411*4882a593Smuzhiyun #define REG_MUTE_CTRL 0x3004 412*4882a593Smuzhiyun #define REG_SLAVE_ADDR 0x3005 413*4882a593Smuzhiyun #define REG_CMTP_REG6 0x3006 414*4882a593Smuzhiyun #define REG_CMTP_REG7 0x3007 415*4882a593Smuzhiyun #define REG_CMTP_REG8 0x3008 416*4882a593Smuzhiyun #define REG_CMTP_REG9 0x3009 417*4882a593Smuzhiyun #define REG_CMTP_REGA 0x300A 418*4882a593Smuzhiyun #define REG_CMTP_REGB 0x300B 419*4882a593Smuzhiyun #define REG_CMTP_REGC 0x300C 420*4882a593Smuzhiyun #define REG_CMTP_REGD 0x300D 421*4882a593Smuzhiyun #define REG_CMTP_REGE 0x300E 422*4882a593Smuzhiyun #define REG_CMTP_REGF 0x300F 423*4882a593Smuzhiyun #define REG_CMTP_REG10 0x3010 424*4882a593Smuzhiyun #define REG_CMTP_REG11 0x3011 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun /* Page 0x80 - CEC */ 427*4882a593Smuzhiyun #define REG_PWR_CONTROL 0x80F4 428*4882a593Smuzhiyun #define REG_OSC_DIVIDER 0x80F5 429*4882a593Smuzhiyun #define REG_EN_OSC_PERIOD_LSB 0x80F8 430*4882a593Smuzhiyun #define REG_CONTROL 0x80FF 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun /* global interrupt flags (INT_FLG_CRL_TOP) */ 433*4882a593Smuzhiyun #define INTERRUPT_AFE BIT(7) /* AFE module */ 434*4882a593Smuzhiyun #define INTERRUPT_HDCP BIT(6) /* HDCP module */ 435*4882a593Smuzhiyun #define INTERRUPT_AUDIO BIT(5) /* Audio module */ 436*4882a593Smuzhiyun #define INTERRUPT_INFO BIT(4) /* Infoframe module */ 437*4882a593Smuzhiyun #define INTERRUPT_MODE BIT(3) /* HDMI mode module */ 438*4882a593Smuzhiyun #define INTERRUPT_RATE BIT(2) /* rate module */ 439*4882a593Smuzhiyun #define INTERRUPT_DDC BIT(1) /* DDC module */ 440*4882a593Smuzhiyun #define INTERRUPT_SUS BIT(0) /* SUS module */ 441*4882a593Smuzhiyun 442*4882a593Smuzhiyun /* INT_FLG_CLR_HDCP bits */ 443*4882a593Smuzhiyun #define MASK_HDCP_MTP BIT(7) /* HDCP MTP busy */ 444*4882a593Smuzhiyun #define MASK_HDCP_DLMTP BIT(4) /* HDCP end download MTP to SRAM */ 445*4882a593Smuzhiyun #define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */ 446*4882a593Smuzhiyun #define MASK_HDCP_ENC BIT(2) /* HDCP ENC */ 447*4882a593Smuzhiyun #define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */ 448*4882a593Smuzhiyun #define MASK_AKSV BIT(0) /* AKSV received (start of auth) */ 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun /* INT_FLG_CLR_RATE bits */ 451*4882a593Smuzhiyun #define MASK_RATE_B_DRIFT BIT(7) /* Rate measurement drifted */ 452*4882a593Smuzhiyun #define MASK_RATE_B_ST BIT(6) /* Rate measurement stability change */ 453*4882a593Smuzhiyun #define MASK_RATE_B_ACT BIT(5) /* Rate measurement activity change */ 454*4882a593Smuzhiyun #define MASK_RATE_B_PST BIT(4) /* Rate measreument presence change */ 455*4882a593Smuzhiyun #define MASK_RATE_A_DRIFT BIT(3) /* Rate measurement drifted */ 456*4882a593Smuzhiyun #define MASK_RATE_A_ST BIT(2) /* Rate measurement stability change */ 457*4882a593Smuzhiyun #define MASK_RATE_A_ACT BIT(1) /* Rate measurement presence change */ 458*4882a593Smuzhiyun #define MASK_RATE_A_PST BIT(0) /* Rate measreument presence change */ 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun /* INT_FLG_CLR_SUS (Start Up Sequencer) bits */ 461*4882a593Smuzhiyun #define MASK_MPT BIT(7) /* Config MTP end of process */ 462*4882a593Smuzhiyun #define MASK_FMT BIT(5) /* Video format changed */ 463*4882a593Smuzhiyun #define MASK_RT_PULSE BIT(4) /* End of termination resistance pulse */ 464*4882a593Smuzhiyun #define MASK_SUS_END BIT(3) /* SUS last state reached */ 465*4882a593Smuzhiyun #define MASK_SUS_ACT BIT(2) /* Activity of selected input changed */ 466*4882a593Smuzhiyun #define MASK_SUS_CH BIT(1) /* Selected input changed */ 467*4882a593Smuzhiyun #define MASK_SUS_ST BIT(0) /* SUS state changed */ 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun /* INT_FLG_CLR_DDC bits */ 470*4882a593Smuzhiyun #define MASK_EDID_MTP BIT(7) /* EDID MTP end of process */ 471*4882a593Smuzhiyun #define MASK_DDC_ERR BIT(6) /* master DDC error */ 472*4882a593Smuzhiyun #define MASK_DDC_CMD_DONE BIT(5) /* master DDC cmd send correct */ 473*4882a593Smuzhiyun #define MASK_READ_DONE BIT(4) /* End of down EDID read */ 474*4882a593Smuzhiyun #define MASK_RX_DDC_SW BIT(3) /* Output DDC switching finished */ 475*4882a593Smuzhiyun #define MASK_HDCP_DDC_SW BIT(2) /* HDCP DDC switching finished */ 476*4882a593Smuzhiyun #define MASK_HDP_PULSE_END BIT(1) /* End of Hot Plug Detect pulse */ 477*4882a593Smuzhiyun #define MASK_DET_5V BIT(0) /* Detection of +5V */ 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun /* INT_FLG_CLR_MODE bits */ 480*4882a593Smuzhiyun #define MASK_HDMI_FLG BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */ 481*4882a593Smuzhiyun #define MASK_GAMUT BIT(6) /* Gamut packet */ 482*4882a593Smuzhiyun #define MASK_ISRC2 BIT(5) /* ISRC2 packet */ 483*4882a593Smuzhiyun #define MASK_ISRC1 BIT(4) /* ISRC1 packet */ 484*4882a593Smuzhiyun #define MASK_ACP BIT(3) /* Audio Content Protection packet */ 485*4882a593Smuzhiyun #define MASK_DC_NO_GCP BIT(2) /* GCP not received in 5 frames */ 486*4882a593Smuzhiyun #define MASK_DC_PHASE BIT(1) /* deepcolor pixel phase needs update */ 487*4882a593Smuzhiyun #define MASK_DC_MODE BIT(0) /* deepcolor color depth changed */ 488*4882a593Smuzhiyun 489*4882a593Smuzhiyun /* INT_FLG_CLR_INFO bits (Infoframe Change Status) */ 490*4882a593Smuzhiyun #define MASK_MPS_IF BIT(6) /* MPEG Source Product */ 491*4882a593Smuzhiyun #define MASK_AUD_IF BIT(5) /* Audio */ 492*4882a593Smuzhiyun #define MASK_SPD_IF BIT(4) /* Source Product Descriptor */ 493*4882a593Smuzhiyun #define MASK_AVI_IF BIT(3) /* Auxiliary Video IF */ 494*4882a593Smuzhiyun #define MASK_VS_IF_OTHER_BK2 BIT(2) /* Vendor Specific (bank2) */ 495*4882a593Smuzhiyun #define MASK_VS_IF_OTHER_BK1 BIT(1) /* Vendor Specific (bank1) */ 496*4882a593Smuzhiyun #define MASK_VS_IF_HDMI BIT(0) /* Vendor Specific (w/ HDMI LLC code) */ 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun /* INT_FLG_CLR_AUDIO bits */ 499*4882a593Smuzhiyun #define MASK_AUDIO_FREQ_FLG BIT(5) /* Audio freq change */ 500*4882a593Smuzhiyun #define MASK_AUDIO_FLG BIT(4) /* DST, OBA, HBR, ASP change */ 501*4882a593Smuzhiyun #define MASK_MUTE_FLG BIT(3) /* Audio Mute */ 502*4882a593Smuzhiyun #define MASK_CH_STATE BIT(2) /* Channel status */ 503*4882a593Smuzhiyun #define MASK_UNMUTE_FIFO BIT(1) /* Audio Unmute */ 504*4882a593Smuzhiyun #define MASK_ERROR_FIFO_PT BIT(0) /* Audio FIFO pointer error */ 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun /* INT_FLG_CLR_AFE bits */ 507*4882a593Smuzhiyun #define MASK_AFE_WDL_UNLOCKED BIT(7) /* Wordlocker was unlocked */ 508*4882a593Smuzhiyun #define MASK_AFE_GAIN_DONE BIT(6) /* Gain calibration done */ 509*4882a593Smuzhiyun #define MASK_AFE_OFFSET_DONE BIT(5) /* Offset calibration done */ 510*4882a593Smuzhiyun #define MASK_AFE_ACTIVITY_DET BIT(4) /* Activity detected on data */ 511*4882a593Smuzhiyun #define MASK_AFE_PLL_LOCK BIT(3) /* TMDS PLL is locked */ 512*4882a593Smuzhiyun #define MASK_AFE_TRMCAL_DONE BIT(2) /* Termination calibration done */ 513*4882a593Smuzhiyun #define MASK_AFE_ASU_STATE BIT(1) /* ASU state is reached */ 514*4882a593Smuzhiyun #define MASK_AFE_ASU_READY BIT(0) /* AFE calibration done: TMDS ready */ 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun /* Audio Output */ 517*4882a593Smuzhiyun #define AUDCFG_CLK_INVERT BIT(7) /* invert A_CLK polarity */ 518*4882a593Smuzhiyun #define AUDCFG_TEST_TONE BIT(6) /* enable test tone generator */ 519*4882a593Smuzhiyun #define AUDCFG_BUS_SHIFT 5 520*4882a593Smuzhiyun #define AUDCFG_BUS_I2S 0L 521*4882a593Smuzhiyun #define AUDCFG_BUS_SPDIF 1L 522*4882a593Smuzhiyun #define AUDCFG_I2SW_SHIFT 4 523*4882a593Smuzhiyun #define AUDCFG_I2SW_16 0L 524*4882a593Smuzhiyun #define AUDCFG_I2SW_32 1L 525*4882a593Smuzhiyun #define AUDCFG_AUTO_MUTE_EN BIT(3) /* Enable Automatic audio mute */ 526*4882a593Smuzhiyun #define AUDCFG_HBR_SHIFT 2 527*4882a593Smuzhiyun #define AUDCFG_HBR_STRAIGHT 0L /* straight via AP0 */ 528*4882a593Smuzhiyun #define AUDCFG_HBR_DEMUX 1L /* demuxed via AP0:AP3 */ 529*4882a593Smuzhiyun #define AUDCFG_TYPE_MASK 0x03 530*4882a593Smuzhiyun #define AUDCFG_TYPE_SHIFT 0 531*4882a593Smuzhiyun #define AUDCFG_TYPE_DST 3L /* Direct Stream Transfer (DST) */ 532*4882a593Smuzhiyun #define AUDCFG_TYPE_OBA 2L /* One Bit Audio (OBA) */ 533*4882a593Smuzhiyun #define AUDCFG_TYPE_HBR 1L /* High Bit Rate (HBR) */ 534*4882a593Smuzhiyun #define AUDCFG_TYPE_PCM 0L /* Audio samples */ 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun /* Video Formatter */ 537*4882a593Smuzhiyun #define OF_VP_ENABLE BIT(7) /* VP[35:0]/HS/VS/DE/CLK */ 538*4882a593Smuzhiyun #define OF_BLK BIT(4) /* blanking codes */ 539*4882a593Smuzhiyun #define OF_TRC BIT(3) /* timing codes (SAV/EAV) */ 540*4882a593Smuzhiyun #define OF_FMT_MASK 0x3 541*4882a593Smuzhiyun #define OF_FMT_444 0L /* RGB444/YUV444 */ 542*4882a593Smuzhiyun #define OF_FMT_422_SMPT 1L /* YUV422 semi-planar */ 543*4882a593Smuzhiyun #define OF_FMT_422_CCIR 2L /* YUV422 CCIR656 */ 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun /* HS/HREF output control */ 546*4882a593Smuzhiyun #define HS_HREF_DELAY_MASK 0xf0 547*4882a593Smuzhiyun #define HS_HREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 548*4882a593Smuzhiyun #define HS_HREF_PXQ_SHIFT 3 /* Timing codes from HREF */ 549*4882a593Smuzhiyun #define HS_HREF_INV_SHIFT 2 /* polarity (1=invert) */ 550*4882a593Smuzhiyun #define HS_HREF_SEL_MASK 0x03 551*4882a593Smuzhiyun #define HS_HREF_SEL_SHIFT 0 552*4882a593Smuzhiyun #define HS_HREF_SEL_HS_VHREF 0L /* HS from VHREF */ 553*4882a593Smuzhiyun #define HS_HREF_SEL_HREF_VHREF 1L /* HREF from VHREF */ 554*4882a593Smuzhiyun #define HS_HREF_SEL_HREF_HDMI 2L /* HREF from HDMI */ 555*4882a593Smuzhiyun #define HS_HREF_SEL_NONE 3L /* not generated */ 556*4882a593Smuzhiyun 557*4882a593Smuzhiyun /* VS output control */ 558*4882a593Smuzhiyun #define VS_VREF_DELAY_MASK 0xf0 559*4882a593Smuzhiyun #define VS_VREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 560*4882a593Smuzhiyun #define VS_VREF_INV_SHIFT 2 /* polarity (1=invert) */ 561*4882a593Smuzhiyun #define VS_VREF_SEL_MASK 0x03 562*4882a593Smuzhiyun #define VS_VREF_SEL_SHIFT 0 563*4882a593Smuzhiyun #define VS_VREF_SEL_VS_VHREF 0L /* VS from VHREF */ 564*4882a593Smuzhiyun #define VS_VREF_SEL_VREF_VHREF 1L /* VREF from VHREF */ 565*4882a593Smuzhiyun #define VS_VREF_SEL_VREF_HDMI 2L /* VREF from HDMI */ 566*4882a593Smuzhiyun #define VS_VREF_SEL_NONE 3L /* not generated */ 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun /* DE/FREF output control */ 569*4882a593Smuzhiyun #define DE_FREF_DELAY_MASK 0xf0 570*4882a593Smuzhiyun #define DE_FREF_DELAY_SHIFT 4 /* Pixel delay (-8..+7) */ 571*4882a593Smuzhiyun #define DE_FREF_DE_PXQ_SHIFT 3 /* Timing codes from DE */ 572*4882a593Smuzhiyun #define DE_FREF_INV_SHIFT 2 /* polarity (1=invert) */ 573*4882a593Smuzhiyun #define DE_FREF_SEL_MASK 0x03 574*4882a593Smuzhiyun #define DE_FREF_SEL_SHIFT 0 575*4882a593Smuzhiyun #define DE_FREF_SEL_DE_VHREF 0L /* DE from VHREF (HREF and not(VREF) */ 576*4882a593Smuzhiyun #define DE_FREF_SEL_FREF_VHREF 1L /* FREF from VHREF */ 577*4882a593Smuzhiyun #define DE_FREF_SEL_FREF_HDMI 2L /* FREF from HDMI */ 578*4882a593Smuzhiyun #define DE_FREF_SEL_NONE 3L /* not generated */ 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun /* HDMI_SOFT_RST bits */ 581*4882a593Smuzhiyun #define RESET_DC BIT(7) /* Reset deep color module */ 582*4882a593Smuzhiyun #define RESET_HDCP BIT(6) /* Reset HDCP module */ 583*4882a593Smuzhiyun #define RESET_KSV BIT(5) /* Reset KSV-FIFO */ 584*4882a593Smuzhiyun #define RESET_SCFG BIT(4) /* Reset HDCP and repeater function */ 585*4882a593Smuzhiyun #define RESET_HCFG BIT(3) /* Reset HDCP DDC part */ 586*4882a593Smuzhiyun #define RESET_PA BIT(2) /* Reset polarity adjust */ 587*4882a593Smuzhiyun #define RESET_EP BIT(1) /* Reset Error protection */ 588*4882a593Smuzhiyun #define RESET_TMDS BIT(0) /* Reset TMDS (calib, encoding, flow) */ 589*4882a593Smuzhiyun 590*4882a593Smuzhiyun /* HDMI_INFO_RST bits */ 591*4882a593Smuzhiyun #define NACK_HDCP BIT(7) /* No ACK on HDCP request */ 592*4882a593Smuzhiyun #define RESET_FIFO BIT(4) /* Reset Audio FIFO control */ 593*4882a593Smuzhiyun #define RESET_GAMUT BIT(3) /* Clear Gamut packet */ 594*4882a593Smuzhiyun #define RESET_AI BIT(2) /* Clear ACP and ISRC packets */ 595*4882a593Smuzhiyun #define RESET_IF BIT(1) /* Clear all Audio infoframe packets */ 596*4882a593Smuzhiyun #define RESET_AUDIO BIT(0) /* Reset Audio FIFO control */ 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun /* HDCP_BCAPS bits */ 599*4882a593Smuzhiyun #define HDCP_HDMI BIT(7) /* HDCP supports HDMI (vs DVI only) */ 600*4882a593Smuzhiyun #define HDCP_REPEATER BIT(6) /* HDCP supports repeater function */ 601*4882a593Smuzhiyun #define HDCP_READY BIT(5) /* set by repeater function */ 602*4882a593Smuzhiyun #define HDCP_FAST BIT(4) /* Up to 400kHz */ 603*4882a593Smuzhiyun #define HDCP_11 BIT(1) /* HDCP 1.1 supported */ 604*4882a593Smuzhiyun #define HDCP_FAST_REAUTH BIT(0) /* fast reauthentication supported */ 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun /* Audio output formatter */ 607*4882a593Smuzhiyun #define AUDIO_LAYOUT_SP_FLAG BIT(2) /* sp flag used by FIFO */ 608*4882a593Smuzhiyun #define AUDIO_LAYOUT_MANUAL BIT(1) /* manual layout (vs per pkt) */ 609*4882a593Smuzhiyun #define AUDIO_LAYOUT_LAYOUT1 BIT(0) /* Layout1: AP0-3 vs Layout0:AP0 */ 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun /* masks for interrupt status registers */ 612*4882a593Smuzhiyun #define MASK_SUS_STATUS 0x1F 613*4882a593Smuzhiyun #define LAST_STATE_REACHED 0x1B 614*4882a593Smuzhiyun #define MASK_CLK_STABLE 0x04 615*4882a593Smuzhiyun #define MASK_CLK_ACTIVE 0x02 616*4882a593Smuzhiyun #define MASK_SUS_STATE 0x10 617*4882a593Smuzhiyun #define MASK_SR_FIFO_FIFO_CTRL 0x30 618*4882a593Smuzhiyun #define MASK_AUDIO_FLAG 0x10 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun /* Rate measurement */ 621*4882a593Smuzhiyun #define RATE_REFTIM_ENABLE 0x01 622*4882a593Smuzhiyun #define CLK_MIN_RATE 0x0057e4 623*4882a593Smuzhiyun #define CLK_MAX_RATE 0x0395f8 624*4882a593Smuzhiyun #define WDL_CFG_VAL 0x82 625*4882a593Smuzhiyun #define DC_FILTER_VAL 0x31 626*4882a593Smuzhiyun 627*4882a593Smuzhiyun /* Infoframe */ 628*4882a593Smuzhiyun #define VS_HDMI_IF_UPDATE 0x0200 629*4882a593Smuzhiyun #define VS_HDMI_IF 0x0201 630*4882a593Smuzhiyun #define VS_BK1_IF_UPDATE 0x0220 631*4882a593Smuzhiyun #define VS_BK1_IF 0x0221 632*4882a593Smuzhiyun #define VS_BK2_IF_UPDATE 0x0240 633*4882a593Smuzhiyun #define VS_BK2_IF 0x0241 634*4882a593Smuzhiyun #define AVI_IF_UPDATE 0x0260 635*4882a593Smuzhiyun #define AVI_IF 0x0261 636*4882a593Smuzhiyun #define SPD_IF_UPDATE 0x0280 637*4882a593Smuzhiyun #define SPD_IF 0x0281 638*4882a593Smuzhiyun #define AUD_IF_UPDATE 0x02a0 639*4882a593Smuzhiyun #define AUD_IF 0x02a1 640*4882a593Smuzhiyun #define MPS_IF_UPDATE 0x02c0 641*4882a593Smuzhiyun #define MPS_IF 0x02c1 642