1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * tc35874x - Toshiba HDMI to CSI-2 bridge - register names and bit masks 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 5*4882a593Smuzhiyun * reserved. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This program is free software; you may redistribute it and/or modify 8*4882a593Smuzhiyun * it under the terms of the GNU General Public License as published by 9*4882a593Smuzhiyun * the Free Software Foundation; version 2 of the License. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 12*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 13*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 14*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 15*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 16*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 17*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 18*4882a593Smuzhiyun * SOFTWARE. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * References (c = chapter, p = page): 24*4882a593Smuzhiyun * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 25*4882a593Smuzhiyun * REF_02 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* Bit masks has prefix 'MASK_' and options after '_'. */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifndef __TC35874X_REGS_H 31*4882a593Smuzhiyun #define __TC35874X_REGS_H 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define CHIPID 0x0000 34*4882a593Smuzhiyun #define MASK_CHIPID 0xff00 35*4882a593Smuzhiyun #define MASK_REVID 0x00ff 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define SYSCTL 0x0002 38*4882a593Smuzhiyun #define MASK_IRRST 0x0800 39*4882a593Smuzhiyun #define MASK_CECRST 0x0400 40*4882a593Smuzhiyun #define MASK_CTXRST 0x0200 41*4882a593Smuzhiyun #define MASK_HDMIRST 0x0100 42*4882a593Smuzhiyun #define MASK_I2SDIS 0x0080 43*4882a593Smuzhiyun #define MASK_SLEEP 0x0001 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define CONFCTL 0x0004 46*4882a593Smuzhiyun #define MASK_PWRISO 0x8000 47*4882a593Smuzhiyun #define MASK_ACLKOPT 0x1000 48*4882a593Smuzhiyun #define MASK_AUDCHNUM 0x0c00 49*4882a593Smuzhiyun #define MASK_AUDCHNUM_8 0x0000 50*4882a593Smuzhiyun #define MASK_AUDCHNUM_6 0x0400 51*4882a593Smuzhiyun #define MASK_AUDCHNUM_4 0x0800 52*4882a593Smuzhiyun #define MASK_AUDCHNUM_2 0x0c00 53*4882a593Smuzhiyun #define MASK_AUDCHSEL 0x0200 54*4882a593Smuzhiyun #define MASK_I2SDLYOPT 0x0100 55*4882a593Smuzhiyun #define MASK_YCBCRFMT 0x00c0 56*4882a593Smuzhiyun #define MASK_YCBCRFMT_444 0x0000 57*4882a593Smuzhiyun #define MASK_YCBCRFMT_422_12_BIT 0x0040 58*4882a593Smuzhiyun #define MASK_YCBCRFMT_COLORBAR 0x0080 59*4882a593Smuzhiyun #define MASK_YCBCRFMT_422_8_BIT 0x00c0 60*4882a593Smuzhiyun #define MASK_INFRMEN 0x0020 61*4882a593Smuzhiyun #define MASK_AUDOUTSEL 0x0018 62*4882a593Smuzhiyun #define MASK_AUDOUTSEL_CSI 0x0000 63*4882a593Smuzhiyun #define MASK_AUDOUTSEL_I2S 0x0010 64*4882a593Smuzhiyun #define MASK_AUDOUTSEL_TDM 0x0018 65*4882a593Smuzhiyun #define MASK_AUTOINDEX 0x0004 66*4882a593Smuzhiyun #define MASK_ABUFEN 0x0002 67*4882a593Smuzhiyun #define MASK_VBUFEN 0x0001 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define FIFOCTL 0x0006 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define PACKETID1 0x000C 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define FCCTL 0x0012 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #define INTSTATUS 0x0014 76*4882a593Smuzhiyun #define MASK_AMUTE_INT 0x0400 77*4882a593Smuzhiyun #define MASK_HDMI_INT 0x0200 78*4882a593Smuzhiyun #define MASK_CSI_INT 0x0100 79*4882a593Smuzhiyun #define MASK_SYS_INT 0x0020 80*4882a593Smuzhiyun #define MASK_CEC_EINT 0x0010 81*4882a593Smuzhiyun #define MASK_CEC_TINT 0x0008 82*4882a593Smuzhiyun #define MASK_CEC_RINT 0x0004 83*4882a593Smuzhiyun #define MASK_IR_EINT 0x0002 84*4882a593Smuzhiyun #define MASK_IR_DINT 0x0001 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define INTMASK 0x0016 87*4882a593Smuzhiyun #define MASK_AMUTE_MSK 0x0400 88*4882a593Smuzhiyun #define MASK_HDMI_MSK 0x0200 89*4882a593Smuzhiyun #define MASK_CSI_MSK 0x0100 90*4882a593Smuzhiyun #define MASK_SYS_MSK 0x0020 91*4882a593Smuzhiyun #define MASK_CEC_EMSK 0x0010 92*4882a593Smuzhiyun #define MASK_CEC_TMSK 0x0008 93*4882a593Smuzhiyun #define MASK_CEC_RMSK 0x0004 94*4882a593Smuzhiyun #define MASK_IR_EMSK 0x0002 95*4882a593Smuzhiyun #define MASK_IR_DMSK 0x0001 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define INTFLAG 0x0018 98*4882a593Smuzhiyun #define INTSYSSTATUS 0x001A 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #define PLLCTL0 0x0020 101*4882a593Smuzhiyun #define MASK_PLL_PRD 0xf000 102*4882a593Smuzhiyun #define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\ 103*4882a593Smuzhiyun MASK_PLL_PRD) 104*4882a593Smuzhiyun #define MASK_PLL_FBD 0x01ff 105*4882a593Smuzhiyun #define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define PLLCTL1 0x0022 108*4882a593Smuzhiyun #define MASK_PLL_FRS 0x0c00 109*4882a593Smuzhiyun #define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_FRS) 110*4882a593Smuzhiyun #define MASK_PLL_LBWS 0x0300 111*4882a593Smuzhiyun #define MASK_LFBREN 0x0040 112*4882a593Smuzhiyun #define MASK_BYPCKEN 0x0020 113*4882a593Smuzhiyun #define MASK_CKEN 0x0010 114*4882a593Smuzhiyun #define MASK_RESETB 0x0002 115*4882a593Smuzhiyun #define MASK_PLL_EN 0x0001 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define CLW_CNTRL 0x0140 118*4882a593Smuzhiyun #define MASK_CLW_LANEDISABLE 0x0001 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define D0W_CNTRL 0x0144 121*4882a593Smuzhiyun #define MASK_D0W_LANEDISABLE 0x0001 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun #define D1W_CNTRL 0x0148 124*4882a593Smuzhiyun #define MASK_D1W_LANEDISABLE 0x0001 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define D2W_CNTRL 0x014C 127*4882a593Smuzhiyun #define MASK_D2W_LANEDISABLE 0x0001 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define D3W_CNTRL 0x0150 130*4882a593Smuzhiyun #define MASK_D3W_LANEDISABLE 0x0001 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define STARTCNTRL 0x0204 133*4882a593Smuzhiyun #define MASK_START 0x00000001 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define LINEINITCNT 0x0210 136*4882a593Smuzhiyun #define LPTXTIMECNT 0x0214 137*4882a593Smuzhiyun #define TCLK_HEADERCNT 0x0218 138*4882a593Smuzhiyun #define TCLK_TRAILCNT 0x021C 139*4882a593Smuzhiyun #define THS_HEADERCNT 0x0220 140*4882a593Smuzhiyun #define TWAKEUP 0x0224 141*4882a593Smuzhiyun #define TCLK_POSTCNT 0x0228 142*4882a593Smuzhiyun #define THS_TRAILCNT 0x022C 143*4882a593Smuzhiyun #define HSTXVREGCNT 0x0230 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define HSTXVREGEN 0x0234 146*4882a593Smuzhiyun #define MASK_D3M_HSTXVREGEN 0x0010 147*4882a593Smuzhiyun #define MASK_D2M_HSTXVREGEN 0x0008 148*4882a593Smuzhiyun #define MASK_D1M_HSTXVREGEN 0x0004 149*4882a593Smuzhiyun #define MASK_D0M_HSTXVREGEN 0x0002 150*4882a593Smuzhiyun #define MASK_CLM_HSTXVREGEN 0x0001 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define TXOPTIONCNTRL 0x0238 154*4882a593Smuzhiyun #define MASK_CONTCLKMODE 0x00000001 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define CSI_CONTROL 0x040C 157*4882a593Smuzhiyun #define MASK_CSI_MODE 0x8000 158*4882a593Smuzhiyun #define MASK_HTXTOEN 0x0400 159*4882a593Smuzhiyun #define MASK_TXHSMD 0x0080 160*4882a593Smuzhiyun #define MASK_HSCKMD 0x0020 161*4882a593Smuzhiyun #define MASK_NOL 0x0006 162*4882a593Smuzhiyun #define MASK_NOL_1 0x0000 163*4882a593Smuzhiyun #define MASK_NOL_2 0x0002 164*4882a593Smuzhiyun #define MASK_NOL_3 0x0004 165*4882a593Smuzhiyun #define MASK_NOL_4 0x0006 166*4882a593Smuzhiyun #define MASK_EOTDIS 0x0001 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun #define CSI_INT 0x0414 169*4882a593Smuzhiyun #define MASK_INTHLT 0x00000008 170*4882a593Smuzhiyun #define MASK_INTER 0x00000004 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun #define CSI_INT_ENA 0x0418 173*4882a593Smuzhiyun #define MASK_IENHLT 0x00000008 174*4882a593Smuzhiyun #define MASK_IENER 0x00000004 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun #define CSI_ERR 0x044C 177*4882a593Smuzhiyun #define MASK_INER 0x00000200 178*4882a593Smuzhiyun #define MASK_WCER 0x00000100 179*4882a593Smuzhiyun #define MASK_QUNK 0x00000010 180*4882a593Smuzhiyun #define MASK_TXBRK 0x00000002 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define CSI_ERR_INTENA 0x0450 183*4882a593Smuzhiyun #define CSI_ERR_HALT 0x0454 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun #define CSI_CONFW 0x0500 186*4882a593Smuzhiyun #define MASK_MODE 0xe0000000 187*4882a593Smuzhiyun #define MASK_MODE_SET 0xa0000000 188*4882a593Smuzhiyun #define MASK_MODE_CLEAR 0xc0000000 189*4882a593Smuzhiyun #define MASK_ADDRESS 0x1f000000 190*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_CONTROL 0x03000000 191*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_INT_ENA 0x06000000 192*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000 193*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_ERR_HALT 0x15000000 194*4882a593Smuzhiyun #define MASK_DATA 0x0000ffff 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define CSI_INT_CLR 0x050C 197*4882a593Smuzhiyun #define MASK_ICRER 0x00000004 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define CSI_START 0x0518 200*4882a593Smuzhiyun #define MASK_STRT 0x00000001 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define CECEN 0x0600 203*4882a593Smuzhiyun #define MASK_CECEN 0x0001 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun #define HDMI_INT0 0x8500 206*4882a593Smuzhiyun #define MASK_I_KEY 0x80 207*4882a593Smuzhiyun #define MASK_I_MISC 0x02 208*4882a593Smuzhiyun #define MASK_I_PHYERR 0x01 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define HDMI_INT1 0x8501 211*4882a593Smuzhiyun #define MASK_I_GBD 0x80 212*4882a593Smuzhiyun #define MASK_I_HDCP 0x40 213*4882a593Smuzhiyun #define MASK_I_ERR 0x20 214*4882a593Smuzhiyun #define MASK_I_AUD 0x10 215*4882a593Smuzhiyun #define MASK_I_CBIT 0x08 216*4882a593Smuzhiyun #define MASK_I_PACKET 0x04 217*4882a593Smuzhiyun #define MASK_I_CLK 0x02 218*4882a593Smuzhiyun #define MASK_I_SYS 0x01 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun #define SYS_INT 0x8502 221*4882a593Smuzhiyun #define MASK_I_ACR_CTS 0x80 222*4882a593Smuzhiyun #define MASK_I_ACRN 0x40 223*4882a593Smuzhiyun #define MASK_I_DVI 0x20 224*4882a593Smuzhiyun #define MASK_I_HDMI 0x10 225*4882a593Smuzhiyun #define MASK_I_NOPMBDET 0x08 226*4882a593Smuzhiyun #define MASK_I_DPMBDET 0x04 227*4882a593Smuzhiyun #define MASK_I_TMDS 0x02 228*4882a593Smuzhiyun #define MASK_I_DDC 0x01 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun #define CLK_INT 0x8503 231*4882a593Smuzhiyun #define MASK_I_OUT_H_CHG 0x40 232*4882a593Smuzhiyun #define MASK_I_IN_DE_CHG 0x20 233*4882a593Smuzhiyun #define MASK_I_IN_HV_CHG 0x10 234*4882a593Smuzhiyun #define MASK_I_DC_CHG 0x08 235*4882a593Smuzhiyun #define MASK_I_PXCLK_CHG 0x04 236*4882a593Smuzhiyun #define MASK_I_PHYCLK_CHG 0x02 237*4882a593Smuzhiyun #define MASK_I_TMDSCLK_CHG 0x01 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #define CBIT_INT 0x8505 240*4882a593Smuzhiyun #define MASK_I_AF_LOCK 0x80 241*4882a593Smuzhiyun #define MASK_I_AF_UNLOCK 0x40 242*4882a593Smuzhiyun #define MASK_I_CBIT_FS 0x02 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun #define AUDIO_INT 0x8506 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #define ERR_INT 0x8507 247*4882a593Smuzhiyun #define MASK_I_EESS_ERR 0x80 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define HDCP_INT 0x8508 250*4882a593Smuzhiyun #define MASK_I_AVM_SET 0x80 251*4882a593Smuzhiyun #define MASK_I_AVM_CLR 0x40 252*4882a593Smuzhiyun #define MASK_I_LINKERR 0x20 253*4882a593Smuzhiyun #define MASK_I_SHA_END 0x10 254*4882a593Smuzhiyun #define MASK_I_R0_END 0x08 255*4882a593Smuzhiyun #define MASK_I_KM_END 0x04 256*4882a593Smuzhiyun #define MASK_I_AKSV_END 0x02 257*4882a593Smuzhiyun #define MASK_I_AN_END 0x01 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun #define MISC_INT 0x850B 260*4882a593Smuzhiyun #define MASK_I_AS_LAYOUT 0x10 261*4882a593Smuzhiyun #define MASK_I_NO_SPD 0x08 262*4882a593Smuzhiyun #define MASK_I_NO_VS 0x03 263*4882a593Smuzhiyun #define MASK_I_SYNC_CHG 0x02 264*4882a593Smuzhiyun #define MASK_I_AUDIO_MUTE 0x01 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #define KEY_INT 0x850F 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #define SYS_INTM 0x8512 269*4882a593Smuzhiyun #define MASK_M_ACR_CTS 0x80 270*4882a593Smuzhiyun #define MASK_M_ACR_N 0x40 271*4882a593Smuzhiyun #define MASK_M_DVI_DET 0x20 272*4882a593Smuzhiyun #define MASK_M_HDMI_DET 0x10 273*4882a593Smuzhiyun #define MASK_M_NOPMBDET 0x08 274*4882a593Smuzhiyun #define MASK_M_BPMBDET 0x04 275*4882a593Smuzhiyun #define MASK_M_TMDS 0x02 276*4882a593Smuzhiyun #define MASK_M_DDC 0x01 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun #define CLK_INTM 0x8513 279*4882a593Smuzhiyun #define MASK_M_OUT_H_CHG 0x40 280*4882a593Smuzhiyun #define MASK_M_IN_DE_CHG 0x20 281*4882a593Smuzhiyun #define MASK_M_IN_HV_CHG 0x10 282*4882a593Smuzhiyun #define MASK_M_DC_CHG 0x08 283*4882a593Smuzhiyun #define MASK_M_PXCLK_CHG 0x04 284*4882a593Smuzhiyun #define MASK_M_PHYCLK_CHG 0x02 285*4882a593Smuzhiyun #define MASK_M_TMDS_CHG 0x01 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #define PACKET_INTM 0x8514 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #define CBIT_INTM 0x8515 290*4882a593Smuzhiyun #define MASK_M_AF_LOCK 0x80 291*4882a593Smuzhiyun #define MASK_M_AF_UNLOCK 0x40 292*4882a593Smuzhiyun #define MASK_M_CBIT_FS 0x02 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #define AUDIO_INTM 0x8516 295*4882a593Smuzhiyun #define MASK_M_BUFINIT_END 0x01 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #define ERR_INTM 0x8517 298*4882a593Smuzhiyun #define MASK_M_EESS_ERR 0x80 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun #define HDCP_INTM 0x8518 301*4882a593Smuzhiyun #define MASK_M_AVM_SET 0x80 302*4882a593Smuzhiyun #define MASK_M_AVM_CLR 0x40 303*4882a593Smuzhiyun #define MASK_M_LINKERR 0x20 304*4882a593Smuzhiyun #define MASK_M_SHA_END 0x10 305*4882a593Smuzhiyun #define MASK_M_R0_END 0x08 306*4882a593Smuzhiyun #define MASK_M_KM_END 0x04 307*4882a593Smuzhiyun #define MASK_M_AKSV_END 0x02 308*4882a593Smuzhiyun #define MASK_M_AN_END 0x01 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun #define MISC_INTM 0x851B 311*4882a593Smuzhiyun #define MASK_M_AS_LAYOUT 0x10 312*4882a593Smuzhiyun #define MASK_M_NO_SPD 0x08 313*4882a593Smuzhiyun #define MASK_M_NO_VS 0x03 314*4882a593Smuzhiyun #define MASK_M_SYNC_CHG 0x02 315*4882a593Smuzhiyun #define MASK_M_AUDIO_MUTE 0x01 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun #define KEY_INTM 0x851F 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #define SYS_STATUS 0x8520 320*4882a593Smuzhiyun #define MASK_S_SYNC 0x80 321*4882a593Smuzhiyun #define MASK_S_AVMUTE 0x40 322*4882a593Smuzhiyun #define MASK_S_HDCP 0x20 323*4882a593Smuzhiyun #define MASK_S_HDMI 0x10 324*4882a593Smuzhiyun #define MASK_S_PHY_SCDT 0x08 325*4882a593Smuzhiyun #define MASK_S_PHY_PLL 0x04 326*4882a593Smuzhiyun #define MASK_S_TMDS 0x02 327*4882a593Smuzhiyun #define MASK_S_DDC5V 0x01 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun #define CSI_STATUS 0x0410 330*4882a593Smuzhiyun #define MASK_S_WSYNC 0x0400 331*4882a593Smuzhiyun #define MASK_S_TXACT 0x0200 332*4882a593Smuzhiyun #define MASK_S_RXACT 0x0100 333*4882a593Smuzhiyun #define MASK_S_HLT 0x0001 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun #define VI_STATUS1 0x8522 336*4882a593Smuzhiyun #define MASK_S_V_GBD 0x08 337*4882a593Smuzhiyun #define MASK_S_DEEPCOLOR 0x0c 338*4882a593Smuzhiyun #define MASK_S_V_422 0x02 339*4882a593Smuzhiyun #define MASK_S_V_INTERLACE 0x01 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #define AU_STATUS0 0x8523 342*4882a593Smuzhiyun #define MASK_S_A_SAMPLE 0x01 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define VI_STATUS3 0x8528 345*4882a593Smuzhiyun #define MASK_S_V_COLOR 0x1e 346*4882a593Smuzhiyun #define MASK_LIMITED 0x01 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun #define PHY_CTL0 0x8531 349*4882a593Smuzhiyun #define MASK_PHY_SYSCLK_IND 0x02 350*4882a593Smuzhiyun #define MASK_PHY_CTL 0x01 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun 353*4882a593Smuzhiyun #define PHY_CTL1 0x8532 /* Not in REF_01 */ 354*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST1 0xf0 355*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST1_OFF 0x00 356*4882a593Smuzhiyun #define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \ 357*4882a593Smuzhiyun MASK_PHY_AUTO_RST1) 358*4882a593Smuzhiyun #define MASK_FREQ_RANGE_MODE 0x0f 359*4882a593Smuzhiyun #define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \ 360*4882a593Smuzhiyun MASK_FREQ_RANGE_MODE) 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun #define PHY_CTL2 0x8533 /* Not in REF_01 */ 363*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST4 0x04 364*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST3 0x02 365*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST2 0x01 366*4882a593Smuzhiyun #define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \ 367*4882a593Smuzhiyun MASK_PHY_AUTO_RST3 | \ 368*4882a593Smuzhiyun MASK_PHY_AUTO_RST2) 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun #define PHY_EN 0x8534 371*4882a593Smuzhiyun #define MASK_ENABLE_PHY 0x01 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun #define PHY_RST 0x8535 374*4882a593Smuzhiyun #define MASK_RESET_CTRL 0x01 /* Reset active low */ 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun #define PHY_BIAS 0x8536 /* Not in REF_01 */ 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun #define PHY_CSQ 0x853F /* Not in REF_01 */ 379*4882a593Smuzhiyun #define MASK_CSQ_CNT 0x0f 380*4882a593Smuzhiyun #define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT) 381*4882a593Smuzhiyun 382*4882a593Smuzhiyun #define SYS_FREQ0 0x8540 383*4882a593Smuzhiyun #define SYS_FREQ1 0x8541 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun #define SYS_CLK 0x8542 /* Not in REF_01 */ 386*4882a593Smuzhiyun #define MASK_CLK_DIFF 0x0C 387*4882a593Smuzhiyun #define MASK_CLK_DIV 0x03 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun #define DDC_CTL 0x8543 390*4882a593Smuzhiyun #define MASK_DDC_ACK_POL 0x08 391*4882a593Smuzhiyun #define MASK_DDC_ACTION 0x04 392*4882a593Smuzhiyun #define MASK_DDC5V_MODE 0x03 393*4882a593Smuzhiyun #define MASK_DDC5V_MODE_0MS 0x00 394*4882a593Smuzhiyun #define MASK_DDC5V_MODE_50MS 0x01 395*4882a593Smuzhiyun #define MASK_DDC5V_MODE_100MS 0x02 396*4882a593Smuzhiyun #define MASK_DDC5V_MODE_200MS 0x03 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun #define HPD_CTL 0x8544 399*4882a593Smuzhiyun #define MASK_HPD_CTL0 0x10 400*4882a593Smuzhiyun #define MASK_HPD_OUT0 0x01 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun #define ANA_CTL 0x8545 403*4882a593Smuzhiyun #define MASK_APPL_PCSX 0x30 404*4882a593Smuzhiyun #define MASK_APPL_PCSX_HIZ 0x00 405*4882a593Smuzhiyun #define MASK_APPL_PCSX_L_FIX 0x10 406*4882a593Smuzhiyun #define MASK_APPL_PCSX_H_FIX 0x20 407*4882a593Smuzhiyun #define MASK_APPL_PCSX_NORMAL 0x30 408*4882a593Smuzhiyun #define MASK_ANALOG_ON 0x01 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun #define AVM_CTL 0x8546 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #define INIT_END 0x854A 413*4882a593Smuzhiyun #define MASK_INIT_END 0x01 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define HDMI_DET 0x8552 /* Not in REF_01 */ 416*4882a593Smuzhiyun #define MASK_HDMI_DET_MOD1 0x80 417*4882a593Smuzhiyun #define MASK_HDMI_DET_MOD0 0x40 418*4882a593Smuzhiyun #define MASK_HDMI_DET_V 0x30 419*4882a593Smuzhiyun #define MASK_HDMI_DET_V_SYNC 0x00 420*4882a593Smuzhiyun #define MASK_HDMI_DET_V_ASYNC_25MS 0x10 421*4882a593Smuzhiyun #define MASK_HDMI_DET_V_ASYNC_50MS 0x20 422*4882a593Smuzhiyun #define MASK_HDMI_DET_V_ASYNC_100MS 0x30 423*4882a593Smuzhiyun #define MASK_HDMI_DET_NUM 0x0f 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun #define HDCP_MODE 0x8560 426*4882a593Smuzhiyun #define MASK_MODE_RST_TN 0x20 427*4882a593Smuzhiyun #define MASK_LINE_REKEY 0x10 428*4882a593Smuzhiyun #define MASK_AUTO_CLR 0x04 429*4882a593Smuzhiyun #define MASK_MANUAL_AUTHENTICATION 0x02 /* Not in REF_01 */ 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun #define HDCP_REG1 0x8563 /* Not in REF_01 */ 432*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL 0x70 433*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70 434*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60 435*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50 436*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40 437*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30 438*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20 439*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10 440*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_ONCE 0x00 441*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH 0x01 442*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_AUTO 0x01 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun #define HDCP_REG2 0x8564 /* Not in REF_01 */ 445*4882a593Smuzhiyun #define MASK_AUTO_P3_RESET 0x0F 446*4882a593Smuzhiyun #define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET) 447*4882a593Smuzhiyun #define MASK_AUTO_P3_RESET_OFF 0x00 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun #define VI_MODE 0x8570 450*4882a593Smuzhiyun #define MASK_RGB_DVI 0x08 /* Not in REF_01 */ 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun #define VOUT_SET2 0x8573 453*4882a593Smuzhiyun #define MASK_SEL422 0x80 454*4882a593Smuzhiyun #define MASK_VOUT_422FIL_100 0x40 455*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE 0x03 456*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE_THROUGH 0x00 457*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE_AUTO 0x01 458*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE_MANUAL 0x03 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun #define VOUT_SET3 0x8574 461*4882a593Smuzhiyun #define MASK_VOUT_EXTCNT 0x08 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun #define VI_REP 0x8576 464*4882a593Smuzhiyun #define MASK_VOUT_COLOR_SEL 0xe0 465*4882a593Smuzhiyun #define MASK_VOUT_COLOR_RGB_FULL 0x00 466*4882a593Smuzhiyun #define MASK_VOUT_COLOR_RGB_LIMITED 0x20 467*4882a593Smuzhiyun #define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40 468*4882a593Smuzhiyun #define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60 469*4882a593Smuzhiyun #define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80 470*4882a593Smuzhiyun #define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0 471*4882a593Smuzhiyun #define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0 472*4882a593Smuzhiyun #define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0 473*4882a593Smuzhiyun #define MASK_IN_REP_HEN 0x10 474*4882a593Smuzhiyun #define MASK_IN_REP 0x0f 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun #define VI_MUTE 0x857F 477*4882a593Smuzhiyun #define MASK_AUTO_MUTE 0xc0 478*4882a593Smuzhiyun #define MASK_VI_MUTE 0x10 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun #define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */ 481*4882a593Smuzhiyun #define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */ 482*4882a593Smuzhiyun #define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */ 483*4882a593Smuzhiyun #define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */ 484*4882a593Smuzhiyun #define H_SIZE_LO 0x858A /* Not in REF_01 */ 485*4882a593Smuzhiyun #define H_SIZE_HI 0x858B /* Not in REF_01 */ 486*4882a593Smuzhiyun #define V_SIZE_LO 0x858C /* Not in REF_01 */ 487*4882a593Smuzhiyun #define V_SIZE_HI 0x858D /* Not in REF_01 */ 488*4882a593Smuzhiyun #define FV_CNT_LO 0x85A1 /* Not in REF_01 */ 489*4882a593Smuzhiyun #define FV_CNT_HI 0x85A2 /* Not in REF_01 */ 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun #define FH_MIN0 0x85AA /* Not in REF_01 */ 492*4882a593Smuzhiyun #define FH_MIN1 0x85AB /* Not in REF_01 */ 493*4882a593Smuzhiyun #define FH_MAX0 0x85AC /* Not in REF_01 */ 494*4882a593Smuzhiyun #define FH_MAX1 0x85AD /* Not in REF_01 */ 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun #define HV_RST 0x85AF /* Not in REF_01 */ 497*4882a593Smuzhiyun #define MASK_H_PI_RST 0x20 498*4882a593Smuzhiyun #define MASK_V_PI_RST 0x10 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun #define EDID_MODE 0x85C7 501*4882a593Smuzhiyun #define MASK_EDID_SPEED 0x40 502*4882a593Smuzhiyun #define MASK_EDID_MODE 0x03 503*4882a593Smuzhiyun #define MASK_EDID_MODE_DISABLE 0x00 504*4882a593Smuzhiyun #define MASK_EDID_MODE_DDC2B 0x01 505*4882a593Smuzhiyun #define MASK_EDID_MODE_E_DDC 0x02 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun #define EDID_LEN1 0x85CA 508*4882a593Smuzhiyun #define EDID_LEN2 0x85CB 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun #define HDCP_REG3 0x85D1 /* Not in REF_01 */ 511*4882a593Smuzhiyun #define KEY_RD_CMD 0x01 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun #define FORCE_MUTE 0x8600 514*4882a593Smuzhiyun #define MASK_FORCE_AMUTE 0x10 515*4882a593Smuzhiyun #define MASK_FORCE_DMUTE 0x01 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun #define CMD_AUD 0x8601 518*4882a593Smuzhiyun #define MASK_CMD_BUFINIT 0x04 519*4882a593Smuzhiyun #define MASK_CMD_LOCKDET 0x02 520*4882a593Smuzhiyun #define MASK_CMD_MUTE 0x01 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun #define AUTO_CMD0 0x8602 523*4882a593Smuzhiyun #define MASK_AUTO_MUTE7 0x80 524*4882a593Smuzhiyun #define MASK_AUTO_MUTE6 0x40 525*4882a593Smuzhiyun #define MASK_AUTO_MUTE5 0x20 526*4882a593Smuzhiyun #define MASK_AUTO_MUTE4 0x10 527*4882a593Smuzhiyun #define MASK_AUTO_MUTE3 0x08 528*4882a593Smuzhiyun #define MASK_AUTO_MUTE2 0x04 529*4882a593Smuzhiyun #define MASK_AUTO_MUTE1 0x02 530*4882a593Smuzhiyun #define MASK_AUTO_MUTE0 0x01 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun #define AUTO_CMD1 0x8603 533*4882a593Smuzhiyun #define MASK_AUTO_MUTE10 0x04 534*4882a593Smuzhiyun #define MASK_AUTO_MUTE9 0x02 535*4882a593Smuzhiyun #define MASK_AUTO_MUTE8 0x01 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun #define AUTO_CMD2 0x8604 538*4882a593Smuzhiyun #define MASK_AUTO_PLAY3 0x08 539*4882a593Smuzhiyun #define MASK_AUTO_PLAY2 0x04 540*4882a593Smuzhiyun 541*4882a593Smuzhiyun #define BUFINIT_START 0x8606 542*4882a593Smuzhiyun #define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100) 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun #define FS_MUTE 0x8607 545*4882a593Smuzhiyun #define MASK_FS_ELSE_MUTE 0x80 546*4882a593Smuzhiyun #define MASK_FS22_MUTE 0x40 547*4882a593Smuzhiyun #define MASK_FS24_MUTE 0x20 548*4882a593Smuzhiyun #define MASK_FS88_MUTE 0x10 549*4882a593Smuzhiyun #define MASK_FS96_MUTE 0x08 550*4882a593Smuzhiyun #define MASK_FS176_MUTE 0x04 551*4882a593Smuzhiyun #define MASK_FS192_MUTE 0x02 552*4882a593Smuzhiyun #define MASK_FS_NO_MUTE 0x01 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun #define FS_IMODE 0x8620 555*4882a593Smuzhiyun #define MASK_NLPCM_HMODE 0x40 556*4882a593Smuzhiyun #define MASK_NLPCM_SMODE 0x20 557*4882a593Smuzhiyun #define MASK_NLPCM_IMODE 0x10 558*4882a593Smuzhiyun #define MASK_FS_HMODE 0x08 559*4882a593Smuzhiyun #define MASK_FS_AMODE 0x04 560*4882a593Smuzhiyun #define MASK_FS_SMODE 0x02 561*4882a593Smuzhiyun #define MASK_FS_IMODE 0x01 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun #define FS_SET 0x8621 564*4882a593Smuzhiyun #define MASK_FS 0x0f 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun #define LOCKDET_REF0 0x8630 567*4882a593Smuzhiyun #define LOCKDET_REF1 0x8631 568*4882a593Smuzhiyun #define LOCKDET_REF2 0x8632 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun #define ACR_MODE 0x8640 571*4882a593Smuzhiyun #define MASK_ACR_LOAD 0x10 572*4882a593Smuzhiyun #define MASK_N_MODE 0x04 573*4882a593Smuzhiyun #define MASK_CTS_MODE 0x01 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun #define ACR_MDF0 0x8641 576*4882a593Smuzhiyun #define MASK_ACR_L2MDF 0x70 577*4882a593Smuzhiyun #define MASK_ACR_L2MDF_0_PPM 0x00 578*4882a593Smuzhiyun #define MASK_ACR_L2MDF_61_PPM 0x10 579*4882a593Smuzhiyun #define MASK_ACR_L2MDF_122_PPM 0x20 580*4882a593Smuzhiyun #define MASK_ACR_L2MDF_244_PPM 0x30 581*4882a593Smuzhiyun #define MASK_ACR_L2MDF_488_PPM 0x40 582*4882a593Smuzhiyun #define MASK_ACR_L2MDF_976_PPM 0x50 583*4882a593Smuzhiyun #define MASK_ACR_L2MDF_1976_PPM 0x60 584*4882a593Smuzhiyun #define MASK_ACR_L2MDF_3906_PPM 0x70 585*4882a593Smuzhiyun #define MASK_ACR_L1MDF 0x07 586*4882a593Smuzhiyun #define MASK_ACR_L1MDF_0_PPM 0x00 587*4882a593Smuzhiyun #define MASK_ACR_L1MDF_61_PPM 0x01 588*4882a593Smuzhiyun #define MASK_ACR_L1MDF_122_PPM 0x02 589*4882a593Smuzhiyun #define MASK_ACR_L1MDF_244_PPM 0x03 590*4882a593Smuzhiyun #define MASK_ACR_L1MDF_488_PPM 0x04 591*4882a593Smuzhiyun #define MASK_ACR_L1MDF_976_PPM 0x05 592*4882a593Smuzhiyun #define MASK_ACR_L1MDF_1976_PPM 0x06 593*4882a593Smuzhiyun #define MASK_ACR_L1MDF_3906_PPM 0x07 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun #define ACR_MDF1 0x8642 596*4882a593Smuzhiyun #define MASK_ACR_L3MDF 0x07 597*4882a593Smuzhiyun #define MASK_ACR_L3MDF_0_PPM 0x00 598*4882a593Smuzhiyun #define MASK_ACR_L3MDF_61_PPM 0x01 599*4882a593Smuzhiyun #define MASK_ACR_L3MDF_122_PPM 0x02 600*4882a593Smuzhiyun #define MASK_ACR_L3MDF_244_PPM 0x03 601*4882a593Smuzhiyun #define MASK_ACR_L3MDF_488_PPM 0x04 602*4882a593Smuzhiyun #define MASK_ACR_L3MDF_976_PPM 0x05 603*4882a593Smuzhiyun #define MASK_ACR_L3MDF_1976_PPM 0x06 604*4882a593Smuzhiyun #define MASK_ACR_L3MDF_3906_PPM 0x07 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun #define SDO_MODE1 0x8652 607*4882a593Smuzhiyun #define MASK_SDO_BIT_LENG 0x70 608*4882a593Smuzhiyun #define MASK_SDO_FMT 0x03 609*4882a593Smuzhiyun #define MASK_SDO_FMT_RIGHT 0x00 610*4882a593Smuzhiyun #define MASK_SDO_FMT_LEFT 0x01 611*4882a593Smuzhiyun #define MASK_SDO_FMT_I2S 0x02 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun #define DIV_MODE 0x8665 /* Not in REF_01 */ 614*4882a593Smuzhiyun #define MASK_DIV_DLY 0xf0 615*4882a593Smuzhiyun #define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \ 616*4882a593Smuzhiyun MASK_DIV_DLY) 617*4882a593Smuzhiyun #define MASK_DIV_MODE 0x01 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun #define NCO_F0_MOD 0x8670 620*4882a593Smuzhiyun #define MASK_NCO_F0_MOD 0x03 621*4882a593Smuzhiyun #define MASK_NCO_F0_MOD_42MHZ 0x00 622*4882a593Smuzhiyun #define MASK_NCO_F0_MOD_27MHZ 0x01 623*4882a593Smuzhiyun 624*4882a593Smuzhiyun #define PK_INT_MODE 0x8709 625*4882a593Smuzhiyun #define MASK_ISRC2_INT_MODE 0x80 626*4882a593Smuzhiyun #define MASK_ISRC_INT_MODE 0x40 627*4882a593Smuzhiyun #define MASK_ACP_INT_MODE 0x20 628*4882a593Smuzhiyun #define MASK_VS_INT_MODE 0x10 629*4882a593Smuzhiyun #define MASK_SPD_INT_MODE 0x08 630*4882a593Smuzhiyun #define MASK_MS_INT_MODE 0x04 631*4882a593Smuzhiyun #define MASK_AUD_INT_MODE 0x02 632*4882a593Smuzhiyun #define MASK_AVI_INT_MODE 0x01 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun #define NO_PKT_LIMIT 0x870B 635*4882a593Smuzhiyun #define MASK_NO_ACP_LIMIT 0xf0 636*4882a593Smuzhiyun #define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \ 637*4882a593Smuzhiyun MASK_NO_ACP_LIMIT) 638*4882a593Smuzhiyun #define MASK_NO_AVI_LIMIT 0x0f 639*4882a593Smuzhiyun #define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \ 640*4882a593Smuzhiyun MASK_NO_AVI_LIMIT) 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun #define NO_PKT_CLR 0x870C 643*4882a593Smuzhiyun #define MASK_NO_VS_CLR 0x40 644*4882a593Smuzhiyun #define MASK_NO_SPD_CLR 0x20 645*4882a593Smuzhiyun #define MASK_NO_ACP_CLR 0x10 646*4882a593Smuzhiyun #define MASK_NO_AVI_CLR1 0x02 647*4882a593Smuzhiyun #define MASK_NO_AVI_CLR0 0x01 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun #define ERR_PK_LIMIT 0x870D 650*4882a593Smuzhiyun #define NO_PKT_LIMIT2 0x870E 651*4882a593Smuzhiyun #define PK_AVI_0HEAD 0x8710 652*4882a593Smuzhiyun #define PK_AVI_1HEAD 0x8711 653*4882a593Smuzhiyun #define PK_AVI_2HEAD 0x8712 654*4882a593Smuzhiyun #define PK_AVI_0BYTE 0x8713 655*4882a593Smuzhiyun #define PK_AVI_1BYTE 0x8714 656*4882a593Smuzhiyun #define PK_AVI_2BYTE 0x8715 657*4882a593Smuzhiyun #define PK_AVI_3BYTE 0x8716 658*4882a593Smuzhiyun #define PK_AVI_4BYTE 0x8717 659*4882a593Smuzhiyun #define PK_AVI_5BYTE 0x8718 660*4882a593Smuzhiyun #define PK_AVI_6BYTE 0x8719 661*4882a593Smuzhiyun #define PK_AVI_7BYTE 0x871A 662*4882a593Smuzhiyun #define PK_AVI_8BYTE 0x871B 663*4882a593Smuzhiyun #define PK_AVI_9BYTE 0x871C 664*4882a593Smuzhiyun #define PK_AVI_10BYTE 0x871D 665*4882a593Smuzhiyun #define PK_AVI_11BYTE 0x871E 666*4882a593Smuzhiyun #define PK_AVI_12BYTE 0x871F 667*4882a593Smuzhiyun #define PK_AVI_13BYTE 0x8720 668*4882a593Smuzhiyun #define PK_AVI_14BYTE 0x8721 669*4882a593Smuzhiyun #define PK_AVI_15BYTE 0x8722 670*4882a593Smuzhiyun #define PK_AVI_16BYTE 0x8723 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun #define BKSV 0x8800 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun #define BCAPS 0x8840 675*4882a593Smuzhiyun #define MASK_HDMI_RSVD 0x80 676*4882a593Smuzhiyun #define MASK_REPEATER 0x40 677*4882a593Smuzhiyun #define MASK_READY 0x20 678*4882a593Smuzhiyun #define MASK_FASTI2C 0x10 679*4882a593Smuzhiyun #define MASK_1_1_FEA 0x02 680*4882a593Smuzhiyun #define MASK_FAST_REAU 0x01 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun #define BSTATUS1 0x8842 683*4882a593Smuzhiyun #define MASK_MAX_EXCED 0x08 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun #define EDID_RAM 0x8C00 686*4882a593Smuzhiyun #define EDID_EXT_RAM 0x8c80 687*4882a593Smuzhiyun #define NO_GDB_LIMIT 0x9007 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun #endif 690