1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * tc358743 - Toshiba HDMI to CSI-2 bridge - register names and bit masks 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights 6*4882a593Smuzhiyun * reserved. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * References (c = chapter, p = page): 11*4882a593Smuzhiyun * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Bit masks has prefix 'MASK_' and options after '_'. */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #ifndef __TC358743_REGS_H 17*4882a593Smuzhiyun #define __TC358743_REGS_H 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CHIPID 0x0000 20*4882a593Smuzhiyun #define MASK_CHIPID 0xff00 21*4882a593Smuzhiyun #define MASK_REVID 0x00ff 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define SYSCTL 0x0002 24*4882a593Smuzhiyun #define MASK_IRRST 0x0800 25*4882a593Smuzhiyun #define MASK_CECRST 0x0400 26*4882a593Smuzhiyun #define MASK_CTXRST 0x0200 27*4882a593Smuzhiyun #define MASK_HDMIRST 0x0100 28*4882a593Smuzhiyun #define MASK_SLEEP 0x0001 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define CONFCTL 0x0004 31*4882a593Smuzhiyun #define MASK_PWRISO 0x8000 32*4882a593Smuzhiyun #define MASK_ACLKOPT 0x1000 33*4882a593Smuzhiyun #define MASK_AUDCHNUM 0x0c00 34*4882a593Smuzhiyun #define MASK_AUDCHNUM_8 0x0000 35*4882a593Smuzhiyun #define MASK_AUDCHNUM_6 0x0400 36*4882a593Smuzhiyun #define MASK_AUDCHNUM_4 0x0800 37*4882a593Smuzhiyun #define MASK_AUDCHNUM_2 0x0c00 38*4882a593Smuzhiyun #define MASK_AUDCHSEL 0x0200 39*4882a593Smuzhiyun #define MASK_I2SDLYOPT 0x0100 40*4882a593Smuzhiyun #define MASK_YCBCRFMT 0x00c0 41*4882a593Smuzhiyun #define MASK_YCBCRFMT_444 0x0000 42*4882a593Smuzhiyun #define MASK_YCBCRFMT_422_12_BIT 0x0040 43*4882a593Smuzhiyun #define MASK_YCBCRFMT_COLORBAR 0x0080 44*4882a593Smuzhiyun #define MASK_YCBCRFMT_422_8_BIT 0x00c0 45*4882a593Smuzhiyun #define MASK_INFRMEN 0x0020 46*4882a593Smuzhiyun #define MASK_AUDOUTSEL 0x0018 47*4882a593Smuzhiyun #define MASK_AUDOUTSEL_CSI 0x0000 48*4882a593Smuzhiyun #define MASK_AUDOUTSEL_I2S 0x0010 49*4882a593Smuzhiyun #define MASK_AUDOUTSEL_TDM 0x0018 50*4882a593Smuzhiyun #define MASK_AUTOINDEX 0x0004 51*4882a593Smuzhiyun #define MASK_ABUFEN 0x0002 52*4882a593Smuzhiyun #define MASK_VBUFEN 0x0001 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define FIFOCTL 0x0006 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define INTSTATUS 0x0014 57*4882a593Smuzhiyun #define MASK_AMUTE_INT 0x0400 58*4882a593Smuzhiyun #define MASK_HDMI_INT 0x0200 59*4882a593Smuzhiyun #define MASK_CSI_INT 0x0100 60*4882a593Smuzhiyun #define MASK_SYS_INT 0x0020 61*4882a593Smuzhiyun #define MASK_CEC_EINT 0x0010 62*4882a593Smuzhiyun #define MASK_CEC_TINT 0x0008 63*4882a593Smuzhiyun #define MASK_CEC_RINT 0x0004 64*4882a593Smuzhiyun #define MASK_IR_EINT 0x0002 65*4882a593Smuzhiyun #define MASK_IR_DINT 0x0001 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define INTMASK 0x0016 68*4882a593Smuzhiyun #define MASK_AMUTE_MSK 0x0400 69*4882a593Smuzhiyun #define MASK_HDMI_MSK 0x0200 70*4882a593Smuzhiyun #define MASK_CSI_MSK 0x0100 71*4882a593Smuzhiyun #define MASK_SYS_MSK 0x0020 72*4882a593Smuzhiyun #define MASK_CEC_EMSK 0x0010 73*4882a593Smuzhiyun #define MASK_CEC_TMSK 0x0008 74*4882a593Smuzhiyun #define MASK_CEC_RMSK 0x0004 75*4882a593Smuzhiyun #define MASK_IR_EMSK 0x0002 76*4882a593Smuzhiyun #define MASK_IR_DMSK 0x0001 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define INTFLAG 0x0018 79*4882a593Smuzhiyun #define INTSYSSTATUS 0x001A 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define PLLCTL0 0x0020 82*4882a593Smuzhiyun #define MASK_PLL_PRD 0xf000 83*4882a593Smuzhiyun #define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\ 84*4882a593Smuzhiyun MASK_PLL_PRD) 85*4882a593Smuzhiyun #define MASK_PLL_FBD 0x01ff 86*4882a593Smuzhiyun #define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define PLLCTL1 0x0022 89*4882a593Smuzhiyun #define MASK_PLL_FRS 0x0c00 90*4882a593Smuzhiyun #define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_FRS) 91*4882a593Smuzhiyun #define MASK_PLL_LBWS 0x0300 92*4882a593Smuzhiyun #define MASK_LFBREN 0x0040 93*4882a593Smuzhiyun #define MASK_BYPCKEN 0x0020 94*4882a593Smuzhiyun #define MASK_CKEN 0x0010 95*4882a593Smuzhiyun #define MASK_RESETB 0x0002 96*4882a593Smuzhiyun #define MASK_PLL_EN 0x0001 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun #define CLW_CNTRL 0x0140 99*4882a593Smuzhiyun #define MASK_CLW_LANEDISABLE 0x0001 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define D0W_CNTRL 0x0144 102*4882a593Smuzhiyun #define MASK_D0W_LANEDISABLE 0x0001 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define D1W_CNTRL 0x0148 105*4882a593Smuzhiyun #define MASK_D1W_LANEDISABLE 0x0001 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define D2W_CNTRL 0x014C 108*4882a593Smuzhiyun #define MASK_D2W_LANEDISABLE 0x0001 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define D3W_CNTRL 0x0150 111*4882a593Smuzhiyun #define MASK_D3W_LANEDISABLE 0x0001 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define STARTCNTRL 0x0204 114*4882a593Smuzhiyun #define MASK_START 0x00000001 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define LINEINITCNT 0x0210 117*4882a593Smuzhiyun #define LPTXTIMECNT 0x0214 118*4882a593Smuzhiyun #define TCLK_HEADERCNT 0x0218 119*4882a593Smuzhiyun #define TCLK_TRAILCNT 0x021C 120*4882a593Smuzhiyun #define THS_HEADERCNT 0x0220 121*4882a593Smuzhiyun #define TWAKEUP 0x0224 122*4882a593Smuzhiyun #define TCLK_POSTCNT 0x0228 123*4882a593Smuzhiyun #define THS_TRAILCNT 0x022C 124*4882a593Smuzhiyun #define HSTXVREGCNT 0x0230 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define HSTXVREGEN 0x0234 127*4882a593Smuzhiyun #define MASK_D3M_HSTXVREGEN 0x0010 128*4882a593Smuzhiyun #define MASK_D2M_HSTXVREGEN 0x0008 129*4882a593Smuzhiyun #define MASK_D1M_HSTXVREGEN 0x0004 130*4882a593Smuzhiyun #define MASK_D0M_HSTXVREGEN 0x0002 131*4882a593Smuzhiyun #define MASK_CLM_HSTXVREGEN 0x0001 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define TXOPTIONCNTRL 0x0238 135*4882a593Smuzhiyun #define MASK_CONTCLKMODE 0x00000001 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define CSI_CONTROL 0x040C 138*4882a593Smuzhiyun #define MASK_CSI_MODE 0x8000 139*4882a593Smuzhiyun #define MASK_HTXTOEN 0x0400 140*4882a593Smuzhiyun #define MASK_TXHSMD 0x0080 141*4882a593Smuzhiyun #define MASK_HSCKMD 0x0020 142*4882a593Smuzhiyun #define MASK_NOL 0x0006 143*4882a593Smuzhiyun #define MASK_NOL_1 0x0000 144*4882a593Smuzhiyun #define MASK_NOL_2 0x0002 145*4882a593Smuzhiyun #define MASK_NOL_3 0x0004 146*4882a593Smuzhiyun #define MASK_NOL_4 0x0006 147*4882a593Smuzhiyun #define MASK_EOTDIS 0x0001 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define CSI_INT 0x0414 150*4882a593Smuzhiyun #define MASK_INTHLT 0x00000008 151*4882a593Smuzhiyun #define MASK_INTER 0x00000004 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun #define CSI_INT_ENA 0x0418 154*4882a593Smuzhiyun #define MASK_IENHLT 0x00000008 155*4882a593Smuzhiyun #define MASK_IENER 0x00000004 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define CSI_ERR 0x044C 158*4882a593Smuzhiyun #define MASK_INER 0x00000200 159*4882a593Smuzhiyun #define MASK_WCER 0x00000100 160*4882a593Smuzhiyun #define MASK_QUNK 0x00000010 161*4882a593Smuzhiyun #define MASK_TXBRK 0x00000002 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define CSI_ERR_INTENA 0x0450 164*4882a593Smuzhiyun #define CSI_ERR_HALT 0x0454 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun #define CSI_CONFW 0x0500 167*4882a593Smuzhiyun #define MASK_MODE 0xe0000000 168*4882a593Smuzhiyun #define MASK_MODE_SET 0xa0000000 169*4882a593Smuzhiyun #define MASK_MODE_CLEAR 0xc0000000 170*4882a593Smuzhiyun #define MASK_ADDRESS 0x1f000000 171*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_CONTROL 0x03000000 172*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_INT_ENA 0x06000000 173*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000 174*4882a593Smuzhiyun #define MASK_ADDRESS_CSI_ERR_HALT 0x15000000 175*4882a593Smuzhiyun #define MASK_DATA 0x0000ffff 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define CSI_INT_CLR 0x050C 178*4882a593Smuzhiyun #define MASK_ICRER 0x00000004 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #define CSI_START 0x0518 181*4882a593Smuzhiyun #define MASK_STRT 0x00000001 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* *** CEC (32 bit) *** */ 184*4882a593Smuzhiyun #define CECHCLK 0x0028 /* 16 bits */ 185*4882a593Smuzhiyun #define MASK_CECHCLK (0x7ff << 0) 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define CECLCLK 0x002a /* 16 bits */ 188*4882a593Smuzhiyun #define MASK_CECLCLK (0x7ff << 0) 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define CECEN 0x0600 191*4882a593Smuzhiyun #define MASK_CECEN 0x0001 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define CECADD 0x0604 194*4882a593Smuzhiyun #define CECRST 0x0608 195*4882a593Smuzhiyun #define MASK_CECRESET 0x0001 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define CECREN 0x060c 198*4882a593Smuzhiyun #define MASK_CECREN 0x0001 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun #define CECRCTL1 0x0614 201*4882a593Smuzhiyun #define MASK_CECACKDIS (1 << 24) 202*4882a593Smuzhiyun #define MASK_CECHNC (3 << 20) 203*4882a593Smuzhiyun #define MASK_CECLNC (7 << 16) 204*4882a593Smuzhiyun #define MASK_CECMIN (7 << 12) 205*4882a593Smuzhiyun #define MASK_CECMAX (7 << 8) 206*4882a593Smuzhiyun #define MASK_CECDAT (7 << 4) 207*4882a593Smuzhiyun #define MASK_CECTOUT (3 << 2) 208*4882a593Smuzhiyun #define MASK_CECRIHLD (1 << 1) 209*4882a593Smuzhiyun #define MASK_CECOTH (1 << 0) 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #define CECRCTL2 0x0618 212*4882a593Smuzhiyun #define MASK_CECSWAV3 (7 << 12) 213*4882a593Smuzhiyun #define MASK_CECSWAV2 (7 << 8) 214*4882a593Smuzhiyun #define MASK_CECSWAV1 (7 << 4) 215*4882a593Smuzhiyun #define MASK_CECSWAV0 (7 << 0) 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun #define CECRCTL3 0x061c 218*4882a593Smuzhiyun #define MASK_CECWAV3 (7 << 20) 219*4882a593Smuzhiyun #define MASK_CECWAV2 (7 << 16) 220*4882a593Smuzhiyun #define MASK_CECWAV1 (7 << 12) 221*4882a593Smuzhiyun #define MASK_CECWAV0 (7 << 8) 222*4882a593Smuzhiyun #define MASK_CECACKEI (1 << 4) 223*4882a593Smuzhiyun #define MASK_CECMINEI (1 << 3) 224*4882a593Smuzhiyun #define MASK_CECMAXEI (1 << 2) 225*4882a593Smuzhiyun #define MASK_CECRSTEI (1 << 1) 226*4882a593Smuzhiyun #define MASK_CECWAVEI (1 << 0) 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #define CECTEN 0x0620 229*4882a593Smuzhiyun #define MASK_CECTBUSY (1 << 1) 230*4882a593Smuzhiyun #define MASK_CECTEN (1 << 0) 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun #define CECTCTL 0x0628 233*4882a593Smuzhiyun #define MASK_CECSTRS (7 << 20) 234*4882a593Smuzhiyun #define MASK_CECSPRD (7 << 16) 235*4882a593Smuzhiyun #define MASK_CECDTRS (7 << 12) 236*4882a593Smuzhiyun #define MASK_CECDPRD (15 << 8) 237*4882a593Smuzhiyun #define MASK_CECBRD (1 << 4) 238*4882a593Smuzhiyun #define MASK_CECFREE (15 << 0) 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun #define CECRSTAT 0x062c 241*4882a593Smuzhiyun #define MASK_CECRIWA (1 << 6) 242*4882a593Smuzhiyun #define MASK_CECRIOR (1 << 5) 243*4882a593Smuzhiyun #define MASK_CECRIACK (1 << 4) 244*4882a593Smuzhiyun #define MASK_CECRIMIN (1 << 3) 245*4882a593Smuzhiyun #define MASK_CECRIMAX (1 << 2) 246*4882a593Smuzhiyun #define MASK_CECRISTA (1 << 1) 247*4882a593Smuzhiyun #define MASK_CECRIEND (1 << 0) 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun #define CECTSTAT 0x0630 250*4882a593Smuzhiyun #define MASK_CECTIUR (1 << 4) 251*4882a593Smuzhiyun #define MASK_CECTIACK (1 << 3) 252*4882a593Smuzhiyun #define MASK_CECTIAL (1 << 2) 253*4882a593Smuzhiyun #define MASK_CECTIEND (1 << 1) 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun #define CECRBUF1 0x0634 256*4882a593Smuzhiyun #define MASK_CECRACK (1 << 9) 257*4882a593Smuzhiyun #define MASK_CECEOM (1 << 8) 258*4882a593Smuzhiyun #define MASK_CECRBYTE (0xff << 0) 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun #define CECTBUF1 0x0674 261*4882a593Smuzhiyun #define MASK_CECTEOM (1 << 8) 262*4882a593Smuzhiyun #define MASK_CECTBYTE (0xff << 0) 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun #define CECRCTR 0x06b4 265*4882a593Smuzhiyun #define MASK_CECRCTR (0x1f << 0) 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun #define CECIMSK 0x06c0 268*4882a593Smuzhiyun #define MASK_CECTIM (1 << 1) 269*4882a593Smuzhiyun #define MASK_CECRIM (1 << 0) 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define CECICLR 0x06cc 272*4882a593Smuzhiyun #define MASK_CECTICLR (1 << 1) 273*4882a593Smuzhiyun #define MASK_CECRICLR (1 << 0) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #define HDMI_INT0 0x8500 277*4882a593Smuzhiyun #define MASK_I_KEY 0x80 278*4882a593Smuzhiyun #define MASK_I_MISC 0x02 279*4882a593Smuzhiyun #define MASK_I_PHYERR 0x01 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun #define HDMI_INT1 0x8501 282*4882a593Smuzhiyun #define MASK_I_GBD 0x80 283*4882a593Smuzhiyun #define MASK_I_HDCP 0x40 284*4882a593Smuzhiyun #define MASK_I_ERR 0x20 285*4882a593Smuzhiyun #define MASK_I_AUD 0x10 286*4882a593Smuzhiyun #define MASK_I_CBIT 0x08 287*4882a593Smuzhiyun #define MASK_I_PACKET 0x04 288*4882a593Smuzhiyun #define MASK_I_CLK 0x02 289*4882a593Smuzhiyun #define MASK_I_SYS 0x01 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun #define SYS_INT 0x8502 292*4882a593Smuzhiyun #define MASK_I_ACR_CTS 0x80 293*4882a593Smuzhiyun #define MASK_I_ACRN 0x40 294*4882a593Smuzhiyun #define MASK_I_DVI 0x20 295*4882a593Smuzhiyun #define MASK_I_HDMI 0x10 296*4882a593Smuzhiyun #define MASK_I_NOPMBDET 0x08 297*4882a593Smuzhiyun #define MASK_I_DPMBDET 0x04 298*4882a593Smuzhiyun #define MASK_I_TMDS 0x02 299*4882a593Smuzhiyun #define MASK_I_DDC 0x01 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun #define CLK_INT 0x8503 302*4882a593Smuzhiyun #define MASK_I_OUT_H_CHG 0x40 303*4882a593Smuzhiyun #define MASK_I_IN_DE_CHG 0x20 304*4882a593Smuzhiyun #define MASK_I_IN_HV_CHG 0x10 305*4882a593Smuzhiyun #define MASK_I_DC_CHG 0x08 306*4882a593Smuzhiyun #define MASK_I_PXCLK_CHG 0x04 307*4882a593Smuzhiyun #define MASK_I_PHYCLK_CHG 0x02 308*4882a593Smuzhiyun #define MASK_I_TMDSCLK_CHG 0x01 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun #define CBIT_INT 0x8505 311*4882a593Smuzhiyun #define MASK_I_AF_LOCK 0x80 312*4882a593Smuzhiyun #define MASK_I_AF_UNLOCK 0x40 313*4882a593Smuzhiyun #define MASK_I_CBIT_FS 0x02 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #define AUDIO_INT 0x8506 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun #define ERR_INT 0x8507 318*4882a593Smuzhiyun #define MASK_I_EESS_ERR 0x80 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun #define HDCP_INT 0x8508 321*4882a593Smuzhiyun #define MASK_I_AVM_SET 0x80 322*4882a593Smuzhiyun #define MASK_I_AVM_CLR 0x40 323*4882a593Smuzhiyun #define MASK_I_LINKERR 0x20 324*4882a593Smuzhiyun #define MASK_I_SHA_END 0x10 325*4882a593Smuzhiyun #define MASK_I_R0_END 0x08 326*4882a593Smuzhiyun #define MASK_I_KM_END 0x04 327*4882a593Smuzhiyun #define MASK_I_AKSV_END 0x02 328*4882a593Smuzhiyun #define MASK_I_AN_END 0x01 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun #define MISC_INT 0x850B 331*4882a593Smuzhiyun #define MASK_I_AS_LAYOUT 0x10 332*4882a593Smuzhiyun #define MASK_I_NO_SPD 0x08 333*4882a593Smuzhiyun #define MASK_I_NO_VS 0x03 334*4882a593Smuzhiyun #define MASK_I_SYNC_CHG 0x02 335*4882a593Smuzhiyun #define MASK_I_AUDIO_MUTE 0x01 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun #define KEY_INT 0x850F 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun #define SYS_INTM 0x8512 340*4882a593Smuzhiyun #define MASK_M_ACR_CTS 0x80 341*4882a593Smuzhiyun #define MASK_M_ACR_N 0x40 342*4882a593Smuzhiyun #define MASK_M_DVI_DET 0x20 343*4882a593Smuzhiyun #define MASK_M_HDMI_DET 0x10 344*4882a593Smuzhiyun #define MASK_M_NOPMBDET 0x08 345*4882a593Smuzhiyun #define MASK_M_BPMBDET 0x04 346*4882a593Smuzhiyun #define MASK_M_TMDS 0x02 347*4882a593Smuzhiyun #define MASK_M_DDC 0x01 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun #define CLK_INTM 0x8513 350*4882a593Smuzhiyun #define MASK_M_OUT_H_CHG 0x40 351*4882a593Smuzhiyun #define MASK_M_IN_DE_CHG 0x20 352*4882a593Smuzhiyun #define MASK_M_IN_HV_CHG 0x10 353*4882a593Smuzhiyun #define MASK_M_DC_CHG 0x08 354*4882a593Smuzhiyun #define MASK_M_PXCLK_CHG 0x04 355*4882a593Smuzhiyun #define MASK_M_PHYCLK_CHG 0x02 356*4882a593Smuzhiyun #define MASK_M_TMDS_CHG 0x01 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun #define PACKET_INTM 0x8514 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun #define CBIT_INTM 0x8515 361*4882a593Smuzhiyun #define MASK_M_AF_LOCK 0x80 362*4882a593Smuzhiyun #define MASK_M_AF_UNLOCK 0x40 363*4882a593Smuzhiyun #define MASK_M_CBIT_FS 0x02 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun #define AUDIO_INTM 0x8516 366*4882a593Smuzhiyun #define MASK_M_BUFINIT_END 0x01 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun #define ERR_INTM 0x8517 369*4882a593Smuzhiyun #define MASK_M_EESS_ERR 0x80 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun #define HDCP_INTM 0x8518 372*4882a593Smuzhiyun #define MASK_M_AVM_SET 0x80 373*4882a593Smuzhiyun #define MASK_M_AVM_CLR 0x40 374*4882a593Smuzhiyun #define MASK_M_LINKERR 0x20 375*4882a593Smuzhiyun #define MASK_M_SHA_END 0x10 376*4882a593Smuzhiyun #define MASK_M_R0_END 0x08 377*4882a593Smuzhiyun #define MASK_M_KM_END 0x04 378*4882a593Smuzhiyun #define MASK_M_AKSV_END 0x02 379*4882a593Smuzhiyun #define MASK_M_AN_END 0x01 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun #define MISC_INTM 0x851B 382*4882a593Smuzhiyun #define MASK_M_AS_LAYOUT 0x10 383*4882a593Smuzhiyun #define MASK_M_NO_SPD 0x08 384*4882a593Smuzhiyun #define MASK_M_NO_VS 0x03 385*4882a593Smuzhiyun #define MASK_M_SYNC_CHG 0x02 386*4882a593Smuzhiyun #define MASK_M_AUDIO_MUTE 0x01 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun #define KEY_INTM 0x851F 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun #define SYS_STATUS 0x8520 391*4882a593Smuzhiyun #define MASK_S_SYNC 0x80 392*4882a593Smuzhiyun #define MASK_S_AVMUTE 0x40 393*4882a593Smuzhiyun #define MASK_S_HDCP 0x20 394*4882a593Smuzhiyun #define MASK_S_HDMI 0x10 395*4882a593Smuzhiyun #define MASK_S_PHY_SCDT 0x08 396*4882a593Smuzhiyun #define MASK_S_PHY_PLL 0x04 397*4882a593Smuzhiyun #define MASK_S_TMDS 0x02 398*4882a593Smuzhiyun #define MASK_S_DDC5V 0x01 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun #define CSI_STATUS 0x0410 401*4882a593Smuzhiyun #define MASK_S_WSYNC 0x0400 402*4882a593Smuzhiyun #define MASK_S_TXACT 0x0200 403*4882a593Smuzhiyun #define MASK_S_RXACT 0x0100 404*4882a593Smuzhiyun #define MASK_S_HLT 0x0001 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun #define VI_STATUS1 0x8522 407*4882a593Smuzhiyun #define MASK_S_V_GBD 0x08 408*4882a593Smuzhiyun #define MASK_S_DEEPCOLOR 0x0c 409*4882a593Smuzhiyun #define MASK_S_V_422 0x02 410*4882a593Smuzhiyun #define MASK_S_V_INTERLACE 0x01 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #define AU_STATUS0 0x8523 413*4882a593Smuzhiyun #define MASK_S_A_SAMPLE 0x01 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun #define VI_STATUS3 0x8528 416*4882a593Smuzhiyun #define MASK_S_V_COLOR 0x1e 417*4882a593Smuzhiyun #define MASK_LIMITED 0x01 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun #define PHY_CTL0 0x8531 420*4882a593Smuzhiyun #define MASK_PHY_SYSCLK_IND 0x02 421*4882a593Smuzhiyun #define MASK_PHY_CTL 0x01 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun 424*4882a593Smuzhiyun #define PHY_CTL1 0x8532 /* Not in REF_01 */ 425*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST1 0xf0 426*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST1_OFF 0x00 427*4882a593Smuzhiyun #define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \ 428*4882a593Smuzhiyun MASK_PHY_AUTO_RST1) 429*4882a593Smuzhiyun #define MASK_FREQ_RANGE_MODE 0x0f 430*4882a593Smuzhiyun #define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \ 431*4882a593Smuzhiyun MASK_FREQ_RANGE_MODE) 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun #define PHY_CTL2 0x8533 /* Not in REF_01 */ 434*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST4 0x04 435*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST3 0x02 436*4882a593Smuzhiyun #define MASK_PHY_AUTO_RST2 0x01 437*4882a593Smuzhiyun #define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \ 438*4882a593Smuzhiyun MASK_PHY_AUTO_RST3 | \ 439*4882a593Smuzhiyun MASK_PHY_AUTO_RST2) 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun #define PHY_EN 0x8534 442*4882a593Smuzhiyun #define MASK_ENABLE_PHY 0x01 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun #define PHY_RST 0x8535 445*4882a593Smuzhiyun #define MASK_RESET_CTRL 0x01 /* Reset active low */ 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun #define PHY_BIAS 0x8536 /* Not in REF_01 */ 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun #define PHY_CSQ 0x853F /* Not in REF_01 */ 450*4882a593Smuzhiyun #define MASK_CSQ_CNT 0x0f 451*4882a593Smuzhiyun #define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT) 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun #define SYS_FREQ0 0x8540 454*4882a593Smuzhiyun #define SYS_FREQ1 0x8541 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun #define SYS_CLK 0x8542 /* Not in REF_01 */ 457*4882a593Smuzhiyun #define MASK_CLK_DIFF 0x0C 458*4882a593Smuzhiyun #define MASK_CLK_DIV 0x03 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun #define DDC_CTL 0x8543 461*4882a593Smuzhiyun #define MASK_DDC_ACK_POL 0x08 462*4882a593Smuzhiyun #define MASK_DDC_ACTION 0x04 463*4882a593Smuzhiyun #define MASK_DDC5V_MODE 0x03 464*4882a593Smuzhiyun #define MASK_DDC5V_MODE_0MS 0x00 465*4882a593Smuzhiyun #define MASK_DDC5V_MODE_50MS 0x01 466*4882a593Smuzhiyun #define MASK_DDC5V_MODE_100MS 0x02 467*4882a593Smuzhiyun #define MASK_DDC5V_MODE_200MS 0x03 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun #define HPD_CTL 0x8544 470*4882a593Smuzhiyun #define MASK_HPD_CTL0 0x10 471*4882a593Smuzhiyun #define MASK_HPD_OUT0 0x01 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun #define ANA_CTL 0x8545 474*4882a593Smuzhiyun #define MASK_APPL_PCSX 0x30 475*4882a593Smuzhiyun #define MASK_APPL_PCSX_HIZ 0x00 476*4882a593Smuzhiyun #define MASK_APPL_PCSX_L_FIX 0x10 477*4882a593Smuzhiyun #define MASK_APPL_PCSX_H_FIX 0x20 478*4882a593Smuzhiyun #define MASK_APPL_PCSX_NORMAL 0x30 479*4882a593Smuzhiyun #define MASK_ANALOG_ON 0x01 480*4882a593Smuzhiyun 481*4882a593Smuzhiyun #define AVM_CTL 0x8546 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun #define INIT_END 0x854A 484*4882a593Smuzhiyun #define MASK_INIT_END 0x01 485*4882a593Smuzhiyun 486*4882a593Smuzhiyun #define HDMI_DET 0x8552 /* Not in REF_01 */ 487*4882a593Smuzhiyun #define MASK_HDMI_DET_MOD1 0x80 488*4882a593Smuzhiyun #define MASK_HDMI_DET_MOD0 0x40 489*4882a593Smuzhiyun #define MASK_HDMI_DET_V 0x30 490*4882a593Smuzhiyun #define MASK_HDMI_DET_V_SYNC 0x00 491*4882a593Smuzhiyun #define MASK_HDMI_DET_V_ASYNC_25MS 0x10 492*4882a593Smuzhiyun #define MASK_HDMI_DET_V_ASYNC_50MS 0x20 493*4882a593Smuzhiyun #define MASK_HDMI_DET_V_ASYNC_100MS 0x30 494*4882a593Smuzhiyun #define MASK_HDMI_DET_NUM 0x0f 495*4882a593Smuzhiyun 496*4882a593Smuzhiyun #define HDCP_MODE 0x8560 497*4882a593Smuzhiyun #define MASK_MODE_RST_TN 0x20 498*4882a593Smuzhiyun #define MASK_LINE_REKEY 0x10 499*4882a593Smuzhiyun #define MASK_AUTO_CLR 0x04 500*4882a593Smuzhiyun #define MASK_MANUAL_AUTHENTICATION 0x02 /* Not in REF_01 */ 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun #define HDCP_REG1 0x8563 /* Not in REF_01 */ 503*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL 0x70 504*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70 505*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60 506*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50 507*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40 508*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30 509*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20 510*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10 511*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_SEL_ONCE 0x00 512*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH 0x01 513*4882a593Smuzhiyun #define MASK_AUTH_UNAUTH_AUTO 0x01 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun #define HDCP_REG2 0x8564 /* Not in REF_01 */ 516*4882a593Smuzhiyun #define MASK_AUTO_P3_RESET 0x0F 517*4882a593Smuzhiyun #define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET) 518*4882a593Smuzhiyun #define MASK_AUTO_P3_RESET_OFF 0x00 519*4882a593Smuzhiyun 520*4882a593Smuzhiyun #define VI_MODE 0x8570 521*4882a593Smuzhiyun #define MASK_RGB_DVI 0x08 /* Not in REF_01 */ 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun #define VOUT_SET2 0x8573 524*4882a593Smuzhiyun #define MASK_SEL422 0x80 525*4882a593Smuzhiyun #define MASK_VOUT_422FIL_100 0x40 526*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE 0x03 527*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE_THROUGH 0x00 528*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE_AUTO 0x01 529*4882a593Smuzhiyun #define MASK_VOUTCOLORMODE_MANUAL 0x03 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun #define VOUT_SET3 0x8574 532*4882a593Smuzhiyun #define MASK_VOUT_EXTCNT 0x08 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun #define VI_REP 0x8576 535*4882a593Smuzhiyun #define MASK_VOUT_COLOR_SEL 0xe0 536*4882a593Smuzhiyun #define MASK_VOUT_COLOR_RGB_FULL 0x00 537*4882a593Smuzhiyun #define MASK_VOUT_COLOR_RGB_LIMITED 0x20 538*4882a593Smuzhiyun #define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40 539*4882a593Smuzhiyun #define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60 540*4882a593Smuzhiyun #define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80 541*4882a593Smuzhiyun #define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0 542*4882a593Smuzhiyun #define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0 543*4882a593Smuzhiyun #define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0 544*4882a593Smuzhiyun #define MASK_IN_REP_HEN 0x10 545*4882a593Smuzhiyun #define MASK_IN_REP 0x0f 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun #define VI_MUTE 0x857F 548*4882a593Smuzhiyun #define MASK_AUTO_MUTE 0xc0 549*4882a593Smuzhiyun #define MASK_VI_MUTE 0x10 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun #define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */ 552*4882a593Smuzhiyun #define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */ 553*4882a593Smuzhiyun #define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */ 554*4882a593Smuzhiyun #define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */ 555*4882a593Smuzhiyun #define H_SIZE_LO 0x858A /* Not in REF_01 */ 556*4882a593Smuzhiyun #define H_SIZE_HI 0x858B /* Not in REF_01 */ 557*4882a593Smuzhiyun #define V_SIZE_LO 0x858C /* Not in REF_01 */ 558*4882a593Smuzhiyun #define V_SIZE_HI 0x858D /* Not in REF_01 */ 559*4882a593Smuzhiyun #define FV_CNT_LO 0x85A1 /* Not in REF_01 */ 560*4882a593Smuzhiyun #define FV_CNT_HI 0x85A2 /* Not in REF_01 */ 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun #define FH_MIN0 0x85AA /* Not in REF_01 */ 563*4882a593Smuzhiyun #define FH_MIN1 0x85AB /* Not in REF_01 */ 564*4882a593Smuzhiyun #define FH_MAX0 0x85AC /* Not in REF_01 */ 565*4882a593Smuzhiyun #define FH_MAX1 0x85AD /* Not in REF_01 */ 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun #define HV_RST 0x85AF /* Not in REF_01 */ 568*4882a593Smuzhiyun #define MASK_H_PI_RST 0x20 569*4882a593Smuzhiyun #define MASK_V_PI_RST 0x10 570*4882a593Smuzhiyun 571*4882a593Smuzhiyun #define EDID_MODE 0x85C7 572*4882a593Smuzhiyun #define MASK_EDID_SPEED 0x40 573*4882a593Smuzhiyun #define MASK_EDID_MODE 0x03 574*4882a593Smuzhiyun #define MASK_EDID_MODE_DISABLE 0x00 575*4882a593Smuzhiyun #define MASK_EDID_MODE_DDC2B 0x01 576*4882a593Smuzhiyun #define MASK_EDID_MODE_E_DDC 0x02 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun #define EDID_LEN1 0x85CA 579*4882a593Smuzhiyun #define EDID_LEN2 0x85CB 580*4882a593Smuzhiyun 581*4882a593Smuzhiyun #define HDCP_REG3 0x85D1 /* Not in REF_01 */ 582*4882a593Smuzhiyun #define KEY_RD_CMD 0x01 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun #define FORCE_MUTE 0x8600 585*4882a593Smuzhiyun #define MASK_FORCE_AMUTE 0x10 586*4882a593Smuzhiyun #define MASK_FORCE_DMUTE 0x01 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun #define CMD_AUD 0x8601 589*4882a593Smuzhiyun #define MASK_CMD_BUFINIT 0x04 590*4882a593Smuzhiyun #define MASK_CMD_LOCKDET 0x02 591*4882a593Smuzhiyun #define MASK_CMD_MUTE 0x01 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun #define AUTO_CMD0 0x8602 594*4882a593Smuzhiyun #define MASK_AUTO_MUTE7 0x80 595*4882a593Smuzhiyun #define MASK_AUTO_MUTE6 0x40 596*4882a593Smuzhiyun #define MASK_AUTO_MUTE5 0x20 597*4882a593Smuzhiyun #define MASK_AUTO_MUTE4 0x10 598*4882a593Smuzhiyun #define MASK_AUTO_MUTE3 0x08 599*4882a593Smuzhiyun #define MASK_AUTO_MUTE2 0x04 600*4882a593Smuzhiyun #define MASK_AUTO_MUTE1 0x02 601*4882a593Smuzhiyun #define MASK_AUTO_MUTE0 0x01 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun #define AUTO_CMD1 0x8603 604*4882a593Smuzhiyun #define MASK_AUTO_MUTE10 0x04 605*4882a593Smuzhiyun #define MASK_AUTO_MUTE9 0x02 606*4882a593Smuzhiyun #define MASK_AUTO_MUTE8 0x01 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun #define AUTO_CMD2 0x8604 609*4882a593Smuzhiyun #define MASK_AUTO_PLAY3 0x08 610*4882a593Smuzhiyun #define MASK_AUTO_PLAY2 0x04 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun #define BUFINIT_START 0x8606 613*4882a593Smuzhiyun #define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100) 614*4882a593Smuzhiyun 615*4882a593Smuzhiyun #define FS_MUTE 0x8607 616*4882a593Smuzhiyun #define MASK_FS_ELSE_MUTE 0x80 617*4882a593Smuzhiyun #define MASK_FS22_MUTE 0x40 618*4882a593Smuzhiyun #define MASK_FS24_MUTE 0x20 619*4882a593Smuzhiyun #define MASK_FS88_MUTE 0x10 620*4882a593Smuzhiyun #define MASK_FS96_MUTE 0x08 621*4882a593Smuzhiyun #define MASK_FS176_MUTE 0x04 622*4882a593Smuzhiyun #define MASK_FS192_MUTE 0x02 623*4882a593Smuzhiyun #define MASK_FS_NO_MUTE 0x01 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun #define FS_IMODE 0x8620 626*4882a593Smuzhiyun #define MASK_NLPCM_HMODE 0x40 627*4882a593Smuzhiyun #define MASK_NLPCM_SMODE 0x20 628*4882a593Smuzhiyun #define MASK_NLPCM_IMODE 0x10 629*4882a593Smuzhiyun #define MASK_FS_HMODE 0x08 630*4882a593Smuzhiyun #define MASK_FS_AMODE 0x04 631*4882a593Smuzhiyun #define MASK_FS_SMODE 0x02 632*4882a593Smuzhiyun #define MASK_FS_IMODE 0x01 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun #define FS_SET 0x8621 635*4882a593Smuzhiyun #define MASK_FS 0x0f 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun #define LOCKDET_REF0 0x8630 638*4882a593Smuzhiyun #define LOCKDET_REF1 0x8631 639*4882a593Smuzhiyun #define LOCKDET_REF2 0x8632 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun #define ACR_MODE 0x8640 642*4882a593Smuzhiyun #define MASK_ACR_LOAD 0x10 643*4882a593Smuzhiyun #define MASK_N_MODE 0x04 644*4882a593Smuzhiyun #define MASK_CTS_MODE 0x01 645*4882a593Smuzhiyun 646*4882a593Smuzhiyun #define ACR_MDF0 0x8641 647*4882a593Smuzhiyun #define MASK_ACR_L2MDF 0x70 648*4882a593Smuzhiyun #define MASK_ACR_L2MDF_0_PPM 0x00 649*4882a593Smuzhiyun #define MASK_ACR_L2MDF_61_PPM 0x10 650*4882a593Smuzhiyun #define MASK_ACR_L2MDF_122_PPM 0x20 651*4882a593Smuzhiyun #define MASK_ACR_L2MDF_244_PPM 0x30 652*4882a593Smuzhiyun #define MASK_ACR_L2MDF_488_PPM 0x40 653*4882a593Smuzhiyun #define MASK_ACR_L2MDF_976_PPM 0x50 654*4882a593Smuzhiyun #define MASK_ACR_L2MDF_1976_PPM 0x60 655*4882a593Smuzhiyun #define MASK_ACR_L2MDF_3906_PPM 0x70 656*4882a593Smuzhiyun #define MASK_ACR_L1MDF 0x07 657*4882a593Smuzhiyun #define MASK_ACR_L1MDF_0_PPM 0x00 658*4882a593Smuzhiyun #define MASK_ACR_L1MDF_61_PPM 0x01 659*4882a593Smuzhiyun #define MASK_ACR_L1MDF_122_PPM 0x02 660*4882a593Smuzhiyun #define MASK_ACR_L1MDF_244_PPM 0x03 661*4882a593Smuzhiyun #define MASK_ACR_L1MDF_488_PPM 0x04 662*4882a593Smuzhiyun #define MASK_ACR_L1MDF_976_PPM 0x05 663*4882a593Smuzhiyun #define MASK_ACR_L1MDF_1976_PPM 0x06 664*4882a593Smuzhiyun #define MASK_ACR_L1MDF_3906_PPM 0x07 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun #define ACR_MDF1 0x8642 667*4882a593Smuzhiyun #define MASK_ACR_L3MDF 0x07 668*4882a593Smuzhiyun #define MASK_ACR_L3MDF_0_PPM 0x00 669*4882a593Smuzhiyun #define MASK_ACR_L3MDF_61_PPM 0x01 670*4882a593Smuzhiyun #define MASK_ACR_L3MDF_122_PPM 0x02 671*4882a593Smuzhiyun #define MASK_ACR_L3MDF_244_PPM 0x03 672*4882a593Smuzhiyun #define MASK_ACR_L3MDF_488_PPM 0x04 673*4882a593Smuzhiyun #define MASK_ACR_L3MDF_976_PPM 0x05 674*4882a593Smuzhiyun #define MASK_ACR_L3MDF_1976_PPM 0x06 675*4882a593Smuzhiyun #define MASK_ACR_L3MDF_3906_PPM 0x07 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun #define SDO_MODE1 0x8652 678*4882a593Smuzhiyun #define MASK_SDO_BIT_LENG 0x70 679*4882a593Smuzhiyun #define MASK_SDO_FMT 0x03 680*4882a593Smuzhiyun #define MASK_SDO_FMT_RIGHT 0x00 681*4882a593Smuzhiyun #define MASK_SDO_FMT_LEFT 0x01 682*4882a593Smuzhiyun #define MASK_SDO_FMT_I2S 0x02 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun #define DIV_MODE 0x8665 /* Not in REF_01 */ 685*4882a593Smuzhiyun #define MASK_DIV_DLY 0xf0 686*4882a593Smuzhiyun #define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \ 687*4882a593Smuzhiyun MASK_DIV_DLY) 688*4882a593Smuzhiyun #define MASK_DIV_MODE 0x01 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun #define NCO_F0_MOD 0x8670 691*4882a593Smuzhiyun #define MASK_NCO_F0_MOD 0x03 692*4882a593Smuzhiyun #define MASK_NCO_F0_MOD_42MHZ 0x00 693*4882a593Smuzhiyun #define MASK_NCO_F0_MOD_27MHZ 0x01 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun #define PK_INT_MODE 0x8709 696*4882a593Smuzhiyun #define MASK_ISRC2_INT_MODE 0x80 697*4882a593Smuzhiyun #define MASK_ISRC_INT_MODE 0x40 698*4882a593Smuzhiyun #define MASK_ACP_INT_MODE 0x20 699*4882a593Smuzhiyun #define MASK_VS_INT_MODE 0x10 700*4882a593Smuzhiyun #define MASK_SPD_INT_MODE 0x08 701*4882a593Smuzhiyun #define MASK_MS_INT_MODE 0x04 702*4882a593Smuzhiyun #define MASK_AUD_INT_MODE 0x02 703*4882a593Smuzhiyun #define MASK_AVI_INT_MODE 0x01 704*4882a593Smuzhiyun 705*4882a593Smuzhiyun #define NO_PKT_LIMIT 0x870B 706*4882a593Smuzhiyun #define MASK_NO_ACP_LIMIT 0xf0 707*4882a593Smuzhiyun #define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \ 708*4882a593Smuzhiyun MASK_NO_ACP_LIMIT) 709*4882a593Smuzhiyun #define MASK_NO_AVI_LIMIT 0x0f 710*4882a593Smuzhiyun #define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \ 711*4882a593Smuzhiyun MASK_NO_AVI_LIMIT) 712*4882a593Smuzhiyun 713*4882a593Smuzhiyun #define NO_PKT_CLR 0x870C 714*4882a593Smuzhiyun #define MASK_NO_VS_CLR 0x40 715*4882a593Smuzhiyun #define MASK_NO_SPD_CLR 0x20 716*4882a593Smuzhiyun #define MASK_NO_ACP_CLR 0x10 717*4882a593Smuzhiyun #define MASK_NO_AVI_CLR1 0x02 718*4882a593Smuzhiyun #define MASK_NO_AVI_CLR0 0x01 719*4882a593Smuzhiyun 720*4882a593Smuzhiyun #define ERR_PK_LIMIT 0x870D 721*4882a593Smuzhiyun #define NO_PKT_LIMIT2 0x870E 722*4882a593Smuzhiyun #define PK_AVI_0HEAD 0x8710 723*4882a593Smuzhiyun #define PK_AVI_1HEAD 0x8711 724*4882a593Smuzhiyun #define PK_AVI_2HEAD 0x8712 725*4882a593Smuzhiyun #define PK_AVI_0BYTE 0x8713 726*4882a593Smuzhiyun #define PK_AVI_1BYTE 0x8714 727*4882a593Smuzhiyun #define PK_AVI_2BYTE 0x8715 728*4882a593Smuzhiyun #define PK_AVI_3BYTE 0x8716 729*4882a593Smuzhiyun #define PK_AVI_4BYTE 0x8717 730*4882a593Smuzhiyun #define PK_AVI_5BYTE 0x8718 731*4882a593Smuzhiyun #define PK_AVI_6BYTE 0x8719 732*4882a593Smuzhiyun #define PK_AVI_7BYTE 0x871A 733*4882a593Smuzhiyun #define PK_AVI_8BYTE 0x871B 734*4882a593Smuzhiyun #define PK_AVI_9BYTE 0x871C 735*4882a593Smuzhiyun #define PK_AVI_10BYTE 0x871D 736*4882a593Smuzhiyun #define PK_AVI_11BYTE 0x871E 737*4882a593Smuzhiyun #define PK_AVI_12BYTE 0x871F 738*4882a593Smuzhiyun #define PK_AVI_13BYTE 0x8720 739*4882a593Smuzhiyun #define PK_AVI_14BYTE 0x8721 740*4882a593Smuzhiyun #define PK_AVI_15BYTE 0x8722 741*4882a593Smuzhiyun #define PK_AVI_16BYTE 0x8723 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun #define BKSV 0x8800 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun #define BCAPS 0x8840 746*4882a593Smuzhiyun #define MASK_HDMI_RSVD 0x80 747*4882a593Smuzhiyun #define MASK_REPEATER 0x40 748*4882a593Smuzhiyun #define MASK_READY 0x20 749*4882a593Smuzhiyun #define MASK_FASTI2C 0x10 750*4882a593Smuzhiyun #define MASK_1_1_FEA 0x02 751*4882a593Smuzhiyun #define MASK_FAST_REAU 0x01 752*4882a593Smuzhiyun 753*4882a593Smuzhiyun #define BSTATUS1 0x8842 754*4882a593Smuzhiyun #define MASK_MAX_EXCED 0x08 755*4882a593Smuzhiyun 756*4882a593Smuzhiyun #define EDID_RAM 0x8C00 757*4882a593Smuzhiyun #define NO_GDB_LIMIT 0x9007 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun #endif 760