xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/smiapp/smiapp-quirk.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * drivers/media/i2c/smiapp/smiapp-quirk.c
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Generic driver for SMIA/SMIA++ compliant camera modules
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2011--2012 Nokia Corporation
8*4882a593Smuzhiyun  * Contact: Sakari Ailus <sakari.ailus@iki.fi>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include "smiapp.h"
14*4882a593Smuzhiyun 
smiapp_write_8(struct smiapp_sensor * sensor,u16 reg,u8 val)15*4882a593Smuzhiyun static int smiapp_write_8(struct smiapp_sensor *sensor, u16 reg, u8 val)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun 	return smiapp_write(sensor, SMIAPP_REG_MK_U8(reg), val);
18*4882a593Smuzhiyun }
19*4882a593Smuzhiyun 
smiapp_write_8s(struct smiapp_sensor * sensor,const struct smiapp_reg_8 * regs,int len)20*4882a593Smuzhiyun static int smiapp_write_8s(struct smiapp_sensor *sensor,
21*4882a593Smuzhiyun 			   const struct smiapp_reg_8 *regs, int len)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
24*4882a593Smuzhiyun 	int rval;
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun 	for (; len > 0; len--, regs++) {
27*4882a593Smuzhiyun 		rval = smiapp_write_8(sensor, regs->reg, regs->val);
28*4882a593Smuzhiyun 		if (rval < 0) {
29*4882a593Smuzhiyun 			dev_err(&client->dev,
30*4882a593Smuzhiyun 				"error %d writing reg 0x%4.4x, val 0x%2.2x",
31*4882a593Smuzhiyun 				rval, regs->reg, regs->val);
32*4882a593Smuzhiyun 			return rval;
33*4882a593Smuzhiyun 		}
34*4882a593Smuzhiyun 	}
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	return 0;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun 
smiapp_replace_limit(struct smiapp_sensor * sensor,u32 limit,u32 val)39*4882a593Smuzhiyun void smiapp_replace_limit(struct smiapp_sensor *sensor,
40*4882a593Smuzhiyun 			  u32 limit, u32 val)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" = %d, 0x%x\n",
45*4882a593Smuzhiyun 		smiapp_reg_limits[limit].addr,
46*4882a593Smuzhiyun 		smiapp_reg_limits[limit].what, val, val);
47*4882a593Smuzhiyun 	sensor->limits[limit] = val;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun 
jt8ew9_limits(struct smiapp_sensor * sensor)50*4882a593Smuzhiyun static int jt8ew9_limits(struct smiapp_sensor *sensor)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun 	if (sensor->minfo.revision_number_major < 0x03)
53*4882a593Smuzhiyun 		sensor->frame_skip = 1;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun 	/* Below 24 gain doesn't have effect at all, */
56*4882a593Smuzhiyun 	/* but ~59 is needed for full dynamic range */
57*4882a593Smuzhiyun 	smiapp_replace_limit(sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MIN, 59);
58*4882a593Smuzhiyun 	smiapp_replace_limit(
59*4882a593Smuzhiyun 		sensor, SMIAPP_LIMIT_ANALOGUE_GAIN_CODE_MAX, 6000);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun 
jt8ew9_post_poweron(struct smiapp_sensor * sensor)64*4882a593Smuzhiyun static int jt8ew9_post_poweron(struct smiapp_sensor *sensor)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun 	static const struct smiapp_reg_8 regs[] = {
67*4882a593Smuzhiyun 		{ 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
68*4882a593Smuzhiyun 		{ 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
69*4882a593Smuzhiyun 		{ 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
70*4882a593Smuzhiyun 		{ 0x322d, 0x04 }, /* Adjusting Processing Image Size to Scaler Toshiba Recommendation Setting */
71*4882a593Smuzhiyun 		{ 0x3255, 0x0f }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
72*4882a593Smuzhiyun 		{ 0x3256, 0x15 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
73*4882a593Smuzhiyun 		{ 0x3258, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
74*4882a593Smuzhiyun 		{ 0x3259, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
75*4882a593Smuzhiyun 		{ 0x325f, 0x7c }, /* Analog Gain Control Toshiba Recommendation Setting */
76*4882a593Smuzhiyun 		{ 0x3302, 0x06 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
77*4882a593Smuzhiyun 		{ 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
78*4882a593Smuzhiyun 		{ 0x3307, 0x22 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
79*4882a593Smuzhiyun 		{ 0x3308, 0x8d }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
80*4882a593Smuzhiyun 		{ 0x331e, 0x0f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
81*4882a593Smuzhiyun 		{ 0x3320, 0x30 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
82*4882a593Smuzhiyun 		{ 0x3321, 0x11 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
83*4882a593Smuzhiyun 		{ 0x3322, 0x98 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
84*4882a593Smuzhiyun 		{ 0x3323, 0x64 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
85*4882a593Smuzhiyun 		{ 0x3325, 0x83 }, /* Read Out Timing Control Toshiba Recommendation Setting */
86*4882a593Smuzhiyun 		{ 0x3330, 0x18 }, /* Read Out Timing Control Toshiba Recommendation Setting */
87*4882a593Smuzhiyun 		{ 0x333c, 0x01 }, /* Read Out Timing Control Toshiba Recommendation Setting */
88*4882a593Smuzhiyun 		{ 0x3345, 0x2f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
89*4882a593Smuzhiyun 		{ 0x33de, 0x38 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
90*4882a593Smuzhiyun 		/* Taken from v03. No idea what the rest are. */
91*4882a593Smuzhiyun 		{ 0x32e0, 0x05 },
92*4882a593Smuzhiyun 		{ 0x32e1, 0x05 },
93*4882a593Smuzhiyun 		{ 0x32e2, 0x04 },
94*4882a593Smuzhiyun 		{ 0x32e5, 0x04 },
95*4882a593Smuzhiyun 		{ 0x32e6, 0x04 },
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	};
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun const struct smiapp_quirk smiapp_jt8ew9_quirk = {
103*4882a593Smuzhiyun 	.limits = jt8ew9_limits,
104*4882a593Smuzhiyun 	.post_poweron = jt8ew9_post_poweron,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
imx125es_post_poweron(struct smiapp_sensor * sensor)107*4882a593Smuzhiyun static int imx125es_post_poweron(struct smiapp_sensor *sensor)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun 	/* Taken from v02. No idea what the other two are. */
110*4882a593Smuzhiyun 	static const struct smiapp_reg_8 regs[] = {
111*4882a593Smuzhiyun 		/*
112*4882a593Smuzhiyun 		 * 0x3302: clk during frame blanking:
113*4882a593Smuzhiyun 		 * 0x00 - HS mode, 0x01 - LP11
114*4882a593Smuzhiyun 		 */
115*4882a593Smuzhiyun 		{ 0x3302, 0x01 },
116*4882a593Smuzhiyun 		{ 0x302d, 0x00 },
117*4882a593Smuzhiyun 		{ 0x3b08, 0x8c },
118*4882a593Smuzhiyun 	};
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	return smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun const struct smiapp_quirk smiapp_imx125es_quirk = {
124*4882a593Smuzhiyun 	.post_poweron = imx125es_post_poweron,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
jt8ev1_limits(struct smiapp_sensor * sensor)127*4882a593Smuzhiyun static int jt8ev1_limits(struct smiapp_sensor *sensor)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	smiapp_replace_limit(sensor, SMIAPP_LIMIT_X_ADDR_MAX, 4271);
130*4882a593Smuzhiyun 	smiapp_replace_limit(sensor,
131*4882a593Smuzhiyun 			     SMIAPP_LIMIT_MIN_LINE_BLANKING_PCK_BIN, 184);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun 
jt8ev1_post_poweron(struct smiapp_sensor * sensor)136*4882a593Smuzhiyun static int jt8ev1_post_poweron(struct smiapp_sensor *sensor)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
139*4882a593Smuzhiyun 	int rval;
140*4882a593Smuzhiyun 	static const struct smiapp_reg_8 regs[] = {
141*4882a593Smuzhiyun 		{ 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
142*4882a593Smuzhiyun 		{ 0x30a3, 0xd0 }, /* FLASH STROBE enable */
143*4882a593Smuzhiyun 		{ 0x3237, 0x00 }, /* For control of pulse timing for ADC */
144*4882a593Smuzhiyun 		{ 0x3238, 0x43 },
145*4882a593Smuzhiyun 		{ 0x3301, 0x06 }, /* For analog bias for sensor */
146*4882a593Smuzhiyun 		{ 0x3302, 0x06 },
147*4882a593Smuzhiyun 		{ 0x3304, 0x00 },
148*4882a593Smuzhiyun 		{ 0x3305, 0x88 },
149*4882a593Smuzhiyun 		{ 0x332a, 0x14 },
150*4882a593Smuzhiyun 		{ 0x332c, 0x6b },
151*4882a593Smuzhiyun 		{ 0x3336, 0x01 },
152*4882a593Smuzhiyun 		{ 0x333f, 0x1f },
153*4882a593Smuzhiyun 		{ 0x3355, 0x00 },
154*4882a593Smuzhiyun 		{ 0x3356, 0x20 },
155*4882a593Smuzhiyun 		{ 0x33bf, 0x20 }, /* Adjust the FBC speed */
156*4882a593Smuzhiyun 		{ 0x33c9, 0x20 },
157*4882a593Smuzhiyun 		{ 0x33ce, 0x30 }, /* Adjust the parameter for logic function */
158*4882a593Smuzhiyun 		{ 0x33cf, 0xec }, /* For Black sun */
159*4882a593Smuzhiyun 		{ 0x3328, 0x80 }, /* Ugh. No idea what's this. */
160*4882a593Smuzhiyun 	};
161*4882a593Smuzhiyun 	static const struct smiapp_reg_8 regs_96[] = {
162*4882a593Smuzhiyun 		{ 0x30ae, 0x00 }, /* For control of ADC clock */
163*4882a593Smuzhiyun 		{ 0x30af, 0xd0 },
164*4882a593Smuzhiyun 		{ 0x30b0, 0x01 },
165*4882a593Smuzhiyun 	};
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	rval = smiapp_write_8s(sensor, regs, ARRAY_SIZE(regs));
168*4882a593Smuzhiyun 	if (rval < 0)
169*4882a593Smuzhiyun 		return rval;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	switch (sensor->hwcfg->ext_clk) {
172*4882a593Smuzhiyun 	case 9600000:
173*4882a593Smuzhiyun 		return smiapp_write_8s(sensor, regs_96,
174*4882a593Smuzhiyun 				       ARRAY_SIZE(regs_96));
175*4882a593Smuzhiyun 	default:
176*4882a593Smuzhiyun 		dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
177*4882a593Smuzhiyun 			 sensor->hwcfg->ext_clk);
178*4882a593Smuzhiyun 		return 0;
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun 
jt8ev1_pre_streamon(struct smiapp_sensor * sensor)182*4882a593Smuzhiyun static int jt8ev1_pre_streamon(struct smiapp_sensor *sensor)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	return smiapp_write_8(sensor, 0x3328, 0x00);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
jt8ev1_post_streamoff(struct smiapp_sensor * sensor)187*4882a593Smuzhiyun static int jt8ev1_post_streamoff(struct smiapp_sensor *sensor)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	int rval;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	/* Workaround: allows fast standby to work properly */
192*4882a593Smuzhiyun 	rval = smiapp_write_8(sensor, 0x3205, 0x04);
193*4882a593Smuzhiyun 	if (rval < 0)
194*4882a593Smuzhiyun 		return rval;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	/* Wait for 1 ms + one line => 2 ms is likely enough */
197*4882a593Smuzhiyun 	usleep_range(2000, 2050);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	/* Restore it */
200*4882a593Smuzhiyun 	rval = smiapp_write_8(sensor, 0x3205, 0x00);
201*4882a593Smuzhiyun 	if (rval < 0)
202*4882a593Smuzhiyun 		return rval;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	return smiapp_write_8(sensor, 0x3328, 0x80);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun 
jt8ev1_init(struct smiapp_sensor * sensor)207*4882a593Smuzhiyun static int jt8ev1_init(struct smiapp_sensor *sensor)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	sensor->pll.flags |= SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	return 0;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun const struct smiapp_quirk smiapp_jt8ev1_quirk = {
215*4882a593Smuzhiyun 	.limits = jt8ev1_limits,
216*4882a593Smuzhiyun 	.post_poweron = jt8ev1_post_poweron,
217*4882a593Smuzhiyun 	.pre_streamon = jt8ev1_pre_streamon,
218*4882a593Smuzhiyun 	.post_streamoff = jt8ev1_post_streamoff,
219*4882a593Smuzhiyun 	.init = jt8ev1_init,
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun 
tcm8500md_limits(struct smiapp_sensor * sensor)222*4882a593Smuzhiyun static int tcm8500md_limits(struct smiapp_sensor *sensor)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun 	smiapp_replace_limit(sensor, SMIAPP_LIMIT_MIN_PLL_IP_FREQ_HZ, 2700000);
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	return 0;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun const struct smiapp_quirk smiapp_tcm8500md_quirk = {
230*4882a593Smuzhiyun 	.limits = tcm8500md_limits,
231*4882a593Smuzhiyun };
232