1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * drivers/media/i2c/smiapp-pll.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Generic driver for SMIA/SMIA++ compliant camera modules 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2012 Nokia Corporation 8*4882a593Smuzhiyun * Contact: Sakari Ailus <sakari.ailus@iki.fi> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef SMIAPP_PLL_H 12*4882a593Smuzhiyun #define SMIAPP_PLL_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* CSI-2 or CCP-2 */ 15*4882a593Smuzhiyun #define SMIAPP_PLL_BUS_TYPE_CSI2 0x00 16*4882a593Smuzhiyun #define SMIAPP_PLL_BUS_TYPE_PARALLEL 0x01 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* op pix clock is for all lanes in total normally */ 19*4882a593Smuzhiyun #define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) 20*4882a593Smuzhiyun #define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun struct smiapp_pll_branch { 23*4882a593Smuzhiyun uint16_t sys_clk_div; 24*4882a593Smuzhiyun uint16_t pix_clk_div; 25*4882a593Smuzhiyun uint32_t sys_clk_freq_hz; 26*4882a593Smuzhiyun uint32_t pix_clk_freq_hz; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct smiapp_pll { 30*4882a593Smuzhiyun /* input values */ 31*4882a593Smuzhiyun uint8_t bus_type; 32*4882a593Smuzhiyun union { 33*4882a593Smuzhiyun struct { 34*4882a593Smuzhiyun uint8_t lanes; 35*4882a593Smuzhiyun } csi2; 36*4882a593Smuzhiyun struct { 37*4882a593Smuzhiyun uint8_t bus_width; 38*4882a593Smuzhiyun } parallel; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun unsigned long flags; 41*4882a593Smuzhiyun uint8_t binning_horizontal; 42*4882a593Smuzhiyun uint8_t binning_vertical; 43*4882a593Smuzhiyun uint8_t scale_m; 44*4882a593Smuzhiyun uint8_t scale_n; 45*4882a593Smuzhiyun uint8_t bits_per_pixel; 46*4882a593Smuzhiyun uint32_t link_freq; 47*4882a593Smuzhiyun uint32_t ext_clk_freq_hz; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* output values */ 50*4882a593Smuzhiyun uint16_t pre_pll_clk_div; 51*4882a593Smuzhiyun uint16_t pll_multiplier; 52*4882a593Smuzhiyun uint32_t pll_ip_clk_freq_hz; 53*4882a593Smuzhiyun uint32_t pll_op_clk_freq_hz; 54*4882a593Smuzhiyun struct smiapp_pll_branch vt; 55*4882a593Smuzhiyun struct smiapp_pll_branch op; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun uint32_t pixel_rate_csi; 58*4882a593Smuzhiyun uint32_t pixel_rate_pixel_array; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct smiapp_pll_branch_limits { 62*4882a593Smuzhiyun uint16_t min_sys_clk_div; 63*4882a593Smuzhiyun uint16_t max_sys_clk_div; 64*4882a593Smuzhiyun uint32_t min_sys_clk_freq_hz; 65*4882a593Smuzhiyun uint32_t max_sys_clk_freq_hz; 66*4882a593Smuzhiyun uint16_t min_pix_clk_div; 67*4882a593Smuzhiyun uint16_t max_pix_clk_div; 68*4882a593Smuzhiyun uint32_t min_pix_clk_freq_hz; 69*4882a593Smuzhiyun uint32_t max_pix_clk_freq_hz; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct smiapp_pll_limits { 73*4882a593Smuzhiyun /* Strict PLL limits */ 74*4882a593Smuzhiyun uint32_t min_ext_clk_freq_hz; 75*4882a593Smuzhiyun uint32_t max_ext_clk_freq_hz; 76*4882a593Smuzhiyun uint16_t min_pre_pll_clk_div; 77*4882a593Smuzhiyun uint16_t max_pre_pll_clk_div; 78*4882a593Smuzhiyun uint32_t min_pll_ip_freq_hz; 79*4882a593Smuzhiyun uint32_t max_pll_ip_freq_hz; 80*4882a593Smuzhiyun uint16_t min_pll_multiplier; 81*4882a593Smuzhiyun uint16_t max_pll_multiplier; 82*4882a593Smuzhiyun uint32_t min_pll_op_freq_hz; 83*4882a593Smuzhiyun uint32_t max_pll_op_freq_hz; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun struct smiapp_pll_branch_limits vt; 86*4882a593Smuzhiyun struct smiapp_pll_branch_limits op; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* Other relevant limits */ 89*4882a593Smuzhiyun uint32_t min_line_length_pck_bin; 90*4882a593Smuzhiyun uint32_t min_line_length_pck; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct device; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun int smiapp_pll_calculate(struct device *dev, 96*4882a593Smuzhiyun const struct smiapp_pll_limits *limits, 97*4882a593Smuzhiyun struct smiapp_pll *pll); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun #endif /* SMIAPP_PLL_H */ 100