1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sc850sl driver
4 *
5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version
8 */
9
10 //#define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-subdev.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/rk-preisp.h>
29 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define MIPI_FREQ_540M 540000000
38
39 #define SC850SL_MAX_PIXEL_RATE (MIPI_FREQ_540M / 10 * 2 * SC850SL_4LANES)
40 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
41
42 #define SC850SL_XVCLK_FREQ_24M 24000000
43
44 /* TODO: Get the real chip id from reg */
45 #define CHIP_ID 0x9D1E
46 #define SC850SL_REG_CHIP_ID 0x3107
47
48 #define SC850SL_REG_CTRL_MODE 0x0100
49 #define SC850SL_MODE_SW_STANDBY 0x0
50 #define SC850SL_MODE_STREAMING BIT(0)
51
52 /*expo*/
53 #define SC850SL_EXPOSURE_MIN 2 /*okay*/
54 #define SC850SL_EXPOSURE_STEP 1 /*okay*/
55 #define SC850SL_VTS_MAX 0xffff /*okay*/
56
57 //long exposure
58 #define SC850SL_REG_EXP_LONG_H 0x3e00 //[3:0]
59 #define SC850SL_REG_EXP_LONG_M 0x3e01 //[7:0]
60 #define SC850SL_REG_EXP_LONG_L 0x3e02 //[7:4]
61
62 //short exposure //for hdr
63 #define SC850SL_REG_EXP_SF_H 0x3e22
64 #define SC850SL_REG_EXP_SF_M 0x3e04 //[7:0]
65 #define SC850SL_REG_EXP_SF_L 0x3e05 //[7:4]
66
67 #define SC850SL_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
68 #define SC850SL_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
69 #define SC850SL_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
70
71 /*gain*/
72 //long frame and normal gain reg
73 #define SC850SL_REG_DGAIN 0x3e06
74 #define SC850SL_REG_AGAIN 0x3e08
75 #define SC850SL_REG_AGAIN_FINE 0x3e09
76 //#define SC850SL_REG_DGAIN_FINE 0x3e07
77
78 //short fram gain reg
79 #define SC850SL_SF_REG_AGAIN 0x3e12
80 #define SC850SL_SF_REG_AGAIN_FINE 0x3e13
81 #define SC850SL_SF_REG_DGAIN 0x3e10
82
83 #define SC850SL_GAIN_MIN 0x40 //1.000 = 64 * 1/64
84 #define SC850SL_GAIN_MAX (8 * 50 * 64) /*need_view 8*50*64=25600 */
85 #define SC850SL_GAIN_STEP 1
86 #define SC850SL_GAIN_DEFAULT 0x40
87
88 #define SC850SL_REG_VTS 0x320e
89
90 //group hold
91 #define SC850SL_GROUP_UPDATE_ADDRESS 0x3800
92 #define SC850SL_GROUP_UPDATE_START_DATA 0x00
93 #define SC850SL_GROUP_UPDATE_LAUNCH 0x30
94
95 #define SC850SL_SOFTWARE_RESET_REG 0x0103
96 #define SC850SL_REG_TEST_PATTERN 0x4501
97 #define SC850SL_TEST_PATTERN_ENABLE 0x08
98
99 #define SC850SL_FLIP_REG 0x3221
100 #define SC850SL_FLIP_MASK 0x60
101 #define SC850SL_MIRROR_MASK 0x06
102
103 #define REG_NULL 0xFFFF
104
105 #define SC850SL_REG_VALUE_08BIT 1
106 #define SC850SL_REG_VALUE_16BIT 2
107 #define SC850SL_REG_VALUE_24BIT 3
108
109 #define SC850SL_4LANES 4
110
111 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
112 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
113
114 #define SC850SL_NAME "sc850sl"
115
116
117 static const char * const sc850sl_supply_names[] = {
118 "dvdd", // Digital core power
119 "dovdd", // Digital I/O power
120 "avdd", // Analog power
121 };
122 #define SC850SL_NUM_SUPPLIES ARRAY_SIZE(sc850sl_supply_names)
123
124 struct regval {
125 u16 addr;
126 u8 val;
127 };
128
129 struct sc850sl_mode {
130 u32 bus_fmt;
131 u32 width;
132 u32 height;
133 struct v4l2_fract max_fps;
134 u32 hts_def;
135 u32 vts_def;
136 u32 exp_def;
137 u32 mipi_freq_idx;
138 u32 bpp;
139 const struct regval *reg_list;
140 u32 hdr_mode;
141 u32 vc[PAD_MAX];
142 };
143
144 struct sc850sl {
145 struct i2c_client *client;
146 struct clk *xvclk;
147 struct gpio_desc *reset_gpio;
148 struct gpio_desc *power_gpio;
149 struct regulator_bulk_data supplies[SC850SL_NUM_SUPPLIES];
150
151 struct pinctrl *pinctrl;
152 struct pinctrl_state *pins_default;
153 struct pinctrl_state *pins_sleep;
154
155 struct v4l2_subdev subdev;
156 struct media_pad pad;
157 struct v4l2_ctrl_handler ctrl_handler;
158 struct v4l2_ctrl *exposure;
159 struct v4l2_ctrl *anal_a_gain;
160 struct v4l2_ctrl *digi_gain;
161 struct v4l2_ctrl *hblank;
162 struct v4l2_ctrl *vblank;
163 struct v4l2_ctrl *test_pattern;
164 struct v4l2_ctrl *pixel_rate;
165 struct v4l2_ctrl *link_freq;
166 struct mutex mutex;
167 struct v4l2_fract cur_fps;
168 bool streaming;
169 bool power_on;
170 bool is_first_streamoff;
171 const struct sc850sl_mode *cur_mode;
172 u32 module_index;
173 u32 cfg_num;
174 const char *module_facing;
175 const char *module_name;
176 const char *len_name;
177 u32 cur_vts;
178 bool has_init_exp;
179 struct preisp_hdrae_exp_s init_hdrae_exp;
180 };
181
182
183 #define to_sc850sl(sd) container_of(sd, struct sc850sl, subdev)
184
185 //cleaned_0x20_SC850SL_MIPI_24Minput_1C4D_1080Mbps_10bit_3840x2160_30fps_one_expo.ini
186 static __maybe_unused const struct regval sc850sl_linear10bit_3840x2160_regs[] = {
187 {0x0103, 0x01},
188 {0x0100, 0x00},
189 {0x36e9, 0x80},
190 {0x36f9, 0x80},
191 {0x36ea, 0x09},
192 {0x36eb, 0x0c},
193 {0x36ec, 0x4a},
194 {0x36ed, 0x24},
195 {0x36fa, 0x0b},
196 {0x36fb, 0x33},
197 {0x36fc, 0x10},
198 {0x36fd, 0x37},
199 {0x36e9, 0x24},
200 {0x36f9, 0x53},
201 {0x3018, 0x7a},
202 {0x3019, 0xf0},
203 {0x301a, 0x30},
204 {0x301e, 0x3c},
205 {0x301f, 0x20},
206 {0x302a, 0x00},
207 {0x3031, 0x0a},
208 {0x3032, 0x20},
209 {0x3033, 0x22},
210 {0x3037, 0x00},
211 {0x303e, 0xb4},
212 {0x320c, 0x04},
213 {0x320d, 0x4c},
214 {0x3226, 0x00},
215 {0x3227, 0x03},
216 {0x3250, 0x40},
217 {0x3253, 0x08},
218 {0x327e, 0x00},
219 {0x3280, 0x00},
220 {0x3281, 0x00},
221 {0x3301, 0x3c},
222 {0x3304, 0x30},
223 {0x3306, 0xe8},
224 {0x3308, 0x10},
225 {0x3309, 0x70},
226 {0x330a, 0x01},
227 {0x330b, 0xe0},
228 {0x330d, 0x10},
229 {0x3314, 0x92},
230 {0x331e, 0x29},
231 {0x331f, 0x69},
232 {0x3333, 0x10},
233 {0x3347, 0x05},
234 {0x3348, 0xd0},
235 {0x3352, 0x01},
236 {0x3356, 0x38},
237 {0x335d, 0x60},
238 {0x3362, 0x70},
239 {0x338f, 0x80},
240 {0x33af, 0x48},
241 {0x33fe, 0x00},
242 {0x3400, 0x12},
243 {0x3406, 0x04},
244 {0x3410, 0x12},
245 {0x3416, 0x06},
246 {0x3433, 0x01},
247 {0x3440, 0x12},
248 {0x3446, 0x08},
249 {0x3478, 0x01},
250 {0x3479, 0x01},
251 {0x347a, 0x02},
252 {0x347b, 0x01},
253 {0x347c, 0x04},
254 {0x347d, 0x01},
255 {0x3616, 0x0c},
256 {0x3620, 0x92},
257 {0x3622, 0x74},
258 {0x3629, 0x74},
259 {0x362a, 0xf0},
260 {0x362b, 0x0f},
261 {0x362d, 0x00},
262 {0x3630, 0x68},
263 {0x3633, 0x22},
264 {0x3634, 0x22},
265 {0x3635, 0x20},
266 {0x3637, 0x06},
267 {0x3638, 0x26},
268 {0x363b, 0x06},
269 {0x363c, 0x08},
270 {0x363d, 0x05},
271 {0x363e, 0x8f},
272 {0x3648, 0xe0},
273 {0x3649, 0x0a},
274 {0x364a, 0x06},
275 {0x364c, 0x6a},
276 {0x3650, 0x3d},
277 {0x3654, 0x40},
278 {0x3656, 0x68},
279 {0x3657, 0x0f},
280 {0x3658, 0x3d},
281 {0x365c, 0x40},
282 {0x365e, 0x68},
283 {0x3901, 0x04},
284 {0x3904, 0x20},
285 {0x3905, 0x91},
286 {0x391e, 0x83},
287 {0x3928, 0x04},
288 {0x3933, 0xa0},
289 {0x3934, 0x0a},
290 {0x3935, 0x68},
291 {0x3936, 0x00},
292 {0x3937, 0x20},
293 {0x3938, 0x0a},
294 {0x3946, 0x20},
295 {0x3961, 0x40},
296 {0x3962, 0x40},
297 {0x3963, 0xc8},
298 {0x3964, 0xc8},
299 {0x3965, 0x40},
300 {0x3966, 0x40},
301 {0x3967, 0x00},
302 {0x39cd, 0xc8},
303 {0x39ce, 0xc8},
304 {0x3e01, 0x82},
305 {0x3e02, 0x00},
306 {0x3e0e, 0x02},
307 {0x3e0f, 0x00},
308 {0x3e1c, 0x0f},
309 {0x3e23, 0x00},
310 {0x3e24, 0x00},
311 {0x3e53, 0x00},
312 {0x3e54, 0x00},
313 {0x3e68, 0x00},
314 {0x3e69, 0x80},
315 {0x3e73, 0x00},
316 {0x3e74, 0x00},
317 {0x3e86, 0x03},
318 {0x3e87, 0x40},
319 {0x3f02, 0x24},
320 {0x4424, 0x02},
321 {0x4501, 0xc4},
322 {0x4509, 0x20},
323 {0x4561, 0x12},
324 {0x4800, 0x24},
325 {0x4837, 0x0f},
326 {0x4900, 0x24},
327 {0x4937, 0x0f},
328 {0x5000, 0x0e},
329 {0x500f, 0x35},
330 {0x5020, 0x00},
331 {0x5787, 0x10},
332 {0x5788, 0x06},
333 {0x5789, 0x00},
334 {0x578a, 0x18},
335 {0x578b, 0x0c},
336 {0x578c, 0x00},
337 {0x5790, 0x10},
338 {0x5791, 0x06},
339 {0x5792, 0x01},
340 {0x5793, 0x18},
341 {0x5794, 0x0c},
342 {0x5795, 0x01},
343 {0x5799, 0x06},
344 {0x57a2, 0x60},
345 {0x59e0, 0xfe},
346 {0x59e1, 0x40},
347 {0x59e2, 0x38},
348 {0x59e3, 0x30},
349 {0x59e4, 0x20},
350 {0x59e5, 0x38},
351 {0x59e6, 0x30},
352 {0x59e7, 0x20},
353 {0x59e8, 0x3f},
354 {0x59e9, 0x38},
355 {0x59ea, 0x30},
356 {0x59eb, 0x3f},
357 {0x59ec, 0x38},
358 {0x59ed, 0x30},
359 {0x59ee, 0xfe},
360 {0x59ef, 0x40},
361 {0x59f4, 0x38},
362 {0x59f5, 0x30},
363 {0x59f6, 0x20},
364 {0x59f7, 0x38},
365 {0x59f8, 0x30},
366 {0x59f9, 0x20},
367 {0x59fa, 0x3f},
368 {0x59fb, 0x38},
369 {0x59fc, 0x30},
370 {0x59fd, 0x3f},
371 {0x59fe, 0x38},
372 {0x59ff, 0x30},
373 {0x0100, 0x01},
374 /*
375 * [gain < 2x] {0x363c, 0x05},
376 * [gain >=2x] {0x363c, 0x07},
377 */
378 {0x363c, 0x07},
379 {REG_NULL, 0x00},
380 };
381
382 /*
383 * The width and height must be configured to be
384 * the same as the current output resolution of the sensor.
385 * The input width of the isp needs to be 16 aligned.
386 * The input height of the isp needs to be 8 aligned.
387 * If the width or height does not meet the alignment rules,
388 * you can configure the cropping parameters with the following function to
389 * crop out the appropriate resolution.
390 * struct v4l2_subdev_pad_ops {
391 * .get_selection
392 * }
393 */
394 static const struct sc850sl_mode supported_modes[] = {
395 {
396 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
397 .width = 3840,
398 .height = 2160,
399 .max_fps = {
400 .numerator = 10000,
401 .denominator = 300000,
402 },
403 .exp_def = 0x08c0,
404 .hts_def = 0x0226*5-0x180,
405 .vts_def = 0x08ca,
406 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
407 .reg_list = sc850sl_linear10bit_3840x2160_regs,
408 .hdr_mode = NO_HDR,
409 .mipi_freq_idx = 0,
410 .bpp = 10,
411 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
412 },
413 };
414
415
416
417 static const char * const sc850sl_test_pattern_menu[] = {
418 "Disabled",
419 "Vertical Color Bar Type 1",
420 "Vertical Color Bar Type 2",
421 "Vertical Color Bar Type 3",
422 "Vertical Color Bar Type 4"
423 };
424
425 static const s64 link_freq_items[] = {
426 MIPI_FREQ_540M,
427 };
428
429 /* Write registers up to 4 at a time */
sc850sl_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)430 static int sc850sl_write_reg(struct i2c_client *client, u16 reg,
431 u32 len, u32 val)
432 {
433 u32 buf_i, val_i;
434 u8 buf[6];
435 u8 *val_p;
436 __be32 val_be;
437
438 if (len > 4)
439 return -EINVAL;
440
441 buf[0] = reg >> 8;
442 buf[1] = reg & 0xff;
443
444 val_be = cpu_to_be32(val);
445 val_p = (u8 *)&val_be;
446 buf_i = 2;
447 val_i = 4 - len;
448
449 while (val_i < 4)
450 buf[buf_i++] = val_p[val_i++];
451
452 if (i2c_master_send(client, buf, len + 2) != len + 2)
453 return -EIO;
454
455 return 0;
456 }
457
sc850sl_write_array(struct i2c_client * client,const struct regval * regs)458 static int sc850sl_write_array(struct i2c_client *client,
459 const struct regval *regs)
460 {
461 u32 i;
462 int ret = 0;
463
464 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
465 ret = sc850sl_write_reg(client, regs[i].addr,
466 SC850SL_REG_VALUE_08BIT, regs[i].val);
467 }
468 return ret;
469 }
470
471 /* Read registers up to 4 at a time */
sc850sl_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)472 static int sc850sl_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
473 u32 *val)
474 {
475 struct i2c_msg msgs[2];
476 u8 *data_be_p;
477 __be32 data_be = 0;
478 __be16 reg_addr_be = cpu_to_be16(reg);
479 int ret;
480
481 if (len > 4 || !len)
482 return -EINVAL;
483
484 data_be_p = (u8 *)&data_be;
485 /* Write register address */
486 msgs[0].addr = client->addr;
487 msgs[0].flags = 0;
488 msgs[0].len = 2;
489 msgs[0].buf = (u8 *)®_addr_be;
490
491 /* Read data from register */
492 msgs[1].addr = client->addr;
493 msgs[1].flags = I2C_M_RD;
494 msgs[1].len = len;
495 msgs[1].buf = &data_be_p[4 - len];
496
497 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
498 if (ret != ARRAY_SIZE(msgs))
499 return -EIO;
500
501 *val = be32_to_cpu(data_be);
502
503 return 0;
504 }
505
sc850sl_get_reso_dist(const struct sc850sl_mode * mode,struct v4l2_mbus_framefmt * framefmt)506 static int sc850sl_get_reso_dist(const struct sc850sl_mode *mode,
507 struct v4l2_mbus_framefmt *framefmt)
508 {
509 return abs(mode->width - framefmt->width) +
510 abs(mode->height - framefmt->height);
511 }
512
513 static const struct sc850sl_mode *
sc850sl_find_best_fit(struct sc850sl * sc850sl,struct v4l2_subdev_format * fmt)514 sc850sl_find_best_fit(struct sc850sl *sc850sl, struct v4l2_subdev_format *fmt)
515 {
516 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
517 int dist;
518 int cur_best_fit = 0;
519 int cur_best_fit_dist = -1;
520 unsigned int i;
521
522 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
523 dist = sc850sl_get_reso_dist(&supported_modes[i], framefmt);
524 if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
525 supported_modes[i].bus_fmt == framefmt->code) {
526 cur_best_fit_dist = dist;
527 cur_best_fit = i;
528 }
529 }
530 dev_info(&sc850sl->client->dev, "%s: cur_best_fit(%d)",
531 __func__, cur_best_fit);
532
533 return &supported_modes[cur_best_fit];
534 }
535
sc850sl_change_mode(struct sc850sl * sc850sl,const struct sc850sl_mode * mode)536 static void sc850sl_change_mode(struct sc850sl *sc850sl, const struct sc850sl_mode *mode)
537 {
538 sc850sl->cur_mode = mode;
539 sc850sl->cur_vts = sc850sl->cur_mode->vts_def;
540 dev_info(&sc850sl->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
541 mode->width, mode->height, mode->hdr_mode);
542 }
543
sc850sl_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)544 static int sc850sl_set_fmt(struct v4l2_subdev *sd,
545 struct v4l2_subdev_pad_config *cfg,
546 struct v4l2_subdev_format *fmt)
547 {
548 struct sc850sl *sc850sl = to_sc850sl(sd);
549 const struct sc850sl_mode *mode;
550 s64 h_blank, vblank_def;
551 u64 pixel_rate = 0;
552
553 mutex_lock(&sc850sl->mutex);
554
555 mode = sc850sl_find_best_fit(sc850sl, fmt);
556 fmt->format.code = mode->bus_fmt;
557 fmt->format.width = mode->width;
558 fmt->format.height = mode->height;
559 fmt->format.field = V4L2_FIELD_NONE;
560 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
561 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
562 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
563 #else
564 mutex_unlock(&sc850sl->mutex);
565 return -ENOTTY;
566 #endif
567 } else {
568 sc850sl_change_mode(sc850sl, mode);
569 h_blank = mode->hts_def - mode->width;
570 __v4l2_ctrl_modify_range(sc850sl->hblank, h_blank,
571 h_blank, 1, h_blank);
572 vblank_def = mode->vts_def - mode->height;
573 __v4l2_ctrl_modify_range(sc850sl->vblank, vblank_def,
574 SC850SL_VTS_MAX - mode->height,
575 1, vblank_def);
576 __v4l2_ctrl_s_ctrl(sc850sl->link_freq, mode->mipi_freq_idx);
577 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
578 mode->bpp * 2 * SC850SL_4LANES;
579 __v4l2_ctrl_s_ctrl_int64(sc850sl->pixel_rate, pixel_rate);
580 sc850sl->cur_fps = mode->max_fps;
581 sc850sl->cur_vts = mode->vts_def;
582 }
583
584 mutex_unlock(&sc850sl->mutex);
585
586 return 0;
587 }
588
sc850sl_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)589 static int sc850sl_get_fmt(struct v4l2_subdev *sd,
590 struct v4l2_subdev_pad_config *cfg,
591 struct v4l2_subdev_format *fmt)
592 {
593 struct sc850sl *sc850sl = to_sc850sl(sd);
594 const struct sc850sl_mode *mode = sc850sl->cur_mode;
595
596 mutex_lock(&sc850sl->mutex);
597 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
598 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
599 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
600 #else
601 mutex_unlock(&sc850sl->mutex);
602 return -ENOTTY;
603 #endif
604 } else {
605 fmt->format.width = mode->width;
606 fmt->format.height = mode->height;
607 fmt->format.code = mode->bus_fmt;
608 fmt->format.field = V4L2_FIELD_NONE;
609 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
610 fmt->reserved[0] = mode->vc[fmt->pad];
611 else
612 fmt->reserved[0] = mode->vc[PAD0];
613 }
614 mutex_unlock(&sc850sl->mutex);
615
616 return 0;
617 }
618
sc850sl_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)619 static int sc850sl_enum_mbus_code(struct v4l2_subdev *sd,
620 struct v4l2_subdev_pad_config *cfg,
621 struct v4l2_subdev_mbus_code_enum *code)
622 {
623 struct sc850sl *sc850sl = to_sc850sl(sd);
624
625 if (code->index != 0)
626 return -EINVAL;
627 code->code = sc850sl->cur_mode->bus_fmt;
628
629 return 0;
630 }
631
sc850sl_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)632 static int sc850sl_enum_frame_sizes(struct v4l2_subdev *sd,
633 struct v4l2_subdev_pad_config *cfg,
634 struct v4l2_subdev_frame_size_enum *fse)
635 {
636 struct sc850sl *sc850sl = to_sc850sl(sd);
637
638 if (fse->index >= sc850sl->cfg_num)
639 return -EINVAL;
640
641 if (fse->code != supported_modes[fse->index].bus_fmt)
642 return -EINVAL;
643
644 fse->min_width = supported_modes[fse->index].width;
645 fse->max_width = supported_modes[fse->index].width;
646 fse->max_height = supported_modes[fse->index].height;
647 fse->min_height = supported_modes[fse->index].height;
648
649 return 0;
650 }
651
sc850sl_enable_test_pattern(struct sc850sl * sc850sl,u32 pattern)652 static int sc850sl_enable_test_pattern(struct sc850sl *sc850sl, u32 pattern)
653 {
654 u32 val = 0;
655 int ret = 0;
656
657 ret = sc850sl_read_reg(sc850sl->client, SC850SL_REG_TEST_PATTERN,
658 SC850SL_REG_VALUE_08BIT, &val);
659 if (pattern)
660 val |= SC850SL_TEST_PATTERN_ENABLE;
661 else
662 val &= ~SC850SL_TEST_PATTERN_ENABLE;
663 ret |= sc850sl_write_reg(sc850sl->client, SC850SL_REG_TEST_PATTERN,
664 SC850SL_REG_VALUE_08BIT, val);
665 return ret;
666 }
667
sc850sl_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)668 static int sc850sl_g_frame_interval(struct v4l2_subdev *sd,
669 struct v4l2_subdev_frame_interval *fi)
670 {
671 struct sc850sl *sc850sl = to_sc850sl(sd);
672 const struct sc850sl_mode *mode = sc850sl->cur_mode;
673
674 if (sc850sl->streaming)
675 fi->interval = sc850sl->cur_fps;
676 else
677 fi->interval = mode->max_fps;
678
679 return 0;
680 }
681
sc850sl_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)682 static int sc850sl_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
683 struct v4l2_mbus_config *config)
684 {
685 struct sc850sl *sc850sl = to_sc850sl(sd);
686 const struct sc850sl_mode *mode = sc850sl->cur_mode;
687 u32 val = 0;
688
689 if (mode->hdr_mode == NO_HDR)
690 val = 1 << (SC850SL_4LANES - 1) |
691 V4L2_MBUS_CSI2_CHANNEL_0 |
692 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
693 if (mode->hdr_mode == HDR_X2)
694 val = 1 << (SC850SL_4LANES - 1) |
695 V4L2_MBUS_CSI2_CHANNEL_0 |
696 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
697 V4L2_MBUS_CSI2_CHANNEL_1;
698
699 config->type = V4L2_MBUS_CSI2_DPHY;
700 config->flags = val;
701
702 return 0;
703 }
704
sc850sl_get_module_inf(struct sc850sl * sc850sl,struct rkmodule_inf * inf)705 static void sc850sl_get_module_inf(struct sc850sl *sc850sl,
706 struct rkmodule_inf *inf)
707 {
708 memset(inf, 0, sizeof(*inf));
709 strscpy(inf->base.sensor, SC850SL_NAME, sizeof(inf->base.sensor));
710 strscpy(inf->base.module, sc850sl->module_name,
711 sizeof(inf->base.module));
712 strscpy(inf->base.lens, sc850sl->len_name, sizeof(inf->base.lens));
713 }
714
sc850sl_get_gain_reg(u32 val,u32 * again_reg,u32 * again_fine_reg,u32 * dgain_reg)715 static void sc850sl_get_gain_reg(u32 val, u32 *again_reg, u32 *again_fine_reg,
716 u32 *dgain_reg)
717 {
718 u8 u8Reg0x3e09 = 0x40, u8Reg0x3e08 = 0x03;
719 u32 aCoarseGain = 0;
720 u32 aFineGain = 0;
721 u32 again = 0;
722 u32 dgain = 0;
723
724 if (val < 64)
725 val = 64;
726 else if (val > SC850SL_GAIN_MAX)
727 val = SC850SL_GAIN_MAX;
728
729 if (val <= 3199) {
730 again = val;
731 dgain = 1;
732 } else {
733 again = 3199;
734 dgain = val / again;
735 }
736
737 //again
738 if (again <= 200) {
739 //a_gain < 3.125x
740 for (aCoarseGain = 1; aCoarseGain <= 2; aCoarseGain = aCoarseGain * 2) {
741 //1,2,4,8,16
742 if (again < (64 * 2 * aCoarseGain))
743 break;
744 }
745 aFineGain = again / aCoarseGain;
746 } else {
747 for (aCoarseGain = 1; aCoarseGain <= 8; aCoarseGain = aCoarseGain * 2) {
748 //1,2,4,8
749 if (again < (64 * 2 * aCoarseGain * 3125 / 1000))
750 break;
751 }
752 aFineGain = 1000 * again / aCoarseGain / 3125;
753 }
754 for ( ; aCoarseGain >= 2; aCoarseGain = aCoarseGain / 2)
755 u8Reg0x3e08 = (u8Reg0x3e08 << 1) | 0x01;
756
757 u8Reg0x3e09 = aFineGain;
758 //dcg = 2.72 --> 2.72*1024=2785.28
759 u8Reg0x3e08 = (again > 200) ? (u8Reg0x3e08 | 0x20) : (u8Reg0x3e08 & 0x1f);
760
761 //dgain
762 if (dgain <= 1) { /*1x ~ 2x*/
763 *dgain_reg = 0x00;
764 } else if (dgain <= 2) { /*2x ~ 4x*/
765 *dgain_reg = 0x01;
766 } else if (dgain <= 4) { /*4x ~ 8x*/
767 *dgain_reg = 0x03;
768 } else {
769 *dgain_reg = 0x07;
770 }
771
772 *again_reg = u8Reg0x3e08;
773 *again_fine_reg = u8Reg0x3e09;
774 }
775
sc850sl_get_channel_info(struct sc850sl * sc850sl,struct rkmodule_channel_info * ch_info)776 static int sc850sl_get_channel_info(struct sc850sl *sc850sl, struct rkmodule_channel_info *ch_info)
777 {
778 if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
779 return -EINVAL;
780 ch_info->vc = sc850sl->cur_mode->vc[ch_info->index];
781 ch_info->width = sc850sl->cur_mode->width;
782 ch_info->height = sc850sl->cur_mode->height;
783 ch_info->bus_fmt = sc850sl->cur_mode->bus_fmt;
784 return 0;
785 }
786
sc850sl_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)787 static long sc850sl_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
788 {
789 struct sc850sl *sc850sl = to_sc850sl(sd);
790 struct rkmodule_hdr_cfg *hdr_cfg;
791 const struct sc850sl_mode *mode;
792 struct rkmodule_channel_info *ch_info;
793 long ret = 0;
794 u64 pixel_rate = 0;
795 u32 i, h, w, stream;
796
797 switch (cmd) {
798 case PREISP_CMD_SET_HDRAE_EXP:
799 /*
800 * ret = sc850sl_set_hdrae(sc850sl, arg);
801 */
802 break;
803
804 case RKMODULE_SET_HDR_CFG:
805 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
806 if (sc850sl->streaming) {
807 ret = sc850sl_write_array(sc850sl->client, sc850sl->cur_mode->reg_list);
808 if (ret)
809 return ret;
810 }
811 w = sc850sl->cur_mode->width;
812 h = sc850sl->cur_mode->height;
813 for (i = 0; i < sc850sl->cfg_num; i++) {
814 if (w == supported_modes[i].width &&
815 h == supported_modes[i].height &&
816 supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
817 sc850sl_change_mode(sc850sl, &supported_modes[i]);
818 break;
819 }
820 }
821 if (i == sc850sl->cfg_num) {
822 dev_err(&sc850sl->client->dev,
823 "not find hdr mode:%d %dx%d config\n",
824 hdr_cfg->hdr_mode, w, h);
825 ret = -EINVAL;
826 } else {
827 mode = sc850sl->cur_mode;
828 w = mode->hts_def - mode->width;
829 h = mode->vts_def - mode->height;
830 __v4l2_ctrl_modify_range(sc850sl->hblank, w, w, 1, w);
831 __v4l2_ctrl_modify_range(sc850sl->vblank, h,
832 SC850SL_VTS_MAX - mode->height,
833 1, h);
834 __v4l2_ctrl_s_ctrl(sc850sl->link_freq, mode->mipi_freq_idx);
835 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
836 mode->bpp * 2 * SC850SL_4LANES;
837 __v4l2_ctrl_s_ctrl_int64(sc850sl->pixel_rate,
838 pixel_rate);
839 sc850sl->cur_fps = mode->max_fps;
840 sc850sl->cur_vts = mode->vts_def;
841 dev_info(&sc850sl->client->dev,
842 "sensor mode: %d\n", mode->hdr_mode);
843 }
844 break;
845 case RKMODULE_GET_MODULE_INFO:
846 sc850sl_get_module_inf(sc850sl, (struct rkmodule_inf *)arg);
847 break;
848
849 case RKMODULE_GET_HDR_CFG:
850 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
851 hdr_cfg->esp.mode = HDR_NORMAL_VC;
852 hdr_cfg->hdr_mode = sc850sl->cur_mode->hdr_mode;
853 break;
854
855 case RKMODULE_SET_QUICK_STREAM:
856 stream = *((u32 *)arg);
857
858 if (stream)
859 ret = sc850sl_write_reg(sc850sl->client, SC850SL_REG_CTRL_MODE,
860 SC850SL_REG_VALUE_08BIT, SC850SL_MODE_STREAMING);
861 else
862 ret = sc850sl_write_reg(sc850sl->client, SC850SL_REG_CTRL_MODE,
863 SC850SL_REG_VALUE_08BIT, SC850SL_MODE_SW_STANDBY);
864 break;
865
866 case RKMODULE_GET_CHANNEL_INFO:
867 ch_info = (struct rkmodule_channel_info *)arg;
868 ret = sc850sl_get_channel_info(sc850sl, ch_info);
869 break;
870
871 default:
872 ret = -ENOIOCTLCMD;
873 break;
874 }
875
876 return ret;
877 }
878
879 #ifdef CONFIG_COMPAT
sc850sl_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)880 static long sc850sl_compat_ioctl32(struct v4l2_subdev *sd,
881 unsigned int cmd, unsigned long arg)
882 {
883 void __user *up = compat_ptr(arg);
884 struct rkmodule_inf *inf;
885 struct rkmodule_awb_cfg *cfg;
886 struct rkmodule_hdr_cfg *hdr;
887 struct preisp_hdrae_exp_s *hdrae;
888 struct rkmodule_channel_info *ch_info;
889 long ret;
890 u32 stream;
891 u32 brl = 0;
892 struct rkmodule_csi_dphy_param *dphy_param;
893
894 switch (cmd) {
895 case RKMODULE_GET_MODULE_INFO:
896 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
897 if (!inf) {
898 ret = -ENOMEM;
899 return ret;
900 }
901
902 ret = sc850sl_ioctl(sd, cmd, inf);
903 if (!ret) {
904 if (copy_to_user(up, inf, sizeof(*inf))) {
905 kfree(inf);
906 return -EFAULT;
907 }
908 }
909 kfree(inf);
910 break;
911 case RKMODULE_AWB_CFG:
912 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
913 if (!cfg) {
914 ret = -ENOMEM;
915 return ret;
916 }
917
918 if (copy_from_user(cfg, up, sizeof(*cfg))) {
919 kfree(cfg);
920 return -EFAULT;
921 }
922 ret = sc850sl_ioctl(sd, cmd, cfg);
923 kfree(cfg);
924 break;
925 case RKMODULE_GET_HDR_CFG:
926 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
927 if (!hdr) {
928 ret = -ENOMEM;
929 return ret;
930 }
931
932 ret = sc850sl_ioctl(sd, cmd, hdr);
933 if (!ret) {
934 if (copy_to_user(up, hdr, sizeof(*hdr))) {
935 kfree(hdr);
936 return -EFAULT;
937 }
938 }
939 kfree(hdr);
940 break;
941 case RKMODULE_SET_HDR_CFG:
942 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
943 if (!hdr) {
944 ret = -ENOMEM;
945 return ret;
946 }
947
948 if (copy_from_user(hdr, up, sizeof(*hdr))) {
949 kfree(hdr);
950 return -EFAULT;
951 }
952 ret = sc850sl_ioctl(sd, cmd, hdr);
953 kfree(hdr);
954 break;
955 case PREISP_CMD_SET_HDRAE_EXP:
956 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
957 if (!hdrae) {
958 ret = -ENOMEM;
959 return ret;
960 }
961
962 if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
963 kfree(hdrae);
964 return -EFAULT;
965 }
966 ret = sc850sl_ioctl(sd, cmd, hdrae);
967 kfree(hdrae);
968 break;
969 case RKMODULE_SET_QUICK_STREAM:
970 if (copy_from_user(&stream, up, sizeof(u32)))
971 return -EFAULT;
972 ret = sc850sl_ioctl(sd, cmd, &stream);
973 break;
974 case RKMODULE_GET_SONY_BRL:
975 ret = sc850sl_ioctl(sd, cmd, &brl);
976 if (!ret) {
977 if (copy_to_user(up, &brl, sizeof(u32)))
978 return -EFAULT;
979 }
980 break;
981 case RKMODULE_GET_CHANNEL_INFO:
982 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
983 if (!ch_info) {
984 ret = -ENOMEM;
985 return ret;
986 }
987
988 ret = sc850sl_ioctl(sd, cmd, ch_info);
989 if (!ret) {
990 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
991 if (ret)
992 ret = -EFAULT;
993 }
994 kfree(ch_info);
995 break;
996 case RKMODULE_GET_CSI_DPHY_PARAM:
997 dphy_param = kzalloc(sizeof(*dphy_param), GFP_KERNEL);
998 if (!dphy_param) {
999 ret = -ENOMEM;
1000 return ret;
1001 }
1002
1003 ret = sc850sl_ioctl(sd, cmd, dphy_param);
1004 if (!ret) {
1005 ret = copy_to_user(up, dphy_param, sizeof(*dphy_param));
1006 if (ret)
1007 ret = -EFAULT;
1008 }
1009 kfree(dphy_param);
1010 break;
1011
1012 default:
1013 ret = -ENOIOCTLCMD;
1014 break;
1015 }
1016
1017 return ret;
1018 }
1019 #endif
1020
1021
__sc850sl_start_stream(struct sc850sl * sc850sl)1022 static int __sc850sl_start_stream(struct sc850sl *sc850sl)
1023 {
1024 int ret;
1025
1026 ret = sc850sl_write_array(sc850sl->client, sc850sl->cur_mode->reg_list);
1027 if (ret)
1028 return ret;
1029
1030 ret = __v4l2_ctrl_handler_setup(&sc850sl->ctrl_handler);
1031 if (ret)
1032 return ret;
1033 /* In case these controls are set before streaming */
1034 if (sc850sl->has_init_exp && sc850sl->cur_mode->hdr_mode != NO_HDR) {
1035 ret = sc850sl_ioctl(&sc850sl->subdev, PREISP_CMD_SET_HDRAE_EXP,
1036 &sc850sl->init_hdrae_exp);
1037 if (ret) {
1038 dev_err(&sc850sl->client->dev,
1039 "init exp fail in hdr mode\n");
1040 return ret;
1041 }
1042 }
1043 return sc850sl_write_reg(sc850sl->client, SC850SL_REG_CTRL_MODE,
1044 SC850SL_REG_VALUE_08BIT, SC850SL_MODE_STREAMING);
1045 }
1046
__sc850sl_stop_stream(struct sc850sl * sc850sl)1047 static int __sc850sl_stop_stream(struct sc850sl *sc850sl)
1048 {
1049 sc850sl->has_init_exp = false;
1050 return sc850sl_write_reg(sc850sl->client, SC850SL_REG_CTRL_MODE,
1051 SC850SL_REG_VALUE_08BIT, SC850SL_MODE_SW_STANDBY);
1052 }
1053
sc850sl_s_stream(struct v4l2_subdev * sd,int on)1054 static int sc850sl_s_stream(struct v4l2_subdev *sd, int on)
1055 {
1056 struct sc850sl *sc850sl = to_sc850sl(sd);
1057 struct i2c_client *client = sc850sl->client;
1058 int ret = 0;
1059
1060 dev_info(&sc850sl->client->dev, "s_stream: %d. %dx%d, hdr: %d, bpp: %d\n",
1061 on, sc850sl->cur_mode->width, sc850sl->cur_mode->height,
1062 sc850sl->cur_mode->hdr_mode, sc850sl->cur_mode->bpp);
1063
1064 mutex_lock(&sc850sl->mutex);
1065 on = !!on;
1066 if (on == sc850sl->streaming)
1067 goto unlock_and_return;
1068
1069 if (on) {
1070 ret = pm_runtime_get_sync(&client->dev);
1071 if (ret < 0) {
1072 pm_runtime_put_noidle(&client->dev);
1073 goto unlock_and_return;
1074 }
1075 ret = __sc850sl_start_stream(sc850sl);
1076 if (ret) {
1077 v4l2_err(sd, "start stream failed while write regs\n");
1078 pm_runtime_put(&client->dev);
1079 goto unlock_and_return;
1080 }
1081 } else {
1082 __sc850sl_stop_stream(sc850sl);
1083 pm_runtime_put(&client->dev);
1084 }
1085
1086 sc850sl->streaming = on;
1087
1088 unlock_and_return:
1089 mutex_unlock(&sc850sl->mutex);
1090 return ret;
1091 }
1092
sc850sl_s_power(struct v4l2_subdev * sd,int on)1093 static int sc850sl_s_power(struct v4l2_subdev *sd, int on)
1094 {
1095 struct sc850sl *sc850sl = to_sc850sl(sd);
1096 struct i2c_client *client = sc850sl->client;
1097 int ret = 0;
1098
1099 mutex_lock(&sc850sl->mutex);
1100
1101 /* If the power state is not modified - no work to do. */
1102 if (sc850sl->power_on == !!on)
1103 goto unlock_and_return;
1104
1105 if (on) {
1106 ret = pm_runtime_get_sync(&client->dev);
1107 if (ret < 0) {
1108 pm_runtime_put_noidle(&client->dev);
1109 goto unlock_and_return;
1110 }
1111
1112 ret |= sc850sl_write_reg(sc850sl->client,
1113 SC850SL_SOFTWARE_RESET_REG,
1114 SC850SL_REG_VALUE_08BIT,
1115 0x01);
1116 /*
1117 * usleep_range(100, 200);
1118 * ret |= sc850sl_write_reg(sc2310->client,
1119 * 0x303f,
1120 * SC850SL_REG_VALUE_08BIT,
1121 * 0x01);
1122 */
1123 sc850sl->power_on = true;
1124 } else {
1125 pm_runtime_put(&client->dev);
1126 sc850sl->power_on = false;
1127 }
1128
1129 unlock_and_return:
1130 mutex_unlock(&sc850sl->mutex);
1131
1132 return ret;
1133 }
1134
__sc850sl_power_on(struct sc850sl * sc850sl)1135 static int __sc850sl_power_on(struct sc850sl *sc850sl)
1136 {
1137 int ret;
1138 struct device *dev = &sc850sl->client->dev;
1139
1140 if (!IS_ERR_OR_NULL(sc850sl->pins_default)) {
1141 ret = pinctrl_select_state(sc850sl->pinctrl, sc850sl->pins_default);
1142 if (ret < 0)
1143 dev_err(dev, "could not set pins\n");
1144 }
1145
1146 if (!IS_ERR(sc850sl->power_gpio))
1147 gpiod_direction_output(sc850sl->power_gpio, 1);
1148
1149 usleep_range(4000, 6000);
1150 if (!IS_ERR(sc850sl->reset_gpio))
1151 gpiod_direction_output(sc850sl->reset_gpio, 0);
1152
1153 usleep_range(4000, 6000);
1154 ret = clk_set_rate(sc850sl->xvclk, SC850SL_XVCLK_FREQ_24M);
1155 if (ret < 0)
1156 dev_warn(dev, "Failed to set xvclk rate 24MHz\n");
1157 if (clk_get_rate(sc850sl->xvclk) != SC850SL_XVCLK_FREQ_24M)
1158 dev_warn(dev, "xvclk mismatched\n");
1159 ret = clk_prepare_enable(sc850sl->xvclk);
1160 if (ret < 0) {
1161 dev_err(dev, "Failed to enable xvclk\n");
1162 goto err_clk;
1163 }
1164
1165 ret = regulator_bulk_enable(SC850SL_NUM_SUPPLIES, sc850sl->supplies);
1166 if (ret < 0) {
1167 dev_err(dev, "Failed to enable regulators\n");
1168 goto disable_clk;
1169 }
1170
1171 usleep_range(4000, 6000);
1172 return 0;
1173 err_clk:
1174 if (!IS_ERR(sc850sl->reset_gpio))
1175 gpiod_direction_output(sc850sl->reset_gpio, 1);
1176 disable_clk:
1177 clk_disable_unprepare(sc850sl->xvclk);
1178
1179 return ret;
1180 }
1181
__sc850sl_power_off(struct sc850sl * sc850sl)1182 static void __sc850sl_power_off(struct sc850sl *sc850sl)
1183 {
1184 int ret;
1185 struct device *dev = &sc850sl->client->dev;
1186
1187 if (!IS_ERR(sc850sl->reset_gpio))
1188 gpiod_direction_output(sc850sl->reset_gpio, 1);
1189 clk_disable_unprepare(sc850sl->xvclk);
1190 if (!IS_ERR_OR_NULL(sc850sl->pins_sleep)) {
1191 ret = pinctrl_select_state(sc850sl->pinctrl,
1192 sc850sl->pins_sleep);
1193 if (ret < 0)
1194 dev_dbg(dev, "could not set pins\n");
1195 }
1196 if (!IS_ERR(sc850sl->power_gpio))
1197 gpiod_direction_output(sc850sl->power_gpio, 0);
1198 regulator_bulk_disable(SC850SL_NUM_SUPPLIES, sc850sl->supplies);
1199 }
1200
sc850sl_runtime_resume(struct device * dev)1201 static int sc850sl_runtime_resume(struct device *dev)
1202 {
1203 struct i2c_client *client = to_i2c_client(dev);
1204 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1205 struct sc850sl *sc850sl = to_sc850sl(sd);
1206
1207 return __sc850sl_power_on(sc850sl);
1208 }
1209
sc850sl_runtime_suspend(struct device * dev)1210 static int sc850sl_runtime_suspend(struct device *dev)
1211 {
1212 struct i2c_client *client = to_i2c_client(dev);
1213 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1214 struct sc850sl *sc850sl = to_sc850sl(sd);
1215
1216 __sc850sl_power_off(sc850sl);
1217
1218 return 0;
1219 }
1220
1221 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc850sl_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1222 static int sc850sl_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1223 {
1224 struct sc850sl *sc850sl = to_sc850sl(sd);
1225 struct v4l2_mbus_framefmt *try_fmt =
1226 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1227 const struct sc850sl_mode *def_mode = &supported_modes[0];
1228
1229 mutex_lock(&sc850sl->mutex);
1230 /* Initialize try_fmt */
1231 try_fmt->width = def_mode->width;
1232 try_fmt->height = def_mode->height;
1233 try_fmt->code = def_mode->bus_fmt;
1234 try_fmt->field = V4L2_FIELD_NONE;
1235
1236 mutex_unlock(&sc850sl->mutex);
1237 /* No crop or compose */
1238
1239 return 0;
1240 }
1241 #endif
1242
sc850sl_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1243 static int sc850sl_enum_frame_interval(struct v4l2_subdev *sd,
1244 struct v4l2_subdev_pad_config *cfg,
1245 struct v4l2_subdev_frame_interval_enum *fie)
1246 {
1247 struct sc850sl *sc850sl = to_sc850sl(sd);
1248
1249 if (fie->index >= sc850sl->cfg_num)
1250 return -EINVAL;
1251
1252 fie->code = supported_modes[fie->index].bus_fmt;
1253 fie->width = supported_modes[fie->index].width;
1254 fie->height = supported_modes[fie->index].height;
1255 fie->interval = supported_modes[fie->index].max_fps;
1256 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1257 return 0;
1258 }
1259
1260 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1261 #define DST_WIDTH_3840 3840
1262 #define DST_HEIGHT_2160 2160
1263 #define DST_WIDTH_1920 1920
1264 #define DST_HEIGHT_1080 1080
1265
sc850sl_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1266 static int sc850sl_get_selection(struct v4l2_subdev *sd,
1267 struct v4l2_subdev_pad_config *cfg,
1268 struct v4l2_subdev_selection *sel)
1269 {
1270 struct sc850sl *sc850sl = to_sc850sl(sd);
1271
1272 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1273 if (sc850sl->cur_mode->width == 3856) {
1274 sel->r.left = CROP_START(sc850sl->cur_mode->width, DST_WIDTH_3840);
1275 sel->r.width = DST_WIDTH_3840;
1276 sel->r.top = CROP_START(sc850sl->cur_mode->height, DST_HEIGHT_2160);
1277 sel->r.height = DST_HEIGHT_2160;
1278 } else if (sc850sl->cur_mode->width == 1944) {
1279 sel->r.left = CROP_START(sc850sl->cur_mode->width, DST_WIDTH_1920);
1280 sel->r.width = DST_WIDTH_1920;
1281 sel->r.top = CROP_START(sc850sl->cur_mode->height, DST_HEIGHT_1080);
1282 sel->r.height = DST_HEIGHT_1080;
1283 } else {
1284 sel->r.left = CROP_START(sc850sl->cur_mode->width,
1285 sc850sl->cur_mode->width);
1286 sel->r.width = sc850sl->cur_mode->width;
1287 sel->r.top = CROP_START(sc850sl->cur_mode->height,
1288 sc850sl->cur_mode->height);
1289 sel->r.height = sc850sl->cur_mode->height;
1290 }
1291 return 0;
1292 }
1293 return -EINVAL;
1294 }
1295
1296 static const struct dev_pm_ops sc850sl_pm_ops = {
1297 SET_RUNTIME_PM_OPS(sc850sl_runtime_suspend,
1298 sc850sl_runtime_resume, NULL)
1299 };
1300
1301 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1302 static const struct v4l2_subdev_internal_ops sc850sl_internal_ops = {
1303 .open = sc850sl_open,
1304 };
1305 #endif
1306
1307 static const struct v4l2_subdev_core_ops sc850sl_core_ops = {
1308 .s_power = sc850sl_s_power,
1309 .ioctl = sc850sl_ioctl,
1310 #ifdef CONFIG_COMPAT
1311 .compat_ioctl32 = sc850sl_compat_ioctl32,
1312 #endif
1313 };
1314
1315 static const struct v4l2_subdev_video_ops sc850sl_video_ops = {
1316 .s_stream = sc850sl_s_stream,
1317 .g_frame_interval = sc850sl_g_frame_interval,
1318 };
1319
1320 static const struct v4l2_subdev_pad_ops sc850sl_pad_ops = {
1321 .enum_mbus_code = sc850sl_enum_mbus_code,
1322 .enum_frame_size = sc850sl_enum_frame_sizes,
1323 .enum_frame_interval = sc850sl_enum_frame_interval,
1324 .get_fmt = sc850sl_get_fmt,
1325 .set_fmt = sc850sl_set_fmt,
1326 .get_selection = sc850sl_get_selection,
1327 .get_mbus_config = sc850sl_g_mbus_config,
1328 };
1329
1330 static const struct v4l2_subdev_ops sc850sl_subdev_ops = {
1331 .core = &sc850sl_core_ops,
1332 .video = &sc850sl_video_ops,
1333 .pad = &sc850sl_pad_ops,
1334 };
1335
sc850sl_modify_fps_info(struct sc850sl * sc850sl)1336 static void sc850sl_modify_fps_info(struct sc850sl *sc850sl)
1337 {
1338 const struct sc850sl_mode *mode = sc850sl->cur_mode;
1339
1340 sc850sl->cur_fps.denominator = mode->max_fps.denominator * sc850sl->cur_vts /
1341 mode->vts_def;
1342 }
1343
sc850sl_set_ctrl(struct v4l2_ctrl * ctrl)1344 static int sc850sl_set_ctrl(struct v4l2_ctrl *ctrl)
1345 {
1346 struct sc850sl *sc850sl = container_of(ctrl->handler,
1347 struct sc850sl, ctrl_handler);
1348 struct i2c_client *client = sc850sl->client;
1349 s64 max;
1350 u32 again, again_fine, dgain;
1351 int ret = 0;
1352 u32 val;
1353
1354 /* Propagate change of current control to all related controls */
1355 switch (ctrl->id) {
1356 case V4L2_CID_VBLANK:
1357 /* Update max exposure while meeting expected vblanking */
1358 max = sc850sl->cur_mode->height + ctrl->val - 8;
1359 __v4l2_ctrl_modify_range(sc850sl->exposure,
1360 sc850sl->exposure->minimum, max,
1361 sc850sl->exposure->step,
1362 sc850sl->exposure->default_value);
1363 break;
1364 }
1365
1366 if (!pm_runtime_get_if_in_use(&client->dev))
1367 return 0;
1368
1369 switch (ctrl->id) {
1370 case V4L2_CID_EXPOSURE:
1371 if (sc850sl->cur_mode->hdr_mode != NO_HDR)
1372 goto out_ctrl;
1373 ret = sc850sl_write_reg(sc850sl->client,
1374 SC850SL_REG_EXP_LONG_H,
1375 SC850SL_REG_VALUE_08BIT,
1376 SC850SL_FETCH_EXP_H(ctrl->val));
1377 ret |= sc850sl_write_reg(sc850sl->client,
1378 SC850SL_REG_EXP_LONG_M,
1379 SC850SL_REG_VALUE_08BIT,
1380 SC850SL_FETCH_EXP_M(ctrl->val));
1381 ret |= sc850sl_write_reg(sc850sl->client,
1382 SC850SL_REG_EXP_LONG_L,
1383 SC850SL_REG_VALUE_08BIT,
1384 SC850SL_FETCH_EXP_L(ctrl->val));
1385
1386 dev_dbg(&client->dev, "set exposure 0x%x\n",
1387 ctrl->val);
1388 break;
1389 case V4L2_CID_ANALOGUE_GAIN:
1390 if (sc850sl->cur_mode->hdr_mode != NO_HDR)
1391 goto out_ctrl;
1392 sc850sl_get_gain_reg(ctrl->val, &again, &again_fine, &dgain);
1393 dev_dbg(&client->dev, "recv_gain:%d set again 0x%x, again_fine 0x%x, set dgain 0x%x\n",
1394 ctrl->val, again, again_fine, dgain);
1395
1396 ret |= sc850sl_write_reg(sc850sl->client,
1397 SC850SL_REG_AGAIN,
1398 SC850SL_REG_VALUE_08BIT,
1399 again);
1400 ret |= sc850sl_write_reg(sc850sl->client,
1401 SC850SL_REG_AGAIN_FINE,
1402 SC850SL_REG_VALUE_08BIT,
1403 again_fine);
1404 ret |= sc850sl_write_reg(sc850sl->client,
1405 SC850SL_REG_DGAIN,
1406 SC850SL_REG_VALUE_08BIT,
1407 dgain);
1408 break;
1409 case V4L2_CID_VBLANK:
1410 ret = sc850sl_write_reg(sc850sl->client, SC850SL_REG_VTS,
1411 SC850SL_REG_VALUE_16BIT,
1412 ctrl->val + sc850sl->cur_mode->height);
1413 if (!ret)
1414 sc850sl->cur_vts = ctrl->val + sc850sl->cur_mode->height;
1415 sc850sl_modify_fps_info(sc850sl);
1416 dev_dbg(&client->dev, "set vblank 0x%x\n",
1417 ctrl->val);
1418 break;
1419 case V4L2_CID_TEST_PATTERN:
1420 ret = sc850sl_enable_test_pattern(sc850sl, ctrl->val);
1421 break;
1422 case V4L2_CID_HFLIP:
1423 ret = sc850sl_read_reg(sc850sl->client, SC850SL_FLIP_REG,
1424 SC850SL_REG_VALUE_08BIT, &val);
1425 if (ret)
1426 break;
1427 if (ctrl->val)
1428 val |= SC850SL_MIRROR_MASK;
1429 else
1430 val &= ~SC850SL_MIRROR_MASK;
1431 ret |= sc850sl_write_reg(sc850sl->client, SC850SL_FLIP_REG,
1432 SC850SL_REG_VALUE_08BIT, val);
1433 break;
1434 case V4L2_CID_VFLIP:
1435 ret = sc850sl_read_reg(sc850sl->client, SC850SL_FLIP_REG,
1436 SC850SL_REG_VALUE_08BIT, &val);
1437 if (ret)
1438 break;
1439 if (ctrl->val)
1440 val |= SC850SL_FLIP_MASK;
1441 else
1442 val &= ~SC850SL_FLIP_MASK;
1443 ret |= sc850sl_write_reg(sc850sl->client, SC850SL_FLIP_REG,
1444 SC850SL_REG_VALUE_08BIT, val);
1445 break;
1446 default:
1447 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1448 __func__, ctrl->id, ctrl->val);
1449 break;
1450 }
1451
1452 out_ctrl:
1453 pm_runtime_put(&client->dev);
1454
1455 return ret;
1456 }
1457
1458 static const struct v4l2_ctrl_ops sc850sl_ctrl_ops = {
1459 .s_ctrl = sc850sl_set_ctrl,
1460 };
1461
sc850sl_initialize_controls(struct sc850sl * sc850sl)1462 static int sc850sl_initialize_controls(struct sc850sl *sc850sl)
1463 {
1464 const struct sc850sl_mode *mode;
1465 struct v4l2_ctrl_handler *handler;
1466 s64 exposure_max, vblank_def;
1467 u64 pixel_rate = 0;
1468 u32 h_blank;
1469 int ret;
1470
1471 handler = &sc850sl->ctrl_handler;
1472 mode = sc850sl->cur_mode;
1473 ret = v4l2_ctrl_handler_init(handler, 9);
1474 if (ret)
1475 return ret;
1476 handler->lock = &sc850sl->mutex;
1477
1478 sc850sl->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1479 V4L2_CID_LINK_FREQ, 0, 0, link_freq_items);
1480 v4l2_ctrl_s_ctrl(sc850sl->link_freq, mode->mipi_freq_idx);
1481
1482 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1483 pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC850SL_4LANES;
1484 sc850sl->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1485 V4L2_CID_PIXEL_RATE, 0, SC850SL_MAX_PIXEL_RATE,
1486 1, pixel_rate);
1487
1488 h_blank = mode->hts_def - mode->width;
1489 sc850sl->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1490 h_blank, h_blank, 1, h_blank);
1491 if (sc850sl->hblank)
1492 sc850sl->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1493
1494 vblank_def = mode->vts_def - mode->height;
1495 sc850sl->vblank = v4l2_ctrl_new_std(handler, &sc850sl_ctrl_ops,
1496 V4L2_CID_VBLANK, vblank_def,
1497 SC850SL_VTS_MAX - mode->height,
1498 1, vblank_def);
1499
1500 exposure_max = mode->vts_def - 4; /*vts_def 0x08ca=2250*/
1501 sc850sl->exposure = v4l2_ctrl_new_std(handler, &sc850sl_ctrl_ops,
1502 V4L2_CID_EXPOSURE, SC850SL_EXPOSURE_MIN,
1503 exposure_max, SC850SL_EXPOSURE_STEP,
1504 mode->exp_def); /*exp_def 0x08c0=2240*/
1505
1506 sc850sl->anal_a_gain = v4l2_ctrl_new_std(handler, &sc850sl_ctrl_ops,
1507 V4L2_CID_ANALOGUE_GAIN, SC850SL_GAIN_MIN,
1508 SC850SL_GAIN_MAX, SC850SL_GAIN_STEP,
1509 SC850SL_GAIN_DEFAULT);
1510
1511 sc850sl->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1512 &sc850sl_ctrl_ops, V4L2_CID_TEST_PATTERN,
1513 ARRAY_SIZE(sc850sl_test_pattern_menu) - 1,
1514 0, 0, sc850sl_test_pattern_menu);
1515
1516 v4l2_ctrl_new_std(handler, &sc850sl_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1517 v4l2_ctrl_new_std(handler, &sc850sl_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1518
1519 if (handler->error) {
1520 ret = handler->error;
1521 dev_err(&sc850sl->client->dev,
1522 "Failed to init controls(%d)\n", ret);
1523 goto err_free_handler;
1524 }
1525
1526 sc850sl->subdev.ctrl_handler = handler;
1527 sc850sl->has_init_exp = false;
1528 sc850sl->cur_fps = mode->max_fps;
1529 sc850sl->cur_vts = mode->vts_def;
1530
1531 return 0;
1532
1533 err_free_handler:
1534 v4l2_ctrl_handler_free(handler);
1535
1536 return ret;
1537 }
1538
sc850sl_check_sensor_id(struct sc850sl * sc850sl,struct i2c_client * client)1539 static int sc850sl_check_sensor_id(struct sc850sl *sc850sl,
1540 struct i2c_client *client)
1541 {
1542 struct device *dev = &sc850sl->client->dev;
1543 u32 id = 0;
1544 int ret;
1545
1546 ret = sc850sl_read_reg(client, SC850SL_REG_CHIP_ID,
1547 SC850SL_REG_VALUE_16BIT, &id);
1548 if (id != CHIP_ID) {
1549 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1550 return -ENODEV;
1551 }
1552
1553 dev_info(dev, "Detected sc850sl id %06x\n", CHIP_ID);
1554
1555 return 0;
1556 }
1557
sc850sl_configure_regulators(struct sc850sl * sc850sl)1558 static int sc850sl_configure_regulators(struct sc850sl *sc850sl)
1559 {
1560 unsigned int i;
1561
1562 for (i = 0; i < SC850SL_NUM_SUPPLIES; i++)
1563 sc850sl->supplies[i].supply = sc850sl_supply_names[i];
1564
1565 return devm_regulator_bulk_get(&sc850sl->client->dev,
1566 SC850SL_NUM_SUPPLIES,
1567 sc850sl->supplies);
1568 }
1569
sc850sl_probe(struct i2c_client * client,const struct i2c_device_id * id)1570 static int sc850sl_probe(struct i2c_client *client,
1571 const struct i2c_device_id *id)
1572 {
1573 struct device *dev = &client->dev;
1574 struct device_node *node = dev->of_node;
1575 struct sc850sl *sc850sl;
1576 struct v4l2_subdev *sd;
1577 char facing[2];
1578 int ret;
1579 u32 i, hdr_mode = 0;
1580
1581 dev_info(dev, "driver version: %02x.%02x.%02x",
1582 DRIVER_VERSION >> 16,
1583 (DRIVER_VERSION & 0xff00) >> 8,
1584 DRIVER_VERSION & 0x00ff);
1585
1586 sc850sl = devm_kzalloc(dev, sizeof(*sc850sl), GFP_KERNEL);
1587 if (!sc850sl)
1588 return -ENOMEM;
1589
1590 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1591 &sc850sl->module_index);
1592 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1593 &sc850sl->module_facing);
1594 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1595 &sc850sl->module_name);
1596 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1597 &sc850sl->len_name);
1598 if (ret) {
1599 dev_err(dev, "could not get module information!\n");
1600 return -EINVAL;
1601 }
1602
1603 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1604 if (ret) {
1605 hdr_mode = NO_HDR;
1606 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1607 }
1608
1609 sc850sl->client = client;
1610 sc850sl->cfg_num = ARRAY_SIZE(supported_modes);
1611 for (i = 0; i < sc850sl->cfg_num; i++) {
1612 if (hdr_mode == supported_modes[i].hdr_mode) {
1613 sc850sl->cur_mode = &supported_modes[i];
1614 break;
1615 }
1616 }
1617
1618 sc850sl->xvclk = devm_clk_get(dev, "xvclk");
1619 if (IS_ERR(sc850sl->xvclk)) {
1620 dev_err(dev, "Failed to get xvclk\n");
1621 return -EINVAL;
1622 }
1623
1624 sc850sl->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1625 if (IS_ERR(sc850sl->reset_gpio))
1626 dev_warn(dev, "Failed to get reset-gpios\n");
1627 sc850sl->power_gpio = devm_gpiod_get(dev, "power", GPIOD_ASIS);
1628 if (IS_ERR(sc850sl->power_gpio))
1629 dev_warn(dev, "Failed to get power_gpios\n");
1630
1631 sc850sl->pinctrl = devm_pinctrl_get(dev);
1632 if (!IS_ERR(sc850sl->pinctrl)) {
1633 sc850sl->pins_default =
1634 pinctrl_lookup_state(sc850sl->pinctrl,
1635 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1636 if (IS_ERR(sc850sl->pins_default))
1637 dev_info(dev, "could not get default pinstate\n");
1638
1639 sc850sl->pins_sleep =
1640 pinctrl_lookup_state(sc850sl->pinctrl,
1641 OF_CAMERA_PINCTRL_STATE_SLEEP);
1642 if (IS_ERR(sc850sl->pins_sleep))
1643 dev_info(dev, "could not get sleep pinstate\n");
1644 } else {
1645 dev_info(dev, "no pinctrl\n");
1646 }
1647
1648 ret = sc850sl_configure_regulators(sc850sl);
1649 if (ret) {
1650 dev_err(dev, "Failed to get power regulators\n");
1651 return ret;
1652 }
1653
1654 mutex_init(&sc850sl->mutex);
1655
1656 sd = &sc850sl->subdev;
1657 v4l2_i2c_subdev_init(sd, client, &sc850sl_subdev_ops);
1658 ret = sc850sl_initialize_controls(sc850sl);
1659 if (ret)
1660 goto err_destroy_mutex;
1661
1662 ret = __sc850sl_power_on(sc850sl);
1663 if (ret)
1664 goto err_free_handler;
1665
1666 ret = sc850sl_check_sensor_id(sc850sl, client);
1667 if (ret)
1668 goto err_power_off;
1669 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1670 sd->internal_ops = &sc850sl_internal_ops;
1671 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1672 V4L2_SUBDEV_FL_HAS_EVENTS;
1673 #endif
1674 #if defined(CONFIG_MEDIA_CONTROLLER)
1675 sc850sl->pad.flags = MEDIA_PAD_FL_SOURCE;
1676 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1677 ret = media_entity_pads_init(&sd->entity, 1, &sc850sl->pad);
1678 if (ret < 0)
1679 goto err_power_off;
1680 #endif
1681
1682 memset(facing, 0, sizeof(facing));
1683 if (strcmp(sc850sl->module_facing, "back") == 0)
1684 facing[0] = 'b';
1685 else
1686 facing[0] = 'f';
1687 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1688 sc850sl->module_index, facing,
1689 SC850SL_NAME, dev_name(sd->dev));
1690
1691 ret = v4l2_async_register_subdev_sensor_common(sd);
1692 if (ret) {
1693 dev_err(dev, "v4l2 async register subdev failed\n");
1694 goto err_clean_entity;
1695 }
1696
1697 pm_runtime_set_active(dev);
1698 pm_runtime_enable(dev);
1699 pm_runtime_idle(dev);
1700
1701 return 0;
1702
1703 err_clean_entity:
1704 #if defined(CONFIG_MEDIA_CONTROLLER)
1705 media_entity_cleanup(&sd->entity);
1706 #endif
1707 err_power_off:
1708 __sc850sl_power_off(sc850sl);
1709 err_free_handler:
1710 v4l2_ctrl_handler_free(&sc850sl->ctrl_handler);
1711 err_destroy_mutex:
1712 mutex_destroy(&sc850sl->mutex);
1713
1714 return ret;
1715 }
1716
sc850sl_remove(struct i2c_client * client)1717 static int sc850sl_remove(struct i2c_client *client)
1718 {
1719 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1720 struct sc850sl *sc850sl = to_sc850sl(sd);
1721
1722 v4l2_async_unregister_subdev(sd);
1723 #if defined(CONFIG_MEDIA_CONTROLLER)
1724 media_entity_cleanup(&sd->entity);
1725 #endif
1726 v4l2_ctrl_handler_free(&sc850sl->ctrl_handler);
1727 mutex_destroy(&sc850sl->mutex);
1728
1729 pm_runtime_disable(&client->dev);
1730 if (!pm_runtime_status_suspended(&client->dev))
1731 __sc850sl_power_off(sc850sl);
1732 pm_runtime_set_suspended(&client->dev);
1733
1734 return 0;
1735 }
1736
1737 #if IS_ENABLED(CONFIG_OF)
1738 static const struct of_device_id sc850sl_of_match[] = {
1739 { .compatible = "smartsens,sc850sl" },
1740 {},
1741 };
1742 MODULE_DEVICE_TABLE(of, sc850sl_of_match);
1743 #endif
1744
1745 static const struct i2c_device_id sc850sl_match_id[] = {
1746 { "smartsens,sc850sl", 0 },
1747 { },
1748 };
1749
1750 static struct i2c_driver sc850sl_i2c_driver = {
1751 .driver = {
1752 .name = SC850SL_NAME,
1753 .pm = &sc850sl_pm_ops,
1754 .of_match_table = of_match_ptr(sc850sl_of_match),
1755 },
1756 .probe = &sc850sl_probe,
1757 .remove = &sc850sl_remove,
1758 .id_table = sc850sl_match_id,
1759 };
1760
sensor_mod_init(void)1761 static int __init sensor_mod_init(void)
1762 {
1763 return i2c_add_driver(&sc850sl_i2c_driver);
1764 }
1765
sensor_mod_exit(void)1766 static void __exit sensor_mod_exit(void)
1767 {
1768 i2c_del_driver(&sc850sl_i2c_driver);
1769 }
1770
1771 device_initcall_sync(sensor_mod_init);
1772 module_exit(sensor_mod_exit);
1773
1774 MODULE_DESCRIPTION("smartsens,sc850sl sensor driver");
1775 MODULE_LICENSE("GPL");
1776