1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * sc230ai driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun //#define DEBUG
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/pm_runtime.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun #include <linux/sysfs.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/version.h>
21*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
22*4882a593Smuzhiyun #include <linux/rk-preisp.h>
23*4882a593Smuzhiyun #include <media/media-entity.h>
24*4882a593Smuzhiyun #include <media/v4l2-async.h>
25*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
26*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
27*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
28*4882a593Smuzhiyun #include "../platform/rockchip/isp/rkisp_tb_helper.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
33*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
34*4882a593Smuzhiyun #endif
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define SC230AI_LANES 2
37*4882a593Smuzhiyun #define SC230AI_BITS_PER_SAMPLE 10
38*4882a593Smuzhiyun #define SC230AI_LINK_FREQ_185 92812500// 185.625Mbps
39*4882a593Smuzhiyun #define SC230AI_LINK_FREQ_371 185625000// 371.25Mbps
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define PIXEL_RATE_WITH_185M_10BIT (SC230AI_LINK_FREQ_185 * 2 * \
42*4882a593Smuzhiyun SC230AI_LANES / SC230AI_BITS_PER_SAMPLE)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define PIXEL_RATE_WITH_371M_10BIT (SC230AI_LINK_FREQ_371 * 2 * \
45*4882a593Smuzhiyun SC230AI_LANES / SC230AI_BITS_PER_SAMPLE)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define SC230AI_XVCLK_FREQ 27000000
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define CHIP_ID 0xcb34
50*4882a593Smuzhiyun #define SC230AI_REG_CHIP_ID 0x3107
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define SC230AI_REG_CTRL_MODE 0x0100
53*4882a593Smuzhiyun #define SC230AI_MODE_SW_STANDBY 0x0
54*4882a593Smuzhiyun #define SC230AI_MODE_STREAMING BIT(0)
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define SC230AI_REG_EXPOSURE_H 0x3e00
57*4882a593Smuzhiyun #define SC230AI_REG_EXPOSURE_M 0x3e01
58*4882a593Smuzhiyun #define SC230AI_REG_EXPOSURE_L 0x3e02
59*4882a593Smuzhiyun #define SC230AI_REG_SEXPOSURE_H 0x3e22
60*4882a593Smuzhiyun #define SC230AI_REG_SEXPOSURE_M 0x3e04
61*4882a593Smuzhiyun #define SC230AI_REG_SEXPOSURE_L 0x3e05
62*4882a593Smuzhiyun #define SC230AI_EXPOSURE_MIN 1
63*4882a593Smuzhiyun #define SC230AI_EXPOSURE_STEP 1
64*4882a593Smuzhiyun #define SC230AI_EXPOSURE_LIN_MAX (2 * 0x465 - 9)
65*4882a593Smuzhiyun #define SC230AI_EXPOSURE_HDR_MAX_S (2 * 0x465 - 9)
66*4882a593Smuzhiyun #define SC230AI_EXPOSURE_HDR_MAX_L (2 * 0x465 - 9)
67*4882a593Smuzhiyun #define SC230AI_VTS_MAX 0x7fff
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define SC230AI_REG_DIG_GAIN 0x3e06
70*4882a593Smuzhiyun #define SC230AI_REG_DIG_FINE_GAIN 0x3e07
71*4882a593Smuzhiyun #define SC230AI_REG_ANA_GAIN 0x3e09
72*4882a593Smuzhiyun #define SC230AI_REG_SDIG_GAIN 0x3e10
73*4882a593Smuzhiyun #define SC230AI_REG_SDIG_FINE_GAIN 0x3e11
74*4882a593Smuzhiyun #define SC230AI_REG_SANA_GAIN 0x3e12
75*4882a593Smuzhiyun #define SC230AI_REG_SANA_FINE_GAIN 0x3e13
76*4882a593Smuzhiyun #define SC230AI_GAIN_MIN 1000
77*4882a593Smuzhiyun #define SC230AI_GAIN_MAX 1722628 //108.512*15.875*1000
78*4882a593Smuzhiyun #define SC230AI_GAIN_STEP 1
79*4882a593Smuzhiyun #define SC230AI_GAIN_DEFAULT 1000
80*4882a593Smuzhiyun #define SC230AI_LGAIN 0
81*4882a593Smuzhiyun #define SC230AI_SGAIN 1
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define SC230AI_REG_GROUP_HOLD 0x3812
84*4882a593Smuzhiyun #define SC230AI_GROUP_HOLD_START 0x00
85*4882a593Smuzhiyun #define SC230AI_GROUP_HOLD_END 0x30
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define SC230AI_REG_HIGH_TEMP_H 0x3974
88*4882a593Smuzhiyun #define SC230AI_REG_HIGH_TEMP_L 0x3975
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define SC230AI_REG_TEST_PATTERN 0x4501
91*4882a593Smuzhiyun #define SC230AI_TEST_PATTERN_BIT_MASK BIT(3)
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define SC230AI_REG_VTS_H 0x320e
94*4882a593Smuzhiyun #define SC230AI_REG_VTS_L 0x320f
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define SC230AI_FLIP_MIRROR_REG 0x3221
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #define SC230AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
99*4882a593Smuzhiyun #define SC230AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
100*4882a593Smuzhiyun #define SC230AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun #define SC230AI_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
103*4882a593Smuzhiyun #define SC230AI_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #define SC230AI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
106*4882a593Smuzhiyun #define SC230AI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #define REG_DELAY 0xFFFE
109*4882a593Smuzhiyun #define REG_NULL 0xFFFF
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #define SC230AI_REG_VALUE_08BIT 1
112*4882a593Smuzhiyun #define SC230AI_REG_VALUE_16BIT 2
113*4882a593Smuzhiyun #define SC230AI_REG_VALUE_24BIT 3
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
116*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
117*4882a593Smuzhiyun #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
118*4882a593Smuzhiyun #define SC230AI_NAME "sc230ai"
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static const char * const sc230ai_supply_names[] = {
121*4882a593Smuzhiyun "avdd", /* Analog power */
122*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
123*4882a593Smuzhiyun "dvdd", /* Digital core power */
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun #define SC230AI_NUM_SUPPLIES ARRAY_SIZE(sc230ai_supply_names)
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun struct regval {
129*4882a593Smuzhiyun u16 addr;
130*4882a593Smuzhiyun u8 val;
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun struct sc230ai_mode {
134*4882a593Smuzhiyun u32 bus_fmt;
135*4882a593Smuzhiyun u32 width;
136*4882a593Smuzhiyun u32 height;
137*4882a593Smuzhiyun struct v4l2_fract max_fps;
138*4882a593Smuzhiyun u32 hts_def;
139*4882a593Smuzhiyun u32 vts_def;
140*4882a593Smuzhiyun u32 exp_def;
141*4882a593Smuzhiyun u32 mipi_freq_idx;
142*4882a593Smuzhiyun u32 bpp;
143*4882a593Smuzhiyun const struct regval *reg_list;
144*4882a593Smuzhiyun u32 hdr_mode;
145*4882a593Smuzhiyun u32 vc[PAD_MAX];
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun struct sc230ai {
149*4882a593Smuzhiyun struct i2c_client *client;
150*4882a593Smuzhiyun struct clk *xvclk;
151*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
152*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
153*4882a593Smuzhiyun struct regulator_bulk_data supplies[SC230AI_NUM_SUPPLIES];
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun struct pinctrl *pinctrl;
156*4882a593Smuzhiyun struct pinctrl_state *pins_default;
157*4882a593Smuzhiyun struct pinctrl_state *pins_sleep;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun struct v4l2_subdev subdev;
160*4882a593Smuzhiyun struct media_pad pad;
161*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
162*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
163*4882a593Smuzhiyun struct v4l2_ctrl *anal_gain;
164*4882a593Smuzhiyun struct v4l2_ctrl *digi_gain;
165*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
166*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
167*4882a593Smuzhiyun struct v4l2_ctrl *pixel_rate;
168*4882a593Smuzhiyun struct v4l2_ctrl *link_freq;
169*4882a593Smuzhiyun struct v4l2_ctrl *test_pattern;
170*4882a593Smuzhiyun struct mutex mutex;
171*4882a593Smuzhiyun struct v4l2_fract cur_fps;
172*4882a593Smuzhiyun bool streaming;
173*4882a593Smuzhiyun bool power_on;
174*4882a593Smuzhiyun const struct sc230ai_mode *cur_mode;
175*4882a593Smuzhiyun u32 module_index;
176*4882a593Smuzhiyun const char *module_facing;
177*4882a593Smuzhiyun const char *module_name;
178*4882a593Smuzhiyun const char *len_name;
179*4882a593Smuzhiyun u32 cur_vts;
180*4882a593Smuzhiyun bool has_init_exp;
181*4882a593Smuzhiyun bool is_thunderboot;
182*4882a593Smuzhiyun bool is_first_streamoff;
183*4882a593Smuzhiyun struct preisp_hdrae_exp_s init_hdrae_exp;
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun #define to_sc230ai(sd) container_of(sd, struct sc230ai, subdev)
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun /*
189*4882a593Smuzhiyun * Xclk 27Mhz
190*4882a593Smuzhiyun */
191*4882a593Smuzhiyun static const struct regval sc230ai_global_regs[] = {
192*4882a593Smuzhiyun {REG_NULL, 0x00},
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static const struct regval sc230ai_linear_10_640x480_regs[] = {
196*4882a593Smuzhiyun {0x0103, 0x01},
197*4882a593Smuzhiyun {0x0100, 0x00},
198*4882a593Smuzhiyun {0x36e9, 0x80},
199*4882a593Smuzhiyun {0x37f9, 0x80},
200*4882a593Smuzhiyun {0x301f, 0x2d},
201*4882a593Smuzhiyun {0x3200, 0x00},
202*4882a593Smuzhiyun {0x3201, 0x00},
203*4882a593Smuzhiyun {0x3202, 0x00},
204*4882a593Smuzhiyun {0x3203, 0x3c},
205*4882a593Smuzhiyun {0x3204, 0x07},
206*4882a593Smuzhiyun {0x3205, 0x87},
207*4882a593Smuzhiyun {0x3206, 0x04},
208*4882a593Smuzhiyun {0x3207, 0x03},
209*4882a593Smuzhiyun {0x3208, 0x02},
210*4882a593Smuzhiyun {0x3209, 0x80},
211*4882a593Smuzhiyun {0x320a, 0x01},
212*4882a593Smuzhiyun {0x320b, 0xe0},
213*4882a593Smuzhiyun {0x320e, 0x02},
214*4882a593Smuzhiyun {0x320f, 0x32},
215*4882a593Smuzhiyun {0x3210, 0x00},
216*4882a593Smuzhiyun {0x3211, 0xa2},
217*4882a593Smuzhiyun {0x3212, 0x00},
218*4882a593Smuzhiyun {0x3213, 0x02},
219*4882a593Smuzhiyun {0x3215, 0x31},
220*4882a593Smuzhiyun {0x3220, 0x01},
221*4882a593Smuzhiyun {0x3301, 0x09},
222*4882a593Smuzhiyun {0x3304, 0x50},
223*4882a593Smuzhiyun {0x3306, 0x48},
224*4882a593Smuzhiyun {0x3308, 0x18},
225*4882a593Smuzhiyun {0x3309, 0x68},
226*4882a593Smuzhiyun {0x330a, 0x00},
227*4882a593Smuzhiyun {0x330b, 0xc0},
228*4882a593Smuzhiyun {0x331e, 0x41},
229*4882a593Smuzhiyun {0x331f, 0x59},
230*4882a593Smuzhiyun {0x3333, 0x10},
231*4882a593Smuzhiyun {0x3334, 0x40},
232*4882a593Smuzhiyun {0x335d, 0x60},
233*4882a593Smuzhiyun {0x335e, 0x06},
234*4882a593Smuzhiyun {0x335f, 0x08},
235*4882a593Smuzhiyun {0x3364, 0x5e},
236*4882a593Smuzhiyun {0x337c, 0x02},
237*4882a593Smuzhiyun {0x337d, 0x0a},
238*4882a593Smuzhiyun {0x3390, 0x01},
239*4882a593Smuzhiyun {0x3391, 0x0b},
240*4882a593Smuzhiyun {0x3392, 0x0f},
241*4882a593Smuzhiyun {0x3393, 0x0c},
242*4882a593Smuzhiyun {0x3394, 0x0d},
243*4882a593Smuzhiyun {0x3395, 0x60},
244*4882a593Smuzhiyun {0x3396, 0x48},
245*4882a593Smuzhiyun {0x3397, 0x49},
246*4882a593Smuzhiyun {0x3398, 0x4f},
247*4882a593Smuzhiyun {0x3399, 0x0a},
248*4882a593Smuzhiyun {0x339a, 0x0f},
249*4882a593Smuzhiyun {0x339b, 0x14},
250*4882a593Smuzhiyun {0x339c, 0x60},
251*4882a593Smuzhiyun {0x33a2, 0x04},
252*4882a593Smuzhiyun {0x33af, 0x40},
253*4882a593Smuzhiyun {0x33b1, 0x80},
254*4882a593Smuzhiyun {0x33b3, 0x40},
255*4882a593Smuzhiyun {0x33b9, 0x0a},
256*4882a593Smuzhiyun {0x33f9, 0x70},
257*4882a593Smuzhiyun {0x33fb, 0x90},
258*4882a593Smuzhiyun {0x33fc, 0x4b},
259*4882a593Smuzhiyun {0x33fd, 0x5f},
260*4882a593Smuzhiyun {0x349f, 0x03},
261*4882a593Smuzhiyun {0x34a6, 0x4b},
262*4882a593Smuzhiyun {0x34a7, 0x4f},
263*4882a593Smuzhiyun {0x34a8, 0x30},
264*4882a593Smuzhiyun {0x34a9, 0x20},
265*4882a593Smuzhiyun {0x34aa, 0x00},
266*4882a593Smuzhiyun {0x34ab, 0xe0},
267*4882a593Smuzhiyun {0x34ac, 0x01},
268*4882a593Smuzhiyun {0x34ad, 0x00},
269*4882a593Smuzhiyun {0x34f8, 0x5f},
270*4882a593Smuzhiyun {0x34f9, 0x10},
271*4882a593Smuzhiyun {0x3630, 0xc0},
272*4882a593Smuzhiyun {0x3633, 0x44},
273*4882a593Smuzhiyun {0x3637, 0x29},
274*4882a593Smuzhiyun {0x363b, 0x20},
275*4882a593Smuzhiyun {0x3670, 0x09},
276*4882a593Smuzhiyun {0x3674, 0xb0},
277*4882a593Smuzhiyun {0x3675, 0x80},
278*4882a593Smuzhiyun {0x3676, 0x88},
279*4882a593Smuzhiyun {0x367c, 0x40},
280*4882a593Smuzhiyun {0x367d, 0x49},
281*4882a593Smuzhiyun {0x3690, 0x44},
282*4882a593Smuzhiyun {0x3691, 0x44},
283*4882a593Smuzhiyun {0x3692, 0x54},
284*4882a593Smuzhiyun {0x369c, 0x49},
285*4882a593Smuzhiyun {0x369d, 0x4f},
286*4882a593Smuzhiyun {0x36ae, 0x4b},
287*4882a593Smuzhiyun {0x36af, 0x4f},
288*4882a593Smuzhiyun {0x36b0, 0x87},
289*4882a593Smuzhiyun {0x36b1, 0x9b},
290*4882a593Smuzhiyun {0x36b2, 0xb7},
291*4882a593Smuzhiyun {0x36d0, 0x01},
292*4882a593Smuzhiyun {0x36ea, 0x0b},
293*4882a593Smuzhiyun {0x36eb, 0x04},
294*4882a593Smuzhiyun {0x36ec, 0x1c},
295*4882a593Smuzhiyun {0x36ed, 0x24},
296*4882a593Smuzhiyun {0x370f, 0x01},
297*4882a593Smuzhiyun {0x3722, 0x17},
298*4882a593Smuzhiyun {0x3728, 0x90},
299*4882a593Smuzhiyun {0x37b0, 0x17},
300*4882a593Smuzhiyun {0x37b1, 0x17},
301*4882a593Smuzhiyun {0x37b2, 0x97},
302*4882a593Smuzhiyun {0x37b3, 0x4b},
303*4882a593Smuzhiyun {0x37b4, 0x4f},
304*4882a593Smuzhiyun {0x37fa, 0x0b},
305*4882a593Smuzhiyun {0x37fb, 0x24},
306*4882a593Smuzhiyun {0x37fc, 0x10},
307*4882a593Smuzhiyun {0x37fd, 0x22},
308*4882a593Smuzhiyun {0x3901, 0x02},
309*4882a593Smuzhiyun {0x3902, 0xc5},
310*4882a593Smuzhiyun {0x3904, 0x04},
311*4882a593Smuzhiyun {0x3907, 0x00},
312*4882a593Smuzhiyun {0x3908, 0x41},
313*4882a593Smuzhiyun {0x3909, 0x00},
314*4882a593Smuzhiyun {0x390a, 0x00},
315*4882a593Smuzhiyun {0x391f, 0x04},
316*4882a593Smuzhiyun {0x3933, 0x84},
317*4882a593Smuzhiyun {0x3934, 0x02},
318*4882a593Smuzhiyun {0x3940, 0x62},
319*4882a593Smuzhiyun {0x3941, 0x00},
320*4882a593Smuzhiyun {0x3942, 0x04},
321*4882a593Smuzhiyun {0x3943, 0x03},
322*4882a593Smuzhiyun {0x3e00, 0x00},
323*4882a593Smuzhiyun {0x3e01, 0x45},
324*4882a593Smuzhiyun {0x3e02, 0xb0},
325*4882a593Smuzhiyun {0x440e, 0x02},
326*4882a593Smuzhiyun {0x450d, 0x11},
327*4882a593Smuzhiyun {0x4819, 0x05},
328*4882a593Smuzhiyun {0x481b, 0x03},
329*4882a593Smuzhiyun {0x481d, 0x0a},
330*4882a593Smuzhiyun {0x481f, 0x02},
331*4882a593Smuzhiyun {0x4821, 0x08},
332*4882a593Smuzhiyun {0x4823, 0x03},
333*4882a593Smuzhiyun {0x4825, 0x02},
334*4882a593Smuzhiyun {0x4827, 0x03},
335*4882a593Smuzhiyun {0x4829, 0x04},
336*4882a593Smuzhiyun {0x5000, 0x46},
337*4882a593Smuzhiyun {0x5010, 0x01},
338*4882a593Smuzhiyun {0x5787, 0x08},
339*4882a593Smuzhiyun {0x5788, 0x03},
340*4882a593Smuzhiyun {0x5789, 0x00},
341*4882a593Smuzhiyun {0x578a, 0x10},
342*4882a593Smuzhiyun {0x578b, 0x08},
343*4882a593Smuzhiyun {0x578c, 0x00},
344*4882a593Smuzhiyun {0x5790, 0x08},
345*4882a593Smuzhiyun {0x5791, 0x04},
346*4882a593Smuzhiyun {0x5792, 0x00},
347*4882a593Smuzhiyun {0x5793, 0x10},
348*4882a593Smuzhiyun {0x5794, 0x08},
349*4882a593Smuzhiyun {0x5795, 0x00},
350*4882a593Smuzhiyun {0x5799, 0x06},
351*4882a593Smuzhiyun {0x57ad, 0x00},
352*4882a593Smuzhiyun {0x5900, 0xf1},
353*4882a593Smuzhiyun {0x5901, 0x04},
354*4882a593Smuzhiyun {0x5ae0, 0xfe},
355*4882a593Smuzhiyun {0x5ae1, 0x40},
356*4882a593Smuzhiyun {0x5ae2, 0x3f},
357*4882a593Smuzhiyun {0x5ae3, 0x38},
358*4882a593Smuzhiyun {0x5ae4, 0x28},
359*4882a593Smuzhiyun {0x5ae5, 0x3f},
360*4882a593Smuzhiyun {0x5ae6, 0x38},
361*4882a593Smuzhiyun {0x5ae7, 0x28},
362*4882a593Smuzhiyun {0x5ae8, 0x3f},
363*4882a593Smuzhiyun {0x5ae9, 0x3c},
364*4882a593Smuzhiyun {0x5aea, 0x2c},
365*4882a593Smuzhiyun {0x5aeb, 0x3f},
366*4882a593Smuzhiyun {0x5aec, 0x3c},
367*4882a593Smuzhiyun {0x5aed, 0x2c},
368*4882a593Smuzhiyun {0x5af4, 0x3f},
369*4882a593Smuzhiyun {0x5af5, 0x38},
370*4882a593Smuzhiyun {0x5af6, 0x28},
371*4882a593Smuzhiyun {0x5af7, 0x3f},
372*4882a593Smuzhiyun {0x5af8, 0x38},
373*4882a593Smuzhiyun {0x5af9, 0x28},
374*4882a593Smuzhiyun {0x5afa, 0x3f},
375*4882a593Smuzhiyun {0x5afb, 0x3c},
376*4882a593Smuzhiyun {0x5afc, 0x2c},
377*4882a593Smuzhiyun {0x5afd, 0x3f},
378*4882a593Smuzhiyun {0x5afe, 0x3c},
379*4882a593Smuzhiyun {0x5aff, 0x2c},
380*4882a593Smuzhiyun {0x36e9, 0x20},
381*4882a593Smuzhiyun {0x37f9, 0x24},
382*4882a593Smuzhiyun {REG_NULL, 0x00},
383*4882a593Smuzhiyun };
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun /*
386*4882a593Smuzhiyun * Xclk 27Mhz
387*4882a593Smuzhiyun * max_framerate 25fps
388*4882a593Smuzhiyun * mipi_datarate per lane 371.25Mbps, 2lane
389*4882a593Smuzhiyun */
390*4882a593Smuzhiyun static const struct regval sc230ai_linear_10_1920x1080_regs[] = {
391*4882a593Smuzhiyun {0x0103, 0x01},
392*4882a593Smuzhiyun {0x0100, 0x00},
393*4882a593Smuzhiyun {0x36e9, 0x80},
394*4882a593Smuzhiyun {0x37f9, 0x80},
395*4882a593Smuzhiyun {0x301f, 0x01},
396*4882a593Smuzhiyun {0x320e, 0x05},
397*4882a593Smuzhiyun {0x320f, 0x46},
398*4882a593Smuzhiyun {0x3301, 0x07},
399*4882a593Smuzhiyun {0x3304, 0x50},
400*4882a593Smuzhiyun {0x3306, 0x70},
401*4882a593Smuzhiyun {0x3308, 0x18},
402*4882a593Smuzhiyun {0x3309, 0x68},
403*4882a593Smuzhiyun {0x330a, 0x01},
404*4882a593Smuzhiyun {0x330b, 0x20},
405*4882a593Smuzhiyun {0x3314, 0x15},
406*4882a593Smuzhiyun {0x331e, 0x41},
407*4882a593Smuzhiyun {0x331f, 0x59},
408*4882a593Smuzhiyun {0x3333, 0x10},
409*4882a593Smuzhiyun {0x3334, 0x40},
410*4882a593Smuzhiyun {0x335d, 0x60},
411*4882a593Smuzhiyun {0x335e, 0x06},
412*4882a593Smuzhiyun {0x335f, 0x08},
413*4882a593Smuzhiyun {0x3364, 0x5e},
414*4882a593Smuzhiyun {0x337c, 0x02},
415*4882a593Smuzhiyun {0x337d, 0x0a},
416*4882a593Smuzhiyun {0x3390, 0x01},
417*4882a593Smuzhiyun {0x3391, 0x0b},
418*4882a593Smuzhiyun {0x3392, 0x0f},
419*4882a593Smuzhiyun {0x3393, 0x09},
420*4882a593Smuzhiyun {0x3394, 0x0d},
421*4882a593Smuzhiyun {0x3395, 0x60},
422*4882a593Smuzhiyun {0x3396, 0x48},
423*4882a593Smuzhiyun {0x3397, 0x49},
424*4882a593Smuzhiyun {0x3398, 0x4b},
425*4882a593Smuzhiyun {0x3399, 0x06},
426*4882a593Smuzhiyun {0x339a, 0x0a},
427*4882a593Smuzhiyun {0x339b, 0x0d},
428*4882a593Smuzhiyun {0x339c, 0x60},
429*4882a593Smuzhiyun {0x33a2, 0x04},
430*4882a593Smuzhiyun {0x33ad, 0x2c},
431*4882a593Smuzhiyun {0x33af, 0x40},
432*4882a593Smuzhiyun {0x33b1, 0x80},
433*4882a593Smuzhiyun {0x33b3, 0x40},
434*4882a593Smuzhiyun {0x33b9, 0x0a},
435*4882a593Smuzhiyun {0x33f9, 0x78},
436*4882a593Smuzhiyun {0x33fb, 0xa0},
437*4882a593Smuzhiyun {0x33fc, 0x4f},
438*4882a593Smuzhiyun {0x33fd, 0x5f},
439*4882a593Smuzhiyun {0x349f, 0x03},
440*4882a593Smuzhiyun {0x34a6, 0x4b},
441*4882a593Smuzhiyun {0x34a7, 0x5f},
442*4882a593Smuzhiyun {0x34a8, 0x30},
443*4882a593Smuzhiyun {0x34a9, 0x20},
444*4882a593Smuzhiyun {0x34aa, 0x01},
445*4882a593Smuzhiyun {0x34ab, 0x28},
446*4882a593Smuzhiyun {0x34ac, 0x01},
447*4882a593Smuzhiyun {0x34ad, 0x58},
448*4882a593Smuzhiyun {0x34f8, 0x7f},
449*4882a593Smuzhiyun {0x34f9, 0x10},
450*4882a593Smuzhiyun {0x3630, 0xc0},
451*4882a593Smuzhiyun {0x3632, 0x54},
452*4882a593Smuzhiyun {0x3633, 0x44},
453*4882a593Smuzhiyun {0x363b, 0x20},
454*4882a593Smuzhiyun {0x363c, 0x08},
455*4882a593Smuzhiyun {0x3670, 0x09},
456*4882a593Smuzhiyun {0x3674, 0xb0},
457*4882a593Smuzhiyun {0x3675, 0x80},
458*4882a593Smuzhiyun {0x3676, 0x88},
459*4882a593Smuzhiyun {0x367c, 0x40},
460*4882a593Smuzhiyun {0x367d, 0x49},
461*4882a593Smuzhiyun {0x3690, 0x33},
462*4882a593Smuzhiyun {0x3691, 0x33},
463*4882a593Smuzhiyun {0x3692, 0x43},
464*4882a593Smuzhiyun {0x369c, 0x49},
465*4882a593Smuzhiyun {0x369d, 0x4f},
466*4882a593Smuzhiyun {0x36ae, 0x4b},
467*4882a593Smuzhiyun {0x36af, 0x4f},
468*4882a593Smuzhiyun {0x36b0, 0x87},
469*4882a593Smuzhiyun {0x36b1, 0x9b},
470*4882a593Smuzhiyun {0x36b2, 0xb7},
471*4882a593Smuzhiyun {0x36d0, 0x01},
472*4882a593Smuzhiyun {0x3722, 0x97},
473*4882a593Smuzhiyun {0x3724, 0x22},
474*4882a593Smuzhiyun {0x3728, 0x90},
475*4882a593Smuzhiyun {0x3901, 0x02},
476*4882a593Smuzhiyun {0x3902, 0xc5},
477*4882a593Smuzhiyun {0x3904, 0x04},
478*4882a593Smuzhiyun {0x3907, 0x00},
479*4882a593Smuzhiyun {0x3908, 0x41},
480*4882a593Smuzhiyun {0x3909, 0x00},
481*4882a593Smuzhiyun {0x390a, 0x00},
482*4882a593Smuzhiyun {0x3933, 0x84},
483*4882a593Smuzhiyun {0x3934, 0x0a},
484*4882a593Smuzhiyun {0x3940, 0x64},
485*4882a593Smuzhiyun {0x3941, 0x00},
486*4882a593Smuzhiyun {0x3942, 0x04},
487*4882a593Smuzhiyun {0x3943, 0x0b},
488*4882a593Smuzhiyun {0x3e00, 0x00},
489*4882a593Smuzhiyun {0x3e01, 0x8c},
490*4882a593Smuzhiyun {0x3e02, 0x10},
491*4882a593Smuzhiyun {0x440e, 0x02},
492*4882a593Smuzhiyun {0x450d, 0x11},
493*4882a593Smuzhiyun {0x5010, 0x01},
494*4882a593Smuzhiyun {0x5787, 0x08},
495*4882a593Smuzhiyun {0x5788, 0x03},
496*4882a593Smuzhiyun {0x5789, 0x00},
497*4882a593Smuzhiyun {0x578a, 0x10},
498*4882a593Smuzhiyun {0x578b, 0x08},
499*4882a593Smuzhiyun {0x578c, 0x00},
500*4882a593Smuzhiyun {0x5790, 0x08},
501*4882a593Smuzhiyun {0x5791, 0x04},
502*4882a593Smuzhiyun {0x5792, 0x00},
503*4882a593Smuzhiyun {0x5793, 0x10},
504*4882a593Smuzhiyun {0x5794, 0x08},
505*4882a593Smuzhiyun {0x5795, 0x00},
506*4882a593Smuzhiyun {0x5799, 0x06},
507*4882a593Smuzhiyun {0x57ad, 0x00},
508*4882a593Smuzhiyun {0x5ae0, 0xfe},
509*4882a593Smuzhiyun {0x5ae1, 0x40},
510*4882a593Smuzhiyun {0x5ae2, 0x3f},
511*4882a593Smuzhiyun {0x5ae3, 0x38},
512*4882a593Smuzhiyun {0x5ae4, 0x28},
513*4882a593Smuzhiyun {0x5ae5, 0x3f},
514*4882a593Smuzhiyun {0x5ae6, 0x38},
515*4882a593Smuzhiyun {0x5ae7, 0x28},
516*4882a593Smuzhiyun {0x5ae8, 0x3f},
517*4882a593Smuzhiyun {0x5ae9, 0x3c},
518*4882a593Smuzhiyun {0x5aea, 0x2c},
519*4882a593Smuzhiyun {0x5aeb, 0x3f},
520*4882a593Smuzhiyun {0x5aec, 0x3c},
521*4882a593Smuzhiyun {0x5aed, 0x2c},
522*4882a593Smuzhiyun {0x5af4, 0x3f},
523*4882a593Smuzhiyun {0x5af5, 0x38},
524*4882a593Smuzhiyun {0x5af6, 0x28},
525*4882a593Smuzhiyun {0x5af7, 0x3f},
526*4882a593Smuzhiyun {0x5af8, 0x38},
527*4882a593Smuzhiyun {0x5af9, 0x28},
528*4882a593Smuzhiyun {0x5afa, 0x3f},
529*4882a593Smuzhiyun {0x5afb, 0x3c},
530*4882a593Smuzhiyun {0x5afc, 0x2c},
531*4882a593Smuzhiyun {0x5afd, 0x3f},
532*4882a593Smuzhiyun {0x5afe, 0x3c},
533*4882a593Smuzhiyun {0x5aff, 0x2c},
534*4882a593Smuzhiyun {0x36e9, 0x20},
535*4882a593Smuzhiyun {0x37f9, 0x27},
536*4882a593Smuzhiyun //{0x0100, 0x01},
537*4882a593Smuzhiyun {REG_NULL, 0x00},
538*4882a593Smuzhiyun };
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun static const struct sc230ai_mode supported_modes[] = {
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun .width = 1920,
544*4882a593Smuzhiyun .height = 1080,
545*4882a593Smuzhiyun .max_fps = {
546*4882a593Smuzhiyun .numerator = 10000,
547*4882a593Smuzhiyun .denominator = 250000,
548*4882a593Smuzhiyun },
549*4882a593Smuzhiyun .exp_def = 0x0460,
550*4882a593Smuzhiyun .hts_def = 0x44C * 2,
551*4882a593Smuzhiyun .vts_def = 0x0546,
552*4882a593Smuzhiyun .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
553*4882a593Smuzhiyun .reg_list = sc230ai_linear_10_1920x1080_regs,
554*4882a593Smuzhiyun .hdr_mode = NO_HDR,
555*4882a593Smuzhiyun .bpp = 10,
556*4882a593Smuzhiyun .mipi_freq_idx = 1,
557*4882a593Smuzhiyun .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
558*4882a593Smuzhiyun }, {
559*4882a593Smuzhiyun .width = 640,
560*4882a593Smuzhiyun .height = 480,
561*4882a593Smuzhiyun .max_fps = {
562*4882a593Smuzhiyun .numerator = 10000,
563*4882a593Smuzhiyun .denominator = 1200000,
564*4882a593Smuzhiyun },
565*4882a593Smuzhiyun .exp_def = 0x0232 - 9,
566*4882a593Smuzhiyun .hts_def = 0x96 * 8,
567*4882a593Smuzhiyun .vts_def = 0x0232,
568*4882a593Smuzhiyun .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
569*4882a593Smuzhiyun .reg_list = sc230ai_linear_10_640x480_regs,
570*4882a593Smuzhiyun .hdr_mode = NO_HDR,
571*4882a593Smuzhiyun .bpp = 10,
572*4882a593Smuzhiyun .mipi_freq_idx = 1,
573*4882a593Smuzhiyun .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
574*4882a593Smuzhiyun },
575*4882a593Smuzhiyun };
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
578*4882a593Smuzhiyun SC230AI_LINK_FREQ_185,
579*4882a593Smuzhiyun SC230AI_LINK_FREQ_371
580*4882a593Smuzhiyun };
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun static const char * const sc230ai_test_pattern_menu[] = {
583*4882a593Smuzhiyun "Disabled",
584*4882a593Smuzhiyun "Vertical Color Bar Type 1",
585*4882a593Smuzhiyun "Vertical Color Bar Type 2",
586*4882a593Smuzhiyun "Vertical Color Bar Type 3",
587*4882a593Smuzhiyun "Vertical Color Bar Type 4"
588*4882a593Smuzhiyun };
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun /* Write registers up to 4 at a time */
sc230ai_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)591*4882a593Smuzhiyun static int sc230ai_write_reg(struct i2c_client *client, u16 reg,
592*4882a593Smuzhiyun u32 len, u32 val)
593*4882a593Smuzhiyun {
594*4882a593Smuzhiyun u32 buf_i, val_i;
595*4882a593Smuzhiyun u8 buf[6];
596*4882a593Smuzhiyun u8 *val_p;
597*4882a593Smuzhiyun __be32 val_be;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun if (len > 4)
600*4882a593Smuzhiyun return -EINVAL;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun buf[0] = reg >> 8;
603*4882a593Smuzhiyun buf[1] = reg & 0xff;
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun val_be = cpu_to_be32(val);
606*4882a593Smuzhiyun val_p = (u8 *)&val_be;
607*4882a593Smuzhiyun buf_i = 2;
608*4882a593Smuzhiyun val_i = 4 - len;
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun while (val_i < 4)
611*4882a593Smuzhiyun buf[buf_i++] = val_p[val_i++];
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun if (i2c_master_send(client, buf, len + 2) != len + 2)
614*4882a593Smuzhiyun return -EIO;
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
sc230ai_write_array(struct i2c_client * client,const struct regval * regs)619*4882a593Smuzhiyun static int sc230ai_write_array(struct i2c_client *client,
620*4882a593Smuzhiyun const struct regval *regs)
621*4882a593Smuzhiyun {
622*4882a593Smuzhiyun u32 i;
623*4882a593Smuzhiyun int ret = 0;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
626*4882a593Smuzhiyun ret = sc230ai_write_reg(client, regs[i].addr,
627*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, regs[i].val);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun return ret;
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun /* Read registers up to 4 at a time */
sc230ai_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)633*4882a593Smuzhiyun static int sc230ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
634*4882a593Smuzhiyun u32 *val)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun struct i2c_msg msgs[2];
637*4882a593Smuzhiyun u8 *data_be_p;
638*4882a593Smuzhiyun __be32 data_be = 0;
639*4882a593Smuzhiyun __be16 reg_addr_be = cpu_to_be16(reg);
640*4882a593Smuzhiyun int ret;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun if (len > 4 || !len)
643*4882a593Smuzhiyun return -EINVAL;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun data_be_p = (u8 *)&data_be;
646*4882a593Smuzhiyun /* Write register address */
647*4882a593Smuzhiyun msgs[0].addr = client->addr;
648*4882a593Smuzhiyun msgs[0].flags = 0;
649*4882a593Smuzhiyun msgs[0].len = 2;
650*4882a593Smuzhiyun msgs[0].buf = (u8 *)®_addr_be;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /* Read data from register */
653*4882a593Smuzhiyun msgs[1].addr = client->addr;
654*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
655*4882a593Smuzhiyun msgs[1].len = len;
656*4882a593Smuzhiyun msgs[1].buf = &data_be_p[4 - len];
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
659*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
660*4882a593Smuzhiyun return -EIO;
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun *val = be32_to_cpu(data_be);
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun return 0;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
sc230ai_get_gain_reg(struct sc230ai * sc230ai,u32 * again,u32 * dgain,u32 * dgain_fine,u32 total_gain)667*4882a593Smuzhiyun static int sc230ai_get_gain_reg(struct sc230ai *sc230ai, u32 *again, u32 *dgain,
668*4882a593Smuzhiyun u32 *dgain_fine, u32 total_gain)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun int ret = 0;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun if (total_gain < SC230AI_GAIN_MIN)
673*4882a593Smuzhiyun total_gain = SC230AI_GAIN_MIN;
674*4882a593Smuzhiyun else if (total_gain > SC230AI_GAIN_MAX)
675*4882a593Smuzhiyun total_gain = SC230AI_GAIN_MAX;
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun if (total_gain < 2000) { /* 1 ~ 2 gain*/
678*4882a593Smuzhiyun *again = 0x00;
679*4882a593Smuzhiyun *dgain = 0x00;
680*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 1000;
681*4882a593Smuzhiyun } else if (total_gain < 3391) { /* 2 ~ 3.391 gain*/
682*4882a593Smuzhiyun *again = 0x01;
683*4882a593Smuzhiyun *dgain = 0x00;
684*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 1000 / 2;
685*4882a593Smuzhiyun } else if (total_gain < 3391 * 2) { /* 3.391 ~ 6.782 gain*/
686*4882a593Smuzhiyun *again = 0x40;
687*4882a593Smuzhiyun *dgain = 0x00;
688*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391;
689*4882a593Smuzhiyun } else if (total_gain < 3391 * 4) { /* 6.782 ~ 13.564 gain*/
690*4882a593Smuzhiyun *again = 0x48;
691*4882a593Smuzhiyun *dgain = 0x00;
692*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 2;
693*4882a593Smuzhiyun } else if (total_gain < 3391 * 8) { /* 13.564 ~ 27.128 gain*/
694*4882a593Smuzhiyun *again = 0x49;
695*4882a593Smuzhiyun *dgain = 0x00;
696*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 4;
697*4882a593Smuzhiyun } else if (total_gain < 3391 * 16) { /* 27.128 ~ 54.256 gain*/
698*4882a593Smuzhiyun *again = 0x4b;
699*4882a593Smuzhiyun *dgain = 0x00;
700*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 8;
701*4882a593Smuzhiyun } else if (total_gain < 3391 * 32) { /* 54.256 ~ 108.512 gain*/
702*4882a593Smuzhiyun *again = 0x4f;
703*4882a593Smuzhiyun *dgain = 0x00;
704*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 16;
705*4882a593Smuzhiyun } else if (total_gain < 3391 * 64) { /* 108.512 ~ 217.024 gain*/
706*4882a593Smuzhiyun *again = 0x5f;
707*4882a593Smuzhiyun *dgain = 0x00;
708*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 32;
709*4882a593Smuzhiyun } else if (total_gain < 3391 * 128) { /* 217.024 ~ 434.048 gain*/
710*4882a593Smuzhiyun *again = 0x5f;
711*4882a593Smuzhiyun *dgain = 0x01;
712*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 64;
713*4882a593Smuzhiyun } else if (total_gain < 3391 * 256) { /* 434.048 ~ 868.096 gain*/
714*4882a593Smuzhiyun *again = 0x5f;
715*4882a593Smuzhiyun *dgain = 0x03;
716*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 128;
717*4882a593Smuzhiyun } else if (total_gain < 3391 * 512) { /* 868.096 ~ 1736.192 gain*/
718*4882a593Smuzhiyun *again = 0x5f;
719*4882a593Smuzhiyun *dgain = 0x07;
720*4882a593Smuzhiyun *dgain_fine = total_gain * 128 / 3391 / 128;
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun return ret;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
sc230ai_set_hdrae(struct sc230ai * sc230ai,struct preisp_hdrae_exp_s * ae)726*4882a593Smuzhiyun static int sc230ai_set_hdrae(struct sc230ai *sc230ai,
727*4882a593Smuzhiyun struct preisp_hdrae_exp_s *ae)
728*4882a593Smuzhiyun {
729*4882a593Smuzhiyun int ret = 0;
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun return ret;
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun
sc230ai_get_reso_dist(const struct sc230ai_mode * mode,struct v4l2_mbus_framefmt * framefmt)734*4882a593Smuzhiyun static int sc230ai_get_reso_dist(const struct sc230ai_mode *mode,
735*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
738*4882a593Smuzhiyun abs(mode->height - framefmt->height);
739*4882a593Smuzhiyun }
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun static const struct sc230ai_mode *
sc230ai_find_best_fit(struct v4l2_subdev_format * fmt)742*4882a593Smuzhiyun sc230ai_find_best_fit(struct v4l2_subdev_format *fmt)
743*4882a593Smuzhiyun {
744*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
745*4882a593Smuzhiyun int dist;
746*4882a593Smuzhiyun int cur_best_fit = 0;
747*4882a593Smuzhiyun int cur_best_fit_dist = -1;
748*4882a593Smuzhiyun unsigned int i;
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
751*4882a593Smuzhiyun dist = sc230ai_get_reso_dist(&supported_modes[i], framefmt);
752*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
753*4882a593Smuzhiyun cur_best_fit_dist = dist;
754*4882a593Smuzhiyun cur_best_fit = i;
755*4882a593Smuzhiyun }
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun return &supported_modes[cur_best_fit];
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
sc230ai_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)761*4882a593Smuzhiyun static int sc230ai_set_fmt(struct v4l2_subdev *sd,
762*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
763*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
764*4882a593Smuzhiyun {
765*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
766*4882a593Smuzhiyun const struct sc230ai_mode *mode;
767*4882a593Smuzhiyun s64 h_blank, vblank_def;
768*4882a593Smuzhiyun u64 pixel_rate = 0;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun mutex_lock(&sc230ai->mutex);
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun mode = sc230ai_find_best_fit(fmt);
773*4882a593Smuzhiyun fmt->format.code = mode->bus_fmt;
774*4882a593Smuzhiyun fmt->format.width = mode->width;
775*4882a593Smuzhiyun fmt->format.height = mode->height;
776*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
777*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
778*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
779*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
780*4882a593Smuzhiyun #else
781*4882a593Smuzhiyun mutex_unlock(&sc230ai->mutex);
782*4882a593Smuzhiyun return -ENOTTY;
783*4882a593Smuzhiyun #endif
784*4882a593Smuzhiyun } else {
785*4882a593Smuzhiyun sc230ai->cur_mode = mode;
786*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
787*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc230ai->hblank, h_blank,
788*4882a593Smuzhiyun h_blank, 1, h_blank);
789*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
790*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc230ai->vblank, vblank_def,
791*4882a593Smuzhiyun SC230AI_VTS_MAX - mode->height,
792*4882a593Smuzhiyun 1, vblank_def);
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(sc230ai->link_freq, mode->mipi_freq_idx);
795*4882a593Smuzhiyun pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] /
796*4882a593Smuzhiyun mode->bpp * 2 * SC230AI_LANES;
797*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl_int64(sc230ai->pixel_rate, pixel_rate);
798*4882a593Smuzhiyun sc230ai->cur_fps = mode->max_fps;
799*4882a593Smuzhiyun }
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun mutex_unlock(&sc230ai->mutex);
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun return 0;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
sc230ai_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)806*4882a593Smuzhiyun static int sc230ai_get_fmt(struct v4l2_subdev *sd,
807*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
808*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
809*4882a593Smuzhiyun {
810*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
811*4882a593Smuzhiyun const struct sc230ai_mode *mode = sc230ai->cur_mode;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun mutex_lock(&sc230ai->mutex);
814*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
815*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
816*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
817*4882a593Smuzhiyun #else
818*4882a593Smuzhiyun mutex_unlock(&sc230ai->mutex);
819*4882a593Smuzhiyun return -ENOTTY;
820*4882a593Smuzhiyun #endif
821*4882a593Smuzhiyun } else {
822*4882a593Smuzhiyun fmt->format.width = mode->width;
823*4882a593Smuzhiyun fmt->format.height = mode->height;
824*4882a593Smuzhiyun fmt->format.code = mode->bus_fmt;
825*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
826*4882a593Smuzhiyun /* format info: width/height/data type/virctual channel */
827*4882a593Smuzhiyun if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
828*4882a593Smuzhiyun fmt->reserved[0] = mode->vc[fmt->pad];
829*4882a593Smuzhiyun else
830*4882a593Smuzhiyun fmt->reserved[0] = mode->vc[PAD0];
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun mutex_unlock(&sc230ai->mutex);
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun return 0;
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
sc230ai_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)837*4882a593Smuzhiyun static int sc230ai_enum_mbus_code(struct v4l2_subdev *sd,
838*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
839*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
840*4882a593Smuzhiyun {
841*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun if (code->index != 0)
844*4882a593Smuzhiyun return -EINVAL;
845*4882a593Smuzhiyun code->code = sc230ai->cur_mode->bus_fmt;
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun return 0;
848*4882a593Smuzhiyun }
849*4882a593Smuzhiyun
sc230ai_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)850*4882a593Smuzhiyun static int sc230ai_enum_frame_sizes(struct v4l2_subdev *sd,
851*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
852*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
853*4882a593Smuzhiyun {
854*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(supported_modes))
855*4882a593Smuzhiyun return -EINVAL;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun if (fse->code != supported_modes[fse->index].bus_fmt)
858*4882a593Smuzhiyun return -EINVAL;
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun fse->min_width = supported_modes[fse->index].width;
861*4882a593Smuzhiyun fse->max_width = supported_modes[fse->index].width;
862*4882a593Smuzhiyun fse->max_height = supported_modes[fse->index].height;
863*4882a593Smuzhiyun fse->min_height = supported_modes[fse->index].height;
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun return 0;
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
sc230ai_enable_test_pattern(struct sc230ai * sc230ai,u32 pattern)868*4882a593Smuzhiyun static int sc230ai_enable_test_pattern(struct sc230ai *sc230ai, u32 pattern)
869*4882a593Smuzhiyun {
870*4882a593Smuzhiyun u32 val = 0;
871*4882a593Smuzhiyun int ret = 0;
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun ret = sc230ai_read_reg(sc230ai->client, SC230AI_REG_TEST_PATTERN,
874*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, &val);
875*4882a593Smuzhiyun if (pattern)
876*4882a593Smuzhiyun val |= SC230AI_TEST_PATTERN_BIT_MASK;
877*4882a593Smuzhiyun else
878*4882a593Smuzhiyun val &= ~SC230AI_TEST_PATTERN_BIT_MASK;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client, SC230AI_REG_TEST_PATTERN,
881*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, val);
882*4882a593Smuzhiyun return ret;
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun
sc230ai_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)885*4882a593Smuzhiyun static int sc230ai_g_frame_interval(struct v4l2_subdev *sd,
886*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
887*4882a593Smuzhiyun {
888*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
889*4882a593Smuzhiyun const struct sc230ai_mode *mode = sc230ai->cur_mode;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun if (sc230ai->streaming)
892*4882a593Smuzhiyun fi->interval = sc230ai->cur_fps;
893*4882a593Smuzhiyun else
894*4882a593Smuzhiyun fi->interval = mode->max_fps;
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun return 0;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun
sc230ai_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)899*4882a593Smuzhiyun static int sc230ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
900*4882a593Smuzhiyun struct v4l2_mbus_config *config)
901*4882a593Smuzhiyun {
902*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
903*4882a593Smuzhiyun const struct sc230ai_mode *mode = sc230ai->cur_mode;
904*4882a593Smuzhiyun u32 val = 1 << (SC230AI_LANES - 1) |
905*4882a593Smuzhiyun V4L2_MBUS_CSI2_CHANNEL_0 |
906*4882a593Smuzhiyun V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun if (mode->hdr_mode != NO_HDR)
909*4882a593Smuzhiyun val |= V4L2_MBUS_CSI2_CHANNEL_1;
910*4882a593Smuzhiyun if (mode->hdr_mode == HDR_X3)
911*4882a593Smuzhiyun val |= V4L2_MBUS_CSI2_CHANNEL_2;
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun config->type = V4L2_MBUS_CSI2_DPHY;
914*4882a593Smuzhiyun config->flags = val;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun return 0;
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun
sc230ai_get_module_inf(struct sc230ai * sc230ai,struct rkmodule_inf * inf)919*4882a593Smuzhiyun static void sc230ai_get_module_inf(struct sc230ai *sc230ai,
920*4882a593Smuzhiyun struct rkmodule_inf *inf)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
923*4882a593Smuzhiyun strscpy(inf->base.sensor, SC230AI_NAME, sizeof(inf->base.sensor));
924*4882a593Smuzhiyun strscpy(inf->base.module, sc230ai->module_name,
925*4882a593Smuzhiyun sizeof(inf->base.module));
926*4882a593Smuzhiyun strscpy(inf->base.lens, sc230ai->len_name, sizeof(inf->base.lens));
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
sc230ai_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)929*4882a593Smuzhiyun static long sc230ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
930*4882a593Smuzhiyun {
931*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
932*4882a593Smuzhiyun struct rkmodule_hdr_cfg *hdr;
933*4882a593Smuzhiyun u32 i, h, w;
934*4882a593Smuzhiyun long ret = 0;
935*4882a593Smuzhiyun u32 stream = 0;
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun switch (cmd) {
938*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
939*4882a593Smuzhiyun sc230ai_get_module_inf(sc230ai, (struct rkmodule_inf *)arg);
940*4882a593Smuzhiyun break;
941*4882a593Smuzhiyun case RKMODULE_GET_HDR_CFG:
942*4882a593Smuzhiyun hdr = (struct rkmodule_hdr_cfg *)arg;
943*4882a593Smuzhiyun hdr->esp.mode = HDR_NORMAL_VC;
944*4882a593Smuzhiyun hdr->hdr_mode = sc230ai->cur_mode->hdr_mode;
945*4882a593Smuzhiyun break;
946*4882a593Smuzhiyun case RKMODULE_SET_HDR_CFG:
947*4882a593Smuzhiyun hdr = (struct rkmodule_hdr_cfg *)arg;
948*4882a593Smuzhiyun w = sc230ai->cur_mode->width;
949*4882a593Smuzhiyun h = sc230ai->cur_mode->height;
950*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
951*4882a593Smuzhiyun if (w == supported_modes[i].width &&
952*4882a593Smuzhiyun h == supported_modes[i].height &&
953*4882a593Smuzhiyun supported_modes[i].hdr_mode == hdr->hdr_mode) {
954*4882a593Smuzhiyun sc230ai->cur_mode = &supported_modes[i];
955*4882a593Smuzhiyun break;
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun if (i == ARRAY_SIZE(supported_modes)) {
959*4882a593Smuzhiyun dev_err(&sc230ai->client->dev,
960*4882a593Smuzhiyun "not find hdr mode:%d %dx%d config\n",
961*4882a593Smuzhiyun hdr->hdr_mode, w, h);
962*4882a593Smuzhiyun ret = -EINVAL;
963*4882a593Smuzhiyun } else {
964*4882a593Smuzhiyun w = sc230ai->cur_mode->hts_def - sc230ai->cur_mode->width;
965*4882a593Smuzhiyun h = sc230ai->cur_mode->vts_def - sc230ai->cur_mode->height;
966*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc230ai->hblank, w, w, 1, w);
967*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc230ai->vblank, h,
968*4882a593Smuzhiyun SC230AI_VTS_MAX - sc230ai->cur_mode->height, 1, h);
969*4882a593Smuzhiyun sc230ai->cur_fps = sc230ai->cur_mode->max_fps;
970*4882a593Smuzhiyun }
971*4882a593Smuzhiyun break;
972*4882a593Smuzhiyun case PREISP_CMD_SET_HDRAE_EXP:
973*4882a593Smuzhiyun sc230ai_set_hdrae(sc230ai, arg);
974*4882a593Smuzhiyun break;
975*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun stream = *((u32 *)arg);
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun if (stream)
980*4882a593Smuzhiyun ret = sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
981*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, SC230AI_MODE_STREAMING);
982*4882a593Smuzhiyun else
983*4882a593Smuzhiyun ret = sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
984*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, SC230AI_MODE_SW_STANDBY);
985*4882a593Smuzhiyun break;
986*4882a593Smuzhiyun default:
987*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
988*4882a593Smuzhiyun break;
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun return ret;
992*4882a593Smuzhiyun }
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
sc230ai_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)995*4882a593Smuzhiyun static long sc230ai_compat_ioctl32(struct v4l2_subdev *sd,
996*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
997*4882a593Smuzhiyun {
998*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
999*4882a593Smuzhiyun struct rkmodule_inf *inf;
1000*4882a593Smuzhiyun struct rkmodule_hdr_cfg *hdr;
1001*4882a593Smuzhiyun struct preisp_hdrae_exp_s *hdrae;
1002*4882a593Smuzhiyun long ret;
1003*4882a593Smuzhiyun u32 stream = 0;
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun switch (cmd) {
1006*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1007*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1008*4882a593Smuzhiyun if (!inf) {
1009*4882a593Smuzhiyun ret = -ENOMEM;
1010*4882a593Smuzhiyun return ret;
1011*4882a593Smuzhiyun }
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun ret = sc230ai_ioctl(sd, cmd, inf);
1014*4882a593Smuzhiyun if (!ret) {
1015*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
1016*4882a593Smuzhiyun if (ret)
1017*4882a593Smuzhiyun return -EFAULT;
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun kfree(inf);
1020*4882a593Smuzhiyun break;
1021*4882a593Smuzhiyun case RKMODULE_GET_HDR_CFG:
1022*4882a593Smuzhiyun hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1023*4882a593Smuzhiyun if (!hdr) {
1024*4882a593Smuzhiyun ret = -ENOMEM;
1025*4882a593Smuzhiyun return ret;
1026*4882a593Smuzhiyun }
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun ret = sc230ai_ioctl(sd, cmd, hdr);
1029*4882a593Smuzhiyun if (!ret) {
1030*4882a593Smuzhiyun ret = copy_to_user(up, hdr, sizeof(*hdr));
1031*4882a593Smuzhiyun if (ret)
1032*4882a593Smuzhiyun return -EFAULT;
1033*4882a593Smuzhiyun }
1034*4882a593Smuzhiyun kfree(hdr);
1035*4882a593Smuzhiyun break;
1036*4882a593Smuzhiyun case RKMODULE_SET_HDR_CFG:
1037*4882a593Smuzhiyun hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
1038*4882a593Smuzhiyun if (!hdr) {
1039*4882a593Smuzhiyun ret = -ENOMEM;
1040*4882a593Smuzhiyun return ret;
1041*4882a593Smuzhiyun }
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun if (copy_from_user(hdr, up, sizeof(*hdr))) {
1044*4882a593Smuzhiyun kfree(hdr);
1045*4882a593Smuzhiyun return -EFAULT;
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun ret = sc230ai_ioctl(sd, cmd, hdr);
1049*4882a593Smuzhiyun kfree(hdr);
1050*4882a593Smuzhiyun break;
1051*4882a593Smuzhiyun case PREISP_CMD_SET_HDRAE_EXP:
1052*4882a593Smuzhiyun hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
1053*4882a593Smuzhiyun if (!hdrae) {
1054*4882a593Smuzhiyun ret = -ENOMEM;
1055*4882a593Smuzhiyun return ret;
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun
1058*4882a593Smuzhiyun if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
1059*4882a593Smuzhiyun kfree(hdrae);
1060*4882a593Smuzhiyun return -EFAULT;
1061*4882a593Smuzhiyun }
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun ret = sc230ai_ioctl(sd, cmd, hdrae);
1064*4882a593Smuzhiyun kfree(hdrae);
1065*4882a593Smuzhiyun break;
1066*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1067*4882a593Smuzhiyun if (copy_from_user(&stream, up, sizeof(u32)))
1068*4882a593Smuzhiyun return -EFAULT;
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun ret = sc230ai_ioctl(sd, cmd, &stream);
1071*4882a593Smuzhiyun break;
1072*4882a593Smuzhiyun default:
1073*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1074*4882a593Smuzhiyun break;
1075*4882a593Smuzhiyun }
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun return ret;
1078*4882a593Smuzhiyun }
1079*4882a593Smuzhiyun #endif
1080*4882a593Smuzhiyun
__sc230ai_start_stream(struct sc230ai * sc230ai)1081*4882a593Smuzhiyun static int __sc230ai_start_stream(struct sc230ai *sc230ai)
1082*4882a593Smuzhiyun {
1083*4882a593Smuzhiyun int ret;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun if (!sc230ai->is_thunderboot) {
1086*4882a593Smuzhiyun ret = sc230ai_write_array(sc230ai->client, sc230ai->cur_mode->reg_list);
1087*4882a593Smuzhiyun if (ret)
1088*4882a593Smuzhiyun return ret;
1089*4882a593Smuzhiyun /* In case these controls are set before streaming */
1090*4882a593Smuzhiyun ret = __v4l2_ctrl_handler_setup(&sc230ai->ctrl_handler);
1091*4882a593Smuzhiyun if (ret)
1092*4882a593Smuzhiyun return ret;
1093*4882a593Smuzhiyun if (sc230ai->has_init_exp && sc230ai->cur_mode->hdr_mode != NO_HDR) {
1094*4882a593Smuzhiyun ret = sc230ai_ioctl(&sc230ai->subdev, PREISP_CMD_SET_HDRAE_EXP,
1095*4882a593Smuzhiyun &sc230ai->init_hdrae_exp);
1096*4882a593Smuzhiyun if (ret) {
1097*4882a593Smuzhiyun dev_err(&sc230ai->client->dev,
1098*4882a593Smuzhiyun "init exp fail in hdr mode\n");
1099*4882a593Smuzhiyun return ret;
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun }
1102*4882a593Smuzhiyun }
1103*4882a593Smuzhiyun return sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
1104*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, SC230AI_MODE_STREAMING);
1105*4882a593Smuzhiyun }
1106*4882a593Smuzhiyun
__sc230ai_stop_stream(struct sc230ai * sc230ai)1107*4882a593Smuzhiyun static int __sc230ai_stop_stream(struct sc230ai *sc230ai)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun sc230ai->has_init_exp = false;
1110*4882a593Smuzhiyun if (sc230ai->is_thunderboot) {
1111*4882a593Smuzhiyun sc230ai->is_first_streamoff = true;
1112*4882a593Smuzhiyun pm_runtime_put(&sc230ai->client->dev);
1113*4882a593Smuzhiyun }
1114*4882a593Smuzhiyun return sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
1115*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, SC230AI_MODE_SW_STANDBY);
1116*4882a593Smuzhiyun }
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun static int __sc230ai_power_on(struct sc230ai *sc230ai);
sc230ai_s_stream(struct v4l2_subdev * sd,int on)1119*4882a593Smuzhiyun static int sc230ai_s_stream(struct v4l2_subdev *sd, int on)
1120*4882a593Smuzhiyun {
1121*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
1122*4882a593Smuzhiyun struct i2c_client *client = sc230ai->client;
1123*4882a593Smuzhiyun int ret = 0;
1124*4882a593Smuzhiyun
1125*4882a593Smuzhiyun mutex_lock(&sc230ai->mutex);
1126*4882a593Smuzhiyun on = !!on;
1127*4882a593Smuzhiyun if (on == sc230ai->streaming)
1128*4882a593Smuzhiyun goto unlock_and_return;
1129*4882a593Smuzhiyun
1130*4882a593Smuzhiyun if (on) {
1131*4882a593Smuzhiyun if (sc230ai->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
1132*4882a593Smuzhiyun sc230ai->is_thunderboot = false;
1133*4882a593Smuzhiyun __sc230ai_power_on(sc230ai);
1134*4882a593Smuzhiyun }
1135*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
1136*4882a593Smuzhiyun if (ret < 0) {
1137*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1138*4882a593Smuzhiyun goto unlock_and_return;
1139*4882a593Smuzhiyun }
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun ret = __sc230ai_start_stream(sc230ai);
1142*4882a593Smuzhiyun if (ret) {
1143*4882a593Smuzhiyun v4l2_err(sd, "start stream failed while write regs\n");
1144*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1145*4882a593Smuzhiyun goto unlock_and_return;
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun } else {
1148*4882a593Smuzhiyun __sc230ai_stop_stream(sc230ai);
1149*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1150*4882a593Smuzhiyun }
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun sc230ai->streaming = on;
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun unlock_and_return:
1155*4882a593Smuzhiyun mutex_unlock(&sc230ai->mutex);
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun return ret;
1158*4882a593Smuzhiyun }
1159*4882a593Smuzhiyun
sc230ai_s_power(struct v4l2_subdev * sd,int on)1160*4882a593Smuzhiyun static int sc230ai_s_power(struct v4l2_subdev *sd, int on)
1161*4882a593Smuzhiyun {
1162*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
1163*4882a593Smuzhiyun struct i2c_client *client = sc230ai->client;
1164*4882a593Smuzhiyun int ret = 0;
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun mutex_lock(&sc230ai->mutex);
1167*4882a593Smuzhiyun
1168*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
1169*4882a593Smuzhiyun if (sc230ai->power_on == !!on)
1170*4882a593Smuzhiyun goto unlock_and_return;
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun if (on) {
1173*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
1174*4882a593Smuzhiyun if (ret < 0) {
1175*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1176*4882a593Smuzhiyun goto unlock_and_return;
1177*4882a593Smuzhiyun }
1178*4882a593Smuzhiyun if (!sc230ai->is_thunderboot) {
1179*4882a593Smuzhiyun ret = sc230ai_write_array(sc230ai->client, sc230ai_global_regs);
1180*4882a593Smuzhiyun if (ret) {
1181*4882a593Smuzhiyun v4l2_err(sd, "could not set init registers\n");
1182*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1183*4882a593Smuzhiyun goto unlock_and_return;
1184*4882a593Smuzhiyun }
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun
1187*4882a593Smuzhiyun sc230ai->power_on = true;
1188*4882a593Smuzhiyun } else {
1189*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1190*4882a593Smuzhiyun sc230ai->power_on = false;
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun unlock_and_return:
1194*4882a593Smuzhiyun mutex_unlock(&sc230ai->mutex);
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun return ret;
1197*4882a593Smuzhiyun }
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
sc230ai_cal_delay(u32 cycles)1200*4882a593Smuzhiyun static inline u32 sc230ai_cal_delay(u32 cycles)
1201*4882a593Smuzhiyun {
1202*4882a593Smuzhiyun return DIV_ROUND_UP(cycles, SC230AI_XVCLK_FREQ / 1000 / 1000);
1203*4882a593Smuzhiyun }
1204*4882a593Smuzhiyun
__sc230ai_power_on(struct sc230ai * sc230ai)1205*4882a593Smuzhiyun static int __sc230ai_power_on(struct sc230ai *sc230ai)
1206*4882a593Smuzhiyun {
1207*4882a593Smuzhiyun int ret;
1208*4882a593Smuzhiyun u32 delay_us;
1209*4882a593Smuzhiyun struct device *dev = &sc230ai->client->dev;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(sc230ai->pins_default)) {
1212*4882a593Smuzhiyun ret = pinctrl_select_state(sc230ai->pinctrl,
1213*4882a593Smuzhiyun sc230ai->pins_default);
1214*4882a593Smuzhiyun if (ret < 0)
1215*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
1216*4882a593Smuzhiyun }
1217*4882a593Smuzhiyun ret = clk_set_rate(sc230ai->xvclk, SC230AI_XVCLK_FREQ);
1218*4882a593Smuzhiyun if (ret < 0)
1219*4882a593Smuzhiyun dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1220*4882a593Smuzhiyun if (clk_get_rate(sc230ai->xvclk) != SC230AI_XVCLK_FREQ)
1221*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1222*4882a593Smuzhiyun ret = clk_prepare_enable(sc230ai->xvclk);
1223*4882a593Smuzhiyun if (ret < 0) {
1224*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
1225*4882a593Smuzhiyun return ret;
1226*4882a593Smuzhiyun }
1227*4882a593Smuzhiyun if (sc230ai->is_thunderboot)
1228*4882a593Smuzhiyun return 0;
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun if (!IS_ERR(sc230ai->reset_gpio))
1231*4882a593Smuzhiyun gpiod_set_value_cansleep(sc230ai->reset_gpio, 0);
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun ret = regulator_bulk_enable(SC230AI_NUM_SUPPLIES, sc230ai->supplies);
1234*4882a593Smuzhiyun if (ret < 0) {
1235*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
1236*4882a593Smuzhiyun goto disable_clk;
1237*4882a593Smuzhiyun }
1238*4882a593Smuzhiyun
1239*4882a593Smuzhiyun if (!IS_ERR(sc230ai->reset_gpio))
1240*4882a593Smuzhiyun gpiod_set_value_cansleep(sc230ai->reset_gpio, 1);
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun usleep_range(500, 1000);
1243*4882a593Smuzhiyun if (!IS_ERR(sc230ai->pwdn_gpio))
1244*4882a593Smuzhiyun gpiod_set_value_cansleep(sc230ai->pwdn_gpio, 1);
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun if (!IS_ERR(sc230ai->reset_gpio))
1247*4882a593Smuzhiyun usleep_range(6000, 8000);
1248*4882a593Smuzhiyun else
1249*4882a593Smuzhiyun usleep_range(12000, 16000);
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun /* 8192 cycles prior to first SCCB transaction */
1252*4882a593Smuzhiyun delay_us = sc230ai_cal_delay(8192);
1253*4882a593Smuzhiyun usleep_range(delay_us, delay_us * 2);
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun return 0;
1256*4882a593Smuzhiyun
1257*4882a593Smuzhiyun disable_clk:
1258*4882a593Smuzhiyun clk_disable_unprepare(sc230ai->xvclk);
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun return ret;
1261*4882a593Smuzhiyun }
1262*4882a593Smuzhiyun
__sc230ai_power_off(struct sc230ai * sc230ai)1263*4882a593Smuzhiyun static void __sc230ai_power_off(struct sc230ai *sc230ai)
1264*4882a593Smuzhiyun {
1265*4882a593Smuzhiyun int ret;
1266*4882a593Smuzhiyun struct device *dev = &sc230ai->client->dev;
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun clk_disable_unprepare(sc230ai->xvclk);
1269*4882a593Smuzhiyun if (sc230ai->is_thunderboot) {
1270*4882a593Smuzhiyun if (sc230ai->is_first_streamoff) {
1271*4882a593Smuzhiyun sc230ai->is_thunderboot = false;
1272*4882a593Smuzhiyun sc230ai->is_first_streamoff = false;
1273*4882a593Smuzhiyun } else {
1274*4882a593Smuzhiyun return;
1275*4882a593Smuzhiyun }
1276*4882a593Smuzhiyun }
1277*4882a593Smuzhiyun if (!IS_ERR(sc230ai->pwdn_gpio))
1278*4882a593Smuzhiyun gpiod_set_value_cansleep(sc230ai->pwdn_gpio, 0);
1279*4882a593Smuzhiyun if (!IS_ERR(sc230ai->reset_gpio))
1280*4882a593Smuzhiyun gpiod_set_value_cansleep(sc230ai->reset_gpio, 0);
1281*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(sc230ai->pins_sleep)) {
1282*4882a593Smuzhiyun ret = pinctrl_select_state(sc230ai->pinctrl,
1283*4882a593Smuzhiyun sc230ai->pins_sleep);
1284*4882a593Smuzhiyun if (ret < 0)
1285*4882a593Smuzhiyun dev_dbg(dev, "could not set pins\n");
1286*4882a593Smuzhiyun }
1287*4882a593Smuzhiyun regulator_bulk_disable(SC230AI_NUM_SUPPLIES, sc230ai->supplies);
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun
sc230ai_runtime_resume(struct device * dev)1290*4882a593Smuzhiyun static int sc230ai_runtime_resume(struct device *dev)
1291*4882a593Smuzhiyun {
1292*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1293*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1294*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun return __sc230ai_power_on(sc230ai);
1297*4882a593Smuzhiyun }
1298*4882a593Smuzhiyun
sc230ai_runtime_suspend(struct device * dev)1299*4882a593Smuzhiyun static int sc230ai_runtime_suspend(struct device *dev)
1300*4882a593Smuzhiyun {
1301*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1302*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1303*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
1304*4882a593Smuzhiyun
1305*4882a593Smuzhiyun __sc230ai_power_off(sc230ai);
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun return 0;
1308*4882a593Smuzhiyun }
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc230ai_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1311*4882a593Smuzhiyun static int sc230ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1312*4882a593Smuzhiyun {
1313*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
1314*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt =
1315*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
1316*4882a593Smuzhiyun const struct sc230ai_mode *def_mode = &supported_modes[0];
1317*4882a593Smuzhiyun
1318*4882a593Smuzhiyun mutex_lock(&sc230ai->mutex);
1319*4882a593Smuzhiyun /* Initialize try_fmt */
1320*4882a593Smuzhiyun try_fmt->width = def_mode->width;
1321*4882a593Smuzhiyun try_fmt->height = def_mode->height;
1322*4882a593Smuzhiyun try_fmt->code = def_mode->bus_fmt;
1323*4882a593Smuzhiyun try_fmt->field = V4L2_FIELD_NONE;
1324*4882a593Smuzhiyun
1325*4882a593Smuzhiyun mutex_unlock(&sc230ai->mutex);
1326*4882a593Smuzhiyun /* No crop or compose */
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun return 0;
1329*4882a593Smuzhiyun }
1330*4882a593Smuzhiyun #endif
1331*4882a593Smuzhiyun
sc230ai_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1332*4882a593Smuzhiyun static int sc230ai_enum_frame_interval(struct v4l2_subdev *sd,
1333*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1334*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
1335*4882a593Smuzhiyun {
1336*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(supported_modes))
1337*4882a593Smuzhiyun return -EINVAL;
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun fie->code = supported_modes[fie->index].bus_fmt;
1340*4882a593Smuzhiyun fie->width = supported_modes[fie->index].width;
1341*4882a593Smuzhiyun fie->height = supported_modes[fie->index].height;
1342*4882a593Smuzhiyun fie->interval = supported_modes[fie->index].max_fps;
1343*4882a593Smuzhiyun fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1344*4882a593Smuzhiyun return 0;
1345*4882a593Smuzhiyun }
1346*4882a593Smuzhiyun
1347*4882a593Smuzhiyun static const struct dev_pm_ops sc230ai_pm_ops = {
1348*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(sc230ai_runtime_suspend,
1349*4882a593Smuzhiyun sc230ai_runtime_resume, NULL)
1350*4882a593Smuzhiyun };
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1353*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops sc230ai_internal_ops = {
1354*4882a593Smuzhiyun .open = sc230ai_open,
1355*4882a593Smuzhiyun };
1356*4882a593Smuzhiyun #endif
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops sc230ai_core_ops = {
1359*4882a593Smuzhiyun .s_power = sc230ai_s_power,
1360*4882a593Smuzhiyun .ioctl = sc230ai_ioctl,
1361*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1362*4882a593Smuzhiyun .compat_ioctl32 = sc230ai_compat_ioctl32,
1363*4882a593Smuzhiyun #endif
1364*4882a593Smuzhiyun };
1365*4882a593Smuzhiyun
1366*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops sc230ai_video_ops = {
1367*4882a593Smuzhiyun .s_stream = sc230ai_s_stream,
1368*4882a593Smuzhiyun .g_frame_interval = sc230ai_g_frame_interval,
1369*4882a593Smuzhiyun };
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops sc230ai_pad_ops = {
1372*4882a593Smuzhiyun .enum_mbus_code = sc230ai_enum_mbus_code,
1373*4882a593Smuzhiyun .enum_frame_size = sc230ai_enum_frame_sizes,
1374*4882a593Smuzhiyun .enum_frame_interval = sc230ai_enum_frame_interval,
1375*4882a593Smuzhiyun .get_fmt = sc230ai_get_fmt,
1376*4882a593Smuzhiyun .set_fmt = sc230ai_set_fmt,
1377*4882a593Smuzhiyun .get_mbus_config = sc230ai_g_mbus_config,
1378*4882a593Smuzhiyun };
1379*4882a593Smuzhiyun
1380*4882a593Smuzhiyun static const struct v4l2_subdev_ops sc230ai_subdev_ops = {
1381*4882a593Smuzhiyun .core = &sc230ai_core_ops,
1382*4882a593Smuzhiyun .video = &sc230ai_video_ops,
1383*4882a593Smuzhiyun .pad = &sc230ai_pad_ops,
1384*4882a593Smuzhiyun };
1385*4882a593Smuzhiyun
sc230ai_modify_fps_info(struct sc230ai * sc230ai)1386*4882a593Smuzhiyun static void sc230ai_modify_fps_info(struct sc230ai *sc230ai)
1387*4882a593Smuzhiyun {
1388*4882a593Smuzhiyun const struct sc230ai_mode *mode = sc230ai->cur_mode;
1389*4882a593Smuzhiyun
1390*4882a593Smuzhiyun sc230ai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
1391*4882a593Smuzhiyun sc230ai->cur_vts;
1392*4882a593Smuzhiyun }
1393*4882a593Smuzhiyun
sc230ai_set_ctrl(struct v4l2_ctrl * ctrl)1394*4882a593Smuzhiyun static int sc230ai_set_ctrl(struct v4l2_ctrl *ctrl)
1395*4882a593Smuzhiyun {
1396*4882a593Smuzhiyun struct sc230ai *sc230ai = container_of(ctrl->handler,
1397*4882a593Smuzhiyun struct sc230ai, ctrl_handler);
1398*4882a593Smuzhiyun struct i2c_client *client = sc230ai->client;
1399*4882a593Smuzhiyun u32 again = 0, dgain = 0, dgain_fine = 0x80;
1400*4882a593Smuzhiyun s64 max;
1401*4882a593Smuzhiyun int ret = 0;
1402*4882a593Smuzhiyun u32 val = 0;
1403*4882a593Smuzhiyun s32 temp = 0;
1404*4882a593Smuzhiyun
1405*4882a593Smuzhiyun /* Propagate change of current control to all related controls */
1406*4882a593Smuzhiyun switch (ctrl->id) {
1407*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1408*4882a593Smuzhiyun /* Update max exposure while meeting expected vblanking */
1409*4882a593Smuzhiyun max = sc230ai->cur_mode->height + ctrl->val - 4;
1410*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc230ai->exposure,
1411*4882a593Smuzhiyun sc230ai->exposure->minimum, max,
1412*4882a593Smuzhiyun sc230ai->exposure->step,
1413*4882a593Smuzhiyun sc230ai->exposure->default_value);
1414*4882a593Smuzhiyun break;
1415*4882a593Smuzhiyun }
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun if (!pm_runtime_get_if_in_use(&client->dev))
1418*4882a593Smuzhiyun return 0;
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun switch (ctrl->id) {
1421*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
1422*4882a593Smuzhiyun dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
1423*4882a593Smuzhiyun if (sc230ai->cur_mode->hdr_mode == NO_HDR) {
1424*4882a593Smuzhiyun temp = ctrl->val * 2;
1425*4882a593Smuzhiyun /* 4 least significant bits of expsoure are fractional part */
1426*4882a593Smuzhiyun ret = sc230ai_write_reg(sc230ai->client,
1427*4882a593Smuzhiyun SC230AI_REG_EXPOSURE_H,
1428*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1429*4882a593Smuzhiyun SC230AI_FETCH_EXP_H(temp));
1430*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client,
1431*4882a593Smuzhiyun SC230AI_REG_EXPOSURE_M,
1432*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1433*4882a593Smuzhiyun SC230AI_FETCH_EXP_M(temp));
1434*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client,
1435*4882a593Smuzhiyun SC230AI_REG_EXPOSURE_L,
1436*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1437*4882a593Smuzhiyun SC230AI_FETCH_EXP_L(temp));
1438*4882a593Smuzhiyun }
1439*4882a593Smuzhiyun break;
1440*4882a593Smuzhiyun case V4L2_CID_ANALOGUE_GAIN:
1441*4882a593Smuzhiyun if (sc230ai->cur_mode->hdr_mode == NO_HDR)
1442*4882a593Smuzhiyun sc230ai_get_gain_reg(sc230ai, &again, &dgain,
1443*4882a593Smuzhiyun &dgain_fine, ctrl->val);
1444*4882a593Smuzhiyun dev_dbg(&client->dev, "gain %d, ag 0x%x, dg 0x%x, dg_f 0x%x\n",
1445*4882a593Smuzhiyun ctrl->val, again, dgain, dgain_fine);
1446*4882a593Smuzhiyun ret = sc230ai_write_reg(sc230ai->client,
1447*4882a593Smuzhiyun SC230AI_REG_ANA_GAIN,
1448*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1449*4882a593Smuzhiyun again);
1450*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client,
1451*4882a593Smuzhiyun SC230AI_REG_DIG_GAIN,
1452*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1453*4882a593Smuzhiyun dgain);
1454*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client,
1455*4882a593Smuzhiyun SC230AI_REG_DIG_FINE_GAIN,
1456*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1457*4882a593Smuzhiyun dgain_fine);
1458*4882a593Smuzhiyun break;
1459*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1460*4882a593Smuzhiyun dev_dbg(&client->dev, "set blank value 0x%x\n", ctrl->val);
1461*4882a593Smuzhiyun ret = sc230ai_write_reg(sc230ai->client,
1462*4882a593Smuzhiyun SC230AI_REG_VTS_H,
1463*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1464*4882a593Smuzhiyun (ctrl->val + sc230ai->cur_mode->height)
1465*4882a593Smuzhiyun >> 8);
1466*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client,
1467*4882a593Smuzhiyun SC230AI_REG_VTS_L,
1468*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1469*4882a593Smuzhiyun (ctrl->val + sc230ai->cur_mode->height)
1470*4882a593Smuzhiyun & 0xff);
1471*4882a593Smuzhiyun sc230ai->cur_vts = ctrl->val + sc230ai->cur_mode->height;
1472*4882a593Smuzhiyun sc230ai_modify_fps_info(sc230ai);
1473*4882a593Smuzhiyun break;
1474*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
1475*4882a593Smuzhiyun ret = sc230ai_enable_test_pattern(sc230ai, ctrl->val);
1476*4882a593Smuzhiyun break;
1477*4882a593Smuzhiyun case V4L2_CID_HFLIP:
1478*4882a593Smuzhiyun ret = sc230ai_read_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
1479*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, &val);
1480*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
1481*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1482*4882a593Smuzhiyun SC230AI_FETCH_MIRROR(val, ctrl->val));
1483*4882a593Smuzhiyun break;
1484*4882a593Smuzhiyun case V4L2_CID_VFLIP:
1485*4882a593Smuzhiyun ret = sc230ai_read_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
1486*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT, &val);
1487*4882a593Smuzhiyun ret |= sc230ai_write_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
1488*4882a593Smuzhiyun SC230AI_REG_VALUE_08BIT,
1489*4882a593Smuzhiyun SC230AI_FETCH_FLIP(val, ctrl->val));
1490*4882a593Smuzhiyun break;
1491*4882a593Smuzhiyun default:
1492*4882a593Smuzhiyun dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1493*4882a593Smuzhiyun __func__, ctrl->id, ctrl->val);
1494*4882a593Smuzhiyun break;
1495*4882a593Smuzhiyun }
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1498*4882a593Smuzhiyun
1499*4882a593Smuzhiyun return ret;
1500*4882a593Smuzhiyun }
1501*4882a593Smuzhiyun
1502*4882a593Smuzhiyun static const struct v4l2_ctrl_ops sc230ai_ctrl_ops = {
1503*4882a593Smuzhiyun .s_ctrl = sc230ai_set_ctrl,
1504*4882a593Smuzhiyun };
1505*4882a593Smuzhiyun
sc230ai_initialize_controls(struct sc230ai * sc230ai)1506*4882a593Smuzhiyun static int sc230ai_initialize_controls(struct sc230ai *sc230ai)
1507*4882a593Smuzhiyun {
1508*4882a593Smuzhiyun const struct sc230ai_mode *mode;
1509*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
1510*4882a593Smuzhiyun s64 exposure_max, vblank_def;
1511*4882a593Smuzhiyun u64 dst_pixel_rate = 0;
1512*4882a593Smuzhiyun u32 h_blank;
1513*4882a593Smuzhiyun int ret;
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun handler = &sc230ai->ctrl_handler;
1516*4882a593Smuzhiyun mode = sc230ai->cur_mode;
1517*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 9);
1518*4882a593Smuzhiyun if (ret)
1519*4882a593Smuzhiyun return ret;
1520*4882a593Smuzhiyun handler->lock = &sc230ai->mutex;
1521*4882a593Smuzhiyun
1522*4882a593Smuzhiyun sc230ai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1523*4882a593Smuzhiyun V4L2_CID_LINK_FREQ,
1524*4882a593Smuzhiyun ARRAY_SIZE(link_freq_menu_items) - 1, 0,
1525*4882a593Smuzhiyun link_freq_menu_items);
1526*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(sc230ai->link_freq, mode->mipi_freq_idx);
1527*4882a593Smuzhiyun
1528*4882a593Smuzhiyun if (mode->mipi_freq_idx == 0)
1529*4882a593Smuzhiyun dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT;
1530*4882a593Smuzhiyun else if (mode->mipi_freq_idx == 1)
1531*4882a593Smuzhiyun dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT;
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun sc230ai->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1534*4882a593Smuzhiyun V4L2_CID_PIXEL_RATE, 0,
1535*4882a593Smuzhiyun PIXEL_RATE_WITH_371M_10BIT,
1536*4882a593Smuzhiyun 1, dst_pixel_rate);
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
1539*4882a593Smuzhiyun sc230ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1540*4882a593Smuzhiyun h_blank, h_blank, 1, h_blank);
1541*4882a593Smuzhiyun if (sc230ai->hblank)
1542*4882a593Smuzhiyun sc230ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1543*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
1544*4882a593Smuzhiyun sc230ai->vblank = v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
1545*4882a593Smuzhiyun V4L2_CID_VBLANK, vblank_def,
1546*4882a593Smuzhiyun SC230AI_VTS_MAX - mode->height,
1547*4882a593Smuzhiyun 1, vblank_def);
1548*4882a593Smuzhiyun exposure_max = SC230AI_EXPOSURE_LIN_MAX;
1549*4882a593Smuzhiyun sc230ai->exposure = v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
1550*4882a593Smuzhiyun V4L2_CID_EXPOSURE, SC230AI_EXPOSURE_MIN,
1551*4882a593Smuzhiyun exposure_max, SC230AI_EXPOSURE_STEP,
1552*4882a593Smuzhiyun mode->exp_def);
1553*4882a593Smuzhiyun sc230ai->anal_gain = v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
1554*4882a593Smuzhiyun V4L2_CID_ANALOGUE_GAIN, SC230AI_GAIN_MIN,
1555*4882a593Smuzhiyun SC230AI_GAIN_MAX, SC230AI_GAIN_STEP,
1556*4882a593Smuzhiyun SC230AI_GAIN_DEFAULT);
1557*4882a593Smuzhiyun sc230ai->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1558*4882a593Smuzhiyun &sc230ai_ctrl_ops,
1559*4882a593Smuzhiyun V4L2_CID_TEST_PATTERN,
1560*4882a593Smuzhiyun ARRAY_SIZE(sc230ai_test_pattern_menu) - 1,
1561*4882a593Smuzhiyun 0, 0, sc230ai_test_pattern_menu);
1562*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
1563*4882a593Smuzhiyun V4L2_CID_HFLIP, 0, 1, 1, 0);
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
1566*4882a593Smuzhiyun V4L2_CID_VFLIP, 0, 1, 1, 0);
1567*4882a593Smuzhiyun
1568*4882a593Smuzhiyun if (handler->error) {
1569*4882a593Smuzhiyun ret = handler->error;
1570*4882a593Smuzhiyun dev_err(&sc230ai->client->dev,
1571*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
1572*4882a593Smuzhiyun goto err_free_handler;
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun
1575*4882a593Smuzhiyun sc230ai->subdev.ctrl_handler = handler;
1576*4882a593Smuzhiyun sc230ai->has_init_exp = false;
1577*4882a593Smuzhiyun sc230ai->cur_fps = mode->max_fps;
1578*4882a593Smuzhiyun return 0;
1579*4882a593Smuzhiyun
1580*4882a593Smuzhiyun err_free_handler:
1581*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
1582*4882a593Smuzhiyun
1583*4882a593Smuzhiyun return ret;
1584*4882a593Smuzhiyun }
1585*4882a593Smuzhiyun
sc230ai_check_sensor_id(struct sc230ai * sc230ai,struct i2c_client * client)1586*4882a593Smuzhiyun static int sc230ai_check_sensor_id(struct sc230ai *sc230ai,
1587*4882a593Smuzhiyun struct i2c_client *client)
1588*4882a593Smuzhiyun {
1589*4882a593Smuzhiyun struct device *dev = &sc230ai->client->dev;
1590*4882a593Smuzhiyun u32 id = 0;
1591*4882a593Smuzhiyun int ret;
1592*4882a593Smuzhiyun
1593*4882a593Smuzhiyun if (sc230ai->is_thunderboot) {
1594*4882a593Smuzhiyun dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
1595*4882a593Smuzhiyun return 0;
1596*4882a593Smuzhiyun }
1597*4882a593Smuzhiyun ret = sc230ai_read_reg(client, SC230AI_REG_CHIP_ID,
1598*4882a593Smuzhiyun SC230AI_REG_VALUE_16BIT, &id);
1599*4882a593Smuzhiyun if (id != CHIP_ID) {
1600*4882a593Smuzhiyun dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1601*4882a593Smuzhiyun return -ENODEV;
1602*4882a593Smuzhiyun }
1603*4882a593Smuzhiyun
1604*4882a593Smuzhiyun dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1605*4882a593Smuzhiyun
1606*4882a593Smuzhiyun return 0;
1607*4882a593Smuzhiyun }
1608*4882a593Smuzhiyun
sc230ai_configure_regulators(struct sc230ai * sc230ai)1609*4882a593Smuzhiyun static int sc230ai_configure_regulators(struct sc230ai *sc230ai)
1610*4882a593Smuzhiyun {
1611*4882a593Smuzhiyun unsigned int i;
1612*4882a593Smuzhiyun
1613*4882a593Smuzhiyun for (i = 0; i < SC230AI_NUM_SUPPLIES; i++)
1614*4882a593Smuzhiyun sc230ai->supplies[i].supply = sc230ai_supply_names[i];
1615*4882a593Smuzhiyun
1616*4882a593Smuzhiyun return devm_regulator_bulk_get(&sc230ai->client->dev,
1617*4882a593Smuzhiyun SC230AI_NUM_SUPPLIES,
1618*4882a593Smuzhiyun sc230ai->supplies);
1619*4882a593Smuzhiyun }
1620*4882a593Smuzhiyun
sc230ai_probe(struct i2c_client * client,const struct i2c_device_id * id)1621*4882a593Smuzhiyun static int sc230ai_probe(struct i2c_client *client,
1622*4882a593Smuzhiyun const struct i2c_device_id *id)
1623*4882a593Smuzhiyun {
1624*4882a593Smuzhiyun struct device *dev = &client->dev;
1625*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1626*4882a593Smuzhiyun struct sc230ai *sc230ai;
1627*4882a593Smuzhiyun struct v4l2_subdev *sd;
1628*4882a593Smuzhiyun char facing[2];
1629*4882a593Smuzhiyun int ret;
1630*4882a593Smuzhiyun u32 i, hdr_mode = 0;
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1633*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1634*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1635*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1636*4882a593Smuzhiyun
1637*4882a593Smuzhiyun sc230ai = devm_kzalloc(dev, sizeof(*sc230ai), GFP_KERNEL);
1638*4882a593Smuzhiyun if (!sc230ai)
1639*4882a593Smuzhiyun return -ENOMEM;
1640*4882a593Smuzhiyun
1641*4882a593Smuzhiyun of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1642*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1643*4882a593Smuzhiyun &sc230ai->module_index);
1644*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1645*4882a593Smuzhiyun &sc230ai->module_facing);
1646*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1647*4882a593Smuzhiyun &sc230ai->module_name);
1648*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1649*4882a593Smuzhiyun &sc230ai->len_name);
1650*4882a593Smuzhiyun if (ret) {
1651*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
1652*4882a593Smuzhiyun return -EINVAL;
1653*4882a593Smuzhiyun }
1654*4882a593Smuzhiyun sc230ai->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
1655*4882a593Smuzhiyun sc230ai->client = client;
1656*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1657*4882a593Smuzhiyun if (hdr_mode == supported_modes[i].hdr_mode) {
1658*4882a593Smuzhiyun sc230ai->cur_mode = &supported_modes[i];
1659*4882a593Smuzhiyun break;
1660*4882a593Smuzhiyun }
1661*4882a593Smuzhiyun }
1662*4882a593Smuzhiyun if (i == ARRAY_SIZE(supported_modes))
1663*4882a593Smuzhiyun sc230ai->cur_mode = &supported_modes[0];
1664*4882a593Smuzhiyun
1665*4882a593Smuzhiyun sc230ai->xvclk = devm_clk_get(dev, "xvclk");
1666*4882a593Smuzhiyun if (IS_ERR(sc230ai->xvclk)) {
1667*4882a593Smuzhiyun dev_err(dev, "Failed to get xvclk\n");
1668*4882a593Smuzhiyun return -EINVAL;
1669*4882a593Smuzhiyun }
1670*4882a593Smuzhiyun
1671*4882a593Smuzhiyun sc230ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1672*4882a593Smuzhiyun if (IS_ERR(sc230ai->reset_gpio))
1673*4882a593Smuzhiyun dev_warn(dev, "Failed to get reset-gpios\n");
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun sc230ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1676*4882a593Smuzhiyun if (IS_ERR(sc230ai->pwdn_gpio))
1677*4882a593Smuzhiyun dev_warn(dev, "Failed to get pwdn-gpios\n");
1678*4882a593Smuzhiyun
1679*4882a593Smuzhiyun sc230ai->pinctrl = devm_pinctrl_get(dev);
1680*4882a593Smuzhiyun if (!IS_ERR(sc230ai->pinctrl)) {
1681*4882a593Smuzhiyun sc230ai->pins_default =
1682*4882a593Smuzhiyun pinctrl_lookup_state(sc230ai->pinctrl,
1683*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_DEFAULT);
1684*4882a593Smuzhiyun if (IS_ERR(sc230ai->pins_default))
1685*4882a593Smuzhiyun dev_err(dev, "could not get default pinstate\n");
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun sc230ai->pins_sleep =
1688*4882a593Smuzhiyun pinctrl_lookup_state(sc230ai->pinctrl,
1689*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_SLEEP);
1690*4882a593Smuzhiyun if (IS_ERR(sc230ai->pins_sleep))
1691*4882a593Smuzhiyun dev_err(dev, "could not get sleep pinstate\n");
1692*4882a593Smuzhiyun } else {
1693*4882a593Smuzhiyun dev_err(dev, "no pinctrl\n");
1694*4882a593Smuzhiyun }
1695*4882a593Smuzhiyun
1696*4882a593Smuzhiyun ret = sc230ai_configure_regulators(sc230ai);
1697*4882a593Smuzhiyun if (ret) {
1698*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
1699*4882a593Smuzhiyun return ret;
1700*4882a593Smuzhiyun }
1701*4882a593Smuzhiyun
1702*4882a593Smuzhiyun mutex_init(&sc230ai->mutex);
1703*4882a593Smuzhiyun
1704*4882a593Smuzhiyun sd = &sc230ai->subdev;
1705*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &sc230ai_subdev_ops);
1706*4882a593Smuzhiyun ret = sc230ai_initialize_controls(sc230ai);
1707*4882a593Smuzhiyun if (ret)
1708*4882a593Smuzhiyun goto err_destroy_mutex;
1709*4882a593Smuzhiyun
1710*4882a593Smuzhiyun ret = __sc230ai_power_on(sc230ai);
1711*4882a593Smuzhiyun if (ret)
1712*4882a593Smuzhiyun goto err_free_handler;
1713*4882a593Smuzhiyun
1714*4882a593Smuzhiyun ret = sc230ai_check_sensor_id(sc230ai, client);
1715*4882a593Smuzhiyun if (ret)
1716*4882a593Smuzhiyun goto err_power_off;
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1719*4882a593Smuzhiyun sd->internal_ops = &sc230ai_internal_ops;
1720*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1721*4882a593Smuzhiyun V4L2_SUBDEV_FL_HAS_EVENTS;
1722*4882a593Smuzhiyun #endif
1723*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1724*4882a593Smuzhiyun sc230ai->pad.flags = MEDIA_PAD_FL_SOURCE;
1725*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1726*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &sc230ai->pad);
1727*4882a593Smuzhiyun if (ret < 0)
1728*4882a593Smuzhiyun goto err_power_off;
1729*4882a593Smuzhiyun #endif
1730*4882a593Smuzhiyun
1731*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1732*4882a593Smuzhiyun if (strcmp(sc230ai->module_facing, "back") == 0)
1733*4882a593Smuzhiyun facing[0] = 'b';
1734*4882a593Smuzhiyun else
1735*4882a593Smuzhiyun facing[0] = 'f';
1736*4882a593Smuzhiyun
1737*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1738*4882a593Smuzhiyun sc230ai->module_index, facing,
1739*4882a593Smuzhiyun SC230AI_NAME, dev_name(sd->dev));
1740*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
1741*4882a593Smuzhiyun if (ret) {
1742*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
1743*4882a593Smuzhiyun goto err_clean_entity;
1744*4882a593Smuzhiyun }
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun pm_runtime_set_active(dev);
1747*4882a593Smuzhiyun pm_runtime_enable(dev);
1748*4882a593Smuzhiyun if (sc230ai->is_thunderboot)
1749*4882a593Smuzhiyun pm_runtime_get_sync(dev);
1750*4882a593Smuzhiyun else
1751*4882a593Smuzhiyun pm_runtime_idle(dev);
1752*4882a593Smuzhiyun
1753*4882a593Smuzhiyun return 0;
1754*4882a593Smuzhiyun
1755*4882a593Smuzhiyun err_clean_entity:
1756*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1757*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1758*4882a593Smuzhiyun #endif
1759*4882a593Smuzhiyun err_power_off:
1760*4882a593Smuzhiyun __sc230ai_power_off(sc230ai);
1761*4882a593Smuzhiyun err_free_handler:
1762*4882a593Smuzhiyun v4l2_ctrl_handler_free(&sc230ai->ctrl_handler);
1763*4882a593Smuzhiyun err_destroy_mutex:
1764*4882a593Smuzhiyun mutex_destroy(&sc230ai->mutex);
1765*4882a593Smuzhiyun
1766*4882a593Smuzhiyun return ret;
1767*4882a593Smuzhiyun }
1768*4882a593Smuzhiyun
sc230ai_remove(struct i2c_client * client)1769*4882a593Smuzhiyun static int sc230ai_remove(struct i2c_client *client)
1770*4882a593Smuzhiyun {
1771*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1772*4882a593Smuzhiyun struct sc230ai *sc230ai = to_sc230ai(sd);
1773*4882a593Smuzhiyun
1774*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1775*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1776*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1777*4882a593Smuzhiyun #endif
1778*4882a593Smuzhiyun v4l2_ctrl_handler_free(&sc230ai->ctrl_handler);
1779*4882a593Smuzhiyun mutex_destroy(&sc230ai->mutex);
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1782*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
1783*4882a593Smuzhiyun __sc230ai_power_off(sc230ai);
1784*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1785*4882a593Smuzhiyun
1786*4882a593Smuzhiyun return 0;
1787*4882a593Smuzhiyun }
1788*4882a593Smuzhiyun
1789*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1790*4882a593Smuzhiyun static const struct of_device_id sc230ai_of_match[] = {
1791*4882a593Smuzhiyun { .compatible = "smartsens,sc230ai" },
1792*4882a593Smuzhiyun {},
1793*4882a593Smuzhiyun };
1794*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sc230ai_of_match);
1795*4882a593Smuzhiyun #endif
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun static const struct i2c_device_id sc230ai_match_id[] = {
1798*4882a593Smuzhiyun { "smartsens,sc230ai", 0 },
1799*4882a593Smuzhiyun { },
1800*4882a593Smuzhiyun };
1801*4882a593Smuzhiyun
1802*4882a593Smuzhiyun static struct i2c_driver sc230ai_i2c_driver = {
1803*4882a593Smuzhiyun .driver = {
1804*4882a593Smuzhiyun .name = SC230AI_NAME,
1805*4882a593Smuzhiyun .pm = &sc230ai_pm_ops,
1806*4882a593Smuzhiyun .of_match_table = of_match_ptr(sc230ai_of_match),
1807*4882a593Smuzhiyun },
1808*4882a593Smuzhiyun .probe = &sc230ai_probe,
1809*4882a593Smuzhiyun .remove = &sc230ai_remove,
1810*4882a593Smuzhiyun .id_table = sc230ai_match_id,
1811*4882a593Smuzhiyun };
1812*4882a593Smuzhiyun
sensor_mod_init(void)1813*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1814*4882a593Smuzhiyun {
1815*4882a593Smuzhiyun return i2c_add_driver(&sc230ai_i2c_driver);
1816*4882a593Smuzhiyun }
1817*4882a593Smuzhiyun
sensor_mod_exit(void)1818*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1819*4882a593Smuzhiyun {
1820*4882a593Smuzhiyun i2c_del_driver(&sc230ai_i2c_driver);
1821*4882a593Smuzhiyun }
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
1824*4882a593Smuzhiyun subsys_initcall(sensor_mod_init);
1825*4882a593Smuzhiyun #else
1826*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1827*4882a593Smuzhiyun #endif
1828*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1829*4882a593Smuzhiyun
1830*4882a593Smuzhiyun MODULE_DESCRIPTION("smartsens sc230ai sensor driver");
1831*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1832