1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * sc2239 driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * V0.0X01.0X00 first version.
8*4882a593Smuzhiyun * V0.0X01.0X01 add quick stream support.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun //#define DEBUG
11*4882a593Smuzhiyun #include <linux/clk.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun #include <linux/sysfs.h>
20*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/version.h>
23*4882a593Smuzhiyun #include <media/media-entity.h>
24*4882a593Smuzhiyun #include <media/v4l2-async.h>
25*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
26*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
31*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
32*4882a593Smuzhiyun #endif
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define SC2239_LANES 1
35*4882a593Smuzhiyun #define SC2239_BITS_PER_SAMPLE 10
36*4882a593Smuzhiyun #define SC2239_LINK_FREQ 371250000 // 742.5Mbps
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define SC2239_PIXEL_RATE (SC2239_LINK_FREQ * 2 * \
39*4882a593Smuzhiyun SC2239_LANES / SC2239_BITS_PER_SAMPLE)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define SC2239_XVCLK_FREQ 24000000
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define CHIP_ID 0xcb10
44*4882a593Smuzhiyun #define SC2239_REG_CHIP_ID 0x3107
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define SC2239_REG_CTRL_MODE 0x0100
47*4882a593Smuzhiyun #define SC2239_MODE_SW_STANDBY 0x0
48*4882a593Smuzhiyun #define SC2239_MODE_STREAMING BIT(0)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define SC2239_REG_EXPOSURE 0x3e00
51*4882a593Smuzhiyun #define SC2239_EXPOSURE_MIN 1
52*4882a593Smuzhiyun #define SC2239_EXPOSURE_STEP 1
53*4882a593Smuzhiyun #define SC2239_VTS_MAX 0xffff
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define SC2239_REG_COARSE_AGAIN 0x3e08
56*4882a593Smuzhiyun #define SC2239_REG_FINE_AGAIN 0x3e09
57*4882a593Smuzhiyun #define ANALOG_GAIN_MIN 0x20
58*4882a593Smuzhiyun #define ANALOG_GAIN_MAX 0x1F8
59*4882a593Smuzhiyun #define ANALOG_GAIN_STEP 1
60*4882a593Smuzhiyun #define ANALOG_GAIN_DEFAULT 0x40
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define SC4238_GROUP_UPDATE_ADDRESS 0x3812
63*4882a593Smuzhiyun #define SC4238_GROUP_UPDATE_START_DATA 0x00
64*4882a593Smuzhiyun #define SC4238_GROUP_UPDATE_END_DATA 0x30
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define SC2239_REG_TEST_PATTERN 0x4501
67*4882a593Smuzhiyun #define SC2239_TEST_PATTERN_BIT_MASK BIT(3)
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define SC2239_REG_VTS 0x320e
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun #define REG_NULL 0xFFFF
72*4882a593Smuzhiyun #define DELAY_MS 0xEEEE /* Array delay token */
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun #define SC2239_REG_VALUE_08BIT 1
75*4882a593Smuzhiyun #define SC2239_REG_VALUE_16BIT 2
76*4882a593Smuzhiyun #define SC2239_REG_VALUE_24BIT 3
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define PIX_FORMAT MEDIA_BUS_FMT_SBGGR10_1X10
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define SC2239_NAME "sc2239"
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const char * const sc2239_supply_names[] = {
83*4882a593Smuzhiyun "avdd", /* Analog power */
84*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
85*4882a593Smuzhiyun "dvdd", /* Digital core power */
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define SC2239_NUM_SUPPLIES ARRAY_SIZE(sc2239_supply_names)
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct regval {
91*4882a593Smuzhiyun u16 addr;
92*4882a593Smuzhiyun u8 val;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct sc2239_mode {
96*4882a593Smuzhiyun u32 width;
97*4882a593Smuzhiyun u32 height;
98*4882a593Smuzhiyun struct v4l2_fract max_fps;
99*4882a593Smuzhiyun u32 hts_def;
100*4882a593Smuzhiyun u32 vts_def;
101*4882a593Smuzhiyun u32 exp_def;
102*4882a593Smuzhiyun const struct regval *reg_list;
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun struct sc2239 {
106*4882a593Smuzhiyun struct i2c_client *client;
107*4882a593Smuzhiyun struct clk *xvclk;
108*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
109*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
110*4882a593Smuzhiyun struct regulator_bulk_data supplies[SC2239_NUM_SUPPLIES];
111*4882a593Smuzhiyun struct v4l2_subdev subdev;
112*4882a593Smuzhiyun struct media_pad pad;
113*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
114*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
115*4882a593Smuzhiyun struct v4l2_ctrl *anal_gain;
116*4882a593Smuzhiyun struct v4l2_ctrl *digi_gain;
117*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
118*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
119*4882a593Smuzhiyun struct v4l2_ctrl *test_pattern;
120*4882a593Smuzhiyun struct mutex mutex;
121*4882a593Smuzhiyun struct v4l2_fract cur_fps;
122*4882a593Smuzhiyun u32 cur_vts;
123*4882a593Smuzhiyun bool streaming;
124*4882a593Smuzhiyun bool power_on;
125*4882a593Smuzhiyun const struct sc2239_mode *cur_mode;
126*4882a593Smuzhiyun u32 module_index;
127*4882a593Smuzhiyun const char *module_facing;
128*4882a593Smuzhiyun const char *module_name;
129*4882a593Smuzhiyun const char *len_name;
130*4882a593Smuzhiyun u32 old_gain;
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #define to_sc2239(sd) container_of(sd, struct sc2239, subdev)
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun * Xclk 24Mhz
137*4882a593Smuzhiyun * max_framerate 30fps
138*4882a593Smuzhiyun * mipi_datarate per lane 742.5Mbps, 1 lane
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun static const struct regval sc2239_global_regs[] = {
141*4882a593Smuzhiyun {0x0103, 0x01},
142*4882a593Smuzhiyun {0x0100, 0x00},
143*4882a593Smuzhiyun {0x36e9, 0x80},
144*4882a593Smuzhiyun {0x36f9, 0x80},
145*4882a593Smuzhiyun {0x301f, 0x34},
146*4882a593Smuzhiyun {0x3038, 0x44},
147*4882a593Smuzhiyun {0x3253, 0x12},
148*4882a593Smuzhiyun {0x3301, 0x05},
149*4882a593Smuzhiyun {0x3304, 0xa8},
150*4882a593Smuzhiyun {0x3306, 0x68},
151*4882a593Smuzhiyun {0x3308, 0x10},
152*4882a593Smuzhiyun {0x3309, 0x48},
153*4882a593Smuzhiyun {0x330a, 0x01},
154*4882a593Smuzhiyun {0x330b, 0x40},
155*4882a593Smuzhiyun {0x331e, 0xa1},
156*4882a593Smuzhiyun {0x331f, 0x41},
157*4882a593Smuzhiyun {0x3333, 0x10},
158*4882a593Smuzhiyun {0x3364, 0x17},
159*4882a593Smuzhiyun {0x3390, 0x08},
160*4882a593Smuzhiyun {0x3391, 0x18},
161*4882a593Smuzhiyun {0x3392, 0x38},
162*4882a593Smuzhiyun {0x3393, 0x08},
163*4882a593Smuzhiyun {0x3394, 0x0d},
164*4882a593Smuzhiyun {0x3395, 0x70},
165*4882a593Smuzhiyun {0x33af, 0x20},
166*4882a593Smuzhiyun {0x360f, 0x01},
167*4882a593Smuzhiyun {0x3630, 0x00},
168*4882a593Smuzhiyun {0x3634, 0x64},
169*4882a593Smuzhiyun {0x3637, 0x10},
170*4882a593Smuzhiyun {0x363c, 0x05},
171*4882a593Smuzhiyun {0x3670, 0x0c},
172*4882a593Smuzhiyun {0x3671, 0xc2},
173*4882a593Smuzhiyun {0x3672, 0x02},
174*4882a593Smuzhiyun {0x3673, 0x02},
175*4882a593Smuzhiyun {0x3677, 0x84},
176*4882a593Smuzhiyun {0x3678, 0x84},
177*4882a593Smuzhiyun {0x3679, 0x8e},
178*4882a593Smuzhiyun {0x367a, 0x18},
179*4882a593Smuzhiyun {0x367b, 0x38},
180*4882a593Smuzhiyun {0x367e, 0x08},
181*4882a593Smuzhiyun {0x367f, 0x38},
182*4882a593Smuzhiyun {0x3690, 0x64},
183*4882a593Smuzhiyun {0x3691, 0x64},
184*4882a593Smuzhiyun {0x3692, 0x64},
185*4882a593Smuzhiyun {0x369c, 0x08},
186*4882a593Smuzhiyun {0x369d, 0x18},
187*4882a593Smuzhiyun {0x36ea, 0x75},
188*4882a593Smuzhiyun {0x36ed, 0x24},
189*4882a593Smuzhiyun {0x36fa, 0x75},
190*4882a593Smuzhiyun {0x36fb, 0x00},
191*4882a593Smuzhiyun {0x36fc, 0x10},
192*4882a593Smuzhiyun {0x36fd, 0x34},
193*4882a593Smuzhiyun {0x3904, 0x08},
194*4882a593Smuzhiyun {0x3908, 0x82},
195*4882a593Smuzhiyun {0x3933, 0x82},
196*4882a593Smuzhiyun {0x3934, 0x1b},
197*4882a593Smuzhiyun {0x3940, 0x77},
198*4882a593Smuzhiyun {0x3941, 0x18},
199*4882a593Smuzhiyun {0x3942, 0x02},
200*4882a593Smuzhiyun {0x3943, 0x1c},
201*4882a593Smuzhiyun {0x3944, 0x0b},
202*4882a593Smuzhiyun {0x3945, 0x80},
203*4882a593Smuzhiyun {0x3e01, 0x8c},
204*4882a593Smuzhiyun {0x3e02, 0x20},
205*4882a593Smuzhiyun {0x4509, 0x20},
206*4882a593Smuzhiyun {0x4800, 0x64},
207*4882a593Smuzhiyun {0x4819, 0x09},
208*4882a593Smuzhiyun {0x481b, 0x05},
209*4882a593Smuzhiyun {0x481d, 0x14},
210*4882a593Smuzhiyun {0x4821, 0x0a},
211*4882a593Smuzhiyun {0x4823, 0x05},
212*4882a593Smuzhiyun {0x5000, 0x06},
213*4882a593Smuzhiyun {0x5780, 0x7f},
214*4882a593Smuzhiyun {0x5781, 0x04},
215*4882a593Smuzhiyun {0x5782, 0x03},
216*4882a593Smuzhiyun {0x5783, 0x02},
217*4882a593Smuzhiyun {0x5784, 0x01},
218*4882a593Smuzhiyun {0x5785, 0x18},
219*4882a593Smuzhiyun {0x5786, 0x10},
220*4882a593Smuzhiyun {0x5787, 0x08},
221*4882a593Smuzhiyun {0x5788, 0x02},
222*4882a593Smuzhiyun {0x5789, 0x20},
223*4882a593Smuzhiyun {0x578a, 0x7f},
224*4882a593Smuzhiyun {0x36e9, 0x29},
225*4882a593Smuzhiyun {0x36f9, 0x29},
226*4882a593Smuzhiyun {DELAY_MS, 0x0a},
227*4882a593Smuzhiyun {REG_NULL, 0x00},
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun /*
231*4882a593Smuzhiyun * Xclk 24Mhz
232*4882a593Smuzhiyun * max_framerate 30fps
233*4882a593Smuzhiyun * mipi_datarate per lane 742.5Mbps, 1lane
234*4882a593Smuzhiyun */
235*4882a593Smuzhiyun static const struct regval sc2239_1920x1080_regs_1lane[] = {
236*4882a593Smuzhiyun {REG_NULL, 0x00},
237*4882a593Smuzhiyun };
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun static const struct sc2239_mode supported_modes[] = {
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun .width = 1920,
242*4882a593Smuzhiyun .height = 1080,
243*4882a593Smuzhiyun .max_fps = {
244*4882a593Smuzhiyun .numerator = 10000,
245*4882a593Smuzhiyun .denominator = 300000,
246*4882a593Smuzhiyun },
247*4882a593Smuzhiyun .exp_def = 0x0400,
248*4882a593Smuzhiyun .hts_def = 0x44C * 2,
249*4882a593Smuzhiyun .vts_def = 0x0465,
250*4882a593Smuzhiyun .reg_list = sc2239_1920x1080_regs_1lane,
251*4882a593Smuzhiyun },
252*4882a593Smuzhiyun };
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun static const char * const sc2239_test_pattern_menu[] = {
255*4882a593Smuzhiyun "Disabled",
256*4882a593Smuzhiyun "Vertical Color Bar Type 1",
257*4882a593Smuzhiyun "Vertical Color Bar Type 2",
258*4882a593Smuzhiyun "Vertical Color Bar Type 3",
259*4882a593Smuzhiyun "Vertical Color Bar Type 4"
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
263*4882a593Smuzhiyun SC2239_LINK_FREQ
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun /* Write registers up to 4 at a time */
sc2239_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)267*4882a593Smuzhiyun static int sc2239_write_reg(struct i2c_client *client,
268*4882a593Smuzhiyun u16 reg, u32 len, u32 val)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun u32 buf_i, val_i;
271*4882a593Smuzhiyun u8 buf[6];
272*4882a593Smuzhiyun u8 *val_p;
273*4882a593Smuzhiyun __be32 val_be;
274*4882a593Smuzhiyun u32 ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun if (len > 4)
277*4882a593Smuzhiyun return -EINVAL;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun buf[0] = reg >> 8;
280*4882a593Smuzhiyun buf[1] = reg & 0xff;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun val_be = cpu_to_be32(val);
283*4882a593Smuzhiyun val_p = (u8 *)&val_be;
284*4882a593Smuzhiyun buf_i = 2;
285*4882a593Smuzhiyun val_i = 4 - len;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun while (val_i < 4)
288*4882a593Smuzhiyun buf[buf_i++] = val_p[val_i++];
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun ret = i2c_master_send(client, buf, len + 2);
291*4882a593Smuzhiyun if (ret != len + 2)
292*4882a593Smuzhiyun return -EIO;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
sc2239_write_array(struct i2c_client * client,const struct regval * regs)297*4882a593Smuzhiyun static int sc2239_write_array(struct i2c_client *client,
298*4882a593Smuzhiyun const struct regval *regs)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun u32 i;
301*4882a593Smuzhiyun int delay_ms = 0, ret = 0;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
304*4882a593Smuzhiyun if (regs[i].addr == DELAY_MS) {
305*4882a593Smuzhiyun delay_ms = regs[i].val;
306*4882a593Smuzhiyun dev_info(&client->dev, "delay(%d) ms !\n", delay_ms);
307*4882a593Smuzhiyun usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
308*4882a593Smuzhiyun i++;
309*4882a593Smuzhiyun continue;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun ret = sc2239_write_reg(client, regs[i].addr,
312*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, regs[i].val);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun return ret;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* Read registers up to 4 at a time */
sc2239_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)319*4882a593Smuzhiyun static int sc2239_read_reg(struct i2c_client *client,
320*4882a593Smuzhiyun u16 reg, unsigned int len, u32 *val)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun struct i2c_msg msgs[2];
323*4882a593Smuzhiyun u8 *data_be_p;
324*4882a593Smuzhiyun __be32 data_be = 0;
325*4882a593Smuzhiyun __be16 reg_addr_be = cpu_to_be16(reg);
326*4882a593Smuzhiyun int ret;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun if (len > 4 || !len)
329*4882a593Smuzhiyun return -EINVAL;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun data_be_p = (u8 *)&data_be;
332*4882a593Smuzhiyun /* Write register address */
333*4882a593Smuzhiyun msgs[0].addr = client->addr;
334*4882a593Smuzhiyun msgs[0].flags = 0;
335*4882a593Smuzhiyun msgs[0].len = 2;
336*4882a593Smuzhiyun msgs[0].buf = (u8 *)®_addr_be;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun /* Read data from register */
339*4882a593Smuzhiyun msgs[1].addr = client->addr;
340*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
341*4882a593Smuzhiyun msgs[1].len = len;
342*4882a593Smuzhiyun msgs[1].buf = &data_be_p[4 - len];
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
345*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
346*4882a593Smuzhiyun return -EIO;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun *val = be32_to_cpu(data_be);
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun return 0;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
sc2239_get_reso_dist(const struct sc2239_mode * mode,struct v4l2_mbus_framefmt * framefmt)353*4882a593Smuzhiyun static int sc2239_get_reso_dist(const struct sc2239_mode *mode,
354*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun return abs(mode->width - framefmt->width) +
357*4882a593Smuzhiyun abs(mode->height - framefmt->height);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun static const struct sc2239_mode *
sc2239_find_best_fit(struct v4l2_subdev_format * fmt)361*4882a593Smuzhiyun sc2239_find_best_fit(struct v4l2_subdev_format *fmt)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun struct v4l2_mbus_framefmt *framefmt = &fmt->format;
364*4882a593Smuzhiyun int dist;
365*4882a593Smuzhiyun int cur_best_fit = 0;
366*4882a593Smuzhiyun int cur_best_fit_dist = -1;
367*4882a593Smuzhiyun unsigned int i;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
370*4882a593Smuzhiyun dist = sc2239_get_reso_dist(&supported_modes[i], framefmt);
371*4882a593Smuzhiyun if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
372*4882a593Smuzhiyun cur_best_fit_dist = dist;
373*4882a593Smuzhiyun cur_best_fit = i;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun return &supported_modes[cur_best_fit];
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
sc2239_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)380*4882a593Smuzhiyun static int sc2239_set_fmt(struct v4l2_subdev *sd,
381*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
382*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
385*4882a593Smuzhiyun const struct sc2239_mode *mode;
386*4882a593Smuzhiyun s64 h_blank, vblank_def;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun mutex_lock(&sc2239->mutex);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun mode = sc2239_find_best_fit(fmt);
391*4882a593Smuzhiyun fmt->format.code = PIX_FORMAT;
392*4882a593Smuzhiyun fmt->format.width = mode->width;
393*4882a593Smuzhiyun fmt->format.height = mode->height;
394*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
395*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
396*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
397*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
398*4882a593Smuzhiyun #else
399*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
400*4882a593Smuzhiyun return -ENOTTY;
401*4882a593Smuzhiyun #endif
402*4882a593Smuzhiyun } else {
403*4882a593Smuzhiyun sc2239->cur_mode = mode;
404*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
405*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc2239->hblank, h_blank,
406*4882a593Smuzhiyun h_blank, 1, h_blank);
407*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
408*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc2239->vblank, vblank_def,
409*4882a593Smuzhiyun SC2239_VTS_MAX - mode->height,
410*4882a593Smuzhiyun 1, vblank_def);
411*4882a593Smuzhiyun sc2239->cur_fps = mode->max_fps;
412*4882a593Smuzhiyun sc2239->cur_vts = mode->vts_def;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun return 0;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun
sc2239_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)420*4882a593Smuzhiyun static int sc2239_get_fmt(struct v4l2_subdev *sd,
421*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
422*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
425*4882a593Smuzhiyun const struct sc2239_mode *mode = sc2239->cur_mode;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun mutex_lock(&sc2239->mutex);
428*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
429*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
430*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
431*4882a593Smuzhiyun #else
432*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
433*4882a593Smuzhiyun return -ENOTTY;
434*4882a593Smuzhiyun #endif
435*4882a593Smuzhiyun } else {
436*4882a593Smuzhiyun fmt->format.width = mode->width;
437*4882a593Smuzhiyun fmt->format.height = mode->height;
438*4882a593Smuzhiyun fmt->format.code = PIX_FORMAT;
439*4882a593Smuzhiyun fmt->format.field = V4L2_FIELD_NONE;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun return 0;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
sc2239_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)446*4882a593Smuzhiyun static int sc2239_enum_mbus_code(struct v4l2_subdev *sd,
447*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
448*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun if (code->index != 0)
451*4882a593Smuzhiyun return -EINVAL;
452*4882a593Smuzhiyun code->code = PIX_FORMAT;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun return 0;
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
sc2239_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)457*4882a593Smuzhiyun static int sc2239_enum_frame_sizes(struct v4l2_subdev *sd,
458*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
459*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(supported_modes))
462*4882a593Smuzhiyun return -EINVAL;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun if (fse->code != PIX_FORMAT)
465*4882a593Smuzhiyun return -EINVAL;
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun fse->min_width = supported_modes[fse->index].width;
468*4882a593Smuzhiyun fse->max_width = supported_modes[fse->index].width;
469*4882a593Smuzhiyun fse->max_height = supported_modes[fse->index].height;
470*4882a593Smuzhiyun fse->min_height = supported_modes[fse->index].height;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun return 0;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
sc2239_enable_test_pattern(struct sc2239 * sc2239,u32 pattern)475*4882a593Smuzhiyun static int sc2239_enable_test_pattern(struct sc2239 *sc2239, u32 pattern)
476*4882a593Smuzhiyun {
477*4882a593Smuzhiyun u32 val = 0;
478*4882a593Smuzhiyun int ret = 0;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun ret = sc2239_read_reg(sc2239->client, SC2239_REG_TEST_PATTERN,
481*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, &val);
482*4882a593Smuzhiyun if (pattern)
483*4882a593Smuzhiyun val |= SC2239_TEST_PATTERN_BIT_MASK;
484*4882a593Smuzhiyun else
485*4882a593Smuzhiyun val &= ~SC2239_TEST_PATTERN_BIT_MASK;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun ret |= sc2239_write_reg(sc2239->client, SC2239_REG_TEST_PATTERN,
488*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, val);
489*4882a593Smuzhiyun return ret;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun
sc2239_get_module_inf(struct sc2239 * sc2239,struct rkmodule_inf * inf)492*4882a593Smuzhiyun static void sc2239_get_module_inf(struct sc2239 *sc2239,
493*4882a593Smuzhiyun struct rkmodule_inf *inf)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
496*4882a593Smuzhiyun strlcpy(inf->base.sensor, SC2239_NAME, sizeof(inf->base.sensor));
497*4882a593Smuzhiyun strlcpy(inf->base.module, sc2239->module_name,
498*4882a593Smuzhiyun sizeof(inf->base.module));
499*4882a593Smuzhiyun strlcpy(inf->base.lens, sc2239->len_name, sizeof(inf->base.lens));
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
sc2239_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)502*4882a593Smuzhiyun static long sc2239_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
505*4882a593Smuzhiyun long ret = 0;
506*4882a593Smuzhiyun u32 stream;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun switch (cmd) {
509*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
510*4882a593Smuzhiyun sc2239_get_module_inf(sc2239, (struct rkmodule_inf *)arg);
511*4882a593Smuzhiyun break;
512*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
513*4882a593Smuzhiyun stream = *((u32 *)arg);
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun if (stream)
516*4882a593Smuzhiyun ret = sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
517*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, SC2239_MODE_STREAMING);
518*4882a593Smuzhiyun else
519*4882a593Smuzhiyun ret = sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
520*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, SC2239_MODE_SW_STANDBY);
521*4882a593Smuzhiyun break;
522*4882a593Smuzhiyun default:
523*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
524*4882a593Smuzhiyun break;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
527*4882a593Smuzhiyun return ret;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
sc2239_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)531*4882a593Smuzhiyun static long sc2239_compat_ioctl32(struct v4l2_subdev *sd,
532*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
535*4882a593Smuzhiyun struct rkmodule_inf *inf;
536*4882a593Smuzhiyun struct rkmodule_awb_cfg *cfg;
537*4882a593Smuzhiyun long ret;
538*4882a593Smuzhiyun u32 stream;
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun switch (cmd) {
541*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
542*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
543*4882a593Smuzhiyun if (!inf) {
544*4882a593Smuzhiyun ret = -ENOMEM;
545*4882a593Smuzhiyun return ret;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun ret = sc2239_ioctl(sd, cmd, inf);
549*4882a593Smuzhiyun if (!ret) {
550*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
551*4882a593Smuzhiyun if (ret)
552*4882a593Smuzhiyun ret = -EFAULT;
553*4882a593Smuzhiyun }
554*4882a593Smuzhiyun kfree(inf);
555*4882a593Smuzhiyun break;
556*4882a593Smuzhiyun case RKMODULE_AWB_CFG:
557*4882a593Smuzhiyun cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
558*4882a593Smuzhiyun if (!cfg) {
559*4882a593Smuzhiyun ret = -ENOMEM;
560*4882a593Smuzhiyun return ret;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun ret = copy_from_user(cfg, up, sizeof(*cfg));
564*4882a593Smuzhiyun if (!ret)
565*4882a593Smuzhiyun ret = sc2239_ioctl(sd, cmd, cfg);
566*4882a593Smuzhiyun else
567*4882a593Smuzhiyun ret = -EFAULT;
568*4882a593Smuzhiyun kfree(cfg);
569*4882a593Smuzhiyun break;
570*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
571*4882a593Smuzhiyun ret = copy_from_user(&stream, up, sizeof(u32));
572*4882a593Smuzhiyun if (!ret)
573*4882a593Smuzhiyun ret = sc2239_ioctl(sd, cmd, &stream);
574*4882a593Smuzhiyun else
575*4882a593Smuzhiyun ret = -EFAULT;
576*4882a593Smuzhiyun break;
577*4882a593Smuzhiyun default:
578*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
579*4882a593Smuzhiyun break;
580*4882a593Smuzhiyun }
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun return ret;
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun #endif
585*4882a593Smuzhiyun
sc2239_set_ctrl_gain(struct sc2239 * sc2239,u32 a_gain)586*4882a593Smuzhiyun static int sc2239_set_ctrl_gain(struct sc2239 *sc2239, u32 a_gain)
587*4882a593Smuzhiyun {
588*4882a593Smuzhiyun int ret = 0;
589*4882a593Smuzhiyun u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
590*4882a593Smuzhiyun u32 switch_value;
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun if ( a_gain != sc2239->old_gain) {
593*4882a593Smuzhiyun if (a_gain < 0x40) { /*1x ~ 2x*/
594*4882a593Smuzhiyun fine_again = a_gain - 32;
595*4882a593Smuzhiyun coarse_again = 0x03;
596*4882a593Smuzhiyun fine_again_reg = ((0x01 << 5) & 0x20) |
597*4882a593Smuzhiyun (fine_again & 0x1f);
598*4882a593Smuzhiyun coarse_again_reg = coarse_again & 0x1F;
599*4882a593Smuzhiyun switch_value = 0x64;
600*4882a593Smuzhiyun } else if (a_gain < 0x80) { /*2x ~ 4x*/
601*4882a593Smuzhiyun fine_again = (a_gain >> 1) - 32;
602*4882a593Smuzhiyun coarse_again = 0x7;
603*4882a593Smuzhiyun fine_again_reg = ((0x01 << 5) & 0x20) |
604*4882a593Smuzhiyun (fine_again & 0x1f);
605*4882a593Smuzhiyun coarse_again_reg = coarse_again & 0x1F;
606*4882a593Smuzhiyun switch_value = 0x64;
607*4882a593Smuzhiyun } else if (a_gain < 0x100) { /*4x ~ 8x*/
608*4882a593Smuzhiyun fine_again = (a_gain >> 2) - 32;
609*4882a593Smuzhiyun coarse_again = 0xf;
610*4882a593Smuzhiyun fine_again_reg = ((0x01 << 5) & 0x20) |
611*4882a593Smuzhiyun (fine_again & 0x1f);
612*4882a593Smuzhiyun coarse_again_reg = coarse_again & 0x1F;
613*4882a593Smuzhiyun switch_value = 0x44;
614*4882a593Smuzhiyun } else { /*8x ~ 16x*/
615*4882a593Smuzhiyun fine_again = (a_gain >> 3) - 32;
616*4882a593Smuzhiyun coarse_again = 0x1f;
617*4882a593Smuzhiyun fine_again_reg = ((0x01 << 5) & 0x20) |
618*4882a593Smuzhiyun (fine_again & 0x1f);
619*4882a593Smuzhiyun coarse_again_reg = coarse_again & 0x1F;
620*4882a593Smuzhiyun switch_value = 0x24;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun ret = sc2239_write_reg(sc2239->client, 0x3634,
624*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, switch_value);
625*4882a593Smuzhiyun ret |= sc2239_write_reg(sc2239->client,
626*4882a593Smuzhiyun SC2239_REG_COARSE_AGAIN,
627*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT,
628*4882a593Smuzhiyun coarse_again_reg);
629*4882a593Smuzhiyun ret |= sc2239_write_reg(sc2239->client,
630*4882a593Smuzhiyun SC2239_REG_FINE_AGAIN,
631*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT,
632*4882a593Smuzhiyun fine_again_reg);
633*4882a593Smuzhiyun sc2239->old_gain = a_gain;
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun return ret;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
__sc2239_start_stream(struct sc2239 * sc2239)638*4882a593Smuzhiyun static int __sc2239_start_stream(struct sc2239 *sc2239)
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun int ret;
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun ret = sc2239_write_array(sc2239->client, sc2239->cur_mode->reg_list);
643*4882a593Smuzhiyun if (ret)
644*4882a593Smuzhiyun return ret;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun /* In case these controls are set before streaming */
647*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
648*4882a593Smuzhiyun ret = v4l2_ctrl_handler_setup(&sc2239->ctrl_handler);
649*4882a593Smuzhiyun mutex_lock(&sc2239->mutex);
650*4882a593Smuzhiyun if (ret)
651*4882a593Smuzhiyun return ret;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun return sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
654*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, SC2239_MODE_STREAMING);
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun
__sc2239_stop_stream(struct sc2239 * sc2239)657*4882a593Smuzhiyun static int __sc2239_stop_stream(struct sc2239 *sc2239)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun return sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
660*4882a593Smuzhiyun SC2239_REG_VALUE_08BIT, SC2239_MODE_SW_STANDBY);
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun
sc2239_s_stream(struct v4l2_subdev * sd,int on)663*4882a593Smuzhiyun static int sc2239_s_stream(struct v4l2_subdev *sd, int on)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
666*4882a593Smuzhiyun struct i2c_client *client = sc2239->client;
667*4882a593Smuzhiyun int ret = 0;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
670*4882a593Smuzhiyun sc2239->cur_mode->width,
671*4882a593Smuzhiyun sc2239->cur_mode->height,
672*4882a593Smuzhiyun DIV_ROUND_CLOSEST(sc2239->cur_mode->max_fps.denominator,
673*4882a593Smuzhiyun sc2239->cur_mode->max_fps.numerator));
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun mutex_lock(&sc2239->mutex);
676*4882a593Smuzhiyun on = !!on;
677*4882a593Smuzhiyun if (on == sc2239->streaming)
678*4882a593Smuzhiyun goto unlock_and_return;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun if (on) {
681*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
682*4882a593Smuzhiyun if (ret < 0) {
683*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
684*4882a593Smuzhiyun goto unlock_and_return;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun ret = __sc2239_start_stream(sc2239);
688*4882a593Smuzhiyun if (ret) {
689*4882a593Smuzhiyun v4l2_err(sd, "start stream failed while write regs\n");
690*4882a593Smuzhiyun pm_runtime_put(&client->dev);
691*4882a593Smuzhiyun goto unlock_and_return;
692*4882a593Smuzhiyun }
693*4882a593Smuzhiyun } else {
694*4882a593Smuzhiyun __sc2239_stop_stream(sc2239);
695*4882a593Smuzhiyun pm_runtime_put(&client->dev);
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun sc2239->streaming = on;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun unlock_and_return:
701*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun return ret;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun
sc2239_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)706*4882a593Smuzhiyun static int sc2239_g_frame_interval(struct v4l2_subdev *sd,
707*4882a593Smuzhiyun struct v4l2_subdev_frame_interval *fi)
708*4882a593Smuzhiyun {
709*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
710*4882a593Smuzhiyun const struct sc2239_mode *mode = sc2239->cur_mode;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun if (sc2239->streaming)
713*4882a593Smuzhiyun fi->interval = sc2239->cur_fps;
714*4882a593Smuzhiyun else
715*4882a593Smuzhiyun fi->interval = mode->max_fps;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun return 0;
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun
sc2239_s_power(struct v4l2_subdev * sd,int on)720*4882a593Smuzhiyun static int sc2239_s_power(struct v4l2_subdev *sd, int on)
721*4882a593Smuzhiyun {
722*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
723*4882a593Smuzhiyun struct i2c_client *client = sc2239->client;
724*4882a593Smuzhiyun int ret = 0;
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun mutex_lock(&sc2239->mutex);
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
729*4882a593Smuzhiyun if (sc2239->power_on == !!on)
730*4882a593Smuzhiyun goto unlock_and_return;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun if (on) {
733*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
734*4882a593Smuzhiyun if (ret < 0) {
735*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
736*4882a593Smuzhiyun goto unlock_and_return;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun ret = sc2239_write_array(sc2239->client, sc2239_global_regs);
739*4882a593Smuzhiyun if (ret) {
740*4882a593Smuzhiyun v4l2_err(sd, "could not set init registers\n");
741*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
742*4882a593Smuzhiyun goto unlock_and_return;
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun sc2239->power_on = true;
745*4882a593Smuzhiyun } else {
746*4882a593Smuzhiyun pm_runtime_put(&client->dev);
747*4882a593Smuzhiyun sc2239->power_on = false;
748*4882a593Smuzhiyun }
749*4882a593Smuzhiyun
750*4882a593Smuzhiyun unlock_and_return:
751*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun return ret;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun /* Calculate the delay in us by clock rate and clock cycles */
sc2239_cal_delay(u32 cycles)757*4882a593Smuzhiyun static inline u32 sc2239_cal_delay(u32 cycles)
758*4882a593Smuzhiyun {
759*4882a593Smuzhiyun return DIV_ROUND_UP(cycles, SC2239_XVCLK_FREQ / 1000 / 1000);
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
__sc2239_power_on(struct sc2239 * sc2239)762*4882a593Smuzhiyun static int __sc2239_power_on(struct sc2239 *sc2239)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun int ret;
765*4882a593Smuzhiyun u32 delay_us;
766*4882a593Smuzhiyun struct device *dev = &sc2239->client->dev;
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun ret = clk_set_rate(sc2239->xvclk, SC2239_XVCLK_FREQ);
769*4882a593Smuzhiyun if (ret < 0)
770*4882a593Smuzhiyun dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
771*4882a593Smuzhiyun if (clk_get_rate(sc2239->xvclk) != SC2239_XVCLK_FREQ)
772*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
773*4882a593Smuzhiyun ret = clk_prepare_enable(sc2239->xvclk);
774*4882a593Smuzhiyun if (ret < 0) {
775*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
776*4882a593Smuzhiyun return ret;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun if (!IS_ERR(sc2239->reset_gpio))
779*4882a593Smuzhiyun gpiod_set_value_cansleep(sc2239->reset_gpio, 0);
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun ret = regulator_bulk_enable(SC2239_NUM_SUPPLIES, sc2239->supplies);
782*4882a593Smuzhiyun if (ret < 0) {
783*4882a593Smuzhiyun dev_err(dev, "Failed to enable regulators\n");
784*4882a593Smuzhiyun goto disable_clk;
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun if (!IS_ERR(sc2239->reset_gpio))
788*4882a593Smuzhiyun gpiod_set_value_cansleep(sc2239->reset_gpio, 1);
789*4882a593Smuzhiyun
790*4882a593Smuzhiyun if (!IS_ERR(sc2239->pwdn_gpio))
791*4882a593Smuzhiyun gpiod_set_value_cansleep(sc2239->pwdn_gpio, 1);
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun /* 8192 cycles prior to first SCCB transaction */
794*4882a593Smuzhiyun delay_us = sc2239_cal_delay(8192);
795*4882a593Smuzhiyun usleep_range(delay_us, delay_us * 2);
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun return 0;
798*4882a593Smuzhiyun
799*4882a593Smuzhiyun disable_clk:
800*4882a593Smuzhiyun clk_disable_unprepare(sc2239->xvclk);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun return ret;
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun
__sc2239_power_off(struct sc2239 * sc2239)805*4882a593Smuzhiyun static void __sc2239_power_off(struct sc2239 *sc2239)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun if (!IS_ERR(sc2239->pwdn_gpio))
808*4882a593Smuzhiyun gpiod_set_value_cansleep(sc2239->pwdn_gpio, 0);
809*4882a593Smuzhiyun clk_disable_unprepare(sc2239->xvclk);
810*4882a593Smuzhiyun if (!IS_ERR(sc2239->reset_gpio))
811*4882a593Smuzhiyun gpiod_set_value_cansleep(sc2239->reset_gpio, 0);
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun regulator_bulk_disable(SC2239_NUM_SUPPLIES, sc2239->supplies);
814*4882a593Smuzhiyun }
815*4882a593Smuzhiyun
sc2239_runtime_resume(struct device * dev)816*4882a593Smuzhiyun static int sc2239_runtime_resume(struct device *dev)
817*4882a593Smuzhiyun {
818*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
819*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
820*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun return __sc2239_power_on(sc2239);
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
sc2239_runtime_suspend(struct device * dev)825*4882a593Smuzhiyun static int sc2239_runtime_suspend(struct device *dev)
826*4882a593Smuzhiyun {
827*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
828*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
829*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
830*4882a593Smuzhiyun
831*4882a593Smuzhiyun __sc2239_power_off(sc2239);
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun return 0;
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
sc2239_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)837*4882a593Smuzhiyun static int sc2239_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
838*4882a593Smuzhiyun {
839*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
840*4882a593Smuzhiyun struct v4l2_mbus_framefmt *try_fmt =
841*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0);
842*4882a593Smuzhiyun const struct sc2239_mode *def_mode = &supported_modes[0];
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun mutex_lock(&sc2239->mutex);
845*4882a593Smuzhiyun /* Initialize try_fmt */
846*4882a593Smuzhiyun try_fmt->width = def_mode->width;
847*4882a593Smuzhiyun try_fmt->height = def_mode->height;
848*4882a593Smuzhiyun try_fmt->code = PIX_FORMAT;
849*4882a593Smuzhiyun try_fmt->field = V4L2_FIELD_NONE;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun mutex_unlock(&sc2239->mutex);
852*4882a593Smuzhiyun /* No crop or compose */
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun return 0;
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun #endif
857*4882a593Smuzhiyun
sc2239_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)858*4882a593Smuzhiyun static int sc2239_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
859*4882a593Smuzhiyun struct v4l2_mbus_config *config)
860*4882a593Smuzhiyun {
861*4882a593Smuzhiyun u32 val = 1 << (SC2239_LANES - 1) |
862*4882a593Smuzhiyun V4L2_MBUS_CSI2_CHANNEL_0 |
863*4882a593Smuzhiyun V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun config->type = V4L2_MBUS_CSI2_DPHY;
866*4882a593Smuzhiyun config->flags = val;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun return 0;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun
sc2239_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)871*4882a593Smuzhiyun static int sc2239_enum_frame_interval(struct v4l2_subdev *sd,
872*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
873*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(supported_modes))
876*4882a593Smuzhiyun return -EINVAL;
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun fie->code = PIX_FORMAT;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun fie->width = supported_modes[fie->index].width;
881*4882a593Smuzhiyun fie->height = supported_modes[fie->index].height;
882*4882a593Smuzhiyun fie->interval = supported_modes[fie->index].max_fps;
883*4882a593Smuzhiyun return 0;
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun static const struct dev_pm_ops sc2239_pm_ops = {
887*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(sc2239_runtime_suspend,
888*4882a593Smuzhiyun sc2239_runtime_resume, NULL)
889*4882a593Smuzhiyun };
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
892*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops sc2239_internal_ops = {
893*4882a593Smuzhiyun .open = sc2239_open,
894*4882a593Smuzhiyun };
895*4882a593Smuzhiyun #endif
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops sc2239_core_ops = {
898*4882a593Smuzhiyun .s_power = sc2239_s_power,
899*4882a593Smuzhiyun .ioctl = sc2239_ioctl,
900*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
901*4882a593Smuzhiyun .compat_ioctl32 = sc2239_compat_ioctl32,
902*4882a593Smuzhiyun #endif
903*4882a593Smuzhiyun };
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops sc2239_video_ops = {
906*4882a593Smuzhiyun .s_stream = sc2239_s_stream,
907*4882a593Smuzhiyun .g_frame_interval = sc2239_g_frame_interval,
908*4882a593Smuzhiyun };
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops sc2239_pad_ops = {
911*4882a593Smuzhiyun .enum_mbus_code = sc2239_enum_mbus_code,
912*4882a593Smuzhiyun .enum_frame_size = sc2239_enum_frame_sizes,
913*4882a593Smuzhiyun .enum_frame_interval = sc2239_enum_frame_interval,
914*4882a593Smuzhiyun .get_fmt = sc2239_get_fmt,
915*4882a593Smuzhiyun .set_fmt = sc2239_set_fmt,
916*4882a593Smuzhiyun .get_mbus_config = sc2239_g_mbus_config,
917*4882a593Smuzhiyun };
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun static const struct v4l2_subdev_ops sc2239_subdev_ops = {
920*4882a593Smuzhiyun .core = &sc2239_core_ops,
921*4882a593Smuzhiyun .video = &sc2239_video_ops,
922*4882a593Smuzhiyun .pad = &sc2239_pad_ops,
923*4882a593Smuzhiyun };
924*4882a593Smuzhiyun
sc2239_modify_fps_info(struct sc2239 * sc2239)925*4882a593Smuzhiyun static void sc2239_modify_fps_info(struct sc2239 *sc2239)
926*4882a593Smuzhiyun {
927*4882a593Smuzhiyun const struct sc2239_mode *mode = sc2239->cur_mode;
928*4882a593Smuzhiyun
929*4882a593Smuzhiyun sc2239->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
930*4882a593Smuzhiyun sc2239->cur_vts;
931*4882a593Smuzhiyun }
932*4882a593Smuzhiyun
sc2239_set_ctrl(struct v4l2_ctrl * ctrl)933*4882a593Smuzhiyun static int sc2239_set_ctrl(struct v4l2_ctrl *ctrl)
934*4882a593Smuzhiyun {
935*4882a593Smuzhiyun struct sc2239 *sc2239 = container_of(ctrl->handler,
936*4882a593Smuzhiyun struct sc2239, ctrl_handler);
937*4882a593Smuzhiyun struct i2c_client *client = sc2239->client;
938*4882a593Smuzhiyun s64 max;
939*4882a593Smuzhiyun int ret = 0;
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun dev_dbg(&client->dev, "ctrl->id(0x%x) val 0x%x\n",
942*4882a593Smuzhiyun ctrl->id, ctrl->val);
943*4882a593Smuzhiyun /* Propagate change of current control to all related controls */
944*4882a593Smuzhiyun switch (ctrl->id) {
945*4882a593Smuzhiyun case V4L2_CID_VBLANK:
946*4882a593Smuzhiyun /* Update max exposure while meeting expected vblanking */
947*4882a593Smuzhiyun max = sc2239->cur_mode->height + ctrl->val - 4;
948*4882a593Smuzhiyun __v4l2_ctrl_modify_range(sc2239->exposure,
949*4882a593Smuzhiyun sc2239->exposure->minimum, max,
950*4882a593Smuzhiyun sc2239->exposure->step,
951*4882a593Smuzhiyun sc2239->exposure->default_value);
952*4882a593Smuzhiyun break;
953*4882a593Smuzhiyun }
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun if (!pm_runtime_get_if_in_use(&client->dev))
956*4882a593Smuzhiyun return 0;
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun switch (ctrl->id) {
959*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
960*4882a593Smuzhiyun /* 4 least significant bits of expsoure are fractional part */
961*4882a593Smuzhiyun ret = sc2239_write_reg(sc2239->client, SC2239_REG_EXPOSURE,
962*4882a593Smuzhiyun SC2239_REG_VALUE_24BIT, ctrl->val << 5);
963*4882a593Smuzhiyun dev_dbg(&client->dev, "set exposure 0x%x\n",
964*4882a593Smuzhiyun ctrl->val);
965*4882a593Smuzhiyun break;
966*4882a593Smuzhiyun case V4L2_CID_ANALOGUE_GAIN:
967*4882a593Smuzhiyun ret = sc2239_set_ctrl_gain(sc2239, ctrl->val);
968*4882a593Smuzhiyun dev_dbg(&client->dev, "set analog gain 0x%x\n",
969*4882a593Smuzhiyun ctrl->val);
970*4882a593Smuzhiyun break;
971*4882a593Smuzhiyun case V4L2_CID_VBLANK:
972*4882a593Smuzhiyun ret = sc2239_write_reg(sc2239->client, SC2239_REG_VTS,
973*4882a593Smuzhiyun SC2239_REG_VALUE_16BIT,
974*4882a593Smuzhiyun ctrl->val + sc2239->cur_mode->height);
975*4882a593Smuzhiyun if (!ret)
976*4882a593Smuzhiyun sc2239->cur_vts = ctrl->val + sc2239->cur_mode->height;
977*4882a593Smuzhiyun sc2239_modify_fps_info(sc2239);
978*4882a593Smuzhiyun break;
979*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
980*4882a593Smuzhiyun ret = sc2239_enable_test_pattern(sc2239, ctrl->val);
981*4882a593Smuzhiyun break;
982*4882a593Smuzhiyun default:
983*4882a593Smuzhiyun dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
984*4882a593Smuzhiyun __func__, ctrl->id, ctrl->val);
985*4882a593Smuzhiyun break;
986*4882a593Smuzhiyun }
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun pm_runtime_put(&client->dev);
989*4882a593Smuzhiyun
990*4882a593Smuzhiyun return ret;
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun static const struct v4l2_ctrl_ops sc2239_ctrl_ops = {
994*4882a593Smuzhiyun .s_ctrl = sc2239_set_ctrl,
995*4882a593Smuzhiyun };
996*4882a593Smuzhiyun
sc2239_initialize_controls(struct sc2239 * sc2239)997*4882a593Smuzhiyun static int sc2239_initialize_controls(struct sc2239 *sc2239)
998*4882a593Smuzhiyun {
999*4882a593Smuzhiyun const struct sc2239_mode *mode;
1000*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
1001*4882a593Smuzhiyun struct v4l2_ctrl *ctrl;
1002*4882a593Smuzhiyun s64 exposure_max, vblank_def;
1003*4882a593Smuzhiyun u32 h_blank;
1004*4882a593Smuzhiyun int ret;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun handler = &sc2239->ctrl_handler;
1007*4882a593Smuzhiyun mode = sc2239->cur_mode;
1008*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 8);
1009*4882a593Smuzhiyun if (ret)
1010*4882a593Smuzhiyun return ret;
1011*4882a593Smuzhiyun handler->lock = &sc2239->mutex;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1014*4882a593Smuzhiyun 0, 0, link_freq_menu_items);
1015*4882a593Smuzhiyun if (ctrl)
1016*4882a593Smuzhiyun ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1019*4882a593Smuzhiyun 0, SC2239_PIXEL_RATE, 1, SC2239_PIXEL_RATE);
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun h_blank = mode->hts_def - mode->width;
1022*4882a593Smuzhiyun sc2239->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1023*4882a593Smuzhiyun h_blank, h_blank, 1, h_blank);
1024*4882a593Smuzhiyun if (sc2239->hblank)
1025*4882a593Smuzhiyun sc2239->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
1028*4882a593Smuzhiyun sc2239->vblank = v4l2_ctrl_new_std(handler, &sc2239_ctrl_ops,
1029*4882a593Smuzhiyun V4L2_CID_VBLANK, vblank_def,
1030*4882a593Smuzhiyun SC2239_VTS_MAX - mode->height,
1031*4882a593Smuzhiyun 1, vblank_def);
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun exposure_max = mode->vts_def - 4;
1034*4882a593Smuzhiyun sc2239->exposure = v4l2_ctrl_new_std(handler, &sc2239_ctrl_ops,
1035*4882a593Smuzhiyun V4L2_CID_EXPOSURE, SC2239_EXPOSURE_MIN,
1036*4882a593Smuzhiyun exposure_max, SC2239_EXPOSURE_STEP,
1037*4882a593Smuzhiyun mode->exp_def);
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun sc2239->anal_gain = v4l2_ctrl_new_std(handler, &sc2239_ctrl_ops,
1040*4882a593Smuzhiyun V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
1041*4882a593Smuzhiyun ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
1042*4882a593Smuzhiyun ANALOG_GAIN_DEFAULT);
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun sc2239->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1045*4882a593Smuzhiyun &sc2239_ctrl_ops, V4L2_CID_TEST_PATTERN,
1046*4882a593Smuzhiyun ARRAY_SIZE(sc2239_test_pattern_menu) - 1,
1047*4882a593Smuzhiyun 0, 0, sc2239_test_pattern_menu);
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun if (handler->error) {
1050*4882a593Smuzhiyun ret = handler->error;
1051*4882a593Smuzhiyun dev_err(&sc2239->client->dev,
1052*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
1053*4882a593Smuzhiyun goto err_free_handler;
1054*4882a593Smuzhiyun }
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun sc2239->subdev.ctrl_handler = handler;
1057*4882a593Smuzhiyun sc2239->old_gain = ANALOG_GAIN_DEFAULT;
1058*4882a593Smuzhiyun sc2239->cur_fps = mode->max_fps;
1059*4882a593Smuzhiyun sc2239->cur_vts = mode->vts_def;
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun return 0;
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun err_free_handler:
1064*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
1065*4882a593Smuzhiyun
1066*4882a593Smuzhiyun return ret;
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun
sc2239_check_sensor_id(struct sc2239 * sc2239,struct i2c_client * client)1069*4882a593Smuzhiyun static int sc2239_check_sensor_id(struct sc2239 *sc2239,
1070*4882a593Smuzhiyun struct i2c_client *client)
1071*4882a593Smuzhiyun {
1072*4882a593Smuzhiyun struct device *dev = &sc2239->client->dev;
1073*4882a593Smuzhiyun u32 id = 0;
1074*4882a593Smuzhiyun int ret;
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun ret = sc2239_read_reg(client, SC2239_REG_CHIP_ID,
1077*4882a593Smuzhiyun SC2239_REG_VALUE_16BIT, &id);
1078*4882a593Smuzhiyun if (id != CHIP_ID) {
1079*4882a593Smuzhiyun dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1080*4882a593Smuzhiyun return -ENODEV;
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun
1083*4882a593Smuzhiyun dev_info(dev, "Detected SC2239 CHIP ID = 0x%04x sensor\n", CHIP_ID);
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun return 0;
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun
sc2239_configure_regulators(struct sc2239 * sc2239)1088*4882a593Smuzhiyun static int sc2239_configure_regulators(struct sc2239 *sc2239)
1089*4882a593Smuzhiyun {
1090*4882a593Smuzhiyun unsigned int i;
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun for (i = 0; i < SC2239_NUM_SUPPLIES; i++)
1093*4882a593Smuzhiyun sc2239->supplies[i].supply = sc2239_supply_names[i];
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun return devm_regulator_bulk_get(&sc2239->client->dev,
1096*4882a593Smuzhiyun SC2239_NUM_SUPPLIES,
1097*4882a593Smuzhiyun sc2239->supplies);
1098*4882a593Smuzhiyun }
1099*4882a593Smuzhiyun
sc2239_probe(struct i2c_client * client,const struct i2c_device_id * id)1100*4882a593Smuzhiyun static int sc2239_probe(struct i2c_client *client,
1101*4882a593Smuzhiyun const struct i2c_device_id *id)
1102*4882a593Smuzhiyun {
1103*4882a593Smuzhiyun struct device *dev = &client->dev;
1104*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1105*4882a593Smuzhiyun struct sc2239 *sc2239;
1106*4882a593Smuzhiyun struct v4l2_subdev *sd;
1107*4882a593Smuzhiyun char facing[2];
1108*4882a593Smuzhiyun int ret;
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1111*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1112*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1113*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1114*4882a593Smuzhiyun
1115*4882a593Smuzhiyun sc2239 = devm_kzalloc(dev, sizeof(*sc2239), GFP_KERNEL);
1116*4882a593Smuzhiyun if (!sc2239)
1117*4882a593Smuzhiyun return -ENOMEM;
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1120*4882a593Smuzhiyun &sc2239->module_index);
1121*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1122*4882a593Smuzhiyun &sc2239->module_facing);
1123*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1124*4882a593Smuzhiyun &sc2239->module_name);
1125*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1126*4882a593Smuzhiyun &sc2239->len_name);
1127*4882a593Smuzhiyun if (ret) {
1128*4882a593Smuzhiyun dev_err(dev, "could not get module information!\n");
1129*4882a593Smuzhiyun return -EINVAL;
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
1132*4882a593Smuzhiyun sc2239->client = client;
1133*4882a593Smuzhiyun sc2239->cur_mode = &supported_modes[0];
1134*4882a593Smuzhiyun
1135*4882a593Smuzhiyun sc2239->xvclk = devm_clk_get(dev, "xvclk");
1136*4882a593Smuzhiyun if (IS_ERR(sc2239->xvclk)) {
1137*4882a593Smuzhiyun dev_err(dev, "Failed to get xvclk\n");
1138*4882a593Smuzhiyun return -EINVAL;
1139*4882a593Smuzhiyun }
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun sc2239->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1142*4882a593Smuzhiyun if (IS_ERR(sc2239->reset_gpio))
1143*4882a593Smuzhiyun dev_warn(dev, "Failed to get reset-gpios\n");
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun sc2239->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1146*4882a593Smuzhiyun if (IS_ERR(sc2239->pwdn_gpio))
1147*4882a593Smuzhiyun dev_warn(dev, "Failed to get pwdn-gpios\n");
1148*4882a593Smuzhiyun ret = sc2239_configure_regulators(sc2239);
1149*4882a593Smuzhiyun if (ret) {
1150*4882a593Smuzhiyun dev_err(dev, "Failed to get power regulators\n");
1151*4882a593Smuzhiyun return ret;
1152*4882a593Smuzhiyun }
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun mutex_init(&sc2239->mutex);
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun sd = &sc2239->subdev;
1157*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &sc2239_subdev_ops);
1158*4882a593Smuzhiyun ret = sc2239_initialize_controls(sc2239);
1159*4882a593Smuzhiyun if (ret)
1160*4882a593Smuzhiyun goto err_destroy_mutex;
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun ret = __sc2239_power_on(sc2239);
1163*4882a593Smuzhiyun if (ret)
1164*4882a593Smuzhiyun goto err_free_handler;
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun ret = sc2239_check_sensor_id(sc2239, client);
1167*4882a593Smuzhiyun if (ret)
1168*4882a593Smuzhiyun goto err_power_off;
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1171*4882a593Smuzhiyun sd->internal_ops = &sc2239_internal_ops;
1172*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1173*4882a593Smuzhiyun V4L2_SUBDEV_FL_HAS_EVENTS;
1174*4882a593Smuzhiyun #endif
1175*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1176*4882a593Smuzhiyun sc2239->pad.flags = MEDIA_PAD_FL_SOURCE;
1177*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1178*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, 1, &sc2239->pad);
1179*4882a593Smuzhiyun if (ret < 0)
1180*4882a593Smuzhiyun goto err_power_off;
1181*4882a593Smuzhiyun #endif
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1184*4882a593Smuzhiyun if (strcmp(sc2239->module_facing, "back") == 0)
1185*4882a593Smuzhiyun facing[0] = 'b';
1186*4882a593Smuzhiyun else
1187*4882a593Smuzhiyun facing[0] = 'f';
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1190*4882a593Smuzhiyun sc2239->module_index, facing,
1191*4882a593Smuzhiyun SC2239_NAME, dev_name(sd->dev));
1192*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
1193*4882a593Smuzhiyun if (ret) {
1194*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
1195*4882a593Smuzhiyun goto err_clean_entity;
1196*4882a593Smuzhiyun }
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun pm_runtime_set_active(dev);
1199*4882a593Smuzhiyun pm_runtime_enable(dev);
1200*4882a593Smuzhiyun pm_runtime_idle(dev);
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun return 0;
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun err_clean_entity:
1205*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1206*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1207*4882a593Smuzhiyun #endif
1208*4882a593Smuzhiyun err_power_off:
1209*4882a593Smuzhiyun __sc2239_power_off(sc2239);
1210*4882a593Smuzhiyun err_free_handler:
1211*4882a593Smuzhiyun v4l2_ctrl_handler_free(&sc2239->ctrl_handler);
1212*4882a593Smuzhiyun err_destroy_mutex:
1213*4882a593Smuzhiyun mutex_destroy(&sc2239->mutex);
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun return ret;
1216*4882a593Smuzhiyun }
1217*4882a593Smuzhiyun
sc2239_remove(struct i2c_client * client)1218*4882a593Smuzhiyun static int sc2239_remove(struct i2c_client *client)
1219*4882a593Smuzhiyun {
1220*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1221*4882a593Smuzhiyun struct sc2239 *sc2239 = to_sc2239(sd);
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1224*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1225*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1226*4882a593Smuzhiyun #endif
1227*4882a593Smuzhiyun v4l2_ctrl_handler_free(&sc2239->ctrl_handler);
1228*4882a593Smuzhiyun mutex_destroy(&sc2239->mutex);
1229*4882a593Smuzhiyun
1230*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1231*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
1232*4882a593Smuzhiyun __sc2239_power_off(sc2239);
1233*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun return 0;
1236*4882a593Smuzhiyun }
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1239*4882a593Smuzhiyun static const struct of_device_id sc2239_of_match[] = {
1240*4882a593Smuzhiyun { .compatible = "smartsens,sc2239" },
1241*4882a593Smuzhiyun {},
1242*4882a593Smuzhiyun };
1243*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sc2239_of_match);
1244*4882a593Smuzhiyun #endif
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun static const struct i2c_device_id sc2239_match_id[] = {
1247*4882a593Smuzhiyun { "smartsens,sc2239", 0 },
1248*4882a593Smuzhiyun { },
1249*4882a593Smuzhiyun };
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun static struct i2c_driver sc2239_i2c_driver = {
1252*4882a593Smuzhiyun .driver = {
1253*4882a593Smuzhiyun .name = SC2239_NAME,
1254*4882a593Smuzhiyun .pm = &sc2239_pm_ops,
1255*4882a593Smuzhiyun .of_match_table = of_match_ptr(sc2239_of_match),
1256*4882a593Smuzhiyun },
1257*4882a593Smuzhiyun .probe = &sc2239_probe,
1258*4882a593Smuzhiyun .remove = &sc2239_remove,
1259*4882a593Smuzhiyun .id_table = sc2239_match_id,
1260*4882a593Smuzhiyun };
1261*4882a593Smuzhiyun
sensor_mod_init(void)1262*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1263*4882a593Smuzhiyun {
1264*4882a593Smuzhiyun return i2c_add_driver(&sc2239_i2c_driver);
1265*4882a593Smuzhiyun }
1266*4882a593Smuzhiyun
sensor_mod_exit(void)1267*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1268*4882a593Smuzhiyun {
1269*4882a593Smuzhiyun i2c_del_driver(&sc2239_i2c_driver);
1270*4882a593Smuzhiyun }
1271*4882a593Smuzhiyun
1272*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1273*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun MODULE_DESCRIPTION("Smartsens sc2239 sensor driver");
1276*4882a593Smuzhiyun MODULE_AUTHOR("zack.zeng");
1277*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1278