xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/saa7110.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * saa7110 - Philips SAA7110(A) video decoder driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 1998 Pauline Middelink <middelin@polyware.nl>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 1999 Wolfgang Scherr <scherr@net4you.net>
8*4882a593Smuzhiyun  * Copyright (C) 2000 Serguei Miridonov <mirsev@cicese.mx>
9*4882a593Smuzhiyun  *    - some corrections for Pinnacle Systems Inc. DC10plus card.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Changes by Ronald Bultje <rbultje@ronald.bitfreak.net>
12*4882a593Smuzhiyun  *    - moved over to linux>=2.4.x i2c protocol (1/1/2003)
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun #include <linux/types.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/wait.h>
21*4882a593Smuzhiyun #include <linux/uaccess.h>
22*4882a593Smuzhiyun #include <linux/i2c.h>
23*4882a593Smuzhiyun #include <linux/videodev2.h>
24*4882a593Smuzhiyun #include <media/v4l2-device.h>
25*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun MODULE_DESCRIPTION("Philips SAA7110 video decoder driver");
28*4882a593Smuzhiyun MODULE_AUTHOR("Pauline Middelink");
29*4882a593Smuzhiyun MODULE_LICENSE("GPL");
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static int debug;
33*4882a593Smuzhiyun module_param(debug, int, 0);
34*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Debug level (0-1)");
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define SAA7110_MAX_INPUT	9	/* 6 CVBS, 3 SVHS */
37*4882a593Smuzhiyun #define SAA7110_MAX_OUTPUT	1	/* 1 YUV */
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define SAA7110_NR_REG		0x35
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun struct saa7110 {
42*4882a593Smuzhiyun 	struct v4l2_subdev sd;
43*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
44*4882a593Smuzhiyun 	u8 reg[SAA7110_NR_REG];
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	v4l2_std_id norm;
47*4882a593Smuzhiyun 	int input;
48*4882a593Smuzhiyun 	int enable;
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	wait_queue_head_t wq;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun 
to_saa7110(struct v4l2_subdev * sd)53*4882a593Smuzhiyun static inline struct saa7110 *to_saa7110(struct v4l2_subdev *sd)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun 	return container_of(sd, struct saa7110, sd);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun 
to_sd(struct v4l2_ctrl * ctrl)58*4882a593Smuzhiyun static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun 	return &container_of(ctrl->handler, struct saa7110, hdl)->sd;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
64*4882a593Smuzhiyun /* I2C support functions						   */
65*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
66*4882a593Smuzhiyun 
saa7110_write(struct v4l2_subdev * sd,u8 reg,u8 value)67*4882a593Smuzhiyun static int saa7110_write(struct v4l2_subdev *sd, u8 reg, u8 value)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
70*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	decoder->reg[reg] = value;
73*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(client, reg, value);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
saa7110_write_block(struct v4l2_subdev * sd,const u8 * data,unsigned int len)76*4882a593Smuzhiyun static int saa7110_write_block(struct v4l2_subdev *sd, const u8 *data, unsigned int len)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
79*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
80*4882a593Smuzhiyun 	int ret = -1;
81*4882a593Smuzhiyun 	u8 reg = *data;		/* first register to write to */
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	/* Sanity check */
84*4882a593Smuzhiyun 	if (reg + (len - 1) > SAA7110_NR_REG)
85*4882a593Smuzhiyun 		return ret;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	/* the saa7110 has an autoincrement function, use it if
88*4882a593Smuzhiyun 	 * the adapter understands raw I2C */
89*4882a593Smuzhiyun 	if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
90*4882a593Smuzhiyun 		ret = i2c_master_send(client, data, len);
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 		/* Cache the written data */
93*4882a593Smuzhiyun 		memcpy(decoder->reg + reg, data + 1, len - 1);
94*4882a593Smuzhiyun 	} else {
95*4882a593Smuzhiyun 		for (++data, --len; len; len--) {
96*4882a593Smuzhiyun 			ret = saa7110_write(sd, reg++, *data++);
97*4882a593Smuzhiyun 			if (ret < 0)
98*4882a593Smuzhiyun 				break;
99*4882a593Smuzhiyun 		}
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	return ret;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
saa7110_read(struct v4l2_subdev * sd)105*4882a593Smuzhiyun static inline int saa7110_read(struct v4l2_subdev *sd)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	return i2c_smbus_read_byte(client);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
113*4882a593Smuzhiyun /* SAA7110 functions							   */
114*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun #define FRESP_06H_COMPST 0x03	/*0x13*/
117*4882a593Smuzhiyun #define FRESP_06H_SVIDEO 0x83	/*0xC0*/
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 
saa7110_selmux(struct v4l2_subdev * sd,int chan)120*4882a593Smuzhiyun static int saa7110_selmux(struct v4l2_subdev *sd, int chan)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	static const unsigned char modes[9][8] = {
123*4882a593Smuzhiyun 		/* mode 0 */
124*4882a593Smuzhiyun 		{FRESP_06H_COMPST, 0xD9, 0x17, 0x40, 0x03,
125*4882a593Smuzhiyun 			      0x44, 0x75, 0x16},
126*4882a593Smuzhiyun 		/* mode 1 */
127*4882a593Smuzhiyun 		{FRESP_06H_COMPST, 0xD8, 0x17, 0x40, 0x03,
128*4882a593Smuzhiyun 			      0x44, 0x75, 0x16},
129*4882a593Smuzhiyun 		/* mode 2 */
130*4882a593Smuzhiyun 		{FRESP_06H_COMPST, 0xBA, 0x07, 0x91, 0x03,
131*4882a593Smuzhiyun 			      0x60, 0xB5, 0x05},
132*4882a593Smuzhiyun 		/* mode 3 */
133*4882a593Smuzhiyun 		{FRESP_06H_COMPST, 0xB8, 0x07, 0x91, 0x03,
134*4882a593Smuzhiyun 			      0x60, 0xB5, 0x05},
135*4882a593Smuzhiyun 		/* mode 4 */
136*4882a593Smuzhiyun 		{FRESP_06H_COMPST, 0x7C, 0x07, 0xD2, 0x83,
137*4882a593Smuzhiyun 			      0x60, 0xB5, 0x03},
138*4882a593Smuzhiyun 		/* mode 5 */
139*4882a593Smuzhiyun 		{FRESP_06H_COMPST, 0x78, 0x07, 0xD2, 0x83,
140*4882a593Smuzhiyun 			      0x60, 0xB5, 0x03},
141*4882a593Smuzhiyun 		/* mode 6 */
142*4882a593Smuzhiyun 		{FRESP_06H_SVIDEO, 0x59, 0x17, 0x42, 0xA3,
143*4882a593Smuzhiyun 			      0x44, 0x75, 0x12},
144*4882a593Smuzhiyun 		/* mode 7 */
145*4882a593Smuzhiyun 		{FRESP_06H_SVIDEO, 0x9A, 0x17, 0xB1, 0x13,
146*4882a593Smuzhiyun 			      0x60, 0xB5, 0x14},
147*4882a593Smuzhiyun 		/* mode 8 */
148*4882a593Smuzhiyun 		{FRESP_06H_SVIDEO, 0x3C, 0x27, 0xC1, 0x23,
149*4882a593Smuzhiyun 			      0x44, 0x75, 0x21}
150*4882a593Smuzhiyun 	};
151*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
152*4882a593Smuzhiyun 	const unsigned char *ptr = modes[chan];
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	saa7110_write(sd, 0x06, ptr[0]);	/* Luminance control    */
155*4882a593Smuzhiyun 	saa7110_write(sd, 0x20, ptr[1]);	/* Analog Control #1    */
156*4882a593Smuzhiyun 	saa7110_write(sd, 0x21, ptr[2]);	/* Analog Control #2    */
157*4882a593Smuzhiyun 	saa7110_write(sd, 0x22, ptr[3]);	/* Mixer Control #1     */
158*4882a593Smuzhiyun 	saa7110_write(sd, 0x2C, ptr[4]);	/* Mixer Control #2     */
159*4882a593Smuzhiyun 	saa7110_write(sd, 0x30, ptr[5]);	/* ADCs gain control    */
160*4882a593Smuzhiyun 	saa7110_write(sd, 0x31, ptr[6]);	/* Mixer Control #3     */
161*4882a593Smuzhiyun 	saa7110_write(sd, 0x21, ptr[7]);	/* Analog Control #2    */
162*4882a593Smuzhiyun 	decoder->input = chan;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	return 0;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const unsigned char initseq[1 + SAA7110_NR_REG] = {
168*4882a593Smuzhiyun 	0, 0x4C, 0x3C, 0x0D, 0xEF, 0xBD, 0xF2, 0x03, 0x00,
169*4882a593Smuzhiyun 	/* 0x08 */ 0xF8, 0xF8, 0x60, 0x60, 0x00, 0x86, 0x18, 0x90,
170*4882a593Smuzhiyun 	/* 0x10 */ 0x00, 0x59, 0x40, 0x46, 0x42, 0x1A, 0xFF, 0xDA,
171*4882a593Smuzhiyun 	/* 0x18 */ 0xF2, 0x8B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
172*4882a593Smuzhiyun 	/* 0x20 */ 0xD9, 0x16, 0x40, 0x41, 0x80, 0x41, 0x80, 0x4F,
173*4882a593Smuzhiyun 	/* 0x28 */ 0xFE, 0x01, 0xCF, 0x0F, 0x03, 0x01, 0x03, 0x0C,
174*4882a593Smuzhiyun 	/* 0x30 */ 0x44, 0x71, 0x02, 0x8C, 0x02
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
determine_norm(struct v4l2_subdev * sd)177*4882a593Smuzhiyun static v4l2_std_id determine_norm(struct v4l2_subdev *sd)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun 	DEFINE_WAIT(wait);
180*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
181*4882a593Smuzhiyun 	int status;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	/* mode changed, start automatic detection */
184*4882a593Smuzhiyun 	saa7110_write_block(sd, initseq, sizeof(initseq));
185*4882a593Smuzhiyun 	saa7110_selmux(sd, decoder->input);
186*4882a593Smuzhiyun 	prepare_to_wait(&decoder->wq, &wait, TASK_UNINTERRUPTIBLE);
187*4882a593Smuzhiyun 	schedule_timeout(msecs_to_jiffies(250));
188*4882a593Smuzhiyun 	finish_wait(&decoder->wq, &wait);
189*4882a593Smuzhiyun 	status = saa7110_read(sd);
190*4882a593Smuzhiyun 	if (status & 0x40) {
191*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "status=0x%02x (no signal)\n", status);
192*4882a593Smuzhiyun 		return V4L2_STD_UNKNOWN;
193*4882a593Smuzhiyun 	}
194*4882a593Smuzhiyun 	if ((status & 3) == 0) {
195*4882a593Smuzhiyun 		saa7110_write(sd, 0x06, 0x83);
196*4882a593Smuzhiyun 		if (status & 0x20) {
197*4882a593Smuzhiyun 			v4l2_dbg(1, debug, sd, "status=0x%02x (NTSC/no color)\n", status);
198*4882a593Smuzhiyun 			/*saa7110_write(sd,0x2E,0x81);*/
199*4882a593Smuzhiyun 			return V4L2_STD_NTSC;
200*4882a593Smuzhiyun 		}
201*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "status=0x%02x (PAL/no color)\n", status);
202*4882a593Smuzhiyun 		/*saa7110_write(sd,0x2E,0x9A);*/
203*4882a593Smuzhiyun 		return V4L2_STD_PAL;
204*4882a593Smuzhiyun 	}
205*4882a593Smuzhiyun 	/*saa7110_write(sd,0x06,0x03);*/
206*4882a593Smuzhiyun 	if (status & 0x20) {	/* 60Hz */
207*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "status=0x%02x (NTSC)\n", status);
208*4882a593Smuzhiyun 		saa7110_write(sd, 0x0D, 0x86);
209*4882a593Smuzhiyun 		saa7110_write(sd, 0x0F, 0x50);
210*4882a593Smuzhiyun 		saa7110_write(sd, 0x11, 0x2C);
211*4882a593Smuzhiyun 		/*saa7110_write(sd,0x2E,0x81);*/
212*4882a593Smuzhiyun 		return V4L2_STD_NTSC;
213*4882a593Smuzhiyun 	}
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	/* 50Hz -> PAL/SECAM */
216*4882a593Smuzhiyun 	saa7110_write(sd, 0x0D, 0x86);
217*4882a593Smuzhiyun 	saa7110_write(sd, 0x0F, 0x10);
218*4882a593Smuzhiyun 	saa7110_write(sd, 0x11, 0x59);
219*4882a593Smuzhiyun 	/*saa7110_write(sd,0x2E,0x9A);*/
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	prepare_to_wait(&decoder->wq, &wait, TASK_UNINTERRUPTIBLE);
222*4882a593Smuzhiyun 	schedule_timeout(msecs_to_jiffies(250));
223*4882a593Smuzhiyun 	finish_wait(&decoder->wq, &wait);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	status = saa7110_read(sd);
226*4882a593Smuzhiyun 	if ((status & 0x03) == 0x01) {
227*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "status=0x%02x (SECAM)\n", status);
228*4882a593Smuzhiyun 		saa7110_write(sd, 0x0D, 0x87);
229*4882a593Smuzhiyun 		return V4L2_STD_SECAM;
230*4882a593Smuzhiyun 	}
231*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "status=0x%02x (PAL)\n", status);
232*4882a593Smuzhiyun 	return V4L2_STD_PAL;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun 
saa7110_g_input_status(struct v4l2_subdev * sd,u32 * pstatus)235*4882a593Smuzhiyun static int saa7110_g_input_status(struct v4l2_subdev *sd, u32 *pstatus)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
238*4882a593Smuzhiyun 	int res = V4L2_IN_ST_NO_SIGNAL;
239*4882a593Smuzhiyun 	int status = saa7110_read(sd);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "status=0x%02x norm=%llx\n",
242*4882a593Smuzhiyun 		       status, (unsigned long long)decoder->norm);
243*4882a593Smuzhiyun 	if (!(status & 0x40))
244*4882a593Smuzhiyun 		res = 0;
245*4882a593Smuzhiyun 	if (!(status & 0x03))
246*4882a593Smuzhiyun 		res |= V4L2_IN_ST_NO_COLOR;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	*pstatus = res;
249*4882a593Smuzhiyun 	return 0;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun 
saa7110_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)252*4882a593Smuzhiyun static int saa7110_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
253*4882a593Smuzhiyun {
254*4882a593Smuzhiyun 	*std &= determine_norm(sd);
255*4882a593Smuzhiyun 	return 0;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
saa7110_s_std(struct v4l2_subdev * sd,v4l2_std_id std)258*4882a593Smuzhiyun static int saa7110_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	if (decoder->norm != std) {
263*4882a593Smuzhiyun 		decoder->norm = std;
264*4882a593Smuzhiyun 		/*saa7110_write(sd, 0x06, 0x03);*/
265*4882a593Smuzhiyun 		if (std & V4L2_STD_NTSC) {
266*4882a593Smuzhiyun 			saa7110_write(sd, 0x0D, 0x86);
267*4882a593Smuzhiyun 			saa7110_write(sd, 0x0F, 0x50);
268*4882a593Smuzhiyun 			saa7110_write(sd, 0x11, 0x2C);
269*4882a593Smuzhiyun 			/*saa7110_write(sd, 0x2E, 0x81);*/
270*4882a593Smuzhiyun 			v4l2_dbg(1, debug, sd, "switched to NTSC\n");
271*4882a593Smuzhiyun 		} else if (std & V4L2_STD_PAL) {
272*4882a593Smuzhiyun 			saa7110_write(sd, 0x0D, 0x86);
273*4882a593Smuzhiyun 			saa7110_write(sd, 0x0F, 0x10);
274*4882a593Smuzhiyun 			saa7110_write(sd, 0x11, 0x59);
275*4882a593Smuzhiyun 			/*saa7110_write(sd, 0x2E, 0x9A);*/
276*4882a593Smuzhiyun 			v4l2_dbg(1, debug, sd, "switched to PAL\n");
277*4882a593Smuzhiyun 		} else if (std & V4L2_STD_SECAM) {
278*4882a593Smuzhiyun 			saa7110_write(sd, 0x0D, 0x87);
279*4882a593Smuzhiyun 			saa7110_write(sd, 0x0F, 0x10);
280*4882a593Smuzhiyun 			saa7110_write(sd, 0x11, 0x59);
281*4882a593Smuzhiyun 			/*saa7110_write(sd, 0x2E, 0x9A);*/
282*4882a593Smuzhiyun 			v4l2_dbg(1, debug, sd, "switched to SECAM\n");
283*4882a593Smuzhiyun 		} else {
284*4882a593Smuzhiyun 			return -EINVAL;
285*4882a593Smuzhiyun 		}
286*4882a593Smuzhiyun 	}
287*4882a593Smuzhiyun 	return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun 
saa7110_s_routing(struct v4l2_subdev * sd,u32 input,u32 output,u32 config)290*4882a593Smuzhiyun static int saa7110_s_routing(struct v4l2_subdev *sd,
291*4882a593Smuzhiyun 			     u32 input, u32 output, u32 config)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	if (input >= SAA7110_MAX_INPUT) {
296*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "input=%d not available\n", input);
297*4882a593Smuzhiyun 		return -EINVAL;
298*4882a593Smuzhiyun 	}
299*4882a593Smuzhiyun 	if (decoder->input != input) {
300*4882a593Smuzhiyun 		saa7110_selmux(sd, input);
301*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "switched to input=%d\n", input);
302*4882a593Smuzhiyun 	}
303*4882a593Smuzhiyun 	return 0;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun 
saa7110_s_stream(struct v4l2_subdev * sd,int enable)306*4882a593Smuzhiyun static int saa7110_s_stream(struct v4l2_subdev *sd, int enable)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	if (decoder->enable != enable) {
311*4882a593Smuzhiyun 		decoder->enable = enable;
312*4882a593Smuzhiyun 		saa7110_write(sd, 0x0E, enable ? 0x18 : 0x80);
313*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "YUV %s\n", enable ? "on" : "off");
314*4882a593Smuzhiyun 	}
315*4882a593Smuzhiyun 	return 0;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
saa7110_s_ctrl(struct v4l2_ctrl * ctrl)318*4882a593Smuzhiyun static int saa7110_s_ctrl(struct v4l2_ctrl *ctrl)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun 	struct v4l2_subdev *sd = to_sd(ctrl);
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	switch (ctrl->id) {
323*4882a593Smuzhiyun 	case V4L2_CID_BRIGHTNESS:
324*4882a593Smuzhiyun 		saa7110_write(sd, 0x19, ctrl->val);
325*4882a593Smuzhiyun 		break;
326*4882a593Smuzhiyun 	case V4L2_CID_CONTRAST:
327*4882a593Smuzhiyun 		saa7110_write(sd, 0x13, ctrl->val);
328*4882a593Smuzhiyun 		break;
329*4882a593Smuzhiyun 	case V4L2_CID_SATURATION:
330*4882a593Smuzhiyun 		saa7110_write(sd, 0x12, ctrl->val);
331*4882a593Smuzhiyun 		break;
332*4882a593Smuzhiyun 	case V4L2_CID_HUE:
333*4882a593Smuzhiyun 		saa7110_write(sd, 0x07, ctrl->val);
334*4882a593Smuzhiyun 		break;
335*4882a593Smuzhiyun 	default:
336*4882a593Smuzhiyun 		return -EINVAL;
337*4882a593Smuzhiyun 	}
338*4882a593Smuzhiyun 	return 0;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun static const struct v4l2_ctrl_ops saa7110_ctrl_ops = {
344*4882a593Smuzhiyun 	.s_ctrl = saa7110_s_ctrl,
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops saa7110_video_ops = {
348*4882a593Smuzhiyun 	.s_std = saa7110_s_std,
349*4882a593Smuzhiyun 	.s_routing = saa7110_s_routing,
350*4882a593Smuzhiyun 	.s_stream = saa7110_s_stream,
351*4882a593Smuzhiyun 	.querystd = saa7110_querystd,
352*4882a593Smuzhiyun 	.g_input_status = saa7110_g_input_status,
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun static const struct v4l2_subdev_ops saa7110_ops = {
356*4882a593Smuzhiyun 	.video = &saa7110_video_ops,
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
360*4882a593Smuzhiyun 
saa7110_probe(struct i2c_client * client,const struct i2c_device_id * id)361*4882a593Smuzhiyun static int saa7110_probe(struct i2c_client *client,
362*4882a593Smuzhiyun 			const struct i2c_device_id *id)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun 	struct saa7110 *decoder;
365*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
366*4882a593Smuzhiyun 	int rv;
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun 	/* Check if the adapter supports the needed features */
369*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter,
370*4882a593Smuzhiyun 		I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
371*4882a593Smuzhiyun 		return -ENODEV;
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun 	v4l_info(client, "chip found @ 0x%x (%s)\n",
374*4882a593Smuzhiyun 			client->addr << 1, client->adapter->name);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
377*4882a593Smuzhiyun 	if (!decoder)
378*4882a593Smuzhiyun 		return -ENOMEM;
379*4882a593Smuzhiyun 	sd = &decoder->sd;
380*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &saa7110_ops);
381*4882a593Smuzhiyun 	decoder->norm = V4L2_STD_PAL;
382*4882a593Smuzhiyun 	decoder->input = 0;
383*4882a593Smuzhiyun 	decoder->enable = 1;
384*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&decoder->hdl, 2);
385*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
386*4882a593Smuzhiyun 		V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
387*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
388*4882a593Smuzhiyun 		V4L2_CID_CONTRAST, 0, 127, 1, 64);
389*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
390*4882a593Smuzhiyun 		V4L2_CID_SATURATION, 0, 127, 1, 64);
391*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
392*4882a593Smuzhiyun 		V4L2_CID_HUE, -128, 127, 1, 0);
393*4882a593Smuzhiyun 	sd->ctrl_handler = &decoder->hdl;
394*4882a593Smuzhiyun 	if (decoder->hdl.error) {
395*4882a593Smuzhiyun 		int err = decoder->hdl.error;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 		v4l2_ctrl_handler_free(&decoder->hdl);
398*4882a593Smuzhiyun 		return err;
399*4882a593Smuzhiyun 	}
400*4882a593Smuzhiyun 	v4l2_ctrl_handler_setup(&decoder->hdl);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	init_waitqueue_head(&decoder->wq);
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	rv = saa7110_write_block(sd, initseq, sizeof(initseq));
405*4882a593Smuzhiyun 	if (rv < 0) {
406*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "init status %d\n", rv);
407*4882a593Smuzhiyun 	} else {
408*4882a593Smuzhiyun 		int ver, status;
409*4882a593Smuzhiyun 		saa7110_write(sd, 0x21, 0x10);
410*4882a593Smuzhiyun 		saa7110_write(sd, 0x0e, 0x18);
411*4882a593Smuzhiyun 		saa7110_write(sd, 0x0D, 0x04);
412*4882a593Smuzhiyun 		ver = saa7110_read(sd);
413*4882a593Smuzhiyun 		saa7110_write(sd, 0x0D, 0x06);
414*4882a593Smuzhiyun 		/*mdelay(150);*/
415*4882a593Smuzhiyun 		status = saa7110_read(sd);
416*4882a593Smuzhiyun 		v4l2_dbg(1, debug, sd, "version %x, status=0x%02x\n",
417*4882a593Smuzhiyun 			       ver, status);
418*4882a593Smuzhiyun 		saa7110_write(sd, 0x0D, 0x86);
419*4882a593Smuzhiyun 		saa7110_write(sd, 0x0F, 0x10);
420*4882a593Smuzhiyun 		saa7110_write(sd, 0x11, 0x59);
421*4882a593Smuzhiyun 		/*saa7110_write(sd, 0x2E, 0x9A);*/
422*4882a593Smuzhiyun 	}
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun 	/*saa7110_selmux(sd,0);*/
425*4882a593Smuzhiyun 	/*determine_norm(sd);*/
426*4882a593Smuzhiyun 	/* setup and implicit mode 0 select has been performed */
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun 
saa7110_remove(struct i2c_client * client)431*4882a593Smuzhiyun static int saa7110_remove(struct i2c_client *client)
432*4882a593Smuzhiyun {
433*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
434*4882a593Smuzhiyun 	struct saa7110 *decoder = to_saa7110(sd);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
437*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&decoder->hdl);
438*4882a593Smuzhiyun 	return 0;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun /* ----------------------------------------------------------------------- */
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun static const struct i2c_device_id saa7110_id[] = {
444*4882a593Smuzhiyun 	{ "saa7110", 0 },
445*4882a593Smuzhiyun 	{ }
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, saa7110_id);
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun static struct i2c_driver saa7110_driver = {
450*4882a593Smuzhiyun 	.driver = {
451*4882a593Smuzhiyun 		.name	= "saa7110",
452*4882a593Smuzhiyun 	},
453*4882a593Smuzhiyun 	.probe		= saa7110_probe,
454*4882a593Smuzhiyun 	.remove		= saa7110_remove,
455*4882a593Smuzhiyun 	.id_table	= saa7110_id,
456*4882a593Smuzhiyun };
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun module_i2c_driver(saa7110_driver);
459