1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * s5k3l6xx camera driver
4 *
5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01
9 * 1.add flip and mirror support
10 * 2.fix stream on sequential
11 *
12 */
13
14 // #define DEBUG
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/delay.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/i2c.h>
20 #include <linux/module.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
25 #include <linux/version.h>
26 #include <linux/compat.h>
27 #include <linux/rk-camera-module.h>
28 #include <media/media-entity.h>
29 #include <media/v4l2-async.h>
30 #include <media/v4l2-ctrls.h>
31 #include <media/v4l2-subdev.h>
32 #include <linux/pinctrl/consumer.h>
33
34 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
35
36 #ifndef V4L2_CID_DIGITAL_GAIN
37 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
38 #endif
39
40 #define S5K3L6XX_LINK_FREQ_600MHZ 600000000U
41 #define S5K3L6XX_LINK_FREQ_284MHZ 284000000U
42 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
43 #define S5K3L6XX_PIXEL_RATE (S5K3L6XX_LINK_FREQ_600MHZ * 2LL * 4LL / 10LL)
44 #define S5K3L6XX_XVCLK_FREQ 24000000
45
46 #define CHIP_ID 0x30c6
47 #define S5K3L6XX_REG_CHIP_ID 0x0000
48
49 #define S5K3L6XX_REG_CTRL_MODE 0x0100
50 #define S5K3L6XX_MODE_SW_STANDBY 0x0
51 #define S5K3L6XX_MODE_STREAMING BIT(0)
52 #define S5K3L6XX_REG_STREAM_ON 0x3C1E
53
54 #define S5K3L6XX_REG_EXPOSURE 0x0202
55 #define S5K3L6XX_EXPOSURE_MIN 1
56 #define S5K3L6XX_EXPOSURE_STEP 1
57 #define S5K3L6XX_VTS_MAX 0xfff7
58
59 #define S5K3L6XX_REG_ANALOG_GAIN 0x0204
60 #define S5K3L6XX_GAIN_MIN 0x20
61 #define S5K3L6XX_GAIN_MAX 0x200
62 #define S5K3L6XX_GAIN_STEP 1
63 #define S5K3L6XX_GAIN_DEFAULT 0x100
64
65 #define S5K3L6XX_REG_TEST_PATTERN 0x0601
66 #define S5K3L6XX_TEST_PATTERN_ENABLE 0x80
67 #define S5K3L6XX_TEST_PATTERN_DISABLE 0x0
68
69 #define S5K3L6XX_REG_VTS 0x0340
70
71 #define REG_NULL 0xFFFF
72
73 #define S5K3L6XX_REG_VALUE_08BIT 1
74 #define S5K3L6XX_REG_VALUE_16BIT 2
75 #define S5K3L6XX_REG_VALUE_24BIT 3
76
77 #define S5K3L6XX_LANES 4
78 #define S5K3L6XX_BITS_PER_SAMPLE 10
79
80 #define S5K3L6XX_CHIP_REVISION_REG 0x0002
81
82 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
83 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
84
85 #define S5K3L6XX_NAME "s5k3l6xx"
86
87 // #define S5K3L6XX_MIRROR
88 // #define S5K3L6XX_FLIP
89 // #define S5K3L6XX_FLIP_MIRROR
90 #ifdef S5K3L6XX_MIRROR
91 #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
92 #elif defined S5K3L6XX_FLIP
93 #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
94 #elif defined S5K3L6XX_FLIP_MIRROR
95 #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGBRG10_1X10
96 #else
97 #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGRBG10_1X10
98 #endif
99
100 static const char * const s5k3l6xx_supply_names[] = {
101 "avdd", /* Analog power */
102 "dovdd", /* Digital I/O power */
103 "dvdd", /* Digital core power */
104 };
105
106 #define S5K3L6XX_NUM_SUPPLIES ARRAY_SIZE(s5k3l6xx_supply_names)
107
108 struct regval {
109 u16 addr;
110 u16 val;
111 };
112
113 struct s5k3l6xx_mode {
114 u32 width;
115 u32 height;
116 struct v4l2_fract max_fps;
117 u32 hts_def;
118 u32 vts_def;
119 u32 exp_def;
120 u32 link_freq_idx;
121 u32 bpp;
122 const struct regval *reg_list;
123 };
124
125 struct s5k3l6xx {
126 struct i2c_client *client;
127 struct clk *xvclk;
128 struct gpio_desc *power_gpio;
129 struct gpio_desc *reset_gpio;
130 struct gpio_desc *pwdn_gpio;
131 struct regulator_bulk_data supplies[S5K3L6XX_NUM_SUPPLIES];
132
133 struct pinctrl *pinctrl;
134 struct pinctrl_state *pins_default;
135 struct pinctrl_state *pins_sleep;
136
137 struct v4l2_subdev subdev;
138 struct media_pad pad;
139 struct v4l2_ctrl_handler ctrl_handler;
140 struct v4l2_ctrl *exposure;
141 struct v4l2_ctrl *anal_gain;
142 struct v4l2_ctrl *digi_gain;
143 struct v4l2_ctrl *hblank;
144 struct v4l2_ctrl *vblank;
145 struct v4l2_ctrl *pixel_rate;
146 struct v4l2_ctrl *link_freq;
147 struct v4l2_ctrl *test_pattern;
148 struct mutex mutex;
149 bool streaming;
150 bool power_on;
151 const struct s5k3l6xx_mode *cur_mode;
152 u32 module_index;
153 const char *module_facing;
154 const char *module_name;
155 const char *len_name;
156 };
157
158 #define to_s5k3l6xx(sd) container_of(sd, struct s5k3l6xx, subdev)
159
160 static const struct regval s5k3l6xx_4208x3120_30fps_regs[] = {
161 #ifdef S5K3L6XX_MIRROR
162 {0x0100, 0x0001},
163 #elif defined S5K3L6XX_FLIP
164 {0x0100, 0x0002},
165 #elif defined S5K3L6XX_FLIP_MIRROR
166 {0x0100, 0x0003},
167 #else
168 {0x0100, 0x0000},
169 #endif
170 {0x0000, 0x0060},
171 {0x0000, 0x30C6},
172 {0x0A02, 0x3400},
173 {0x3084, 0x1314},
174 {0x3266, 0x0001},
175 {0x3242, 0x2020},
176 {0x306A, 0x2F4C},
177 {0x306C, 0xCA01},
178 {0x307A, 0x0D20},
179 {0x309E, 0x002D},
180 {0x3072, 0x0013},
181 {0x3074, 0x0977},
182 {0x3076, 0x9411},
183 {0x3024, 0x0016},
184 {0x3070, 0x3D00},
185 {0x3002, 0x0E00},
186 {0x3006, 0x1000},
187 {0x300A, 0x0C00},
188 {0x3010, 0x0400},
189 {0x3018, 0xC500},
190 {0x303A, 0x0204},
191 {0x3452, 0x0001},
192 {0x3454, 0x0001},
193 {0x3456, 0x0001},
194 {0x3458, 0x0001},
195 {0x345a, 0x0002},
196 {0x345C, 0x0014},
197 {0x345E, 0x0002},
198 {0x3460, 0x0014},
199 {0x3464, 0x0006},
200 {0x3466, 0x0012},
201 {0x3468, 0x0012},
202 {0x346A, 0x0012},
203 {0x346C, 0x0012},
204 {0x346E, 0x0012},
205 {0x3470, 0x0012},
206 {0x3472, 0x0008},
207 {0x3474, 0x0004},
208 {0x3476, 0x0044},
209 {0x3478, 0x0004},
210 {0x347A, 0x0044},
211 {0x347E, 0x0006},
212 {0x3480, 0x0010},
213 {0x3482, 0x0010},
214 {0x3484, 0x0010},
215 {0x3486, 0x0010},
216 {0x3488, 0x0010},
217 {0x348A, 0x0010},
218 {0x348E, 0x000C},
219 {0x3490, 0x004C},
220 {0x3492, 0x000C},
221 {0x3494, 0x004C},
222 {0x3496, 0x0020},
223 {0x3498, 0x0006},
224 {0x349A, 0x0008},
225 {0x349C, 0x0008},
226 {0x349E, 0x0008},
227 {0x34A0, 0x0008},
228 {0x34A2, 0x0008},
229 {0x34A4, 0x0008},
230 {0x34A8, 0x001A},
231 {0x34AA, 0x002A},
232 {0x34AC, 0x001A},
233 {0x34AE, 0x002A},
234 {0x34B0, 0x0080},
235 {0x34B2, 0x0006},
236 {0x32A2, 0x0000},
237 {0x32A4, 0x0000},
238 {0x32A6, 0x0000},
239 {0x32A8, 0x0000},
240 {0x0344, 0x0008},
241 {0x0346, 0x0008},
242 {0x0348, 0x1077},
243 {0x034A, 0x0C37},
244 {0x034C, 0x1070},
245 {0x034E, 0x0C30},
246 {0x0900, 0x0000},
247 {0x0380, 0x0001},
248 {0x0382, 0x0001},
249 {0x0384, 0x0001},
250 {0x0386, 0x0001},
251 {0x0114, 0x0330},
252 {0x0110, 0x0002},
253 {0x0136, 0x1800},
254 {0x0304, 0x0004},
255 {0x0306, 0x0078},
256 {0x3C1E, 0x0000},
257 {0x030C, 0x0004},
258 {0x030E, 0x0064},
259 {0x3C16, 0x0000},
260 {0x0300, 0x0006},
261 {0x0342, 0x1320},
262 {0x0340, 0x0CBC},
263 {0x38C4, 0x0009},
264 {0x38D8, 0x002A},
265 {0x38DA, 0x000A},
266 {0x38DC, 0x000B},
267 {0x38C2, 0x000A},
268 {0x38C0, 0x000F},
269 {0x38D6, 0x000A},
270 {0x38D4, 0x0009},
271 {0x38B0, 0x000F},
272 {0x3932, 0x1000},
273 {0x3934, 0x0180},
274 {0x3938, 0x000C},
275 {0x0820, 0x04B0},
276 {0x380C, 0x0090},
277 {0x3064, 0xEFCF},
278 {0x309C, 0x0640},
279 {0x3090, 0x8800},
280 {0x3238, 0x000C},
281 {0x314A, 0x5F00},
282 {0x32B2, 0x0000},
283 {0x32B4, 0x0000},
284 {0x32B6, 0x0000},
285 {0x32B8, 0x0000},
286 {0x3300, 0x0000},
287 {0x3400, 0x0000},
288 {0x3402, 0x4E42},
289 {0x32B2, 0x0006},
290 {0x32B4, 0x0006},
291 {0x32B6, 0x0006},
292 {0x32B8, 0x0006},
293 {0x3C34, 0x0008},
294 {0x3C36, 0x0000},
295 {0x3C38, 0x0000},
296 {0x393E, 0x4000},
297 {REG_NULL, 0x0000},
298 };
299
300 static const struct regval s5k3l6xx_2104x1560_30fps_regs[] = {
301 #ifdef S5K3L6XX_MIRROR
302 {0x0100, 0x0001},
303 #elif defined S5K3L6XX_FLIP
304 {0x0100, 0x0002},
305 #elif defined S5K3L6XX_FLIP_MIRROR
306 {0x0100, 0x0003},
307 #else
308 {0x0100, 0x0000},
309 #endif
310 {0x0000, 0x0050},
311 {0x0000, 0x30C6},
312 {0x0A02, 0x3400},
313 {0x3084, 0x1314},
314 {0x3266, 0x0001},
315 {0x3242, 0x2020},
316 {0x306A, 0x2F4C},
317 {0x306C, 0xCA01},
318 {0x307A, 0x0D20},
319 {0x309E, 0x002D},
320 {0x3072, 0x0013},
321 {0x3074, 0x0977},
322 {0x3076, 0x9411},
323 {0x3024, 0x0016},
324 {0x3070, 0x3D00},
325 {0x3002, 0x0E00},
326 {0x3006, 0x1000},
327 {0x300A, 0x0C00},
328 {0x3010, 0x0400},
329 {0x3018, 0xC500},
330 {0x303A, 0x0204},
331 {0x3452, 0x0001},
332 {0x3454, 0x0001},
333 {0x3456, 0x0001},
334 {0x3458, 0x0001},
335 {0x345a, 0x0002},
336 {0x345C, 0x0014},
337 {0x345E, 0x0002},
338 {0x3460, 0x0014},
339 {0x3464, 0x0006},
340 {0x3466, 0x0012},
341 {0x3468, 0x0012},
342 {0x346A, 0x0012},
343 {0x346C, 0x0012},
344 {0x346E, 0x0012},
345 {0x3470, 0x0012},
346 {0x3472, 0x0008},
347 {0x3474, 0x0004},
348 {0x3476, 0x0044},
349 {0x3478, 0x0004},
350 {0x347A, 0x0044},
351 {0x347E, 0x0006},
352 {0x3480, 0x0010},
353 {0x3482, 0x0010},
354 {0x3484, 0x0010},
355 {0x3486, 0x0010},
356 {0x3488, 0x0010},
357 {0x348A, 0x0010},
358 {0x348E, 0x000C},
359 {0x3490, 0x004C},
360 {0x3492, 0x000C},
361 {0x3494, 0x004C},
362 {0x3496, 0x0020},
363 {0x3498, 0x0006},
364 {0x349A, 0x0008},
365 {0x349C, 0x0008},
366 {0x349E, 0x0008},
367 {0x34A0, 0x0008},
368 {0x34A2, 0x0008},
369 {0x34A4, 0x0008},
370 {0x34A8, 0x001A},
371 {0x34AA, 0x002A},
372 {0x34AC, 0x001A},
373 {0x34AE, 0x002A},
374 {0x34B0, 0x0080},
375 {0x34B2, 0x0006},
376 {0x32A2, 0x0000},
377 {0x32A4, 0x0000},
378 {0x32A6, 0x0000},
379 {0x32A8, 0x0000},
380 {0x3066, 0x7E00},
381 {0x3004, 0x0800},
382 //mode setting
383 {0x0344, 0x0008},
384 {0x0346, 0x0008},
385 {0x0348, 0x1077},
386 {0x034A, 0x0C37},
387 {0x034C, 0x0838},
388 {0x034E, 0x0618},
389 {0x0900, 0x0122},
390 {0x0380, 0x0001},
391 {0x0382, 0x0001},
392 {0x0384, 0x0001},
393 {0x0386, 0x0003},
394 {0x0114, 0x0330},
395 {0x0110, 0x0002},
396 {0x0136, 0x1800},
397 {0x0304, 0x0004},
398 {0x0306, 0x0078},
399 {0x3C1E, 0x0000},
400 {0x030C, 0x0003},
401 {0x030E, 0x0047},
402 {0x3C16, 0x0001},
403 {0x0300, 0x0006},
404 {0x0342, 0x1320},
405 {0x0340, 0x0CBC},
406 {0x38C4, 0x0004},
407 {0x38D8, 0x0011},
408 {0x38DA, 0x0005},
409 {0x38DC, 0x0005},
410 {0x38C2, 0x0005},
411 {0x38C0, 0x0004},
412 {0x38D6, 0x0004},
413 {0x38D4, 0x0004},
414 {0x38B0, 0x0007},
415 {0x3932, 0x1000},
416 {0x3934, 0x0180},
417 {0x3938, 0x000C},
418 {0x0820, 0x0238},
419 {0x380C, 0x0049},
420 {0x3064, 0xFFCF},
421 {0x309C, 0x0640},
422 {0x3090, 0x8000},
423 {0x3238, 0x000B},
424 {0x314A, 0x5F02},
425 {0x3300, 0x0000},
426 {0x3400, 0x0000},
427 {0x3402, 0x4E46},
428 {0x32B2, 0x0008},
429 {0x32B4, 0x0008},
430 {0x32B6, 0x0008},
431 {0x32B8, 0x0008},
432 {0x3C34, 0x0048},
433 {0x3C36, 0x3000},
434 {0x3C38, 0x0020},
435 {0x393E, 0x4000},
436 {0x303A, 0x0204},
437 {0x3034, 0x4B01},
438 {0x3036, 0x0029},
439 {0x3032, 0x4800},
440 {0x320E, 0x049E},
441 {REG_NULL, 0x0000},
442 };
443
444 static const struct s5k3l6xx_mode supported_modes[] = {
445 {
446 .width = 4208,
447 .height = 3120,
448 .max_fps = {
449 .numerator = 10000,
450 .denominator = 300000,
451 },
452 .exp_def = 0x0cb0,
453 .hts_def = 0x1320,
454 .vts_def = 0x0cbc,
455 .bpp = 10,
456 .reg_list = s5k3l6xx_4208x3120_30fps_regs,
457 .link_freq_idx = 0,
458 },
459 {
460 .width = 2104,
461 .height = 1560,
462 .max_fps = {
463 .numerator = 10000,
464 .denominator = 300000,
465 },
466 .exp_def = 0x0cb0,
467 .hts_def = 0x1320,
468 .vts_def = 0x0cbc,
469 .bpp = 10,
470 .reg_list = s5k3l6xx_2104x1560_30fps_regs,
471 .link_freq_idx = 1,
472 },
473 };
474
475 static const s64 link_freq_items[] = {
476 S5K3L6XX_LINK_FREQ_600MHZ,
477 S5K3L6XX_LINK_FREQ_284MHZ,
478 };
479
480 static const char * const s5k3l6xx_test_pattern_menu[] = {
481 "Disabled",
482 "Vertical Color Bar Type 1",
483 "Vertical Color Bar Type 2",
484 "Vertical Color Bar Type 3"
485 };
486
487 /* Write registers up to 4 at a time */
s5k3l6xx_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)488 static int s5k3l6xx_write_reg(struct i2c_client *client, u16 reg,
489 u32 len, u32 val)
490 {
491 u32 buf_i, val_i;
492 u8 buf[6];
493 u8 *val_p;
494 __be32 val_be;
495
496 dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
497
498 if (len > 4)
499 return -EINVAL;
500
501 buf[0] = reg >> 8;
502 buf[1] = reg & 0xff;
503
504 val_be = cpu_to_be32(val);
505 val_p = (u8 *)&val_be;
506 buf_i = 2;
507 val_i = 4 - len;
508
509 while (val_i < 4)
510 buf[buf_i++] = val_p[val_i++];
511
512 if (i2c_master_send(client, buf, len + 2) != len + 2)
513 return -EIO;
514
515 return 0;
516 }
517
s5k3l6xx_write_array(struct i2c_client * client,const struct regval * regs)518 static int s5k3l6xx_write_array(struct i2c_client *client,
519 const struct regval *regs)
520 {
521 u32 i;
522 int ret = 0;
523
524 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
525 ret = s5k3l6xx_write_reg(client, regs[i].addr,
526 S5K3L6XX_REG_VALUE_16BIT,
527 regs[i].val);
528
529 return ret;
530 }
531
532 /* Read registers up to 4 at a time */
s5k3l6xx_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)533 static int s5k3l6xx_read_reg(struct i2c_client *client, u16 reg,
534 unsigned int len, u32 *val)
535 {
536 struct i2c_msg msgs[2];
537 u8 *data_be_p;
538 __be32 data_be = 0;
539 __be16 reg_addr_be = cpu_to_be16(reg);
540 int ret;
541
542 if (len > 4 || !len)
543 return -EINVAL;
544
545 data_be_p = (u8 *)&data_be;
546 /* Write register address */
547 msgs[0].addr = client->addr;
548 msgs[0].flags = 0;
549 msgs[0].len = 2;
550 msgs[0].buf = (u8 *)®_addr_be;
551
552 /* Read data from register */
553 msgs[1].addr = client->addr;
554 msgs[1].flags = I2C_M_RD;
555 msgs[1].len = len;
556 msgs[1].buf = &data_be_p[4 - len];
557
558 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
559 if (ret != ARRAY_SIZE(msgs))
560 return -EIO;
561
562 *val = be32_to_cpu(data_be);
563
564 return 0;
565 }
566
s5k3l6xx_get_reso_dist(const struct s5k3l6xx_mode * mode,struct v4l2_mbus_framefmt * framefmt)567 static int s5k3l6xx_get_reso_dist(const struct s5k3l6xx_mode *mode,
568 struct v4l2_mbus_framefmt *framefmt)
569 {
570 return abs(mode->width - framefmt->width) +
571 abs(mode->height - framefmt->height);
572 }
573
574 static const struct s5k3l6xx_mode *
s5k3l6xx_find_best_fit(struct v4l2_subdev_format * fmt)575 s5k3l6xx_find_best_fit(struct v4l2_subdev_format *fmt)
576 {
577 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
578 int dist;
579 int cur_best_fit = 0;
580 int cur_best_fit_dist = -1;
581 unsigned int i;
582
583 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
584 dist = s5k3l6xx_get_reso_dist(&supported_modes[i], framefmt);
585 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
586 cur_best_fit_dist = dist;
587 cur_best_fit = i;
588 }
589 }
590
591 return &supported_modes[cur_best_fit];
592 }
593
s5k3l6xx_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)594 static int s5k3l6xx_set_fmt(struct v4l2_subdev *sd,
595 struct v4l2_subdev_pad_config *cfg,
596 struct v4l2_subdev_format *fmt)
597 {
598 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
599 const struct s5k3l6xx_mode *mode;
600 s64 h_blank, vblank_def;
601 u64 pixel_rate = 0;
602 u32 lane_num = S5K3L6XX_LANES;
603
604 mutex_lock(&s5k3l6xx->mutex);
605
606 mode = s5k3l6xx_find_best_fit(fmt);
607 fmt->format.code = S5K3L6XX_MEDIA_BUS_FMT;
608 fmt->format.width = mode->width;
609 fmt->format.height = mode->height;
610 fmt->format.field = V4L2_FIELD_NONE;
611 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
612 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
613 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
614 #else
615 mutex_unlock(&s5k3l6xx->mutex);
616 return -ENOTTY;
617 #endif
618 } else {
619 s5k3l6xx->cur_mode = mode;
620 h_blank = mode->hts_def - mode->width;
621 __v4l2_ctrl_modify_range(s5k3l6xx->hblank, h_blank,
622 h_blank, 1, h_blank);
623 vblank_def = mode->vts_def - mode->height;
624 __v4l2_ctrl_modify_range(s5k3l6xx->vblank, vblank_def,
625 S5K3L6XX_VTS_MAX - mode->height,
626 1, vblank_def);
627 pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
628
629 __v4l2_ctrl_s_ctrl_int64(s5k3l6xx->pixel_rate,
630 pixel_rate);
631 __v4l2_ctrl_s_ctrl(s5k3l6xx->link_freq,
632 mode->link_freq_idx);
633 }
634
635 mutex_unlock(&s5k3l6xx->mutex);
636
637 return 0;
638 }
639
s5k3l6xx_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)640 static int s5k3l6xx_get_fmt(struct v4l2_subdev *sd,
641 struct v4l2_subdev_pad_config *cfg,
642 struct v4l2_subdev_format *fmt)
643 {
644 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
645 const struct s5k3l6xx_mode *mode = s5k3l6xx->cur_mode;
646
647 mutex_lock(&s5k3l6xx->mutex);
648 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
649 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
650 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
651 #else
652 mutex_unlock(&s5k3l6xx->mutex);
653 return -ENOTTY;
654 #endif
655 } else {
656 fmt->format.width = mode->width;
657 fmt->format.height = mode->height;
658 fmt->format.code = S5K3L6XX_MEDIA_BUS_FMT;
659 fmt->format.field = V4L2_FIELD_NONE;
660 }
661 mutex_unlock(&s5k3l6xx->mutex);
662
663 return 0;
664 }
665
s5k3l6xx_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)666 static int s5k3l6xx_enum_mbus_code(struct v4l2_subdev *sd,
667 struct v4l2_subdev_pad_config *cfg,
668 struct v4l2_subdev_mbus_code_enum *code)
669 {
670 if (code->index != 0)
671 return -EINVAL;
672 code->code = S5K3L6XX_MEDIA_BUS_FMT;
673
674 return 0;
675 }
676
s5k3l6xx_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)677 static int s5k3l6xx_enum_frame_sizes(struct v4l2_subdev *sd,
678 struct v4l2_subdev_pad_config *cfg,
679 struct v4l2_subdev_frame_size_enum *fse)
680 {
681 if (fse->index >= ARRAY_SIZE(supported_modes))
682 return -EINVAL;
683
684 if (fse->code != S5K3L6XX_MEDIA_BUS_FMT)
685 return -EINVAL;
686
687 fse->min_width = supported_modes[fse->index].width;
688 fse->max_width = supported_modes[fse->index].width;
689 fse->max_height = supported_modes[fse->index].height;
690 fse->min_height = supported_modes[fse->index].height;
691
692 return 0;
693 }
694
s5k3l6xx_enable_test_pattern(struct s5k3l6xx * s5k3l6xx,u32 pattern)695 static int s5k3l6xx_enable_test_pattern(struct s5k3l6xx *s5k3l6xx, u32 pattern)
696 {
697 u32 val;
698
699 if (pattern)
700 val = (pattern - 1) | S5K3L6XX_TEST_PATTERN_ENABLE;
701 else
702 val = S5K3L6XX_TEST_PATTERN_DISABLE;
703
704 return s5k3l6xx_write_reg(s5k3l6xx->client,
705 S5K3L6XX_REG_TEST_PATTERN,
706 S5K3L6XX_REG_VALUE_08BIT,
707 val);
708 }
709
s5k3l6xx_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)710 static int s5k3l6xx_g_frame_interval(struct v4l2_subdev *sd,
711 struct v4l2_subdev_frame_interval *fi)
712 {
713 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
714 const struct s5k3l6xx_mode *mode = s5k3l6xx->cur_mode;
715
716 mutex_lock(&s5k3l6xx->mutex);
717 fi->interval = mode->max_fps;
718 mutex_unlock(&s5k3l6xx->mutex);
719
720 return 0;
721 }
722
s5k3l6xx_get_module_inf(struct s5k3l6xx * s5k3l6xx,struct rkmodule_inf * inf)723 static void s5k3l6xx_get_module_inf(struct s5k3l6xx *s5k3l6xx,
724 struct rkmodule_inf *inf)
725 {
726 memset(inf, 0, sizeof(*inf));
727 strscpy(inf->base.sensor, S5K3L6XX_NAME, sizeof(inf->base.sensor));
728 strscpy(inf->base.module, s5k3l6xx->module_name,
729 sizeof(inf->base.module));
730 strscpy(inf->base.lens, s5k3l6xx->len_name, sizeof(inf->base.lens));
731 }
732
s5k3l6xx_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)733 static long s5k3l6xx_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
734 {
735 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
736 long ret = 0;
737 u32 stream = 0;
738
739 switch (cmd) {
740 case RKMODULE_GET_MODULE_INFO:
741 s5k3l6xx_get_module_inf(s5k3l6xx, (struct rkmodule_inf *)arg);
742 break;
743 case RKMODULE_SET_QUICK_STREAM:
744
745 stream = *((u32 *)arg);
746
747 if (stream)
748 ret = s5k3l6xx_write_reg(s5k3l6xx->client,
749 S5K3L6XX_REG_CTRL_MODE,
750 S5K3L6XX_REG_VALUE_08BIT,
751 S5K3L6XX_MODE_STREAMING);
752 else
753 ret = s5k3l6xx_write_reg(s5k3l6xx->client,
754 S5K3L6XX_REG_CTRL_MODE,
755 S5K3L6XX_REG_VALUE_08BIT,
756 S5K3L6XX_MODE_SW_STANDBY);
757 break;
758 default:
759 ret = -ENOIOCTLCMD;
760 break;
761 }
762
763 return ret;
764 }
765
766 #ifdef CONFIG_COMPAT
s5k3l6xx_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)767 static long s5k3l6xx_compat_ioctl32(struct v4l2_subdev *sd,
768 unsigned int cmd, unsigned long arg)
769 {
770 void __user *up = compat_ptr(arg);
771 struct rkmodule_inf *inf;
772 struct rkmodule_awb_cfg *cfg;
773 long ret = 0;
774 u32 stream = 0;
775
776 switch (cmd) {
777 case RKMODULE_GET_MODULE_INFO:
778 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
779 if (!inf) {
780 ret = -ENOMEM;
781 return ret;
782 }
783
784 ret = s5k3l6xx_ioctl(sd, cmd, inf);
785 if (!ret) {
786 ret = copy_to_user(up, inf, sizeof(*inf));
787 if (ret)
788 ret = -EFAULT;
789 }
790 kfree(inf);
791 break;
792 case RKMODULE_AWB_CFG:
793 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
794 if (!cfg) {
795 ret = -ENOMEM;
796 return ret;
797 }
798
799 ret = copy_from_user(cfg, up, sizeof(*cfg));
800 if (!ret)
801 ret = s5k3l6xx_ioctl(sd, cmd, cfg);
802 else
803 ret = -EFAULT;
804 kfree(cfg);
805 break;
806 case RKMODULE_SET_QUICK_STREAM:
807 ret = copy_from_user(&stream, up, sizeof(u32));
808 if (!ret)
809 ret = s5k3l6xx_ioctl(sd, cmd, &stream);
810 else
811 ret = -EFAULT;
812 break;
813 default:
814 ret = -ENOIOCTLCMD;
815 break;
816 }
817
818 return ret;
819 }
820 #endif
821
__s5k3l6xx_start_stream(struct s5k3l6xx * s5k3l6xx)822 static int __s5k3l6xx_start_stream(struct s5k3l6xx *s5k3l6xx)
823 {
824 int ret;
825
826 ret = s5k3l6xx_write_array(s5k3l6xx->client, s5k3l6xx->cur_mode->reg_list);
827 if (ret)
828 return ret;
829
830 /* In case these controls are set before streaming */
831 mutex_unlock(&s5k3l6xx->mutex);
832 ret = v4l2_ctrl_handler_setup(&s5k3l6xx->ctrl_handler);
833 mutex_lock(&s5k3l6xx->mutex);
834 if (ret)
835 return ret;
836
837 s5k3l6xx_write_reg(s5k3l6xx->client,
838 S5K3L6XX_REG_STREAM_ON,
839 S5K3L6XX_REG_VALUE_08BIT,
840 S5K3L6XX_MODE_STREAMING);
841 s5k3l6xx_write_reg(s5k3l6xx->client,
842 S5K3L6XX_REG_CTRL_MODE,
843 S5K3L6XX_REG_VALUE_08BIT,
844 S5K3L6XX_MODE_STREAMING);
845 s5k3l6xx_write_reg(s5k3l6xx->client,
846 S5K3L6XX_REG_STREAM_ON,
847 S5K3L6XX_REG_VALUE_08BIT,
848 S5K3L6XX_MODE_SW_STANDBY);
849 return 0;
850 }
851
__s5k3l6xx_stop_stream(struct s5k3l6xx * s5k3l6xx)852 static int __s5k3l6xx_stop_stream(struct s5k3l6xx *s5k3l6xx)
853 {
854 return s5k3l6xx_write_reg(s5k3l6xx->client,
855 S5K3L6XX_REG_CTRL_MODE,
856 S5K3L6XX_REG_VALUE_08BIT,
857 S5K3L6XX_MODE_SW_STANDBY);
858 }
859
s5k3l6xx_s_stream(struct v4l2_subdev * sd,int on)860 static int s5k3l6xx_s_stream(struct v4l2_subdev *sd, int on)
861 {
862 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
863 struct i2c_client *client = s5k3l6xx->client;
864 int ret = 0;
865
866 dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
867 s5k3l6xx->cur_mode->width,
868 s5k3l6xx->cur_mode->height,
869 DIV_ROUND_CLOSEST(s5k3l6xx->cur_mode->max_fps.denominator,
870 s5k3l6xx->cur_mode->max_fps.numerator));
871
872 mutex_lock(&s5k3l6xx->mutex);
873 on = !!on;
874 if (on == s5k3l6xx->streaming)
875 goto unlock_and_return;
876
877 if (on) {
878 ret = pm_runtime_get_sync(&client->dev);
879 if (ret < 0) {
880 pm_runtime_put_noidle(&client->dev);
881 goto unlock_and_return;
882 }
883
884 ret = __s5k3l6xx_start_stream(s5k3l6xx);
885 if (ret) {
886 v4l2_err(sd, "start stream failed while write regs\n");
887 pm_runtime_put(&client->dev);
888 goto unlock_and_return;
889 }
890 } else {
891 __s5k3l6xx_stop_stream(s5k3l6xx);
892 pm_runtime_put(&client->dev);
893 }
894
895 s5k3l6xx->streaming = on;
896
897 unlock_and_return:
898 mutex_unlock(&s5k3l6xx->mutex);
899
900 return ret;
901 }
902
s5k3l6xx_s_power(struct v4l2_subdev * sd,int on)903 static int s5k3l6xx_s_power(struct v4l2_subdev *sd, int on)
904 {
905 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
906 struct i2c_client *client = s5k3l6xx->client;
907 int ret = 0;
908
909 mutex_lock(&s5k3l6xx->mutex);
910
911 /* If the power state is not modified - no work to do. */
912 if (s5k3l6xx->power_on == !!on)
913 goto unlock_and_return;
914
915 if (on) {
916 ret = pm_runtime_get_sync(&client->dev);
917 if (ret < 0) {
918 pm_runtime_put_noidle(&client->dev);
919 goto unlock_and_return;
920 }
921
922 s5k3l6xx->power_on = true;
923 } else {
924 pm_runtime_put(&client->dev);
925 s5k3l6xx->power_on = false;
926 }
927
928 unlock_and_return:
929 mutex_unlock(&s5k3l6xx->mutex);
930
931 return ret;
932 }
933
934 /* Calculate the delay in us by clock rate and clock cycles */
s5k3l6xx_cal_delay(u32 cycles)935 static inline u32 s5k3l6xx_cal_delay(u32 cycles)
936 {
937 return DIV_ROUND_UP(cycles, S5K3L6XX_XVCLK_FREQ / 1000 / 1000);
938 }
939
__s5k3l6xx_power_on(struct s5k3l6xx * s5k3l6xx)940 static int __s5k3l6xx_power_on(struct s5k3l6xx *s5k3l6xx)
941 {
942 int ret;
943 u32 delay_us;
944 struct device *dev = &s5k3l6xx->client->dev;
945
946 if (!IS_ERR(s5k3l6xx->power_gpio))
947 gpiod_set_value_cansleep(s5k3l6xx->power_gpio, 1);
948
949 usleep_range(1000, 2000);
950
951 if (!IS_ERR_OR_NULL(s5k3l6xx->pins_default)) {
952 ret = pinctrl_select_state(s5k3l6xx->pinctrl,
953 s5k3l6xx->pins_default);
954 if (ret < 0)
955 dev_err(dev, "could not set pins\n");
956 }
957 ret = clk_set_rate(s5k3l6xx->xvclk, S5K3L6XX_XVCLK_FREQ);
958 if (ret < 0)
959 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
960 if (clk_get_rate(s5k3l6xx->xvclk) != S5K3L6XX_XVCLK_FREQ)
961 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
962 ret = clk_prepare_enable(s5k3l6xx->xvclk);
963 if (ret < 0) {
964 dev_err(dev, "Failed to enable xvclk\n");
965 return ret;
966 }
967 if (!IS_ERR(s5k3l6xx->reset_gpio))
968 gpiod_set_value_cansleep(s5k3l6xx->reset_gpio, 0);
969
970 ret = regulator_bulk_enable(S5K3L6XX_NUM_SUPPLIES, s5k3l6xx->supplies);
971 if (ret < 0) {
972 dev_err(dev, "Failed to enable regulators\n");
973 goto disable_clk;
974 }
975
976 if (!IS_ERR(s5k3l6xx->reset_gpio))
977 gpiod_set_value_cansleep(s5k3l6xx->reset_gpio, 1);
978
979 usleep_range(500, 1000);
980 if (!IS_ERR(s5k3l6xx->pwdn_gpio))
981 gpiod_set_value_cansleep(s5k3l6xx->pwdn_gpio, 1);
982
983 /* 8192 cycles prior to first SCCB transaction */
984 delay_us = s5k3l6xx_cal_delay(8192);
985 usleep_range(delay_us, delay_us * 2);
986
987 return 0;
988
989 disable_clk:
990 clk_disable_unprepare(s5k3l6xx->xvclk);
991
992 return ret;
993 }
994
__s5k3l6xx_power_off(struct s5k3l6xx * s5k3l6xx)995 static void __s5k3l6xx_power_off(struct s5k3l6xx *s5k3l6xx)
996 {
997 int ret;
998 struct device *dev = &s5k3l6xx->client->dev;
999
1000 if (!IS_ERR(s5k3l6xx->pwdn_gpio))
1001 gpiod_set_value_cansleep(s5k3l6xx->pwdn_gpio, 0);
1002 clk_disable_unprepare(s5k3l6xx->xvclk);
1003 if (!IS_ERR(s5k3l6xx->reset_gpio))
1004 gpiod_set_value_cansleep(s5k3l6xx->reset_gpio, 0);
1005
1006 if (!IS_ERR_OR_NULL(s5k3l6xx->pins_sleep)) {
1007 ret = pinctrl_select_state(s5k3l6xx->pinctrl,
1008 s5k3l6xx->pins_sleep);
1009 if (ret < 0)
1010 dev_dbg(dev, "could not set pins\n");
1011 }
1012 if (!IS_ERR(s5k3l6xx->power_gpio))
1013 gpiod_set_value_cansleep(s5k3l6xx->power_gpio, 0);
1014
1015 regulator_bulk_disable(S5K3L6XX_NUM_SUPPLIES, s5k3l6xx->supplies);
1016 }
1017
s5k3l6xx_runtime_resume(struct device * dev)1018 static int __maybe_unused s5k3l6xx_runtime_resume(struct device *dev)
1019 {
1020 struct i2c_client *client = to_i2c_client(dev);
1021 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1022 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
1023
1024 return __s5k3l6xx_power_on(s5k3l6xx);
1025 }
1026
s5k3l6xx_runtime_suspend(struct device * dev)1027 static int __maybe_unused s5k3l6xx_runtime_suspend(struct device *dev)
1028 {
1029 struct i2c_client *client = to_i2c_client(dev);
1030 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1031 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
1032
1033 __s5k3l6xx_power_off(s5k3l6xx);
1034
1035 return 0;
1036 }
1037
1038 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
s5k3l6xx_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1039 static int s5k3l6xx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1040 {
1041 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
1042 struct v4l2_mbus_framefmt *try_fmt =
1043 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1044 const struct s5k3l6xx_mode *def_mode = &supported_modes[0];
1045
1046 mutex_lock(&s5k3l6xx->mutex);
1047 /* Initialize try_fmt */
1048 try_fmt->width = def_mode->width;
1049 try_fmt->height = def_mode->height;
1050 try_fmt->code = S5K3L6XX_MEDIA_BUS_FMT;
1051 try_fmt->field = V4L2_FIELD_NONE;
1052
1053 mutex_unlock(&s5k3l6xx->mutex);
1054 /* No crop or compose */
1055
1056 return 0;
1057 }
1058 #endif
1059
s5k3l6xx_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1060 static int s5k3l6xx_enum_frame_interval(struct v4l2_subdev *sd,
1061 struct v4l2_subdev_pad_config *cfg,
1062 struct v4l2_subdev_frame_interval_enum *fie)
1063 {
1064 if (fie->index >= ARRAY_SIZE(supported_modes))
1065 return -EINVAL;
1066
1067 fie->code = S5K3L6XX_MEDIA_BUS_FMT;
1068
1069 fie->width = supported_modes[fie->index].width;
1070 fie->height = supported_modes[fie->index].height;
1071 fie->interval = supported_modes[fie->index].max_fps;
1072
1073 return 0;
1074 }
1075
s5k3l6xx_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)1076 static int s5k3l6xx_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
1077 struct v4l2_mbus_config *config)
1078 {
1079 if (2 == S5K3L6XX_LANES) {
1080 config->type = V4L2_MBUS_CSI2_DPHY;
1081 config->flags = V4L2_MBUS_CSI2_2_LANE |
1082 V4L2_MBUS_CSI2_CHANNEL_0 |
1083 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1084 } else if (4 == S5K3L6XX_LANES) {
1085 config->type = V4L2_MBUS_CSI2_DPHY;
1086 config->flags = V4L2_MBUS_CSI2_4_LANE |
1087 V4L2_MBUS_CSI2_CHANNEL_0 |
1088 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1089 }
1090
1091 return 0;
1092 }
1093
1094 #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
1095 #define DST_WIDTH_2096 2096
1096 #define DST_HEIGHT_1560 1560
1097
s5k3l6xx_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1098 static int s5k3l6xx_get_selection(struct v4l2_subdev *sd,
1099 struct v4l2_subdev_pad_config *cfg,
1100 struct v4l2_subdev_selection *sel)
1101 {
1102 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
1103
1104 if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
1105 if (s5k3l6xx->cur_mode->width == 2104) {
1106 sel->r.left = CROP_START(s5k3l6xx->cur_mode->width, DST_WIDTH_2096);
1107 sel->r.width = DST_WIDTH_2096;
1108 sel->r.top = CROP_START(s5k3l6xx->cur_mode->height, DST_HEIGHT_1560);
1109 sel->r.height = DST_HEIGHT_1560;
1110 } else {
1111 sel->r.left = CROP_START(s5k3l6xx->cur_mode->width,
1112 s5k3l6xx->cur_mode->width);
1113 sel->r.width = s5k3l6xx->cur_mode->width;
1114 sel->r.top = CROP_START(s5k3l6xx->cur_mode->height,
1115 s5k3l6xx->cur_mode->height);
1116 sel->r.height = s5k3l6xx->cur_mode->height;
1117 }
1118 return 0;
1119 }
1120
1121 return -EINVAL;
1122 }
1123
1124 static const struct dev_pm_ops s5k3l6xx_pm_ops = {
1125 SET_RUNTIME_PM_OPS(s5k3l6xx_runtime_suspend,
1126 s5k3l6xx_runtime_resume, NULL)
1127 };
1128
1129 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1130 static const struct v4l2_subdev_internal_ops s5k3l6xx_internal_ops = {
1131 .open = s5k3l6xx_open,
1132 };
1133 #endif
1134
1135 static const struct v4l2_subdev_core_ops s5k3l6xx_core_ops = {
1136 .s_power = s5k3l6xx_s_power,
1137 .ioctl = s5k3l6xx_ioctl,
1138 #ifdef CONFIG_COMPAT
1139 .compat_ioctl32 = s5k3l6xx_compat_ioctl32,
1140 #endif
1141 };
1142
1143 static const struct v4l2_subdev_video_ops s5k3l6xx_video_ops = {
1144 .s_stream = s5k3l6xx_s_stream,
1145 .g_frame_interval = s5k3l6xx_g_frame_interval,
1146 };
1147
1148 static const struct v4l2_subdev_pad_ops s5k3l6xx_pad_ops = {
1149 .enum_mbus_code = s5k3l6xx_enum_mbus_code,
1150 .enum_frame_size = s5k3l6xx_enum_frame_sizes,
1151 .enum_frame_interval = s5k3l6xx_enum_frame_interval,
1152 .get_fmt = s5k3l6xx_get_fmt,
1153 .set_fmt = s5k3l6xx_set_fmt,
1154 .get_selection = s5k3l6xx_get_selection,
1155 .get_mbus_config = s5k3l6xx_g_mbus_config,
1156 };
1157
1158 static const struct v4l2_subdev_ops s5k3l6xx_subdev_ops = {
1159 .core = &s5k3l6xx_core_ops,
1160 .video = &s5k3l6xx_video_ops,
1161 .pad = &s5k3l6xx_pad_ops,
1162 };
1163
s5k3l6xx_set_ctrl(struct v4l2_ctrl * ctrl)1164 static int s5k3l6xx_set_ctrl(struct v4l2_ctrl *ctrl)
1165 {
1166 struct s5k3l6xx *s5k3l6xx = container_of(ctrl->handler,
1167 struct s5k3l6xx, ctrl_handler);
1168 struct i2c_client *client = s5k3l6xx->client;
1169 s64 max;
1170 int ret = 0;
1171
1172 /* Propagate change of current control to all related controls */
1173 switch (ctrl->id) {
1174 case V4L2_CID_VBLANK:
1175 /* Update max exposure while meeting expected vblanking */
1176 max = s5k3l6xx->cur_mode->height + ctrl->val - 4;
1177 __v4l2_ctrl_modify_range(s5k3l6xx->exposure,
1178 s5k3l6xx->exposure->minimum, max,
1179 s5k3l6xx->exposure->step,
1180 s5k3l6xx->exposure->default_value);
1181 break;
1182 }
1183
1184 if (!pm_runtime_get_if_in_use(&client->dev))
1185 return 0;
1186
1187 switch (ctrl->id) {
1188 case V4L2_CID_EXPOSURE:
1189 /* 4 least significant bits of expsoure are fractional part */
1190 ret = s5k3l6xx_write_reg(s5k3l6xx->client,
1191 S5K3L6XX_REG_EXPOSURE,
1192 S5K3L6XX_REG_VALUE_16BIT,
1193 ctrl->val);
1194 break;
1195 case V4L2_CID_ANALOGUE_GAIN:
1196 ret = s5k3l6xx_write_reg(s5k3l6xx->client,
1197 S5K3L6XX_REG_ANALOG_GAIN,
1198 S5K3L6XX_REG_VALUE_16BIT,
1199 ctrl->val);
1200 break;
1201 case V4L2_CID_VBLANK:
1202 ret = s5k3l6xx_write_reg(s5k3l6xx->client,
1203 S5K3L6XX_REG_VTS,
1204 S5K3L6XX_REG_VALUE_16BIT,
1205 ctrl->val + s5k3l6xx->cur_mode->height);
1206 break;
1207 case V4L2_CID_TEST_PATTERN:
1208 ret = s5k3l6xx_enable_test_pattern(s5k3l6xx, ctrl->val);
1209 break;
1210 default:
1211 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1212 __func__, ctrl->id, ctrl->val);
1213 break;
1214 }
1215
1216 pm_runtime_put(&client->dev);
1217
1218 return ret;
1219 }
1220
1221 static const struct v4l2_ctrl_ops s5k3l6xx_ctrl_ops = {
1222 .s_ctrl = s5k3l6xx_set_ctrl,
1223 };
1224
s5k3l6xx_initialize_controls(struct s5k3l6xx * s5k3l6xx)1225 static int s5k3l6xx_initialize_controls(struct s5k3l6xx *s5k3l6xx)
1226 {
1227 const struct s5k3l6xx_mode *mode;
1228 struct v4l2_ctrl_handler *handler;
1229 s64 exposure_max, vblank_def;
1230 u32 h_blank;
1231 int ret;
1232 u64 dst_pixel_rate = 0;
1233 u32 lane_num = S5K3L6XX_LANES;
1234
1235 handler = &s5k3l6xx->ctrl_handler;
1236 mode = s5k3l6xx->cur_mode;
1237 ret = v4l2_ctrl_handler_init(handler, 8);
1238 if (ret)
1239 return ret;
1240 handler->lock = &s5k3l6xx->mutex;
1241
1242 s5k3l6xx->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1243 V4L2_CID_LINK_FREQ,
1244 1, 0, link_freq_items);
1245
1246 dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
1247
1248 s5k3l6xx->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1249 V4L2_CID_PIXEL_RATE,
1250 0, S5K3L6XX_PIXEL_RATE,
1251 1, dst_pixel_rate);
1252
1253 __v4l2_ctrl_s_ctrl(s5k3l6xx->link_freq,
1254 mode->link_freq_idx);
1255
1256 h_blank = mode->hts_def - mode->width;
1257 s5k3l6xx->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1258 h_blank, h_blank, 1, h_blank);
1259 if (s5k3l6xx->hblank)
1260 s5k3l6xx->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1261
1262 vblank_def = mode->vts_def - mode->height;
1263 s5k3l6xx->vblank = v4l2_ctrl_new_std(handler, &s5k3l6xx_ctrl_ops,
1264 V4L2_CID_VBLANK, vblank_def,
1265 S5K3L6XX_VTS_MAX - mode->height,
1266 1, vblank_def);
1267
1268 exposure_max = mode->vts_def - 4;
1269 s5k3l6xx->exposure = v4l2_ctrl_new_std(handler, &s5k3l6xx_ctrl_ops,
1270 V4L2_CID_EXPOSURE, S5K3L6XX_EXPOSURE_MIN,
1271 exposure_max, S5K3L6XX_EXPOSURE_STEP,
1272 mode->exp_def);
1273
1274 s5k3l6xx->anal_gain = v4l2_ctrl_new_std(handler, &s5k3l6xx_ctrl_ops,
1275 V4L2_CID_ANALOGUE_GAIN, S5K3L6XX_GAIN_MIN,
1276 S5K3L6XX_GAIN_MAX, S5K3L6XX_GAIN_STEP,
1277 S5K3L6XX_GAIN_DEFAULT);
1278
1279 s5k3l6xx->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1280 &s5k3l6xx_ctrl_ops, V4L2_CID_TEST_PATTERN,
1281 ARRAY_SIZE(s5k3l6xx_test_pattern_menu) - 1,
1282 0, 0, s5k3l6xx_test_pattern_menu);
1283
1284 if (handler->error) {
1285 ret = handler->error;
1286 dev_err(&s5k3l6xx->client->dev,
1287 "Failed to init controls(%d)\n", ret);
1288 goto err_free_handler;
1289 }
1290
1291 s5k3l6xx->subdev.ctrl_handler = handler;
1292
1293 return 0;
1294
1295 err_free_handler:
1296 v4l2_ctrl_handler_free(handler);
1297
1298 return ret;
1299 }
1300
s5k3l6xx_check_sensor_id(struct s5k3l6xx * s5k3l6xx,struct i2c_client * client)1301 static int s5k3l6xx_check_sensor_id(struct s5k3l6xx *s5k3l6xx,
1302 struct i2c_client *client)
1303 {
1304 struct device *dev = &s5k3l6xx->client->dev;
1305 u32 id = 0;
1306 int ret;
1307
1308 ret = s5k3l6xx_read_reg(client, S5K3L6XX_REG_CHIP_ID,
1309 S5K3L6XX_REG_VALUE_16BIT, &id);
1310 if (id != CHIP_ID) {
1311 dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
1312 return -ENODEV;
1313 }
1314
1315 ret = s5k3l6xx_read_reg(client, S5K3L6XX_CHIP_REVISION_REG,
1316 S5K3L6XX_REG_VALUE_08BIT, &id);
1317 if (ret) {
1318 dev_err(dev, "Read chip revision register error\n");
1319 return ret;
1320 }
1321
1322 dev_info(dev, "Detected Samsung %04x sensor, REVISION 0x%x\n", CHIP_ID, id);
1323
1324 return 0;
1325 }
1326
s5k3l6xx_configure_regulators(struct s5k3l6xx * s5k3l6xx)1327 static int s5k3l6xx_configure_regulators(struct s5k3l6xx *s5k3l6xx)
1328 {
1329 unsigned int i;
1330
1331 for (i = 0; i < S5K3L6XX_NUM_SUPPLIES; i++)
1332 s5k3l6xx->supplies[i].supply = s5k3l6xx_supply_names[i];
1333
1334 return devm_regulator_bulk_get(&s5k3l6xx->client->dev,
1335 S5K3L6XX_NUM_SUPPLIES,
1336 s5k3l6xx->supplies);
1337 }
1338
s5k3l6xx_probe(struct i2c_client * client,const struct i2c_device_id * id)1339 static int s5k3l6xx_probe(struct i2c_client *client,
1340 const struct i2c_device_id *id)
1341 {
1342 struct device *dev = &client->dev;
1343 struct device_node *node = dev->of_node;
1344 struct s5k3l6xx *s5k3l6xx;
1345 struct v4l2_subdev *sd;
1346 char facing[2];
1347 int ret;
1348
1349 dev_info(dev, "driver version: %02x.%02x.%02x",
1350 DRIVER_VERSION >> 16,
1351 (DRIVER_VERSION & 0xff00) >> 8,
1352 DRIVER_VERSION & 0x00ff);
1353
1354 s5k3l6xx = devm_kzalloc(dev, sizeof(*s5k3l6xx), GFP_KERNEL);
1355 if (!s5k3l6xx)
1356 return -ENOMEM;
1357
1358 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1359 &s5k3l6xx->module_index);
1360 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1361 &s5k3l6xx->module_facing);
1362 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1363 &s5k3l6xx->module_name);
1364 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1365 &s5k3l6xx->len_name);
1366 if (ret) {
1367 dev_err(dev, "could not get module information!\n");
1368 return -EINVAL;
1369 }
1370
1371 s5k3l6xx->client = client;
1372 s5k3l6xx->cur_mode = &supported_modes[0];
1373
1374 s5k3l6xx->xvclk = devm_clk_get(dev, "xvclk");
1375 if (IS_ERR(s5k3l6xx->xvclk)) {
1376 dev_err(dev, "Failed to get xvclk\n");
1377 return -EINVAL;
1378 }
1379
1380 s5k3l6xx->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
1381 if (IS_ERR(s5k3l6xx->power_gpio))
1382 dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
1383
1384 s5k3l6xx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1385 if (IS_ERR(s5k3l6xx->reset_gpio))
1386 dev_warn(dev, "Failed to get reset-gpios\n");
1387
1388 s5k3l6xx->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1389 if (IS_ERR(s5k3l6xx->pwdn_gpio))
1390 dev_warn(dev, "Failed to get pwdn-gpios\n");
1391
1392 ret = s5k3l6xx_configure_regulators(s5k3l6xx);
1393 if (ret) {
1394 dev_err(dev, "Failed to get power regulators\n");
1395 return ret;
1396 }
1397
1398 s5k3l6xx->pinctrl = devm_pinctrl_get(dev);
1399 if (!IS_ERR(s5k3l6xx->pinctrl)) {
1400 s5k3l6xx->pins_default =
1401 pinctrl_lookup_state(s5k3l6xx->pinctrl,
1402 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1403 if (IS_ERR(s5k3l6xx->pins_default))
1404 dev_err(dev, "could not get default pinstate\n");
1405
1406 s5k3l6xx->pins_sleep =
1407 pinctrl_lookup_state(s5k3l6xx->pinctrl,
1408 OF_CAMERA_PINCTRL_STATE_SLEEP);
1409 if (IS_ERR(s5k3l6xx->pins_sleep))
1410 dev_err(dev, "could not get sleep pinstate\n");
1411 }
1412
1413 mutex_init(&s5k3l6xx->mutex);
1414
1415 sd = &s5k3l6xx->subdev;
1416 v4l2_i2c_subdev_init(sd, client, &s5k3l6xx_subdev_ops);
1417 ret = s5k3l6xx_initialize_controls(s5k3l6xx);
1418 if (ret)
1419 goto err_destroy_mutex;
1420
1421 ret = __s5k3l6xx_power_on(s5k3l6xx);
1422 if (ret)
1423 goto err_free_handler;
1424
1425 ret = s5k3l6xx_check_sensor_id(s5k3l6xx, client);
1426 if (ret)
1427 goto err_power_off;
1428
1429 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1430 sd->internal_ops = &s5k3l6xx_internal_ops;
1431 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1432 #endif
1433 #if defined(CONFIG_MEDIA_CONTROLLER)
1434 s5k3l6xx->pad.flags = MEDIA_PAD_FL_SOURCE;
1435 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1436 ret = media_entity_pads_init(&sd->entity, 1, &s5k3l6xx->pad);
1437 if (ret < 0)
1438 goto err_power_off;
1439 #endif
1440
1441 memset(facing, 0, sizeof(facing));
1442 if (strcmp(s5k3l6xx->module_facing, "back") == 0)
1443 facing[0] = 'b';
1444 else
1445 facing[0] = 'f';
1446
1447 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1448 s5k3l6xx->module_index, facing,
1449 S5K3L6XX_NAME, dev_name(sd->dev));
1450 ret = v4l2_async_register_subdev_sensor_common(sd);
1451 if (ret) {
1452 dev_err(dev, "v4l2 async register subdev failed\n");
1453 goto err_clean_entity;
1454 }
1455
1456 pm_runtime_set_active(dev);
1457 pm_runtime_enable(dev);
1458 pm_runtime_idle(dev);
1459
1460 return 0;
1461
1462 err_clean_entity:
1463 #if defined(CONFIG_MEDIA_CONTROLLER)
1464 media_entity_cleanup(&sd->entity);
1465 #endif
1466 err_power_off:
1467 __s5k3l6xx_power_off(s5k3l6xx);
1468 err_free_handler:
1469 v4l2_ctrl_handler_free(&s5k3l6xx->ctrl_handler);
1470 err_destroy_mutex:
1471 mutex_destroy(&s5k3l6xx->mutex);
1472
1473 return ret;
1474 }
1475
s5k3l6xx_remove(struct i2c_client * client)1476 static int s5k3l6xx_remove(struct i2c_client *client)
1477 {
1478 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1479 struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
1480
1481 v4l2_async_unregister_subdev(sd);
1482 #if defined(CONFIG_MEDIA_CONTROLLER)
1483 media_entity_cleanup(&sd->entity);
1484 #endif
1485 v4l2_ctrl_handler_free(&s5k3l6xx->ctrl_handler);
1486 mutex_destroy(&s5k3l6xx->mutex);
1487
1488 pm_runtime_disable(&client->dev);
1489 if (!pm_runtime_status_suspended(&client->dev))
1490 __s5k3l6xx_power_off(s5k3l6xx);
1491 pm_runtime_set_suspended(&client->dev);
1492
1493 return 0;
1494 }
1495
1496 #if IS_ENABLED(CONFIG_OF)
1497 static const struct of_device_id s5k3l6xx_of_match[] = {
1498 { .compatible = "samsung,s5k3l6xx" },
1499 {},
1500 };
1501 MODULE_DEVICE_TABLE(of, s5k3l6xx_of_match);
1502 #endif
1503
1504 static const struct i2c_device_id s5k3l6xx_match_id[] = {
1505 { "samsung,s5k3l6xx", 0 },
1506 {},
1507 };
1508
1509 static struct i2c_driver s5k3l6xx_i2c_driver = {
1510 .driver = {
1511 .name = S5K3L6XX_NAME,
1512 .pm = &s5k3l6xx_pm_ops,
1513 .of_match_table = of_match_ptr(s5k3l6xx_of_match),
1514 },
1515 .probe = &s5k3l6xx_probe,
1516 .remove = &s5k3l6xx_remove,
1517 .id_table = s5k3l6xx_match_id,
1518 };
1519
sensor_mod_init(void)1520 static int __init sensor_mod_init(void)
1521 {
1522 return i2c_add_driver(&s5k3l6xx_i2c_driver);
1523 }
1524
sensor_mod_exit(void)1525 static void __exit sensor_mod_exit(void)
1526 {
1527 i2c_del_driver(&s5k3l6xx_i2c_driver);
1528 }
1529
1530 device_initcall_sync(sensor_mod_init);
1531 module_exit(sensor_mod_exit);
1532
1533 MODULE_DESCRIPTION("Samsung s5k3l6xx sensor driver");
1534 MODULE_LICENSE("GPL v2");
1535