1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Samsung LSI S5C73M3 8M pixel camera driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
6*4882a593Smuzhiyun * Sylwester Nawrocki <s.nawrocki@samsung.com>
7*4882a593Smuzhiyun * Andrzej Hajda <a.hajda@samsung.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun #ifndef S5C73M3_H_
10*4882a593Smuzhiyun #define S5C73M3_H_
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/clk.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
15*4882a593Smuzhiyun #include <media/v4l2-common.h>
16*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
17*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
18*4882a593Smuzhiyun #include <media/i2c/s5c73m3.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define DRIVER_NAME "S5C73M3"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define S5C73M3_ISP_FMT MEDIA_BUS_FMT_VYUY8_2X8
23*4882a593Smuzhiyun #define S5C73M3_JPEG_FMT MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Subdevs pad index definitions */
26*4882a593Smuzhiyun enum s5c73m3_pads {
27*4882a593Smuzhiyun S5C73M3_ISP_PAD,
28*4882a593Smuzhiyun S5C73M3_JPEG_PAD,
29*4882a593Smuzhiyun S5C73M3_NUM_PADS
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun enum s5c73m3_oif_pads {
33*4882a593Smuzhiyun OIF_ISP_PAD,
34*4882a593Smuzhiyun OIF_JPEG_PAD,
35*4882a593Smuzhiyun OIF_SOURCE_PAD,
36*4882a593Smuzhiyun OIF_NUM_PADS
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define S5C73M3_SENSOR_FW_LEN 6
40*4882a593Smuzhiyun #define S5C73M3_SENSOR_TYPE_LEN 12
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define S5C73M3_REG(_addrh, _addrl) (((_addrh) << 16) | _addrl)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define AHB_MSB_ADDR_PTR 0xfcfc
45*4882a593Smuzhiyun #define REG_CMDWR_ADDRH 0x0050
46*4882a593Smuzhiyun #define REG_CMDWR_ADDRL 0x0054
47*4882a593Smuzhiyun #define REG_CMDRD_ADDRH 0x0058
48*4882a593Smuzhiyun #define REG_CMDRD_ADDRL 0x005c
49*4882a593Smuzhiyun #define REG_CMDBUF_ADDR 0x0f14
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
52*4882a593Smuzhiyun #define SEQ_END_PLL (1<<0x0)
53*4882a593Smuzhiyun #define SEQ_END_SENSOR (1<<0x1)
54*4882a593Smuzhiyun #define SEQ_END_GPIO (1<<0x2)
55*4882a593Smuzhiyun #define SEQ_END_FROM (1<<0x3)
56*4882a593Smuzhiyun #define SEQ_END_STABLE_AE_AWB (1<<0x4)
57*4882a593Smuzhiyun #define SEQ_END_READY_I2C_CMD (1<<0x5)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define REG_I2C_STATUS S5C73M3_REG(0x0009, 0x599E)
60*4882a593Smuzhiyun #define I2C_STATUS_CIS_I2C (1<<0x0)
61*4882a593Smuzhiyun #define I2C_STATUS_AF_INIT (1<<0x1)
62*4882a593Smuzhiyun #define I2C_STATUS_CAL_DATA (1<<0x2)
63*4882a593Smuzhiyun #define I2C_STATUS_FRAME_COUNT (1<<0x3)
64*4882a593Smuzhiyun #define I2C_STATUS_FROM_INIT (1<<0x4)
65*4882a593Smuzhiyun #define I2C_STATUS_I2C_CIS_STREAM_OFF (1<<0x5)
66*4882a593Smuzhiyun #define I2C_STATUS_I2C_N_CMD_OVER (1<<0x6)
67*4882a593Smuzhiyun #define I2C_STATUS_I2C_N_CMD_MISMATCH (1<<0x7)
68*4882a593Smuzhiyun #define I2C_STATUS_CHECK_BIN_CRC (1<<0x8)
69*4882a593Smuzhiyun #define I2C_STATUS_EXCEPTION (1<<0x9)
70*4882a593Smuzhiyun #define I2C_STATUS_INIF_INIT_STATE (0x8)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define REG_STATUS S5C73M3_REG(0x0009, 0x5080)
73*4882a593Smuzhiyun #define REG_STATUS_BOOT_SUB_MAIN_ENTER 0xff01
74*4882a593Smuzhiyun #define REG_STATUS_BOOT_SRAM_TIMING_OK 0xff02
75*4882a593Smuzhiyun #define REG_STATUS_BOOT_INTERRUPTS_EN 0xff03
76*4882a593Smuzhiyun #define REG_STATUS_BOOT_R_PLL_DONE 0xff04
77*4882a593Smuzhiyun #define REG_STATUS_BOOT_R_PLL_LOCKTIME_DONE 0xff05
78*4882a593Smuzhiyun #define REG_STATUS_BOOT_DELAY_COUNT_DONE 0xff06
79*4882a593Smuzhiyun #define REG_STATUS_BOOT_I_PLL_DONE 0xff07
80*4882a593Smuzhiyun #define REG_STATUS_BOOT_I_PLL_LOCKTIME_DONE 0xff08
81*4882a593Smuzhiyun #define REG_STATUS_BOOT_PLL_INIT_OK 0xff09
82*4882a593Smuzhiyun #define REG_STATUS_BOOT_SENSOR_INIT_OK 0xff0a
83*4882a593Smuzhiyun #define REG_STATUS_BOOT_GPIO_SETTING_OK 0xff0b
84*4882a593Smuzhiyun #define REG_STATUS_BOOT_READ_CAL_DATA_OK 0xff0c
85*4882a593Smuzhiyun #define REG_STATUS_BOOT_STABLE_AE_AWB_OK 0xff0d
86*4882a593Smuzhiyun #define REG_STATUS_ISP_COMMAND_COMPLETED 0xffff
87*4882a593Smuzhiyun #define REG_STATUS_EXCEPTION_OCCURED 0xdead
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define COMM_RESULT_OFFSET S5C73M3_REG(0x0009, 0x5000)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define COMM_IMG_OUTPUT 0x0902
92*4882a593Smuzhiyun #define COMM_IMG_OUTPUT_HDR 0x0008
93*4882a593Smuzhiyun #define COMM_IMG_OUTPUT_YUV 0x0009
94*4882a593Smuzhiyun #define COMM_IMG_OUTPUT_INTERLEAVED 0x000d
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define COMM_STILL_PRE_FLASH 0x0a00
97*4882a593Smuzhiyun #define COMM_STILL_PRE_FLASH_FIRE 0x0000
98*4882a593Smuzhiyun #define COMM_STILL_PRE_FLASH_NON_FIRED 0x0000
99*4882a593Smuzhiyun #define COMM_STILL_PRE_FLASH_FIRED 0x0001
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define COMM_STILL_MAIN_FLASH 0x0a02
102*4882a593Smuzhiyun #define COMM_STILL_MAIN_FLASH_CANCEL 0x0001
103*4882a593Smuzhiyun #define COMM_STILL_MAIN_FLASH_FIRE 0x0002
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun #define COMM_ZOOM_STEP 0x0b00
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun #define COMM_IMAGE_EFFECT 0x0b0a
108*4882a593Smuzhiyun #define COMM_IMAGE_EFFECT_NONE 0x0001
109*4882a593Smuzhiyun #define COMM_IMAGE_EFFECT_NEGATIVE 0x0002
110*4882a593Smuzhiyun #define COMM_IMAGE_EFFECT_AQUA 0x0003
111*4882a593Smuzhiyun #define COMM_IMAGE_EFFECT_SEPIA 0x0004
112*4882a593Smuzhiyun #define COMM_IMAGE_EFFECT_MONO 0x0005
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #define COMM_IMAGE_QUALITY 0x0b0c
115*4882a593Smuzhiyun #define COMM_IMAGE_QUALITY_SUPERFINE 0x0000
116*4882a593Smuzhiyun #define COMM_IMAGE_QUALITY_FINE 0x0001
117*4882a593Smuzhiyun #define COMM_IMAGE_QUALITY_NORMAL 0x0002
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define COMM_FLASH_MODE 0x0b0e
120*4882a593Smuzhiyun #define COMM_FLASH_MODE_OFF 0x0000
121*4882a593Smuzhiyun #define COMM_FLASH_MODE_ON 0x0001
122*4882a593Smuzhiyun #define COMM_FLASH_MODE_AUTO 0x0002
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #define COMM_FLASH_STATUS 0x0b80
125*4882a593Smuzhiyun #define COMM_FLASH_STATUS_OFF 0x0001
126*4882a593Smuzhiyun #define COMM_FLASH_STATUS_ON 0x0002
127*4882a593Smuzhiyun #define COMM_FLASH_STATUS_AUTO 0x0003
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun #define COMM_FLASH_TORCH 0x0b12
130*4882a593Smuzhiyun #define COMM_FLASH_TORCH_OFF 0x0000
131*4882a593Smuzhiyun #define COMM_FLASH_TORCH_ON 0x0001
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun #define COMM_AE_NEEDS_FLASH 0x0cba
134*4882a593Smuzhiyun #define COMM_AE_NEEDS_FLASH_OFF 0x0000
135*4882a593Smuzhiyun #define COMM_AE_NEEDS_FLASH_ON 0x0001
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun #define COMM_CHG_MODE 0x0b10
138*4882a593Smuzhiyun #define COMM_CHG_MODE_NEW 0x8000
139*4882a593Smuzhiyun #define COMM_CHG_MODE_SUBSAMPLING_HALF 0x2000
140*4882a593Smuzhiyun #define COMM_CHG_MODE_SUBSAMPLING_QUARTER 0x4000
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_320_240 0x0001
143*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_640_480 0x0002
144*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_880_720 0x0003
145*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_960_720 0x0004
146*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1184_666 0x0005
147*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1280_720 0x0006
148*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1536_864 0x0007
149*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1600_1200 0x0008
150*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1632_1224 0x0009
151*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1920_1080 0x000a
152*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1920_1440 0x000b
153*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_2304_1296 0x000c
154*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_3264_2448 0x000d
155*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_352_288 0x000e
156*4882a593Smuzhiyun #define COMM_CHG_MODE_YUV_1008_672 0x000f
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_640_480 0x0010
159*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_800_450 0x0020
160*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_800_600 0x0030
161*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_1280_720 0x0040
162*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_1280_960 0x0050
163*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_1600_900 0x0060
164*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_1600_1200 0x0070
165*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_2048_1152 0x0080
166*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_2048_1536 0x0090
167*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_2560_1440 0x00a0
168*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_2560_1920 0x00b0
169*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_3264_2176 0x00c0
170*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_1024_768 0x00d0
171*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_3264_1836 0x00e0
172*4882a593Smuzhiyun #define COMM_CHG_MODE_JPEG_3264_2448 0x00f0
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun #define COMM_AF_CON 0x0e00
175*4882a593Smuzhiyun #define COMM_AF_CON_STOP 0x0000
176*4882a593Smuzhiyun #define COMM_AF_CON_SCAN 0x0001 /* Full Search */
177*4882a593Smuzhiyun #define COMM_AF_CON_START 0x0002 /* Fast Search */
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun #define COMM_AF_CAL 0x0e06
180*4882a593Smuzhiyun #define COMM_AF_TOUCH_AF 0x0e0a
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun #define REG_AF_STATUS S5C73M3_REG(0x0009, 0x5e80)
183*4882a593Smuzhiyun #define REG_CAF_STATUS_FIND_SEARCH_DIR 0x0001
184*4882a593Smuzhiyun #define REG_CAF_STATUS_FOCUSING 0x0002
185*4882a593Smuzhiyun #define REG_CAF_STATUS_FOCUSED 0x0003
186*4882a593Smuzhiyun #define REG_CAF_STATUS_UNFOCUSED 0x0004
187*4882a593Smuzhiyun #define REG_AF_STATUS_INVALID 0x0010
188*4882a593Smuzhiyun #define REG_AF_STATUS_FOCUSING 0x0020
189*4882a593Smuzhiyun #define REG_AF_STATUS_FOCUSED 0x0030
190*4882a593Smuzhiyun #define REG_AF_STATUS_UNFOCUSED 0x0040
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun #define REG_AF_TOUCH_POSITION S5C73M3_REG(0x0009, 0x5e8e)
193*4882a593Smuzhiyun #define COMM_AF_FACE_ZOOM 0x0e10
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun #define COMM_AF_MODE 0x0e02
196*4882a593Smuzhiyun #define COMM_AF_MODE_NORMAL 0x0000
197*4882a593Smuzhiyun #define COMM_AF_MODE_MACRO 0x0001
198*4882a593Smuzhiyun #define COMM_AF_MODE_MOVIE_CAF_START 0x0002
199*4882a593Smuzhiyun #define COMM_AF_MODE_MOVIE_CAF_STOP 0x0003
200*4882a593Smuzhiyun #define COMM_AF_MODE_PREVIEW_CAF_START 0x0004
201*4882a593Smuzhiyun #define COMM_AF_MODE_PREVIEW_CAF_STOP 0x0005
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun #define COMM_AF_SOFTLANDING 0x0e16
204*4882a593Smuzhiyun #define COMM_AF_SOFTLANDING_ON 0x0000
205*4882a593Smuzhiyun #define COMM_AF_SOFTLANDING_RES_COMPLETE 0x0001
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun #define COMM_FACE_DET 0x0e0c
208*4882a593Smuzhiyun #define COMM_FACE_DET_OFF 0x0000
209*4882a593Smuzhiyun #define COMM_FACE_DET_ON 0x0001
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun #define COMM_FACE_DET_OSD 0x0e0e
212*4882a593Smuzhiyun #define COMM_FACE_DET_OSD_OFF 0x0000
213*4882a593Smuzhiyun #define COMM_FACE_DET_OSD_ON 0x0001
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun #define COMM_AE_CON 0x0c00
216*4882a593Smuzhiyun #define COMM_AE_STOP 0x0000 /* lock */
217*4882a593Smuzhiyun #define COMM_AE_START 0x0001 /* unlock */
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun #define COMM_ISO 0x0c02
220*4882a593Smuzhiyun #define COMM_ISO_AUTO 0x0000
221*4882a593Smuzhiyun #define COMM_ISO_100 0x0001
222*4882a593Smuzhiyun #define COMM_ISO_200 0x0002
223*4882a593Smuzhiyun #define COMM_ISO_400 0x0003
224*4882a593Smuzhiyun #define COMM_ISO_800 0x0004
225*4882a593Smuzhiyun #define COMM_ISO_SPORTS 0x0005
226*4882a593Smuzhiyun #define COMM_ISO_NIGHT 0x0006
227*4882a593Smuzhiyun #define COMM_ISO_INDOOR 0x0007
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun /* 0x00000 (-2.0 EV)...0x0008 (2.0 EV), 0.5EV step */
230*4882a593Smuzhiyun #define COMM_EV 0x0c04
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun #define COMM_METERING 0x0c06
233*4882a593Smuzhiyun #define COMM_METERING_CENTER 0x0000
234*4882a593Smuzhiyun #define COMM_METERING_SPOT 0x0001
235*4882a593Smuzhiyun #define COMM_METERING_AVERAGE 0x0002
236*4882a593Smuzhiyun #define COMM_METERING_SMART 0x0003
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun #define COMM_WDR 0x0c08
239*4882a593Smuzhiyun #define COMM_WDR_OFF 0x0000
240*4882a593Smuzhiyun #define COMM_WDR_ON 0x0001
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun #define COMM_FLICKER_MODE 0x0c12
243*4882a593Smuzhiyun #define COMM_FLICKER_NONE 0x0000
244*4882a593Smuzhiyun #define COMM_FLICKER_MANUAL_50HZ 0x0001
245*4882a593Smuzhiyun #define COMM_FLICKER_MANUAL_60HZ 0x0002
246*4882a593Smuzhiyun #define COMM_FLICKER_AUTO 0x0003
247*4882a593Smuzhiyun #define COMM_FLICKER_AUTO_50HZ 0x0004
248*4882a593Smuzhiyun #define COMM_FLICKER_AUTO_60HZ 0x0005
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun #define COMM_FRAME_RATE 0x0c1e
251*4882a593Smuzhiyun #define COMM_FRAME_RATE_AUTO_SET 0x0000
252*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_30FPS 0x0002
253*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_20FPS 0x0003
254*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_15FPS 0x0004
255*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_60FPS 0x0007
256*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_120FPS 0x0008
257*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_7FPS 0x0009
258*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_10FPS 0x000a
259*4882a593Smuzhiyun #define COMM_FRAME_RATE_FIXED_90FPS 0x000b
260*4882a593Smuzhiyun #define COMM_FRAME_RATE_ANTI_SHAKE 0x0013
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun /* 0x0000...0x0004 -> sharpness: 0, 1, 2, -1, -2 */
263*4882a593Smuzhiyun #define COMM_SHARPNESS 0x0c14
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun /* 0x0000...0x0004 -> saturation: 0, 1, 2, -1, -2 */
266*4882a593Smuzhiyun #define COMM_SATURATION 0x0c16
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun /* 0x0000...0x0004 -> contrast: 0, 1, 2, -1, -2 */
269*4882a593Smuzhiyun #define COMM_CONTRAST 0x0c18
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun #define COMM_SCENE_MODE 0x0c1a
272*4882a593Smuzhiyun #define COMM_SCENE_MODE_NONE 0x0000
273*4882a593Smuzhiyun #define COMM_SCENE_MODE_PORTRAIT 0x0001
274*4882a593Smuzhiyun #define COMM_SCENE_MODE_LANDSCAPE 0x0002
275*4882a593Smuzhiyun #define COMM_SCENE_MODE_SPORTS 0x0003
276*4882a593Smuzhiyun #define COMM_SCENE_MODE_INDOOR 0x0004
277*4882a593Smuzhiyun #define COMM_SCENE_MODE_BEACH 0x0005
278*4882a593Smuzhiyun #define COMM_SCENE_MODE_SUNSET 0x0006
279*4882a593Smuzhiyun #define COMM_SCENE_MODE_DAWN 0x0007
280*4882a593Smuzhiyun #define COMM_SCENE_MODE_FALL 0x0008
281*4882a593Smuzhiyun #define COMM_SCENE_MODE_NIGHT 0x0009
282*4882a593Smuzhiyun #define COMM_SCENE_MODE_AGAINST_LIGHT 0x000a
283*4882a593Smuzhiyun #define COMM_SCENE_MODE_FIRE 0x000b
284*4882a593Smuzhiyun #define COMM_SCENE_MODE_TEXT 0x000c
285*4882a593Smuzhiyun #define COMM_SCENE_MODE_CANDLE 0x000d
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun #define COMM_AE_AUTO_BRACKET 0x0b14
288*4882a593Smuzhiyun #define COMM_AE_AUTO_BRAKET_EV05 0x0080
289*4882a593Smuzhiyun #define COMM_AE_AUTO_BRAKET_EV10 0x0100
290*4882a593Smuzhiyun #define COMM_AE_AUTO_BRAKET_EV15 0x0180
291*4882a593Smuzhiyun #define COMM_AE_AUTO_BRAKET_EV20 0x0200
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun #define COMM_SENSOR_STREAMING 0x090a
294*4882a593Smuzhiyun #define COMM_SENSOR_STREAMING_OFF 0x0000
295*4882a593Smuzhiyun #define COMM_SENSOR_STREAMING_ON 0x0001
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun #define COMM_AWB_MODE 0x0d02
298*4882a593Smuzhiyun #define COMM_AWB_MODE_INCANDESCENT 0x0000
299*4882a593Smuzhiyun #define COMM_AWB_MODE_FLUORESCENT1 0x0001
300*4882a593Smuzhiyun #define COMM_AWB_MODE_FLUORESCENT2 0x0002
301*4882a593Smuzhiyun #define COMM_AWB_MODE_DAYLIGHT 0x0003
302*4882a593Smuzhiyun #define COMM_AWB_MODE_CLOUDY 0x0004
303*4882a593Smuzhiyun #define COMM_AWB_MODE_AUTO 0x0005
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun #define COMM_AWB_CON 0x0d00
306*4882a593Smuzhiyun #define COMM_AWB_STOP 0x0000 /* lock */
307*4882a593Smuzhiyun #define COMM_AWB_START 0x0001 /* unlock */
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun #define COMM_FW_UPDATE 0x0906
310*4882a593Smuzhiyun #define COMM_FW_UPDATE_NOT_READY 0x0000
311*4882a593Smuzhiyun #define COMM_FW_UPDATE_SUCCESS 0x0005
312*4882a593Smuzhiyun #define COMM_FW_UPDATE_FAIL 0x0007
313*4882a593Smuzhiyun #define COMM_FW_UPDATE_BUSY 0xffff
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun #define S5C73M3_MAX_SUPPLIES 6
317*4882a593Smuzhiyun #define S5C73M3_DEFAULT_MCLK_FREQ 24000000U
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun struct s5c73m3_ctrls {
320*4882a593Smuzhiyun struct v4l2_ctrl_handler handler;
321*4882a593Smuzhiyun struct {
322*4882a593Smuzhiyun /* exposure/exposure bias cluster */
323*4882a593Smuzhiyun struct v4l2_ctrl *auto_exposure;
324*4882a593Smuzhiyun struct v4l2_ctrl *exposure_bias;
325*4882a593Smuzhiyun struct v4l2_ctrl *exposure_metering;
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun struct {
328*4882a593Smuzhiyun /* iso/auto iso cluster */
329*4882a593Smuzhiyun struct v4l2_ctrl *auto_iso;
330*4882a593Smuzhiyun struct v4l2_ctrl *iso;
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun struct v4l2_ctrl *auto_wb;
333*4882a593Smuzhiyun struct {
334*4882a593Smuzhiyun /* continuous auto focus/auto focus cluster */
335*4882a593Smuzhiyun struct v4l2_ctrl *focus_auto;
336*4882a593Smuzhiyun struct v4l2_ctrl *af_start;
337*4882a593Smuzhiyun struct v4l2_ctrl *af_stop;
338*4882a593Smuzhiyun struct v4l2_ctrl *af_status;
339*4882a593Smuzhiyun struct v4l2_ctrl *af_distance;
340*4882a593Smuzhiyun };
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun struct v4l2_ctrl *aaa_lock;
343*4882a593Smuzhiyun struct v4l2_ctrl *colorfx;
344*4882a593Smuzhiyun struct v4l2_ctrl *contrast;
345*4882a593Smuzhiyun struct v4l2_ctrl *saturation;
346*4882a593Smuzhiyun struct v4l2_ctrl *sharpness;
347*4882a593Smuzhiyun struct v4l2_ctrl *zoom;
348*4882a593Smuzhiyun struct v4l2_ctrl *wdr;
349*4882a593Smuzhiyun struct v4l2_ctrl *stabilization;
350*4882a593Smuzhiyun struct v4l2_ctrl *jpeg_quality;
351*4882a593Smuzhiyun struct v4l2_ctrl *scene_mode;
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun enum s5c73m3_gpio_id {
355*4882a593Smuzhiyun STBY,
356*4882a593Smuzhiyun RSET,
357*4882a593Smuzhiyun GPIO_NUM,
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun enum s5c73m3_resolution_types {
361*4882a593Smuzhiyun RES_ISP,
362*4882a593Smuzhiyun RES_JPEG,
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun struct s5c73m3_interval {
366*4882a593Smuzhiyun u16 fps_reg;
367*4882a593Smuzhiyun struct v4l2_fract interval;
368*4882a593Smuzhiyun /* Maximum rectangle for the interval */
369*4882a593Smuzhiyun struct v4l2_frmsize_discrete size;
370*4882a593Smuzhiyun };
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun struct s5c73m3 {
373*4882a593Smuzhiyun struct v4l2_subdev sensor_sd;
374*4882a593Smuzhiyun struct media_pad sensor_pads[S5C73M3_NUM_PADS];
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun struct v4l2_subdev oif_sd;
377*4882a593Smuzhiyun struct media_pad oif_pads[OIF_NUM_PADS];
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun struct spi_driver spidrv;
380*4882a593Smuzhiyun struct spi_device *spi_dev;
381*4882a593Smuzhiyun struct i2c_client *i2c_client;
382*4882a593Smuzhiyun u32 i2c_write_address;
383*4882a593Smuzhiyun u32 i2c_read_address;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun struct regulator_bulk_data supplies[S5C73M3_MAX_SUPPLIES];
386*4882a593Smuzhiyun struct s5c73m3_gpio gpio[GPIO_NUM];
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun struct clk *clock;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun /* External master clock frequency */
391*4882a593Smuzhiyun u32 mclk_frequency;
392*4882a593Smuzhiyun /* Video bus type - MIPI-CSI2/parallel */
393*4882a593Smuzhiyun enum v4l2_mbus_type bus_type;
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun const struct s5c73m3_frame_size *sensor_pix_size[2];
396*4882a593Smuzhiyun const struct s5c73m3_frame_size *oif_pix_size[2];
397*4882a593Smuzhiyun u32 mbus_code;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun const struct s5c73m3_interval *fiv;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun struct v4l2_mbus_frame_desc frame_desc;
402*4882a593Smuzhiyun /* protects the struct members below */
403*4882a593Smuzhiyun struct mutex lock;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun struct s5c73m3_ctrls ctrls;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun u8 streaming:1;
408*4882a593Smuzhiyun u8 apply_fmt:1;
409*4882a593Smuzhiyun u8 apply_fiv:1;
410*4882a593Smuzhiyun u8 isp_ready:1;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun short power;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun char sensor_fw[S5C73M3_SENSOR_FW_LEN + 2];
415*4882a593Smuzhiyun char sensor_type[S5C73M3_SENSOR_TYPE_LEN + 2];
416*4882a593Smuzhiyun char fw_file_version[2];
417*4882a593Smuzhiyun unsigned int fw_size;
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun struct s5c73m3_frame_size {
421*4882a593Smuzhiyun u32 width;
422*4882a593Smuzhiyun u32 height;
423*4882a593Smuzhiyun u8 reg_val;
424*4882a593Smuzhiyun };
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun extern int s5c73m3_dbg;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun int s5c73m3_register_spi_driver(struct s5c73m3 *state);
429*4882a593Smuzhiyun void s5c73m3_unregister_spi_driver(struct s5c73m3 *state);
430*4882a593Smuzhiyun int s5c73m3_spi_write(struct s5c73m3 *state, const void *addr,
431*4882a593Smuzhiyun const unsigned int len, const unsigned int tx_size);
432*4882a593Smuzhiyun int s5c73m3_spi_read(struct s5c73m3 *state, void *addr,
433*4882a593Smuzhiyun const unsigned int len, const unsigned int tx_size);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data);
436*4882a593Smuzhiyun int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data);
437*4882a593Smuzhiyun int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data);
438*4882a593Smuzhiyun int s5c73m3_init_controls(struct s5c73m3 *state);
439*4882a593Smuzhiyun
ctrl_to_sensor_sd(struct v4l2_ctrl * ctrl)440*4882a593Smuzhiyun static inline struct v4l2_subdev *ctrl_to_sensor_sd(struct v4l2_ctrl *ctrl)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun return &container_of(ctrl->handler, struct s5c73m3,
443*4882a593Smuzhiyun ctrls.handler)->sensor_sd;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
sensor_sd_to_s5c73m3(struct v4l2_subdev * sd)446*4882a593Smuzhiyun static inline struct s5c73m3 *sensor_sd_to_s5c73m3(struct v4l2_subdev *sd)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun return container_of(sd, struct s5c73m3, sensor_sd);
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
oif_sd_to_s5c73m3(struct v4l2_subdev * sd)451*4882a593Smuzhiyun static inline struct s5c73m3 *oif_sd_to_s5c73m3(struct v4l2_subdev *sd)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun return container_of(sd, struct s5c73m3, oif_sd);
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun #endif /* S5C73M3_H_ */
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