1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Guochun Huang<hero.huang@rock-chips.com> 6 */ 7 8 #ifndef RK628_DSI_H 9 #define RK628_DSI_H 10 11 #include <linux/delay.h> 12 #include <linux/videodev2.h> 13 14 #include "rk628.h" 15 16 #define DSI0_BASE 0x50000 17 #define DSI1_BASE 0x60000 18 19 #define DSI_VERSION 0x0000 20 #define DSI_PWR_UP 0x0004 21 #define RESET 0 22 #define POWER_UP BIT(0) 23 #define DSI_CLKMGR_CFG 0x0008 24 #define TO_CLK_DIVISION(x) UPDATE(x, 15, 8) 25 #define TX_ESC_CLK_DIVISION(x) UPDATE(x, 7, 0) 26 #define DSI_DPI_VCID 0x000c 27 #define DPI_VID(x) UPDATE(x, 1, 0) 28 #define DSI_DPI_COLOR_CODING 0x0010 29 #define LOOSELY18_EN BIT(8) 30 #define DPI_COLOR_CODING(x) UPDATE(x, 3, 0) 31 #define DSI_DPI_CFG_POL 0x0014 32 #define COLORM_ACTIVE_LOW BIT(4) 33 #define SHUTD_ACTIVE_LOW BIT(3) 34 #define HSYNC_ACTIVE_LOW BIT(2) 35 #define VSYNC_ACTIVE_LOW BIT(1) 36 #define DATAEN_ACTIVE_LOW BIT(0) 37 #define DSI_DPI_LP_CMD_TIM 0x0018 38 #define OUTVACT_LPCMD_TIME(x) UPDATE(x, 23, 16) 39 #define INVACT_LPCMD_TIME(x) UPDATE(x, 7, 0) 40 #define DSI_PCKHDL_CFG 0x002c 41 #define CRC_RX_EN BIT(4) 42 #define ECC_RX_EN BIT(3) 43 #define BTA_EN BIT(2) 44 #define EOTP_RX_EN BIT(1) 45 #define EOTP_TX_EN BIT(0) 46 #define DSI_GEN_VCID 0x0030 47 #define DSI_MODE_CFG 0x0034 48 #define CMD_VIDEO_MODE(x) UPDATE(x, 0, 0) 49 #define DSI_VID_MODE_CFG 0x0038 50 #define VPG_EN BIT(16) 51 #define LP_CMD_EN BIT(15) 52 #define FRAME_BTA_ACK_EN BIT(14) 53 #define LP_HFP_EN BIT(13) 54 #define LP_HBP_EN BIT(12) 55 #define LP_VACT_EN BIT(11) 56 #define LP_VFP_EN BIT(10) 57 #define LP_VBP_EN BIT(9) 58 #define LP_VSA_EN BIT(8) 59 #define VID_MODE_TYPE(x) UPDATE(x, 1, 0) 60 #define DSI_VID_PKT_SIZE 0x003c 61 #define VID_PKT_SIZE(x) UPDATE(x, 13, 0) 62 #define DSI_VID_NUM_CHUNKS 0x0040 63 #define DSI_VID_NULL_SIZE 0x0044 64 #define DSI_VID_HSA_TIME 0x0048 65 #define VID_HSA_TIME(x) UPDATE(x, 11, 0) 66 #define DSI_VID_HBP_TIME 0x004c 67 #define VID_HBP_TIME(x) UPDATE(x, 11, 0) 68 #define DSI_VID_HLINE_TIME 0x0050 69 #define VID_HLINE_TIME(x) UPDATE(x, 14, 0) 70 #define DSI_VID_VSA_LINES 0x0054 71 #define VSA_LINES(x) UPDATE(x, 9, 0) 72 #define DSI_VID_VBP_LINES 0x0058 73 #define VBP_LINES(x) UPDATE(x, 9, 0) 74 #define DSI_VID_VFP_LINES 0x005c 75 #define VFP_LINES(x) UPDATE(x, 9, 0) 76 #define DSI_VID_VACTIVE_LINES 0x0060 77 #define V_ACTIVE_LINES(x) UPDATE(x, 13, 0) 78 #define DSI_EDPI_CMD_SIZE 0x0064 79 #define EDPI_ALLOWED_CMD_SIZE(x) UPDATE(x, 15, 0) 80 #define DSI_CMD_MODE_CFG 0x0068 81 #define MAX_RD_PKT_SIZE BIT(24) 82 #define DCS_LW_TX BIT(19) 83 #define DCS_SR_0P_TX BIT(18) 84 #define DCS_SW_1P_TX BIT(17) 85 #define DCS_SW_0P_TX BIT(16) 86 #define GEN_LW_TX BIT(14) 87 #define GEN_SR_2P_TX BIT(13) 88 #define GEN_SR_1P_TX BIT(12) 89 #define GEN_SR_0P_TX BIT(11) 90 #define GEN_SW_2P_TX BIT(10) 91 #define GEN_SW_1P_TX BIT(9) 92 #define GEN_SW_0P_TX BIT(8) 93 #define ACK_RQST_EN BIT(1) 94 #define TEAR_FX_EN BIT(0) 95 #define DSI_GEN_HDR 0x006c 96 #define GEN_WC_MSBYTE(x) UPDATE(x, 23, 16) 97 #define GEN_WC_LSBYTE(x) UPDATE(x, 15, 8) 98 #define GEN_VC(x) UPDATE(x, 7, 6) 99 #define GEN_DT(x) UPDATE(x, 5, 0) 100 #define DSI_GEN_PLD_DATA 0x0070 101 #define DSI_CMD_PKT_STATUS 0x0074 102 #define GEN_RD_CMD_BUSY BIT(6) 103 #define GEN_PLD_R_FULL BIT(5) 104 #define GEN_PLD_R_EMPTY BIT(4) 105 #define GEN_PLD_W_FULL BIT(3) 106 #define GEN_PLD_W_EMPTY BIT(2) 107 #define GEN_CMD_FULL BIT(1) 108 #define GEN_CMD_EMPTY BIT(0) 109 #define DSI_TO_CNT_CFG 0x0078 110 #define HSTX_TO_CNT(x) UPDATE(x, 31, 16) 111 #define LPRX_TO_CNT(x) UPDATE(x, 15, 0) 112 #define DSI_HS_RD_TO_CNT 0x007c 113 #define HS_RD_TO_CNT(x) UPDATE(x, 15, 0) 114 #define DSI_LP_RD_TO_CNT 0x0080 115 #define LP_RD_TO_CNT(x) UPDATE(x, 15, 0) 116 #define DSI_HS_WR_TO_CNT 0x0084 117 #define HS_WR_TO_CNT(x) UPDATE(x, 15, 0) 118 #define DSI_LP_WR_TO_CNT 0x0088 119 #define LP_WR_TO_CNT(x) UPDATE(x, 15, 0) 120 #define DSI_BTA_TO_CNT 0x008c 121 #define BTA_TO_CNT(x) UPDATE(x, 15, 0) 122 #define DSI_SDF_3D 0x0090 123 #define DSI_LPCLK_CTRL 0x0094 124 #define AUTO_CLKLANE_CTRL BIT(1) 125 #define PHY_TXREQUESTCLKHS BIT(0) 126 #define DSI_PHY_TMR_LPCLK_CFG 0x0098 127 #define PHY_CLKHS2LP_TIME(x) UPDATE(x, 25, 16) 128 #define PHY_CLKLP2HS_TIME(x) UPDATE(x, 9, 0) 129 #define DSI_PHY_TMR_CFG 0x009c 130 #define PHY_HS2LP_TIME(x) UPDATE(x, 31, 24) 131 #define PHY_LP2HS_TIME(x) UPDATE(x, 23, 16) 132 #define MAX_RD_TIME(x) UPDATE(x, 14, 0) 133 #define DSI_PHY_RSTZ 0x00a0 134 #define PHY_FORCEPLL BIT(3) 135 #define PHY_ENABLECLK BIT(2) 136 #define PHY_RSTZ BIT(1) 137 #define PHY_SHUTDOWNZ BIT(0) 138 #define DSI_PHY_IF_CFG 0x00a4 139 #define PHY_STOP_WAIT_TIME(x) UPDATE(x, 15, 8) 140 #define N_LANES(x) UPDATE(x, 1, 0) 141 #define DSI_PHY_STATUS 0x00b0 142 #define PHY_STOPSTATE3LANE BIT(11) 143 #define PHY_STOPSTATE2LANE BIT(9) 144 #define PHY_STOPSTATE1LANE BIT(7) 145 #define PHY_STOPSTATE0LANE BIT(4) 146 #define PHY_STOPSTATECLKLANE BIT(2) 147 #define PHY_LOCK BIT(0) 148 #define PHY_STOPSTATELANE (PHY_STOPSTATE0LANE | \ 149 PHY_STOPSTATECLKLANE) 150 #define DSI_INT_ST0 0x00bc 151 #define DSI_INT_ST1 0x00c0 152 #define DSI_INT_MSK0 0x00c4 153 #define DSI_INT_MSK1 0x00c8 154 #define DSI_INT_FORCE0 0x00d8 155 #define DSI_INT_FORCE1 0x00dc 156 #define DSI_MAX_REGISTER DSI_INT_FORCE1 157 158 enum vid_mode_type { 159 VIDEO_MODE, 160 COMMAND_MODE, 161 }; 162 163 struct rk628_dsi { 164 struct rk628 *rk628; 165 struct v4l2_dv_timings timings; 166 u64 lane_mbps; 167 int vid_mode; 168 int mode_flags; 169 }; 170 171 void rk628_mipi_dsi_power_on(struct rk628_dsi *dsi); 172 173 #endif 174