1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Shunqing Chen <csq@rock-chips.com> 6 */ 7 8 #ifndef RK628_CRU_H 9 #define RK628_CRU_H 10 11 #include "rk628.h" 12 13 #define CRU_REG(x) ((x) + 0xc0000) 14 15 #define CRU_CPLL_CON0 CRU_REG(0x0000) 16 #define PLL_BYPASS_MASK BIT(15) 17 #define PLL_BYPASS(x) HIWORD_UPDATE(x, 15, 15) 18 #define PLL_BYPASS_SHIFT 15 19 #define PLL_POSTDIV1_MASK GENMASK(14, 12) 20 #define PLL_POSTDIV1(x) HIWORD_UPDATE(x, 14, 12) 21 #define PLL_POSTDIV1_SHIFT 12 22 #define PLL_FBDIV_MASK GENMASK(11, 0) 23 #define PLL_FBDIV(x) HIWORD_UPDATE(x, 11, 0) 24 #define PLL_FBDIV_SHIFT 0 25 #define CRU_CPLL_CON1 CRU_REG(0x0004) 26 #define PLL_PD_MASK BIT(13) 27 #define PLL_PD(x) HIWORD_UPDATE(x, 13, 13) 28 #define PLL_DSMPD_MASK BIT(12) 29 #define PLL_DSMPD(x) HIWORD_UPDATE(x, 12, 12) 30 #define PLL_DSMPD_SHIFT 12 31 #define PLL_LOCK BIT(10) 32 #define PLL_POSTDIV2_MASK GENMASK(8, 6) 33 #define PLL_POSTDIV2(x) HIWORD_UPDATE(x, 8, 6) 34 #define PLL_POSTDIV2_SHIFT 6 35 #define PLL_REFDIV_MASK GENMASK(5, 0) 36 #define PLL_REFDIV(x) HIWORD_UPDATE(x, 5, 0) 37 #define PLL_REFDIV_SHIFT 0 38 #define CRU_CPLL_CON2 CRU_REG(0x0008) 39 #define PLL_FRAC_MASK GENMASK(23, 0) 40 #define PLL_FRAC(x) ((x) << 0) 41 #define PLL_FRAC_SHIFT 0 42 #define CRU_CPLL_CON3 CRU_REG(0x000c) 43 #define CRU_CPLL_CON4 CRU_REG(0x0010) 44 #define CRU_GPLL_CON0 CRU_REG(0x0020) 45 #define CRU_GPLL_CON1 CRU_REG(0x0024) 46 #define CRU_GPLL_CON2 CRU_REG(0x0028) 47 #define CRU_GPLL_CON3 CRU_REG(0x002c) 48 #define CRU_GPLL_CON4 CRU_REG(0x0030) 49 #define CRU_MODE_CON00 CRU_REG(0x0060) 50 #define CLK_GPLL_MODE_MASK BIT(2) 51 #define CLK_GPLL_MODE_SHIFT 2 52 #define CLK_GPLL_MODE_GPLL 1 53 #define CLK_GPLL_MODE_OSC 0 54 #define CLK_CPLL_MODE_MASK BIT(0) 55 #define CLK_CPLL_MODE_SHIFT 0 56 #define CLK_CPLL_MODE_CPLL 1 57 #define CLK_CPLL_MODE_OSC 0 58 #define CRU_CLKSEL_CON00 CRU_REG(0x0080) 59 #define CRU_CLKSEL_CON01 CRU_REG(0x0084) 60 #define CRU_CLKSEL_CON02 CRU_REG(0x0088) 61 #define SCLK_VOP_SEL_MASK BIT(9) 62 #define SCLK_VOP_SEL_SHIFT 9 63 #define SCLK_VOP_SEL_GPLL 1 64 #define SCLK_VOP_SEL_CPLL 0 65 #define CLK_RX_READ_SEL_MASK BIT(8) 66 #define CLK_RX_READ_SEL_SHIFT 8 67 #define CLK_RX_READ_SEL_GPLL 1 68 #define CLK_RX_READ_SEL_CPLL 0 69 #define CRU_CLKSEL_CON03 CRU_REG(0x008c) 70 #define CRU_CLKSEL_CON04 CRU_REG(0x0090) 71 #define CRU_CLKSEL_CON05 CRU_REG(0x0094) 72 #define CLK_HDMIRX_AUD_SEL BIT(15) 73 #define CRU_CLKSEL_CON06 CRU_REG(0x0098) 74 #define SCLK_UART_SEL(x) HIWORD_UPDATE(x, 15, 14) 75 #define SCLK_UART_SEL_MASK GENMASK(15, 14) 76 #define SCLK_UART_SEL_SHIFT 14 77 #define SCLK_UART_SEL_OSC 2 78 #define SCLK_UART_SEL_UART_FRAC 1 79 #define SCLK_UART_SEL_UART_SRC 0 80 #define CRU_CLKSEL_CON07 CRU_REG(0x009c) 81 #define CRU_CLKSEL_CON08 CRU_REG(0x00a0) 82 #define CRU_CLKSEL_CON09 CRU_REG(0x00a4) 83 #define CRU_CLKSEL_CON10 CRU_REG(0x00a8) 84 #define CRU_CLKSEL_CON11 CRU_REG(0x00ac) 85 #define CRU_CLKSEL_CON12 CRU_REG(0x00b0) 86 #define CRU_CLKSEL_CON13 CRU_REG(0x00b4) 87 #define CRU_CLKSEL_CON14 CRU_REG(0x00b8) 88 #define CRU_CLKSEL_CON15 CRU_REG(0x00bc) 89 #define CRU_CLKSEL_CON16 CRU_REG(0x00c0) 90 #define CRU_CLKSEL_CON17 CRU_REG(0x00c4) 91 #define CRU_CLKSEL_CON18 CRU_REG(0x00c8) 92 #define CRU_CLKSEL_CON20 CRU_REG(0x00d0) 93 #define CRU_CLKSEL_CON21 CRU_REG(0x00d4) 94 #define CLK_UART_SRC_SEL_MASK BIT(15) 95 #define CLK_UART_SRC_SEL_GPLL (1 << 15) 96 #define CLK_UART_SRC_SEL_CPLL (0 << 15) 97 #define CLK_UART_SRC_DIV_MASK GENMASK(12, 8) 98 #define CLK_UART_SRC_DIV_SHIFT 8 99 #define CRU_GATE_CON00 CRU_REG(0x0180) 100 #define CRU_GATE_CON01 CRU_REG(0x0184) 101 #define CRU_GATE_CON02 CRU_REG(0x0188) 102 #define CRU_GATE_CON03 CRU_REG(0x018c) 103 #define CRU_GATE_CON04 CRU_REG(0x0190) 104 #define CRU_GATE_CON05 CRU_REG(0x0194) 105 #define CRU_SOFTRST_CON00 CRU_REG(0x0200) 106 #define CRU_SOFTRST_CON01 CRU_REG(0x0204) 107 #define CRU_SOFTRST_CON02 CRU_REG(0x0208) 108 #define CRU_SOFTRST_CON04 CRU_REG(0x0210) 109 #define CRU_MAX_REGISTER CRU_SOFTRST_CON04 110 111 #define CGU_CLK_CPLL 1 112 #define CGU_CLK_GPLL 2 113 #define CGU_CLK_CPLL_MUX 3 114 #define CGU_CLK_GPLL_MUX 4 115 #define CGU_PCLK_GPIO0 5 116 #define CGU_PCLK_GPIO1 6 117 #define CGU_PCLK_GPIO2 7 118 #define CGU_PCLK_GPIO3 8 119 #define CGU_PCLK_TXPHY_CON 9 120 #define CGU_PCLK_EFUSE 10 121 #define CGU_PCLK_DSI0 11 122 #define CGU_PCLK_DSI1 12 123 #define CGU_PCLK_CSI 13 124 #define CGU_PCLK_HDMITX 14 125 #define CGU_PCLK_RXPHY 15 126 #define CGU_PCLK_HDMIRX 16 127 #define CGU_PCLK_DPRX 17 128 #define CGU_PCLK_GVIHOST 18 129 #define CGU_CLK_CFG_DPHY0 19 130 #define CGU_CLK_CFG_DPHY1 20 131 #define CGU_CLK_TXESC 21 132 #define CGU_CLK_DPRX_VID 22 133 #define CGU_CLK_IMODET 23 134 #define CGU_CLK_HDMIRX_AUD 24 135 #define CGU_CLK_HDMIRX_CEC 25 136 #define CGU_CLK_RX_READ 26 137 #define CGU_SCLK_VOP 27 138 #define CGU_PCLK_LOGIC 28 139 #define CGU_CLK_GPIO_DB0 29 140 #define CGU_CLK_GPIO_DB1 30 141 #define CGU_CLK_GPIO_DB2 31 142 #define CGU_CLK_GPIO_DB3 32 143 #define CGU_CLK_I2S_8CH_SRC 33 144 #define CGU_CLK_I2S_8CH_FRAC 34 145 #define CGU_MCLK_I2S_8CH 35 146 #define CGU_I2S_MCLKOUT 36 147 #define CGU_BT1120DEC 37 148 #define CGU_SCLK_UART 38 149 150 #define RGU_LOGIC 0 151 #define RGU_CRU 1 152 #define RGU_REGFILE 2 153 #define RGU_I2C2APB 3 154 #define RGU_EFUSE 4 155 #define RGU_ADAPTER 5 156 #define RGU_CLK_RX 6 157 #define RGU_BT1120DEC 7 158 #define RGU_VOP 8 159 #define RGU_GPIO0 9 160 #define RGU_GPIO1 10 161 #define RGU_GPIO2 11 162 #define RGU_GPIO3 12 163 #define RGU_GPIO_DB0 13 164 #define RGU_GPIO_DB1 14 165 #define RGU_GPIO_DB2 15 166 #define RGU_GPIO_DB3 16 167 #define RGU_RXPHY 17 168 #define RGU_HDMIRX 18 169 #define RGU_TXPHY_CON 19 170 #define RGU_HDMITX 20 171 #define RGU_GVIHOST 21 172 #define RGU_DSI0 22 173 #define RGU_DSI1 23 174 #define RGU_CSI 24 175 #define RGU_TXDATA 25 176 #define RGU_DECODER 26 177 #define RGU_ENCODER 27 178 #define RGU_HDMIRX_PON 28 179 #define RGU_TXBYTEHS 29 180 #define RGU_TXESC 30 181 182 unsigned long rk628_clk_get_rate(struct rk628 *rk628, unsigned int id); 183 int rk628_clk_set_rate(struct rk628 *rk628, unsigned int id, 184 unsigned long rate); 185 int rk628_control_assert(struct rk628 *rk628, unsigned long id); 186 int rk628_control_deassert(struct rk628 *rk628, unsigned long id); 187 void rk628_cru_initialize(struct rk628 *rk628); 188 void rk628_clk_mux_testout(struct rk628 *rk628, int id); 189 190 #endif 191