1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Shunqing Chen csq@rock-chips.com> 6 */ 7 8 #ifndef _RK628_COMBTXPHY_H 9 #define _RK628_COMBTXPHY_H 10 11 #define COMBTXPHY_BASE 0x90000 12 #define COMBTXPHY_REG(x) ((x) + COMBTXPHY_BASE) 13 14 #define COMBTXPHY_CON0 COMBTXPHY_REG(0x0000) 15 #define SW_TX_IDLE_MASK GENMASK(29, 20) 16 #define SW_TX_IDLE(x) UPDATE(x, 29, 20) 17 #define SW_TX_PD_MASK GENMASK(17, 8) 18 #define SW_TX_PD(x) UPDATE(x, 17, 8) 19 #define SW_BUS_WIDTH_MASK GENMASK(6, 5) 20 #define SW_BUS_WIDTH_7BIT UPDATE(0x3, 6, 5) 21 #define SW_BUS_WIDTH_8BIT UPDATE(0x2, 6, 5) 22 #define SW_BUS_WIDTH_9BIT UPDATE(0x1, 6, 5) 23 #define SW_BUS_WIDTH_10BIT UPDATE(0x0, 6, 5) 24 #define SW_PD_PLL_MASK BIT(4) 25 #define SW_PD_PLL BIT(4) 26 #define SW_GVI_LVDS_EN_MASK BIT(3) 27 #define SW_GVI_LVDS_EN BIT(3) 28 #define SW_MIPI_DSI_EN_MASK BIT(2) 29 #define SW_MIPI_DSI_EN BIT(2) 30 #define SW_MODULEB_EN_MASK BIT(1) 31 #define SW_MODULEB_EN BIT(1) 32 #define SW_MODULEA_EN_MASK BIT(0) 33 #define SW_MODULEA_EN BIT(0) 34 #define COMBTXPHY_CON1 COMBTXPHY_REG(0x0004) 35 #define COMBTXPHY_CON2 COMBTXPHY_REG(0x0008) 36 #define COMBTXPHY_CON3 COMBTXPHY_REG(0x000c) 37 #define COMBTXPHY_CON4 COMBTXPHY_REG(0x0010) 38 #define COMBTXPHY_CON5 COMBTXPHY_REG(0x0014) 39 #define SW_RATE(x) UPDATE(x, 26, 24) 40 #define SW_REF_DIV(x) UPDATE(x, 20, 16) 41 #define SW_PLL_FB_DIV(x) UPDATE(x, 14, 10) 42 #define SW_PLL_FRAC_DIV(x) UPDATE(x, 9, 0) 43 #define COMBTXPHY_CON6 COMBTXPHY_REG(0x0018) 44 #define COMBTXPHY_CON7 COMBTXPHY_REG(0x001c) 45 #define SW_TX_RTERM_MASK GENMASK(22, 20) 46 #define SW_TX_RTERM(x) UPDATE(x, 22, 20) 47 #define SW_TX_MODE_MASK GENMASK(17, 16) 48 #define SW_TX_MODE(x) UPDATE(x, 17, 16) 49 #define SW_TX_CTL_CON5_MASK BIT(10) 50 #define SW_TX_CTL_CON5(x) UPDATE(x, 10, 10) 51 #define SW_TX_CTL_CON4_MASK GENMASK(9, 8) 52 #define SW_TX_CTL_CON4(x) UPDATE(x, 9, 8) 53 #define COMBTXPHY_CON8 COMBTXPHY_REG(0x0020) 54 #define COMBTXPHY_CON9 COMBTXPHY_REG(0x0024) 55 #define SW_DSI_FSET_EN_MASK BIT(29) 56 #define SW_DSI_FSET_EN BIT(29) 57 #define SW_DSI_RCAL_EN_MASK BIT(28) 58 #define SW_DSI_RCAL_EN BIT(28) 59 #define COMBTXPHY_CON10 COMBTXPHY_REG(0x0028) 60 #define TX9_CKDRV_EN BIT(9) 61 #define TX8_CKDRV_EN BIT(8) 62 #define TX7_CKDRV_EN BIT(7) 63 #define TX6_CKDRV_EN BIT(6) 64 #define TX5_CKDRV_EN BIT(5) 65 #define TX4_CKDRV_EN BIT(4) 66 #define TX3_CKDRV_EN BIT(3) 67 #define TX2_CKDRV_EN BIT(2) 68 #define TX1_CKDRV_EN BIT(1) 69 #define TX0_CKDRV_EN BIT(0) 70 71 enum phy_mode { 72 PHY_MODE_INVALID, 73 PHY_MODE_VIDEO_MIPI, 74 PHY_MODE_VIDEO_LVDS, 75 PHY_MODE_VIDEO_GVI, 76 }; 77 78 struct rk628_combtxphy { 79 enum phy_mode mode; 80 unsigned int flags; 81 u8 ref_div; 82 u8 fb_div; 83 u16 frac_div; 84 u8 rate_div; 85 u32 bus_width; 86 }; 87 88 void rk628_txphy_set_mode(struct rk628 *rk628, enum phy_mode mode); 89 void rk628_txphy_set_bus_width(struct rk628 *rk628, u32 bus_width); 90 u32 rk628_txphy_get_bus_width(struct rk628 *rk628); 91 void rk628_txphy_power_on(struct rk628 *rk628); 92 void rk628_txphy_power_off(struct rk628 *rk628); 93 struct rk628_combtxphy *rk628_txphy_register(struct rk628 *rk628); 94 95 #endif 96