1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Shunqing Chen <csq@rock-chips.com>
6 */
7
8 #include <linux/clk.h>
9 #include <linux/compat.h>
10 #include <linux/debugfs.h>
11 #include <linux/delay.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/i2c.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/math64.h>
18 #include <linux/module.h>
19 #include <linux/of_graph.h>
20 #include <linux/platform_device.h>
21 #include <linux/reset.h>
22 #include <linux/rk-camera-module.h>
23 #include <linux/slab.h>
24 #include <linux/timer.h>
25 #include <linux/v4l2-controls.h>
26 #include <linux/v4l2-dv-timings.h>
27 #include <linux/version.h>
28 #include <linux/videodev2.h>
29 #include <linux/workqueue.h>
30 #include <media/v4l2-controls_rockchip.h>
31 #include <media/v4l2-ctrls.h>
32 #include <media/v4l2-device.h>
33 #include <media/v4l2-dv-timings.h>
34 #include <media/v4l2-event.h>
35 #include <media/v4l2-fwnode.h>
36 #include <video/videomode.h>
37
38 #include "rk628.h"
39 #include "rk628_combrxphy.h"
40 #include "rk628_cru.h"
41 #include "rk628_hdmirx.h"
42
43 static int debug;
44 module_param(debug, int, 0644);
45 MODULE_PARM_DESC(debug, "debug level (0-3)");
46
47 #define DRIVER_VERSION KERNEL_VERSION(0, 0x0, 0x1)
48 #define RK628_BT1120_NAME "rk628-bt1120"
49
50 #define EDID_NUM_BLOCKS_MAX 2
51 #define EDID_BLOCK_SIZE 128
52
53 #define RK628_CSI_LINK_FREQ_LOW 350000000
54 #define RK628_CSI_LINK_FREQ_HIGH 400000000
55 #define RK628_CSI_PIXEL_RATE_LOW 400000000
56 #define RK628_CSI_PIXEL_RATE_HIGH 600000000
57 #define MIPI_DATARATE_MBPS_LOW 750
58 #define MIPI_DATARATE_MBPS_HIGH 1250
59
60 #define POLL_INTERVAL_MS 1000
61 #define MODETCLK_CNT_NUM 1000
62 #define MODETCLK_HZ 49500000
63 #define RXPHY_CFG_MAX_TIMES 15
64 #define CSITX_ERR_RETRY_TIMES 3
65
66 #define USE_4_LANES 4
67 #define YUV422_8BIT 0x1e
68 /* Test Code: 0x44 (HS RX Control of Lane 0) */
69 #define HSFREQRANGE(x) UPDATE(x, 6, 1)
70
71 struct rk628_bt1120 {
72 struct device *dev;
73 struct i2c_client *i2c_client;
74 struct rk628 *rk628;
75 struct media_pad pad;
76 struct v4l2_subdev sd;
77 struct v4l2_dv_timings src_timings;
78 struct v4l2_dv_timings timings;
79 struct v4l2_ctrl_handler hdl;
80 struct v4l2_ctrl *detect_tx_5v_ctrl;
81 struct v4l2_ctrl *audio_sampling_rate_ctrl;
82 struct v4l2_ctrl *audio_present_ctrl;
83 struct v4l2_ctrl *link_freq;
84 struct v4l2_ctrl *pixel_rate;
85 struct gpio_desc *enable_gpio;
86 struct gpio_desc *reset_gpio;
87 struct gpio_desc *power_gpio;
88 struct gpio_desc *plugin_det_gpio;
89 struct clk *soc_24M;
90 struct clk *clk_hdmirx_aud;
91 struct clk *clk_vop;
92 struct clk *clk_rx_read;
93 struct delayed_work delayed_work_enable_hotplug;
94 struct delayed_work delayed_work_res_change;
95 struct timer_list timer;
96 struct work_struct work_i2c_poll;
97 struct mutex confctl_mutex;
98 const struct rk628_bt1120_mode *cur_mode;
99 const char *module_facing;
100 const char *module_name;
101 const char *len_name;
102 u32 module_index;
103 u8 edid_blocks_written;
104 u64 lane_mbps;
105 u8 bt1120_lanes_in_use;
106 u32 mbus_fmt_code;
107 u8 fps;
108 u32 stream_state;
109 int hdmirx_irq;
110 int plugin_irq;
111 bool nosignal;
112 bool rxphy_pwron;
113 bool enable_hdcp;
114 bool scaler_en;
115 bool hpd_output_inverted;
116 bool avi_rcv_rdy;
117 bool vid_ints_en;
118 bool dual_edge;
119 struct rk628_hdcp hdcp;
120 bool i2s_enable_default;
121 HAUDINFO audio_info;
122 };
123
124 struct rk628_bt1120_mode {
125 u32 width;
126 u32 height;
127 struct v4l2_fract max_fps;
128 u32 hts_def;
129 u32 vts_def;
130 u32 exp_def;
131 };
132
133 static const s64 link_freq_menu_items[] = {
134 RK628_CSI_LINK_FREQ_LOW,
135 RK628_CSI_LINK_FREQ_HIGH,
136 };
137
138 static const struct v4l2_dv_timings_cap rk628_bt1120_timings_cap = {
139 .type = V4L2_DV_BT_656_1120,
140 /* keep this initialization for compatibility with GCC < 4.4.6 */
141 .reserved = { 0 },
142 V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 400000000,
143 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
144 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
145 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
146 V4L2_DV_BT_CAP_REDUCED_BLANKING |
147 V4L2_DV_BT_CAP_CUSTOM)
148 };
149
150 static u8 edid_init_data[] = {
151 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
152 0x49, 0x73, 0x8D, 0x62, 0x00, 0x88, 0x88, 0x88,
153 0x08, 0x1E, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
154 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
155 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
156 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
157 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
158 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
159 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
160 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
161 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
162 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
163 0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
164 0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
165 0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
166 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x18,
167
168 0x02, 0x03, 0x19, 0x71, 0x46, 0x90, 0x22, 0x04,
169 0x11, 0x02, 0x01, 0x23, 0x09, 0x07, 0x01, 0x83,
170 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00, 0x10,
171 0x00, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0, 0x2D,
172 0x10, 0x10, 0x3E, 0x96, 0x00, 0x13, 0x8E, 0x21,
173 0x00, 0x00, 0x1E, 0xD8, 0x09, 0x80, 0xA0, 0x20,
174 0xE0, 0x2D, 0x10, 0x10, 0x60, 0xA2, 0x00, 0xC4,
175 0x8E, 0x21, 0x00, 0x00, 0x18, 0x02, 0x3A, 0x80,
176 0xD0, 0x72, 0x38, 0x2D, 0x40, 0x10, 0x2C, 0x45,
177 0x80, 0x20, 0xC2, 0x31, 0x00, 0x00, 0x1E, 0x01,
178 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58,
179 0x2C, 0x45, 0x00, 0xC0, 0x6C, 0x00, 0x00, 0x00,
180 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C, 0x16,
181 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC0, 0x6C, 0x00,
182 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x45,
184 };
185
186 static const struct rk628_bt1120_mode supported_modes[] = {
187 {
188 .width = 1920,
189 .height = 1080,
190 .max_fps = {
191 .numerator = 10000,
192 .denominator = 600000,
193 },
194 .hts_def = 2200,
195 .vts_def = 1125,
196 }, {
197 .width = 1280,
198 .height = 720,
199 .max_fps = {
200 .numerator = 10000,
201 .denominator = 600000,
202 },
203 .hts_def = 1650,
204 .vts_def = 750,
205 }, {
206 .width = 720,
207 .height = 576,
208 .max_fps = {
209 .numerator = 10000,
210 .denominator = 500000,
211 },
212 .hts_def = 864,
213 .vts_def = 625,
214 }, {
215 .width = 720,
216 .height = 480,
217 .max_fps = {
218 .numerator = 10000,
219 .denominator = 600000,
220 },
221 .hts_def = 858,
222 .vts_def = 525,
223 },
224 };
225
226 static struct v4l2_dv_timings dst_timing = {
227 .type = V4L2_DV_BT_656_1120,
228 .bt = {
229 .interlaced = V4L2_DV_PROGRESSIVE,
230 .width = 1920,
231 .height = 1080,
232 .hfrontporch = 88,
233 .hsync = 44,
234 .hbackporch = 148,
235 .vfrontporch = 4,
236 .vsync = 5,
237 .vbackporch = 36,
238 .pixelclock = 148500000,
239 },
240 };
241
242 static void rk628_post_process_setup(struct v4l2_subdev *sd);
243 static void rk628_bt1120_enable_interrupts(struct v4l2_subdev *sd, bool en);
244 static int rk628_bt1120_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
245 static int rk628_bt1120_s_dv_timings(struct v4l2_subdev *sd,
246 struct v4l2_dv_timings *timings);
247 static int rk628_bt1120_s_edid(struct v4l2_subdev *sd,
248 struct v4l2_subdev_edid *edid);
249 static int rk628_hdmirx_phy_power_on(struct v4l2_subdev *sd);
250 static int rk628_hdmirx_phy_power_off(struct v4l2_subdev *sd);
251 static int rk628_hdmirx_phy_setup(struct v4l2_subdev *sd);
252 static void rk628_bt1120_format_change(struct v4l2_subdev *sd);
253 static void enable_stream(struct v4l2_subdev *sd, bool enable);
254 static void rk628_hdmirx_vid_enable(struct v4l2_subdev *sd, bool en);
255 static void rk628_hdmirx_hpd_ctrl(struct v4l2_subdev *sd, bool en);
256 static void rk628_hdmirx_controller_reset(struct v4l2_subdev *sd);
257 static void rk628_bt1120_initial_setup(struct v4l2_subdev *sd);
258
to_bt1120(struct v4l2_subdev * sd)259 static inline struct rk628_bt1120 *to_bt1120(struct v4l2_subdev *sd)
260 {
261 return container_of(sd, struct rk628_bt1120, sd);
262 }
263
tx_5v_power_present(struct v4l2_subdev * sd)264 static bool tx_5v_power_present(struct v4l2_subdev *sd)
265 {
266 bool ret;
267 int val, i, cnt;
268 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
269
270 /* Direct Mode */
271 if (!bt1120->plugin_det_gpio)
272 return true;
273
274 cnt = 0;
275 for (i = 0; i < 5; i++) {
276 val = gpiod_get_value(bt1120->plugin_det_gpio);
277 if (val > 0)
278 cnt++;
279 usleep_range(500, 600);
280 }
281
282 ret = (cnt >= 3) ? true : false;
283 v4l2_dbg(1, debug, sd, "%s: %d\n", __func__, ret);
284
285 return ret;
286 }
287
no_signal(struct v4l2_subdev * sd)288 static inline bool no_signal(struct v4l2_subdev *sd)
289 {
290 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
291
292 v4l2_dbg(1, debug, sd, "%s no signal:%d\n", __func__, bt1120->nosignal);
293 return bt1120->nosignal;
294 }
295
audio_present(struct v4l2_subdev * sd)296 static inline bool audio_present(struct v4l2_subdev *sd)
297 {
298 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
299
300 return rk628_hdmirx_audio_present(bt1120->audio_info);
301 }
302
get_audio_sampling_rate(struct v4l2_subdev * sd)303 static int get_audio_sampling_rate(struct v4l2_subdev *sd)
304 {
305 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
306
307 if (no_signal(sd))
308 return 0;
309
310 return rk628_hdmirx_audio_fs(bt1120->audio_info);
311 }
312
rk628_hdmirx_ctrl_enable(struct v4l2_subdev * sd,int en)313 static void rk628_hdmirx_ctrl_enable(struct v4l2_subdev *sd, int en)
314 {
315 u32 mask;
316 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
317
318 if (en) {
319 /* don't enable audio until N CTS updated */
320 mask = HDMI_ENABLE_MASK;
321 v4l2_dbg(1, debug, sd, "%s: %#x %d\n", __func__, mask, en);
322 rk628_i2c_update_bits(bt1120->rk628, HDMI_RX_DMI_DISABLE_IF,
323 mask, HDMI_ENABLE(1) | AUD_ENABLE(1));
324 } else {
325 mask = AUD_ENABLE_MASK | HDMI_ENABLE_MASK;
326 v4l2_dbg(1, debug, sd, "%s: %#x %d\n", __func__, mask, en);
327 rk628_i2c_update_bits(bt1120->rk628, HDMI_RX_DMI_DISABLE_IF,
328 mask, HDMI_ENABLE(0) | AUD_ENABLE(0));
329 }
330 }
rk628_bt1120_get_detected_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)331 static int rk628_bt1120_get_detected_timings(struct v4l2_subdev *sd,
332 struct v4l2_dv_timings *timings)
333 {
334 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
335 struct v4l2_bt_timings *bt = &timings->bt;
336 u32 hact, vact, htotal, vtotal, fps, status;
337 u32 val;
338 u32 modetclk_cnt_hs, modetclk_cnt_vs, hs, vs;
339 u32 hofs_pix, hbp, hfp, vbp, vfp;
340 u32 tmds_clk, tmdsclk_cnt;
341 u64 tmp_data;
342 int retry = 0;
343
344 __retry:
345 memset(timings, 0, sizeof(struct v4l2_dv_timings));
346 timings->type = V4L2_DV_BT_656_1120;
347 rk628_i2c_read(bt1120->rk628, HDMI_RX_SCDC_REGS1, &val);
348 status = val;
349
350 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_STS, &val);
351 bt->interlaced = val & ILACE_STS ?
352 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
353
354 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HACT_PX, &val);
355 hact = val & 0xffff;
356 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VAL, &val);
357 vact = val & 0xffff;
358 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HT1, &val);
359 htotal = (val >> 16) & 0xffff;
360 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VTL, &val);
361 vtotal = val & 0xffff;
362 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HT1, &val);
363 hofs_pix = val & 0xffff;
364 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VOL, &val);
365 vbp = (val & 0xffff) + 1;
366
367 rk628_i2c_read(bt1120->rk628, HDMI_RX_HDMI_CKM_RESULT, &val);
368 tmdsclk_cnt = val & 0xffff;
369 tmp_data = tmdsclk_cnt;
370 tmp_data = ((tmp_data * MODETCLK_HZ) + MODETCLK_CNT_NUM / 2);
371 do_div(tmp_data, MODETCLK_CNT_NUM);
372 tmds_clk = tmp_data;
373 if (!htotal || !vtotal) {
374 v4l2_err(&bt1120->sd, "timing err, htotal:%d, vtotal:%d\n",
375 htotal, vtotal);
376 if (retry++ < 5)
377 goto __retry;
378
379 goto TIMING_ERR;
380 }
381 fps = (tmds_clk + (htotal * vtotal) / 2) / (htotal * vtotal);
382
383 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HT0, &val);
384 modetclk_cnt_hs = val & 0xffff;
385 hs = (tmdsclk_cnt * modetclk_cnt_hs + MODETCLK_CNT_NUM / 2) /
386 MODETCLK_CNT_NUM;
387
388 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VSC, &val);
389 modetclk_cnt_vs = val & 0xffff;
390 vs = (tmdsclk_cnt * modetclk_cnt_vs + MODETCLK_CNT_NUM / 2) /
391 MODETCLK_CNT_NUM;
392 vs = (vs + htotal / 2) / htotal;
393
394 if ((hofs_pix < hs) || (htotal < (hact + hofs_pix)) ||
395 (vtotal < (vact + vs + vbp))) {
396 v4l2_err(sd, "timing err, total:%dx%d, act:%dx%d, hofs:%d, hs:%d, vs:%d, vbp:%d\n",
397 htotal, vtotal, hact, vact, hofs_pix, hs, vs, vbp);
398 goto TIMING_ERR;
399 }
400 hbp = hofs_pix - hs;
401 hfp = htotal - hact - hofs_pix;
402 vfp = vtotal - vact - vs - vbp;
403
404 v4l2_dbg(2, debug, sd, "cnt_num:%d, tmds_cnt:%d, hs_cnt:%d, vs_cnt:%d, hofs:%d\n",
405 MODETCLK_CNT_NUM, tmdsclk_cnt, modetclk_cnt_hs, modetclk_cnt_vs, hofs_pix);
406
407 bt->width = hact;
408 bt->height = vact;
409 bt->hfrontporch = hfp;
410 bt->hsync = hs;
411 bt->hbackporch = hbp;
412 bt->vfrontporch = vfp;
413 bt->vsync = vs;
414 bt->vbackporch = vbp;
415 bt->pixelclock = htotal * vtotal * fps;
416
417 if (bt->interlaced == V4L2_DV_INTERLACED) {
418 bt->height *= 2;
419 bt->il_vsync = bt->vsync + 1;
420 bt->pixelclock /= 2;
421 }
422
423 v4l2_dbg(1, debug, sd, "SCDC_REGS1:%#x, act:%dx%d, total:%dx%d, fps:%d, pixclk:%llu\n",
424 status, hact, vact, htotal, vtotal, fps, bt->pixelclock);
425 v4l2_dbg(1, debug, sd, "hfp:%d, hs:%d, hbp:%d, vfp:%d, vs:%d, vbp:%d, interlace:%d\n",
426 bt->hfrontporch, bt->hsync, bt->hbackporch, bt->vfrontporch,
427 bt->vsync, bt->vbackporch, bt->interlaced);
428
429 bt1120->src_timings = *timings;
430 if (bt1120->scaler_en)
431 *timings = bt1120->timings;
432
433 return 0;
434
435 TIMING_ERR:
436 return -ENOLCK;
437 }
438
rk628_hdmirx_config_all(struct v4l2_subdev * sd)439 static void rk628_hdmirx_config_all(struct v4l2_subdev *sd)
440 {
441 int ret;
442 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
443
444 rk628_hdmirx_controller_setup(bt1120->rk628);
445 ret = rk628_hdmirx_phy_setup(sd);
446 if (ret >= 0) {
447 rk628_bt1120_format_change(sd);
448 bt1120->nosignal = false;
449 }
450 }
451
rk628_hdmirx_reset_regfile(struct v4l2_subdev * sd)452 static void rk628_hdmirx_reset_regfile(struct v4l2_subdev *sd)
453 {
454 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
455
456 rk628_control_assert(bt1120->rk628, RGU_REGFILE);
457 udelay(10);
458 rk628_control_deassert(bt1120->rk628, RGU_REGFILE);
459 udelay(10);
460
461 rk628_cru_initialize(bt1120->rk628);
462 rk628_bt1120_initial_setup(sd);
463 if (tx_5v_power_present(sd))
464 rk628_hdmirx_hpd_ctrl(sd, true);
465 }
466
rk628_set_io_func_to_vop(struct rk628 * rk628)467 static void rk628_set_io_func_to_vop(struct rk628 *rk628)
468 {
469 /* pinctrl for vop pin */
470 rk628_i2c_write(rk628, GRF_GPIO2AB_SEL_CON, 0xffffffff);
471 rk628_i2c_write(rk628, GRF_GPIO2C_SEL_CON, 0xffff5555);
472 rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, 0x10b010b);
473 }
474
rk628_set_io_func_to_gpio(struct rk628 * rk628)475 static void rk628_set_io_func_to_gpio(struct rk628 *rk628)
476 {
477 /* pinctrl for gpio */
478 rk628_i2c_write(rk628, GRF_GPIO2AB_SEL_CON, 0xffff0000);
479 rk628_i2c_write(rk628, GRF_GPIO2C_SEL_CON, 0xffff0000);
480 rk628_i2c_write(rk628, GRF_GPIO3AB_SEL_CON, 0x0fff0000);
481 }
482
rk628_bt1120_delayed_work_enable_hotplug(struct work_struct * work)483 static void rk628_bt1120_delayed_work_enable_hotplug(struct work_struct *work)
484 {
485 struct delayed_work *dwork = to_delayed_work(work);
486 struct rk628_bt1120 *bt1120 = container_of(dwork, struct rk628_bt1120,
487 delayed_work_enable_hotplug);
488 struct v4l2_subdev *sd = &bt1120->sd;
489 bool plugin;
490
491 mutex_lock(&bt1120->confctl_mutex);
492 bt1120->avi_rcv_rdy = false;
493 plugin = tx_5v_power_present(sd);
494 v4l2_dbg(1, debug, sd, "%s: 5v_det:%d\n", __func__, plugin);
495 if (plugin) {
496 rk628_set_io_func_to_vop(bt1120->rk628);
497 rk628_bt1120_enable_interrupts(sd, false);
498 rk628_hdmirx_audio_setup(bt1120->audio_info);
499 rk628_hdmirx_set_hdcp(bt1120->rk628, &bt1120->hdcp, bt1120->enable_hdcp);
500 rk628_hdmirx_hpd_ctrl(sd, true);
501 rk628_hdmirx_config_all(sd);
502 rk628_bt1120_enable_interrupts(sd, true);
503 rk628_i2c_update_bits(bt1120->rk628, GRF_SYSTEM_CON0,
504 SW_I2S_DATA_OEN_MASK, SW_I2S_DATA_OEN(0));
505 } else {
506 rk628_bt1120_enable_interrupts(sd, false);
507 enable_stream(sd, false);
508 cancel_delayed_work(&bt1120->delayed_work_res_change);
509 rk628_hdmirx_audio_cancel_work_audio(bt1120->audio_info, true);
510 rk628_hdmirx_hpd_ctrl(sd, false);
511 rk628_hdmirx_phy_power_off(sd);
512 rk628_hdmirx_controller_reset(sd);
513 bt1120->nosignal = true;
514 rk628_set_io_func_to_gpio(bt1120->rk628);
515 }
516 mutex_unlock(&bt1120->confctl_mutex);
517 }
518
rk628_check_resulotion_change(struct v4l2_subdev * sd)519 static int rk628_check_resulotion_change(struct v4l2_subdev *sd)
520 {
521 u32 val;
522 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
523 u32 htotal, vtotal;
524 u32 old_htotal, old_vtotal;
525 struct v4l2_bt_timings *bt = &bt1120->src_timings.bt;
526
527 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HT1, &val);
528 htotal = (val >> 16) & 0xffff;
529 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VTL, &val);
530 vtotal = val & 0xffff;
531
532 old_htotal = bt->hfrontporch + bt->hsync + bt->width + bt->hbackporch;
533 old_vtotal = bt->vfrontporch + bt->vsync + bt->height + bt->vbackporch;
534
535 v4l2_dbg(1, debug, sd, "new mode: %d x %d\n", htotal, vtotal);
536 v4l2_dbg(1, debug, sd, "old mode: %d x %d\n", old_htotal, old_vtotal);
537
538 if (htotal != old_htotal || vtotal != old_vtotal)
539 return 1;
540
541 return 0;
542 }
543
rk628_delayed_work_res_change(struct work_struct * work)544 static void rk628_delayed_work_res_change(struct work_struct *work)
545 {
546 struct delayed_work *dwork = to_delayed_work(work);
547 struct rk628_bt1120 *bt1120 = container_of(dwork, struct rk628_bt1120,
548 delayed_work_res_change);
549 struct v4l2_subdev *sd = &bt1120->sd;
550 bool plugin;
551
552 mutex_lock(&bt1120->confctl_mutex);
553 bt1120->avi_rcv_rdy = false;
554 plugin = tx_5v_power_present(sd);
555 v4l2_dbg(1, debug, sd, "%s: 5v_det:%d\n", __func__, plugin);
556 if (plugin) {
557 if (rk628_check_resulotion_change(sd)) {
558 v4l2_dbg(1, debug, sd, "res change, recfg ctrler and phy!\n");
559
560 rk628_bt1120_enable_interrupts(sd, false);
561 enable_stream(sd, false);
562 cancel_delayed_work(&bt1120->delayed_work_res_change);
563 rk628_hdmirx_audio_cancel_work_audio(bt1120->audio_info, true);
564 rk628_hdmirx_hpd_ctrl(sd, false);
565 rk628_hdmirx_phy_power_off(sd);
566 rk628_hdmirx_controller_reset(sd);
567 bt1120->nosignal = true;
568 rk628_hdmirx_reset_regfile(sd);
569 } else {
570 rk628_bt1120_format_change(sd);
571 bt1120->nosignal = false;
572 rk628_bt1120_enable_interrupts(sd, true);
573 }
574 }
575 mutex_unlock(&bt1120->confctl_mutex);
576 }
577
rk628_hdmirx_hpd_ctrl(struct v4l2_subdev * sd,bool en)578 static void rk628_hdmirx_hpd_ctrl(struct v4l2_subdev *sd, bool en)
579 {
580 u8 en_level, set_level;
581 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
582
583 v4l2_dbg(1, debug, sd, "%s: %sable, hpd invert:%d\n", __func__,
584 en ? "en" : "dis", bt1120->hpd_output_inverted);
585 en_level = bt1120->hpd_output_inverted ? 0 : 1;
586 set_level = en ? en_level : !en_level;
587 rk628_i2c_update_bits(bt1120->rk628, HDMI_RX_HDMI_SETUP_CTRL,
588 HOT_PLUG_DETECT_MASK, HOT_PLUG_DETECT(set_level));
589 }
590
rk628_bt1120_s_ctrl_detect_tx_5v(struct v4l2_subdev * sd)591 static int rk628_bt1120_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
592 {
593 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
594
595 return v4l2_ctrl_s_ctrl(bt1120->detect_tx_5v_ctrl,
596 tx_5v_power_present(sd));
597 }
598
rk628_bt1120_s_ctrl_audio_sampling_rate(struct v4l2_subdev * sd)599 static int rk628_bt1120_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
600 {
601 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
602
603 return v4l2_ctrl_s_ctrl(bt1120->audio_sampling_rate_ctrl,
604 get_audio_sampling_rate(sd));
605 }
606
rk628_bt1120_s_ctrl_audio_present(struct v4l2_subdev * sd)607 static int rk628_bt1120_s_ctrl_audio_present(struct v4l2_subdev *sd)
608 {
609 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
610
611 return v4l2_ctrl_s_ctrl(bt1120->audio_present_ctrl,
612 audio_present(sd));
613 }
614
rk628_bt1120_update_controls(struct v4l2_subdev * sd)615 static int rk628_bt1120_update_controls(struct v4l2_subdev *sd)
616 {
617 int ret = 0;
618
619 ret |= rk628_bt1120_s_ctrl_detect_tx_5v(sd);
620 ret |= rk628_bt1120_s_ctrl_audio_sampling_rate(sd);
621 ret |= rk628_bt1120_s_ctrl_audio_present(sd);
622
623 return ret;
624 }
625
enable_bt1120tx(struct v4l2_subdev * sd)626 static void enable_bt1120tx(struct v4l2_subdev *sd)
627 {
628 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
629 u8 video_fmt;
630 u32 val = 0;
631 int avi_rdy;
632
633 rk628_post_process_setup(sd);
634
635 rk628_i2c_update_bits(bt1120->rk628, GRF_POST_PROC_CON,
636 SW_DCLK_OUT_INV_EN, SW_DCLK_OUT_INV_EN);
637
638 if (bt1120->dual_edge) {
639 val |= ENC_DUALEDGE_EN(1);
640 rk628_i2c_write(bt1120->rk628, GRF_BT1120_DCLK_DELAY_CON0, 0x10000000);
641 rk628_i2c_write(bt1120->rk628, GRF_BT1120_DCLK_DELAY_CON1, 0);
642 }
643
644 val |= BT1120_UV_SWAP(0);
645 rk628_i2c_write(bt1120->rk628, GRF_RGB_ENC_CON, val);
646 v4l2_dbg(1, debug, sd, "%s bt1120 cofig done\n", __func__);
647
648 avi_rdy = rk628_is_avi_ready(bt1120->rk628, bt1120->avi_rcv_rdy);
649
650 rk628_i2c_read(bt1120->rk628, HDMI_RX_PDEC_AVI_PB, &val);
651 video_fmt = (val & VIDEO_FORMAT_MASK) >> 5;
652 v4l2_dbg(1, debug, &bt1120->sd, "%s PDEC_AVI_PB:%#x, video format:%d\n",
653 __func__, val, video_fmt);
654 if (video_fmt) {
655 /* yuv data: cfg SW_YUV2VYU_SWP */
656 rk628_i2c_write(bt1120->rk628, GRF_CSC_CTRL_CON,
657 SW_YUV2VYU_SWP(1) |
658 SW_R2Y_EN(0));
659 } else {
660 /* rgb data: cfg SW_R2Y_EN */
661 rk628_i2c_write(bt1120->rk628, GRF_CSC_CTRL_CON,
662 SW_YUV2VYU_SWP(0) |
663 SW_R2Y_EN(1));
664 }
665
666 /* if avi packet is not stable, reset ctrl*/
667 if (!avi_rdy)
668 schedule_delayed_work(&bt1120->delayed_work_enable_hotplug, HZ / 20);
669 }
670
enable_stream(struct v4l2_subdev * sd,bool en)671 static void enable_stream(struct v4l2_subdev *sd, bool en)
672 {
673 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
674
675 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, en ? "en" : "dis");
676 if (en) {
677 rk628_hdmirx_vid_enable(sd, true);
678 enable_bt1120tx(sd);
679 } else {
680 rk628_i2c_write(bt1120->rk628, GRF_SCALER_CON0, SCL_EN(0));
681 rk628_hdmirx_vid_enable(sd, false);
682 }
683 }
684
rk628_post_process_setup(struct v4l2_subdev * sd)685 static void rk628_post_process_setup(struct v4l2_subdev *sd)
686 {
687 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
688 struct v4l2_bt_timings *bt = &bt1120->src_timings.bt;
689 struct v4l2_bt_timings *dst_bt = &bt1120->timings.bt;
690 struct videomode src, dst;
691 u64 dst_pclk;
692
693 src.hactive = bt->width;
694 src.hfront_porch = bt->hfrontporch;
695 src.hsync_len = bt->hsync;
696 src.hback_porch = bt->hbackporch;
697 src.vactive = bt->height;
698 src.vfront_porch = bt->vfrontporch;
699 src.vsync_len = bt->vsync;
700 src.vback_porch = bt->vbackporch;
701 src.pixelclock = bt->pixelclock;
702 src.flags = 0;
703 if (bt->interlaced == V4L2_DV_INTERLACED)
704 src.flags |= DISPLAY_FLAGS_INTERLACED;
705 if (!src.pixelclock) {
706 enable_stream(sd, false);
707 bt1120->nosignal = true;
708 schedule_delayed_work(&bt1120->delayed_work_enable_hotplug, HZ / 20);
709 return;
710 }
711
712 dst.hactive = dst_bt->width;
713 dst.hfront_porch = dst_bt->hfrontporch;
714 dst.hsync_len = dst_bt->hsync;
715 dst.hback_porch = dst_bt->hbackporch;
716 dst.vactive = dst_bt->height;
717 dst.vfront_porch = dst_bt->vfrontporch;
718 dst.vsync_len = dst_bt->vsync;
719 dst.vback_porch = dst_bt->vbackporch;
720 dst.pixelclock = dst_bt->pixelclock;
721
722 rk628_post_process_en(bt1120->rk628, &src, &dst, &dst_pclk);
723 dst_bt->pixelclock = dst_pclk;
724 }
725
rk628_hdmirx_phy_power_on(struct v4l2_subdev * sd)726 static int rk628_hdmirx_phy_power_on(struct v4l2_subdev *sd)
727 {
728 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
729 int ret, f;
730
731 /* Bit31 is used to distinguish HDMI cable mode and direct connection
732 * mode in the rk628_combrxphy driver.
733 * Bit31: 0 -direct connection mode;
734 * 1 -cable mode;
735 * The cable mode is to know the input clock frequency through cdr_mode
736 * in the rk628_combrxphy driver, and the cable mode supports up to
737 * 297M, so 297M is passed uniformly here.
738 */
739 f = 297000 | BIT(31);
740
741 if (bt1120->rxphy_pwron) {
742 v4l2_dbg(1, debug, sd, "rxphy already power on, power off!\n");
743 ret = rk628_rxphy_power_off(bt1120->rk628);
744 if (ret)
745 v4l2_err(sd, "hdmi rxphy power off failed!\n");
746 else
747 bt1120->rxphy_pwron = false;
748 usleep_range(100, 110);
749 }
750
751 if (bt1120->rxphy_pwron == false) {
752 rk628_hdmirx_ctrl_enable(sd, 0);
753 ret = rk628_rxphy_power_on(bt1120->rk628, f);
754 if (ret) {
755 bt1120->rxphy_pwron = false;
756 v4l2_err(sd, "hdmi rxphy power on failed\n");
757 } else {
758 bt1120->rxphy_pwron = true;
759 }
760 rk628_hdmirx_ctrl_enable(sd, 1);
761 msleep(100);
762 }
763
764 return ret;
765 }
766
rk628_hdmirx_phy_power_off(struct v4l2_subdev * sd)767 static int rk628_hdmirx_phy_power_off(struct v4l2_subdev *sd)
768 {
769 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
770
771 if (bt1120->rxphy_pwron) {
772 v4l2_dbg(1, debug, sd, "rxphy power off!\n");
773 rk628_rxphy_power_off(bt1120->rk628);
774 bt1120->rxphy_pwron = false;
775 }
776 usleep_range(100, 100);
777
778 return 0;
779 }
780
rk628_hdmirx_vid_enable(struct v4l2_subdev * sd,bool en)781 static void rk628_hdmirx_vid_enable(struct v4l2_subdev *sd, bool en)
782 {
783 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
784
785 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, en ? "en" : "dis");
786 if (en) {
787 if (!bt1120->i2s_enable_default)
788 rk628_hdmirx_audio_i2s_ctrl(bt1120->audio_info, true);
789 rk628_i2c_update_bits(bt1120->rk628, HDMI_RX_DMI_DISABLE_IF,
790 VID_ENABLE_MASK, VID_ENABLE(1));
791 } else {
792 if (!bt1120->i2s_enable_default)
793 rk628_hdmirx_audio_i2s_ctrl(bt1120->audio_info, false);
794 rk628_i2c_update_bits(bt1120->rk628, HDMI_RX_DMI_DISABLE_IF,
795 VID_ENABLE_MASK, VID_ENABLE(0));
796 }
797 }
798
rk628_hdmirx_controller_reset(struct v4l2_subdev * sd)799 static void rk628_hdmirx_controller_reset(struct v4l2_subdev *sd)
800 {
801 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
802
803 rk628_control_assert(bt1120->rk628, RGU_HDMIRX_PON);
804 udelay(10);
805 rk628_control_deassert(bt1120->rk628, RGU_HDMIRX_PON);
806 udelay(10);
807 rk628_i2c_write(bt1120->rk628, HDMI_RX_DMI_SW_RST, 0x000101ff);
808 rk628_i2c_write(bt1120->rk628, HDMI_RX_DMI_DISABLE_IF, 0x00000000);
809 rk628_i2c_write(bt1120->rk628, HDMI_RX_DMI_DISABLE_IF, 0x0000017f);
810 rk628_i2c_write(bt1120->rk628, HDMI_RX_DMI_DISABLE_IF, 0x0001017f);
811 }
812
rk628_rcv_supported_res(struct v4l2_subdev * sd,u32 width,u32 height)813 static bool rk628_rcv_supported_res(struct v4l2_subdev *sd, u32 width,
814 u32 height)
815 {
816 u32 i;
817
818 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
819 if ((supported_modes[i].width == width) &&
820 (supported_modes[i].height == height)) {
821 break;
822 }
823 }
824 if (i == ARRAY_SIZE(supported_modes)) {
825 v4l2_err(sd, "%s do not support res wxh: %dx%d\n", __func__,
826 width, height);
827 return false;
828 } else {
829 return true;
830 }
831 }
832
rk628_hdmirx_phy_setup(struct v4l2_subdev * sd)833 static int rk628_hdmirx_phy_setup(struct v4l2_subdev *sd)
834 {
835 u32 i, cnt, val;
836 u32 width, height, frame_width, frame_height, status;
837 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
838 int ret;
839
840 for (i = 0; i < RXPHY_CFG_MAX_TIMES; i++) {
841 ret = rk628_hdmirx_phy_power_on(sd);
842 if (ret < 0) {
843 msleep(50);
844 continue;
845 }
846 cnt = 0;
847
848 do {
849 cnt++;
850 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HACT_PX, &val);
851 width = val & 0xffff;
852 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VAL, &val);
853 height = val & 0xffff;
854 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HT1, &val);
855 frame_width = (val >> 16) & 0xffff;
856 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VTL, &val);
857 frame_height = val & 0xffff;
858 rk628_i2c_read(bt1120->rk628, HDMI_RX_SCDC_REGS1, &val);
859 status = val;
860 v4l2_dbg(1, debug, sd, "%s read wxh:%dx%d, total:%dx%d, SCDC_REGS1:%#x, cnt:%d\n",
861 __func__, width, height, frame_width, frame_height, status, cnt);
862
863 rk628_i2c_read(bt1120->rk628, HDMI_RX_PDEC_STS, &val);
864 if (val & DVI_DET)
865 dev_info(bt1120->dev, "DVI mode detected\n");
866
867 if (!tx_5v_power_present(sd)) {
868 v4l2_info(sd, "HDMI pull out, return!\n");
869 return -1;
870 }
871
872 if (cnt >= 15)
873 break;
874 } while (((status & 0xfff) != 0xf00) ||
875 (!rk628_rcv_supported_res(sd, width, height)));
876
877 if (((status & 0xfff) != 0xf00) ||
878 (!rk628_rcv_supported_res(sd, width, height))) {
879 v4l2_err(sd, "%s hdmi rxphy lock failed, retry:%d\n",
880 __func__, i);
881 continue;
882 } else {
883 break;
884 }
885 }
886
887 if (i == RXPHY_CFG_MAX_TIMES)
888 return -1;
889
890 return 0;
891 }
892
rk628_bt1120_initial_setup(struct v4l2_subdev * sd)893 static void rk628_bt1120_initial_setup(struct v4l2_subdev *sd)
894 {
895 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
896 struct v4l2_subdev_edid def_edid;
897
898 /* selete int io function */
899 rk628_i2c_write(bt1120->rk628, GRF_GPIO3AB_SEL_CON, 0x30002000);
900 rk628_i2c_write(bt1120->rk628, GRF_GPIO1AB_SEL_CON, HIWORD_UPDATE(0x7, 10, 8));
901 /* I2S_SCKM0 */
902 rk628_i2c_write(bt1120->rk628, GRF_GPIO0AB_SEL_CON, HIWORD_UPDATE(0x1, 2, 2));
903 /* I2SLR_M0 */
904 rk628_i2c_write(bt1120->rk628, GRF_GPIO0AB_SEL_CON, HIWORD_UPDATE(0x1, 3, 3));
905 /* I2SM0D0 */
906 rk628_i2c_write(bt1120->rk628, GRF_GPIO0AB_SEL_CON, HIWORD_UPDATE(0x1, 5, 4));
907 /* hdmirx int en */
908 rk628_i2c_write(bt1120->rk628, GRF_INTR0_EN, 0x01000100);
909
910 udelay(10);
911 rk628_control_assert(bt1120->rk628, RGU_HDMIRX);
912 rk628_control_assert(bt1120->rk628, RGU_HDMIRX_PON);
913 rk628_control_assert(bt1120->rk628, RGU_BT1120DEC);
914 udelay(10);
915 rk628_control_deassert(bt1120->rk628, RGU_HDMIRX);
916 rk628_control_deassert(bt1120->rk628, RGU_HDMIRX_PON);
917 rk628_control_deassert(bt1120->rk628, RGU_BT1120DEC);
918 udelay(10);
919
920 rk628_i2c_update_bits(bt1120->rk628, GRF_SYSTEM_CON0,
921 SW_BT_DATA_OEN_MASK |
922 SW_INPUT_MODE_MASK |
923 SW_OUTPUT_MODE_MASK |
924 SW_EFUSE_HDCP_EN_MASK |
925 SW_HSYNC_POL_MASK |
926 SW_VSYNC_POL_MASK,
927 SW_INPUT_MODE(INPUT_MODE_HDMI) |
928 SW_OUTPUT_MODE(OUTPUT_MODE_BT1120) |
929 SW_EFUSE_HDCP_EN(0) |
930 SW_HSYNC_POL(1) |
931 SW_VSYNC_POL(1));
932 rk628_hdmirx_controller_reset(sd);
933
934 def_edid.pad = 0;
935 def_edid.start_block = 0;
936 def_edid.blocks = 2;
937 def_edid.edid = edid_init_data;
938 rk628_bt1120_s_edid(sd, &def_edid);
939 rk628_hdmirx_set_hdcp(bt1120->rk628, &bt1120->hdcp, false);
940
941 if (tx_5v_power_present(sd))
942 schedule_delayed_work(&bt1120->delayed_work_enable_hotplug, 1000);
943 }
944
rk628_bt1120_format_change(struct v4l2_subdev * sd)945 static void rk628_bt1120_format_change(struct v4l2_subdev *sd)
946 {
947 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
948 struct v4l2_dv_timings timings;
949 const struct v4l2_event rk628_bt1120_ev_fmt = {
950 .type = V4L2_EVENT_SOURCE_CHANGE,
951 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
952 };
953
954 rk628_bt1120_get_detected_timings(sd, &timings);
955 if (!v4l2_match_dv_timings(&bt1120->timings, &timings, 0, false)) {
956 /* automatically set timing rather than set by userspace */
957 rk628_bt1120_s_dv_timings(sd, &timings);
958 v4l2_print_dv_timings(sd->name,
959 "rk628_bt1120_format_change: New format: ",
960 &timings, false);
961 }
962
963 if (sd->devnode)
964 v4l2_subdev_notify_event(sd, &rk628_bt1120_ev_fmt);
965 }
966
rk628_bt1120_enable_interrupts(struct v4l2_subdev * sd,bool en)967 static void rk628_bt1120_enable_interrupts(struct v4l2_subdev *sd, bool en)
968 {
969 u32 pdec_ien, md_ien;
970 u32 pdec_mask = 0, md_mask = 0;
971 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
972
973 pdec_mask |= AVI_RCV_ENSET;
974 md_mask = VACT_LIN_ENSET | HACT_PIX_ENSET | HS_CLK_ENSET |
975 DE_ACTIVITY_ENSET | VS_ACT_ENSET | HS_ACT_ENSET;
976 v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, en ? "en" : "dis");
977 /* clr irq */
978 rk628_i2c_write(bt1120->rk628, HDMI_RX_MD_ICLR, md_mask);
979 rk628_i2c_write(bt1120->rk628, HDMI_RX_PDEC_ICLR, pdec_mask);
980 if (en) {
981 rk628_i2c_write(bt1120->rk628, HDMI_RX_MD_IEN_SET, md_mask);
982 rk628_i2c_write(bt1120->rk628, HDMI_RX_PDEC_IEN_SET, pdec_mask);
983 bt1120->vid_ints_en = true;
984 } else {
985 rk628_i2c_write(bt1120->rk628, HDMI_RX_MD_IEN_CLR, md_mask);
986 rk628_i2c_write(bt1120->rk628, HDMI_RX_PDEC_IEN_CLR, pdec_mask);
987 rk628_i2c_write(bt1120->rk628, HDMI_RX_AUD_FIFO_IEN_CLR, 0x1f);
988 bt1120->vid_ints_en = false;
989 }
990 usleep_range(5000, 5000);
991 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_IEN, &md_ien);
992 rk628_i2c_read(bt1120->rk628, HDMI_RX_PDEC_IEN, &pdec_ien);
993 v4l2_dbg(1, debug, sd, "%s MD_IEN:%#x, PDEC_IEN:%#x\n", __func__, md_ien, pdec_ien);
994 }
995
rk628_bt1120_isr(struct v4l2_subdev * sd,u32 status,bool * handled)996 static int rk628_bt1120_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
997 {
998 u32 md_ints, pdec_ints, fifo_ints, hact, vact;
999 bool plugin;
1000 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1001 void *audio_info = bt1120->audio_info;
1002
1003 if (handled == NULL) {
1004 v4l2_err(sd, "handled NULL, err return!\n");
1005 return -EINVAL;
1006 }
1007 rk628_i2c_read(bt1120->rk628, HDMI_RX_PDEC_ISTS, &pdec_ints);
1008 if (rk628_audio_ctsnints_enabled(audio_info)) {
1009 if (pdec_ints & (ACR_N_CHG_ICLR | ACR_CTS_CHG_ICLR)) {
1010 rk628_csi_isr_ctsn(audio_info, pdec_ints);
1011 pdec_ints &= ~(ACR_CTS_CHG_ICLR | ACR_CTS_CHG_ICLR);
1012 *handled = true;
1013 }
1014 }
1015 if (rk628_audio_fifoints_enabled(audio_info)) {
1016 rk628_i2c_read(bt1120->rk628, HDMI_RX_AUD_FIFO_ISTS, &fifo_ints);
1017 if (fifo_ints & 0x18) {
1018 rk628_csi_isr_fifoints(audio_info, fifo_ints);
1019 *handled = true;
1020 }
1021 }
1022 if (bt1120->vid_ints_en) {
1023 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_ISTS, &md_ints);
1024 plugin = tx_5v_power_present(sd);
1025 v4l2_dbg(1, debug, sd, "%s: md_ints: %#x, pdec_ints:%#x, plugin: %d\n",
1026 __func__, md_ints, pdec_ints, plugin);
1027
1028 if ((md_ints & (VACT_LIN_ISTS | HACT_PIX_ISTS |
1029 HS_CLK_ISTS | DE_ACTIVITY_ISTS |
1030 VS_ACT_ISTS | HS_ACT_ISTS))
1031 && plugin) {
1032
1033 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_HACT_PX, &hact);
1034 rk628_i2c_read(bt1120->rk628, HDMI_RX_MD_VAL, &vact);
1035 v4l2_dbg(1, debug, sd, "%s: HACT:%#x, VACT:%#x\n",
1036 __func__, hact, vact);
1037
1038 rk628_bt1120_enable_interrupts(sd, false);
1039 enable_stream(sd, false);
1040 bt1120->nosignal = true;
1041 schedule_delayed_work(&bt1120->delayed_work_res_change, HZ / 2);
1042
1043 v4l2_dbg(1, debug, sd, "%s: hact/vact change, md_ints: %#x\n",
1044 __func__, (u32)(md_ints & (VACT_LIN_ISTS | HACT_PIX_ISTS)));
1045 *handled = true;
1046 }
1047
1048 if ((pdec_ints & AVI_RCV_ISTS) && plugin && !bt1120->avi_rcv_rdy) {
1049 v4l2_dbg(1, debug, sd, "%s: AVI RCV INT!\n", __func__);
1050 bt1120->avi_rcv_rdy = true;
1051 /* After get the AVI_RCV interrupt state, disable interrupt. */
1052 rk628_i2c_write(bt1120->rk628, HDMI_RX_PDEC_IEN_CLR, AVI_RCV_ISTS);
1053
1054 *handled = true;
1055 }
1056 }
1057 if (*handled != true)
1058 v4l2_dbg(1, debug, sd, "%s: unhandled interrupt!\n", __func__);
1059
1060 /* clear interrupts */
1061 rk628_i2c_write(bt1120->rk628, HDMI_RX_MD_ICLR, 0xffffffff);
1062 rk628_i2c_write(bt1120->rk628, HDMI_RX_PDEC_ICLR, 0xffffffff);
1063 rk628_i2c_write(bt1120->rk628, GRF_INTR0_CLR_EN, 0x01000100);
1064
1065 return 0;
1066 }
1067
rk628_bt1120_irq_handler(int irq,void * dev_id)1068 static irqreturn_t rk628_bt1120_irq_handler(int irq, void *dev_id)
1069 {
1070 struct rk628_bt1120 *bt1120 = dev_id;
1071 bool handled = false;
1072
1073 rk628_bt1120_isr(&bt1120->sd, 0, &handled);
1074
1075 return handled ? IRQ_HANDLED : IRQ_NONE;
1076 }
1077
rk628_bt1120_irq_poll_timer(struct timer_list * t)1078 static void rk628_bt1120_irq_poll_timer(struct timer_list *t)
1079 {
1080 struct rk628_bt1120 *bt1120 = from_timer(bt1120, t, timer);
1081
1082 schedule_work(&bt1120->work_i2c_poll);
1083 mod_timer(&bt1120->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
1084 }
1085
rk628_bt1120_work_i2c_poll(struct work_struct * work)1086 static void rk628_bt1120_work_i2c_poll(struct work_struct *work)
1087 {
1088 struct rk628_bt1120 *bt1120 = container_of(work, struct rk628_bt1120,
1089 work_i2c_poll);
1090 struct v4l2_subdev *sd = &bt1120->sd;
1091
1092 rk628_bt1120_format_change(sd);
1093 }
1094
rk628_bt1120_subscribe_event(struct v4l2_subdev * sd,struct v4l2_fh * fh,struct v4l2_event_subscription * sub)1095 static int rk628_bt1120_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
1096 struct v4l2_event_subscription *sub)
1097 {
1098 switch (sub->type) {
1099 case V4L2_EVENT_SOURCE_CHANGE:
1100 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
1101 case V4L2_EVENT_CTRL:
1102 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
1103 default:
1104 return -EINVAL;
1105 }
1106 }
1107
rk628_bt1120_g_input_status(struct v4l2_subdev * sd,u32 * status)1108 static int rk628_bt1120_g_input_status(struct v4l2_subdev *sd, u32 *status)
1109 {
1110 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1111 static u8 cnt;
1112
1113 *status = 0;
1114 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1115
1116 if (no_signal(sd) && tx_5v_power_present(sd)) {
1117 if (cnt++ >= 6) {
1118 cnt = 0;
1119 v4l2_info(sd, "no signal but 5v_det, recfg hdmirx!\n");
1120 schedule_delayed_work(&bt1120->delayed_work_enable_hotplug,
1121 HZ / 20);
1122 }
1123 } else {
1124 cnt = 0;
1125 }
1126
1127 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1128
1129 return 0;
1130 }
1131
rk628_bt1120_s_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1132 static int rk628_bt1120_s_dv_timings(struct v4l2_subdev *sd,
1133 struct v4l2_dv_timings *timings)
1134 {
1135 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1136
1137 if (!timings)
1138 return -EINVAL;
1139
1140 if (debug)
1141 v4l2_print_dv_timings(sd->name, "rk628_bt1120_s_dv_timings: ",
1142 timings, false);
1143
1144 if (v4l2_match_dv_timings(&bt1120->timings, timings, 0, false)) {
1145 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1146 return 0;
1147 }
1148
1149 if (!v4l2_valid_dv_timings(timings, &rk628_bt1120_timings_cap, NULL,
1150 NULL)) {
1151 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1152 return -ERANGE;
1153 }
1154
1155 bt1120->timings = *timings;
1156 enable_stream(sd, false);
1157
1158 return 0;
1159 }
1160
rk628_bt1120_g_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1161 static int rk628_bt1120_g_dv_timings(struct v4l2_subdev *sd,
1162 struct v4l2_dv_timings *timings)
1163 {
1164 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1165
1166 *timings = bt1120->timings;
1167
1168 return 0;
1169 }
1170
rk628_bt1120_enum_dv_timings(struct v4l2_subdev * sd,struct v4l2_enum_dv_timings * timings)1171 static int rk628_bt1120_enum_dv_timings(struct v4l2_subdev *sd,
1172 struct v4l2_enum_dv_timings *timings)
1173 {
1174 if (timings->pad != 0)
1175 return -EINVAL;
1176
1177 return v4l2_enum_dv_timings_cap(timings, &rk628_bt1120_timings_cap, NULL,
1178 NULL);
1179 }
1180
rk628_bt1120_query_dv_timings(struct v4l2_subdev * sd,struct v4l2_dv_timings * timings)1181 static int rk628_bt1120_query_dv_timings(struct v4l2_subdev *sd,
1182 struct v4l2_dv_timings *timings)
1183 {
1184 int ret;
1185
1186 ret = rk628_bt1120_get_detected_timings(sd, timings);
1187 if (ret)
1188 return ret;
1189
1190 if (debug)
1191 v4l2_print_dv_timings(sd->name, "rk628_bt1120_query_dv_timings: ",
1192 timings, false);
1193
1194 if (!v4l2_valid_dv_timings(timings, &rk628_bt1120_timings_cap, NULL,
1195 NULL)) {
1196 v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
1197 return -ERANGE;
1198 }
1199
1200 return 0;
1201 }
1202
rk628_bt1120_dv_timings_cap(struct v4l2_subdev * sd,struct v4l2_dv_timings_cap * cap)1203 static int rk628_bt1120_dv_timings_cap(struct v4l2_subdev *sd,
1204 struct v4l2_dv_timings_cap *cap)
1205 {
1206 if (cap->pad != 0)
1207 return -EINVAL;
1208
1209 *cap = rk628_bt1120_timings_cap;
1210
1211 return 0;
1212 }
1213
rk628_bt1120_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)1214 static int rk628_bt1120_g_mbus_config(struct v4l2_subdev *sd,
1215 unsigned int pad,
1216 struct v4l2_mbus_config *cfg)
1217 {
1218 cfg->type = V4L2_MBUS_BT656;
1219 cfg->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1220 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1221 V4L2_MBUS_PCLK_SAMPLE_RISING;
1222
1223 return 0;
1224 }
1225
rk628_bt1120_s_stream(struct v4l2_subdev * sd,int enable)1226 static int rk628_bt1120_s_stream(struct v4l2_subdev *sd, int enable)
1227 {
1228 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1229
1230 mutex_lock(&bt1120->confctl_mutex);
1231 enable_stream(sd, enable);
1232 mutex_unlock(&bt1120->confctl_mutex);
1233
1234 return 0;
1235 }
1236
rk628_bt1120_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1237 static int rk628_bt1120_enum_mbus_code(struct v4l2_subdev *sd,
1238 struct v4l2_subdev_pad_config *cfg,
1239 struct v4l2_subdev_mbus_code_enum *code)
1240 {
1241 switch (code->index) {
1242 case 0:
1243 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
1244 break;
1245
1246 default:
1247 return -EINVAL;
1248 }
1249
1250 return 0;
1251 }
1252
rk628_bt1120_get_ctrl(struct v4l2_ctrl * ctrl)1253 static int rk628_bt1120_get_ctrl(struct v4l2_ctrl *ctrl)
1254 {
1255 int ret = -1;
1256 struct rk628_bt1120 *bt1120 = container_of(ctrl->handler, struct rk628_bt1120,
1257 hdl);
1258 struct v4l2_subdev *sd = &(bt1120->sd);
1259
1260 if (ctrl->id == V4L2_CID_DV_RX_POWER_PRESENT) {
1261 ret = tx_5v_power_present(sd);
1262 *ctrl->p_new.p_s32 = ret;
1263 }
1264
1265 return ret;
1266 }
1267
rk628_bt1120_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1268 static int rk628_bt1120_enum_frame_sizes(struct v4l2_subdev *sd,
1269 struct v4l2_subdev_pad_config *cfg,
1270 struct v4l2_subdev_frame_size_enum *fse)
1271 {
1272 if (fse->index >= ARRAY_SIZE(supported_modes))
1273 return -EINVAL;
1274
1275 if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
1276 return -EINVAL;
1277
1278 fse->min_width = supported_modes[fse->index].width;
1279 fse->max_width = supported_modes[fse->index].width;
1280 fse->max_height = supported_modes[fse->index].height;
1281 fse->min_height = supported_modes[fse->index].height;
1282
1283 return 0;
1284 }
1285
rk628_bt1120_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1286 static int rk628_bt1120_enum_frame_interval(struct v4l2_subdev *sd,
1287 struct v4l2_subdev_pad_config *cfg,
1288 struct v4l2_subdev_frame_interval_enum *fie)
1289 {
1290 if (fie->index >= ARRAY_SIZE(supported_modes))
1291 return -EINVAL;
1292
1293 fie->code = MEDIA_BUS_FMT_UYVY8_2X8;
1294
1295 fie->width = supported_modes[fie->index].width;
1296 fie->height = supported_modes[fie->index].height;
1297 fie->interval = supported_modes[fie->index].max_fps;
1298 return 0;
1299 }
1300
rk628_bt1120_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1301 static int rk628_bt1120_get_fmt(struct v4l2_subdev *sd,
1302 struct v4l2_subdev_pad_config *cfg,
1303 struct v4l2_subdev_format *format)
1304 {
1305 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1306
1307 mutex_lock(&bt1120->confctl_mutex);
1308 format->format.code = bt1120->mbus_fmt_code;
1309 format->format.width = bt1120->timings.bt.width;
1310 format->format.height = bt1120->timings.bt.height;
1311 format->format.field = bt1120->timings.bt.interlaced ?
1312 V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
1313 mutex_unlock(&bt1120->confctl_mutex);
1314
1315 v4l2_dbg(1, debug, sd, "%s: fmt code:%d, w:%d, h:%d, field code:%d\n",
1316 __func__, format->format.code, format->format.width,
1317 format->format.height, format->format.field);
1318
1319 return 0;
1320 }
1321
rk628_bt1120_get_reso_dist(const struct rk628_bt1120_mode * mode,struct v4l2_mbus_framefmt * framefmt)1322 static int rk628_bt1120_get_reso_dist(const struct rk628_bt1120_mode *mode,
1323 struct v4l2_mbus_framefmt *framefmt)
1324 {
1325 return abs(mode->width - framefmt->width) +
1326 abs(mode->height - framefmt->height);
1327 }
1328
1329 static const struct rk628_bt1120_mode *
rk628_bt1120_find_best_fit(struct v4l2_subdev_format * fmt)1330 rk628_bt1120_find_best_fit(struct v4l2_subdev_format *fmt)
1331 {
1332 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
1333 int dist;
1334 int cur_best_fit = 0;
1335 int cur_best_fit_dist = -1;
1336 unsigned int i;
1337
1338 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1339 dist = rk628_bt1120_get_reso_dist(&supported_modes[i], framefmt);
1340 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
1341 cur_best_fit_dist = dist;
1342 cur_best_fit = i;
1343 }
1344 }
1345
1346 return &supported_modes[cur_best_fit];
1347 }
1348
rk628_bt1120_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)1349 static int rk628_bt1120_set_fmt(struct v4l2_subdev *sd,
1350 struct v4l2_subdev_pad_config *cfg,
1351 struct v4l2_subdev_format *format)
1352 {
1353 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1354 const struct rk628_bt1120_mode *mode;
1355
1356 u32 code = format->format.code; /* is overwritten by get_fmt */
1357 int ret = rk628_bt1120_get_fmt(sd, cfg, format);
1358
1359 format->format.code = code;
1360
1361 if (ret)
1362 return ret;
1363
1364 switch (code) {
1365 case MEDIA_BUS_FMT_UYVY8_2X8:
1366 break;
1367 default:
1368 return -EINVAL;
1369 }
1370
1371 if (format->which == V4L2_SUBDEV_FORMAT_TRY)
1372 return 0;
1373
1374 bt1120->mbus_fmt_code = format->format.code;
1375 mode = rk628_bt1120_find_best_fit(format);
1376 bt1120->cur_mode = mode;
1377
1378 v4l2_dbg(1, debug, sd,
1379 "%s res wxh:%dx%d, link freq:%llu, pixrate:%u\n",
1380 __func__, mode->width, mode->height,
1381 link_freq_menu_items[0], RK628_CSI_PIXEL_RATE_LOW);
1382 __v4l2_ctrl_s_ctrl(bt1120->link_freq, 0);
1383 __v4l2_ctrl_s_ctrl_int64(bt1120->pixel_rate,
1384 RK628_CSI_PIXEL_RATE_LOW);
1385
1386 mutex_lock(&bt1120->confctl_mutex);
1387 enable_stream(sd, false);
1388 mutex_unlock(&bt1120->confctl_mutex);
1389
1390 return 0;
1391 }
1392
rk628_bt1120_g_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1393 static int rk628_bt1120_g_edid(struct v4l2_subdev *sd,
1394 struct v4l2_subdev_edid *edid)
1395 {
1396 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1397 u32 i, val;
1398
1399 memset(edid->reserved, 0, sizeof(edid->reserved));
1400
1401 if (edid->pad != 0)
1402 return -EINVAL;
1403
1404 if (edid->start_block == 0 && edid->blocks == 0) {
1405 edid->blocks = bt1120->edid_blocks_written;
1406 return 0;
1407 }
1408
1409 if (bt1120->edid_blocks_written == 0)
1410 return -ENODATA;
1411
1412 if (edid->start_block >= bt1120->edid_blocks_written ||
1413 edid->blocks == 0)
1414 return -EINVAL;
1415
1416 if (edid->start_block + edid->blocks > bt1120->edid_blocks_written)
1417 edid->blocks = bt1120->edid_blocks_written - edid->start_block;
1418
1419 /* edid access by apb when read, i2c slave addr: 0x0 */
1420 rk628_i2c_update_bits(bt1120->rk628, GRF_SYSTEM_CON0,
1421 SW_ADAPTER_I2CSLADR_MASK |
1422 SW_EDID_MODE_MASK,
1423 SW_ADAPTER_I2CSLADR(0) |
1424 SW_EDID_MODE(1));
1425
1426 for (i = 0; i < (edid->blocks * EDID_BLOCK_SIZE); i++) {
1427 rk628_i2c_read(bt1120->rk628, EDID_BASE + ((edid->start_block *
1428 EDID_BLOCK_SIZE) + i) * 4, &val);
1429 edid->edid[i] = val;
1430 }
1431
1432 rk628_i2c_update_bits(bt1120->rk628, GRF_SYSTEM_CON0,
1433 SW_EDID_MODE_MASK,
1434 SW_EDID_MODE(0));
1435
1436 return 0;
1437 }
1438
rk628_bt1120_s_edid(struct v4l2_subdev * sd,struct v4l2_subdev_edid * edid)1439 static int rk628_bt1120_s_edid(struct v4l2_subdev *sd,
1440 struct v4l2_subdev_edid *edid)
1441 {
1442 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1443 u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
1444 u32 i, val;
1445
1446 v4l2_dbg(1, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
1447 __func__, edid->pad, edid->start_block, edid->blocks);
1448
1449 memset(edid->reserved, 0, sizeof(edid->reserved));
1450
1451 if (edid->pad != 0)
1452 return -EINVAL;
1453
1454 if (edid->start_block != 0)
1455 return -EINVAL;
1456
1457 if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
1458 edid->blocks = EDID_NUM_BLOCKS_MAX;
1459 return -E2BIG;
1460 }
1461
1462 rk628_hdmirx_hpd_ctrl(sd, false);
1463
1464 if (edid->blocks == 0) {
1465 bt1120->edid_blocks_written = 0;
1466 return 0;
1467 }
1468
1469 /* edid access by apb when write, i2c slave addr: 0x0 */
1470 rk628_i2c_update_bits(bt1120->rk628, GRF_SYSTEM_CON0,
1471 SW_ADAPTER_I2CSLADR_MASK |
1472 SW_EDID_MODE_MASK,
1473 SW_ADAPTER_I2CSLADR(0) |
1474 SW_EDID_MODE(1));
1475
1476 for (i = 0; i < edid_len; i++)
1477 rk628_i2c_write(bt1120->rk628, EDID_BASE + i * 4, edid->edid[i]);
1478
1479 /* read out for debug */
1480 if (debug >= 3) {
1481 pr_info("%s: Read EDID: ======\n", __func__);
1482 for (i = 0; i < edid_len; i++) {
1483 rk628_i2c_read(bt1120->rk628, EDID_BASE + i * 4, &val);
1484 pr_info("0x%02x ", val);
1485 if ((i + 1) % 8 == 0)
1486 pr_info("\n");
1487 }
1488 pr_info("%s: ======\n", __func__);
1489 }
1490
1491 /* edid access by RX's i2c, i2c slave addr: 0x0 */
1492 rk628_i2c_update_bits(bt1120->rk628, GRF_SYSTEM_CON0,
1493 SW_ADAPTER_I2CSLADR_MASK |
1494 SW_EDID_MODE_MASK,
1495 SW_ADAPTER_I2CSLADR(0) |
1496 SW_EDID_MODE(0));
1497 bt1120->edid_blocks_written = edid->blocks;
1498 udelay(100);
1499
1500 if (tx_5v_power_present(sd))
1501 rk628_hdmirx_hpd_ctrl(sd, true);
1502
1503 return 0;
1504 }
1505
rk628_bt1120_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1506 static int rk628_bt1120_g_frame_interval(struct v4l2_subdev *sd,
1507 struct v4l2_subdev_frame_interval *fi)
1508 {
1509 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1510 const struct rk628_bt1120_mode *mode = bt1120->cur_mode;
1511
1512 mutex_lock(&bt1120->confctl_mutex);
1513 fi->interval = mode->max_fps;
1514 mutex_unlock(&bt1120->confctl_mutex);
1515
1516 return 0;
1517 }
1518
rk628_bt1120_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)1519 static int rk628_bt1120_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
1520 {
1521 *std = V4L2_STD_ATSC;
1522
1523 return 0;
1524 }
1525
rk628_bt1120_get_module_inf(struct rk628_bt1120 * rk628_bt1120,struct rkmodule_inf * inf)1526 static void rk628_bt1120_get_module_inf(struct rk628_bt1120 *rk628_bt1120,
1527 struct rkmodule_inf *inf)
1528 {
1529 memset(inf, 0, sizeof(*inf));
1530 strscpy(inf->base.sensor, RK628_BT1120_NAME, sizeof(inf->base.sensor));
1531 strscpy(inf->base.module, rk628_bt1120->module_name,
1532 sizeof(inf->base.module));
1533 strscpy(inf->base.lens, rk628_bt1120->len_name, sizeof(inf->base.lens));
1534 }
1535
rk628_bt1120_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1536 static long rk628_bt1120_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1537 {
1538 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1539 long ret = 0;
1540
1541 switch (cmd) {
1542 case RKMODULE_GET_MODULE_INFO:
1543 rk628_bt1120_get_module_inf(bt1120, (struct rkmodule_inf *)arg);
1544 break;
1545 default:
1546 ret = -ENOIOCTLCMD;
1547 break;
1548 }
1549
1550 return ret;
1551 }
1552
1553 #ifdef CONFIG_COMPAT
rk628_bt1120_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1554 static long rk628_bt1120_compat_ioctl32(struct v4l2_subdev *sd,
1555 unsigned int cmd, unsigned long arg)
1556 {
1557 void __user *up = compat_ptr(arg);
1558 struct rkmodule_inf *inf;
1559 long ret;
1560
1561 switch (cmd) {
1562 case RKMODULE_GET_MODULE_INFO:
1563 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1564 if (!inf) {
1565 ret = -ENOMEM;
1566 return ret;
1567 }
1568
1569 ret = rk628_bt1120_ioctl(sd, cmd, inf);
1570 if (!ret) {
1571 ret = copy_to_user(up, inf, sizeof(*inf));
1572 if (ret)
1573 ret = -EFAULT;
1574 }
1575 kfree(inf);
1576 break;
1577
1578 default:
1579 ret = -ENOIOCTLCMD;
1580 break;
1581 }
1582
1583 return ret;
1584 }
1585 #endif
1586
1587 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
bt1120_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1588 static int bt1120_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1589 {
1590 struct rk628_bt1120 *bt1120 = to_bt1120(sd);
1591 struct v4l2_bt_timings *bt = &(bt1120->timings.bt);
1592 struct v4l2_mbus_framefmt *try_fmt =
1593 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1594 const struct rk628_bt1120_mode *def_mode = &supported_modes[0];
1595
1596 mutex_lock(&bt1120->confctl_mutex);
1597 /* Initialize try_fmt */
1598 try_fmt->width = def_mode->width;
1599 try_fmt->height = def_mode->height;
1600 try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
1601 if (bt->interlaced == V4L2_DV_INTERLACED)
1602 try_fmt->field = V4L2_FIELD_INTERLACED;
1603 else
1604 try_fmt->field = V4L2_FIELD_NONE;
1605 mutex_unlock(&bt1120->confctl_mutex);
1606
1607 return 0;
1608 }
1609
1610 static const struct v4l2_subdev_internal_ops bt1120_subdev_internal_ops = {
1611 .open = bt1120_open,
1612 };
1613 #endif
1614
1615 static const struct v4l2_ctrl_ops rk628_bt1120_ctrl_ops = {
1616 .g_volatile_ctrl = rk628_bt1120_get_ctrl,
1617 };
1618
1619 static const struct v4l2_subdev_core_ops rk628_bt1120_core_ops = {
1620 .interrupt_service_routine = rk628_bt1120_isr,
1621 .subscribe_event = rk628_bt1120_subscribe_event,
1622 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1623 .ioctl = rk628_bt1120_ioctl,
1624 #ifdef CONFIG_COMPAT
1625 .compat_ioctl32 = rk628_bt1120_compat_ioctl32,
1626 #endif
1627 };
1628
1629 static const struct v4l2_subdev_video_ops rk628_bt1120_video_ops = {
1630 .g_input_status = rk628_bt1120_g_input_status,
1631 .s_dv_timings = rk628_bt1120_s_dv_timings,
1632 .g_dv_timings = rk628_bt1120_g_dv_timings,
1633 .query_dv_timings = rk628_bt1120_query_dv_timings,
1634 .s_stream = rk628_bt1120_s_stream,
1635 .g_frame_interval = rk628_bt1120_g_frame_interval,
1636 .querystd = rk628_bt1120_querystd,
1637 };
1638
1639 static const struct v4l2_subdev_pad_ops rk628_bt1120_pad_ops = {
1640 .enum_mbus_code = rk628_bt1120_enum_mbus_code,
1641 .enum_frame_size = rk628_bt1120_enum_frame_sizes,
1642 .enum_frame_interval = rk628_bt1120_enum_frame_interval,
1643 .set_fmt = rk628_bt1120_set_fmt,
1644 .get_fmt = rk628_bt1120_get_fmt,
1645 .get_edid = rk628_bt1120_g_edid,
1646 .set_edid = rk628_bt1120_s_edid,
1647 .enum_dv_timings = rk628_bt1120_enum_dv_timings,
1648 .dv_timings_cap = rk628_bt1120_dv_timings_cap,
1649 .get_mbus_config = rk628_bt1120_g_mbus_config,
1650 };
1651
1652 static const struct v4l2_subdev_ops rk628_bt1120_ops = {
1653 .core = &rk628_bt1120_core_ops,
1654 .video = &rk628_bt1120_video_ops,
1655 .pad = &rk628_bt1120_pad_ops,
1656 };
1657
1658 static const struct v4l2_ctrl_config rk628_bt1120_ctrl_audio_sampling_rate = {
1659 .id = RK_V4L2_CID_AUDIO_SAMPLING_RATE,
1660 .name = "Audio sampling rate",
1661 .type = V4L2_CTRL_TYPE_INTEGER,
1662 .min = 0,
1663 .max = 768000,
1664 .step = 1,
1665 .def = 0,
1666 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1667 };
1668
1669 static const struct v4l2_ctrl_config rk628_bt1120_ctrl_audio_present = {
1670 .id = RK_V4L2_CID_AUDIO_PRESENT,
1671 .name = "Audio present",
1672 .type = V4L2_CTRL_TYPE_BOOLEAN,
1673 .min = 0,
1674 .max = 1,
1675 .step = 1,
1676 .def = 0,
1677 .flags = V4L2_CTRL_FLAG_READ_ONLY,
1678 };
1679
plugin_detect_irq(int irq,void * dev_id)1680 static irqreturn_t plugin_detect_irq(int irq, void *dev_id)
1681 {
1682 struct rk628_bt1120 *bt1120 = dev_id;
1683 struct v4l2_subdev *sd = &bt1120->sd;
1684
1685 /* control hpd after 50ms */
1686 schedule_delayed_work(&bt1120->delayed_work_enable_hotplug, HZ / 20);
1687 tx_5v_power_present(sd);
1688
1689 return IRQ_HANDLED;
1690 }
1691
rk628_bt1120_probe_of(struct rk628_bt1120 * bt1120)1692 static int rk628_bt1120_probe_of(struct rk628_bt1120 *bt1120)
1693 {
1694 struct device *dev = bt1120->dev;
1695 struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
1696 struct device_node *ep;
1697 int ret = -EINVAL;
1698 bool hdcp1x_enable = false, i2s_enable_default = false;
1699 bool scaler_en = false;
1700
1701 bt1120->soc_24M = devm_clk_get(dev, "soc_24M");
1702 if (bt1120->soc_24M == ERR_PTR(-ENOENT))
1703 bt1120->soc_24M = NULL;
1704 if (IS_ERR(bt1120->soc_24M)) {
1705 ret = PTR_ERR(bt1120->soc_24M);
1706 dev_err(dev, "Unable to get soc_24M: %d\n", ret);
1707 }
1708 clk_prepare_enable(bt1120->soc_24M);
1709
1710 bt1120->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1711 GPIOD_OUT_LOW);
1712 if (IS_ERR(bt1120->enable_gpio)) {
1713 ret = PTR_ERR(bt1120->enable_gpio);
1714 dev_err(dev, "failed to request enable GPIO: %d\n", ret);
1715 return ret;
1716 }
1717
1718 bt1120->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1719 if (IS_ERR(bt1120->reset_gpio)) {
1720 ret = PTR_ERR(bt1120->reset_gpio);
1721 dev_err(dev, "failed to request reset GPIO: %d\n", ret);
1722 return ret;
1723 }
1724
1725 bt1120->power_gpio = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_HIGH);
1726 if (IS_ERR(bt1120->power_gpio)) {
1727 dev_err(dev, "failed to get power gpio\n");
1728 ret = PTR_ERR(bt1120->power_gpio);
1729 return ret;
1730 }
1731
1732 bt1120->plugin_det_gpio = devm_gpiod_get_optional(dev, "plugin-det",
1733 GPIOD_IN);
1734 if (IS_ERR(bt1120->plugin_det_gpio)) {
1735 dev_err(dev, "failed to get hdmirx det gpio\n");
1736 ret = PTR_ERR(bt1120->plugin_det_gpio);
1737 return ret;
1738 }
1739
1740 if (bt1120->enable_gpio) {
1741 gpiod_set_value(bt1120->enable_gpio, 1);
1742 usleep_range(10000, 11000);
1743 }
1744 gpiod_set_value(bt1120->reset_gpio, 0);
1745 usleep_range(10000, 11000);
1746 gpiod_set_value(bt1120->reset_gpio, 1);
1747 usleep_range(10000, 11000);
1748 gpiod_set_value(bt1120->reset_gpio, 0);
1749 usleep_range(10000, 11000);
1750
1751 if (bt1120->power_gpio) {
1752 gpiod_set_value(bt1120->power_gpio, 1);
1753 usleep_range(500, 510);
1754 }
1755
1756 if (of_property_read_bool(dev->of_node, "hdcp-enable"))
1757 hdcp1x_enable = true;
1758
1759 if (of_property_read_bool(dev->of_node, "i2s-enable-default"))
1760 i2s_enable_default = true;
1761
1762 if (of_property_read_bool(dev->of_node, "scaler-en"))
1763 scaler_en = true;
1764
1765 if (of_property_read_bool(dev->of_node, "dual-edge"))
1766 bt1120->dual_edge = true;
1767
1768 ep = of_graph_get_next_endpoint(dev->of_node, NULL);
1769 if (!ep) {
1770 dev_err(dev, "missing endpoint node\n");
1771 return -EINVAL;
1772 }
1773
1774 ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
1775 if (ret) {
1776 dev_err(dev, "failed to parse endpoint\n");
1777 of_node_put(ep);
1778 return ret;
1779 }
1780
1781 bt1120->enable_hdcp = hdcp1x_enable;
1782 bt1120->i2s_enable_default = i2s_enable_default;
1783 bt1120->scaler_en = scaler_en;
1784 if (bt1120->scaler_en)
1785 bt1120->timings = dst_timing;
1786 bt1120->rxphy_pwron = false;
1787 bt1120->nosignal = true;
1788 bt1120->stream_state = 0;
1789 bt1120->avi_rcv_rdy = false;
1790
1791 ret = 0;
1792
1793 v4l2_fwnode_endpoint_free(&endpoint);
1794
1795 return ret;
1796 }
1797
rk628_bt1120_probe(struct i2c_client * client,const struct i2c_device_id * id)1798 static int rk628_bt1120_probe(struct i2c_client *client,
1799 const struct i2c_device_id *id)
1800 {
1801 struct rk628_bt1120 *bt1120;
1802 struct v4l2_subdev *sd;
1803 struct device *dev = &client->dev;
1804 struct device_node *node = dev->of_node;
1805 char facing[2];
1806 int err;
1807 struct rk628 *rk628;
1808 unsigned long irq_flags;
1809
1810 dev_info(dev, "RK628 I2C driver version: %02x.%02x.%02x",
1811 DRIVER_VERSION >> 16,
1812 (DRIVER_VERSION & 0xff00) >> 8,
1813 DRIVER_VERSION & 0x00ff);
1814
1815 if (!of_device_is_available(dev->of_node))
1816 return -ENODEV;
1817
1818 bt1120 = devm_kzalloc(dev, sizeof(*bt1120), GFP_KERNEL);
1819 if (!bt1120)
1820 return -ENOMEM;
1821
1822 bt1120->dev = dev;
1823 bt1120->i2c_client = client;
1824 rk628 = rk628_i2c_register(client);
1825 if (!rk628)
1826 return -ENOMEM;
1827 bt1120->rk628 = rk628;
1828 bt1120->cur_mode = &supported_modes[0];
1829 bt1120->hdmirx_irq = client->irq;
1830 sd = &bt1120->sd;
1831 sd->dev = dev;
1832
1833 bt1120->hpd_output_inverted = of_property_read_bool(node,
1834 "hpd-output-inverted");
1835 err = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1836 &bt1120->module_index);
1837 err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1838 &bt1120->module_facing);
1839 err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1840 &bt1120->module_name);
1841 err |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1842 &bt1120->len_name);
1843 if (err) {
1844 dev_err(dev, "could not get module information!\n");
1845 return -EINVAL;
1846 }
1847
1848 err = rk628_bt1120_probe_of(bt1120);
1849 if (err) {
1850 v4l2_err(sd, "rk628_bt1120_probe_of failed! err:%d\n", err);
1851 return err;
1852 }
1853
1854 rk628_cru_initialize(rk628);
1855
1856 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1857 v4l2_i2c_subdev_init(sd, client, &rk628_bt1120_ops);
1858 sd->internal_ops = &bt1120_subdev_internal_ops;
1859 #endif
1860
1861 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
1862
1863 mutex_init(&bt1120->confctl_mutex);
1864
1865 /* control handlers */
1866 v4l2_ctrl_handler_init(&bt1120->hdl, 2);
1867 bt1120->link_freq = v4l2_ctrl_new_int_menu(&bt1120->hdl, NULL,
1868 V4L2_CID_LINK_FREQ,
1869 ARRAY_SIZE(link_freq_menu_items) - 1,
1870 0, link_freq_menu_items);
1871 bt1120->pixel_rate = v4l2_ctrl_new_std(&bt1120->hdl, NULL,
1872 V4L2_CID_PIXEL_RATE, 0, RK628_CSI_PIXEL_RATE_HIGH, 1,
1873 RK628_CSI_PIXEL_RATE_HIGH);
1874 bt1120->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&bt1120->hdl,
1875 &rk628_bt1120_ctrl_ops, V4L2_CID_DV_RX_POWER_PRESENT,
1876 0, 1, 0, 0);
1877 if (bt1120->detect_tx_5v_ctrl)
1878 bt1120->detect_tx_5v_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
1879
1880 /* custom controls */
1881 bt1120->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&bt1120->hdl,
1882 &rk628_bt1120_ctrl_audio_sampling_rate, NULL);
1883 bt1120->audio_present_ctrl = v4l2_ctrl_new_custom(&bt1120->hdl,
1884 &rk628_bt1120_ctrl_audio_present, NULL);
1885
1886 sd->ctrl_handler = &bt1120->hdl;
1887 if (bt1120->hdl.error) {
1888 err = bt1120->hdl.error;
1889 v4l2_err(sd, "cfg v4l2 ctrls failed! err:%d\n", err);
1890 goto err_hdl;
1891 }
1892
1893 if (rk628_bt1120_update_controls(sd)) {
1894 err = -ENODEV;
1895 v4l2_err(sd, "update v4l2 ctrls failed! err:%d\n", err);
1896 goto err_hdl;
1897 }
1898
1899 bt1120->pad.flags = MEDIA_PAD_FL_SOURCE;
1900 #if defined(CONFIG_MEDIA_CONTROLLER)
1901 bt1120->pad.flags = MEDIA_PAD_FL_SOURCE;
1902 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1903 err = media_entity_pads_init(&sd->entity, 1, &bt1120->pad);
1904 #endif
1905
1906 if (err < 0) {
1907 v4l2_err(sd, "media entity init failed! err:%d\n", err);
1908 goto err_hdl;
1909 }
1910
1911 bt1120->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
1912
1913 memset(facing, 0, sizeof(facing));
1914 if (strcmp(bt1120->module_facing, "back") == 0)
1915 facing[0] = 'b';
1916 else
1917 facing[0] = 'f';
1918
1919 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1920 bt1120->module_index, facing,
1921 RK628_BT1120_NAME, dev_name(sd->dev));
1922 err = v4l2_async_register_subdev(sd);
1923 if (err < 0) {
1924 v4l2_err(sd, "v4l2 register subdev failed! err:%d\n", err);
1925 goto err_hdl;
1926 }
1927
1928 INIT_DELAYED_WORK(&bt1120->delayed_work_enable_hotplug,
1929 rk628_bt1120_delayed_work_enable_hotplug);
1930 INIT_DELAYED_WORK(&bt1120->delayed_work_res_change,
1931 rk628_delayed_work_res_change);
1932 bt1120->audio_info = rk628_hdmirx_audioinfo_alloc(dev,
1933 &bt1120->confctl_mutex,
1934 rk628,
1935 bt1120->i2s_enable_default);
1936 if (!bt1120->audio_info) {
1937 v4l2_err(sd, "request audio info fail\n");
1938 goto err_work_queues;
1939 }
1940 rk628_bt1120_initial_setup(sd);
1941
1942 if (bt1120->hdmirx_irq) {
1943 irq_flags = irqd_get_trigger_type(irq_get_irq_data(bt1120->hdmirx_irq));
1944 v4l2_dbg(1, debug, sd, "cfg hdmirx irq, flags: %lu!\n", irq_flags);
1945 err = devm_request_threaded_irq(dev, bt1120->hdmirx_irq, NULL,
1946 rk628_bt1120_irq_handler, irq_flags |
1947 IRQF_ONESHOT, "rk628_bt1120", bt1120);
1948 if (err) {
1949 v4l2_err(sd, "request rk628-bt1120 irq failed! err:%d\n",
1950 err);
1951 goto err_work_queues;
1952 }
1953 } else {
1954 v4l2_dbg(1, debug, sd, "no irq, cfg poll!\n");
1955 INIT_WORK(&bt1120->work_i2c_poll,
1956 rk628_bt1120_work_i2c_poll);
1957 timer_setup(&bt1120->timer, rk628_bt1120_irq_poll_timer, 0);
1958 bt1120->timer.expires = jiffies +
1959 msecs_to_jiffies(POLL_INTERVAL_MS);
1960 add_timer(&bt1120->timer);
1961 }
1962
1963 if (bt1120->plugin_det_gpio) {
1964 bt1120->plugin_irq = gpiod_to_irq(bt1120->plugin_det_gpio);
1965 if (bt1120->plugin_irq < 0) {
1966 dev_err(bt1120->dev, "failed to get plugin det irq\n");
1967 err = bt1120->plugin_irq;
1968 goto err_work_queues;
1969 }
1970
1971 err = devm_request_threaded_irq(dev, bt1120->plugin_irq, NULL,
1972 plugin_detect_irq, IRQF_TRIGGER_FALLING |
1973 IRQF_TRIGGER_RISING | IRQF_ONESHOT, "rk628_bt1120", bt1120);
1974 if (err) {
1975 dev_err(bt1120->dev, "failed to register plugin det irq (%d)\n", err);
1976 goto err_work_queues;
1977 }
1978 }
1979
1980 err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
1981 if (err) {
1982 v4l2_err(sd, "v4l2 ctrl handler setup failed! err:%d\n", err);
1983 goto err_work_queues;
1984 }
1985
1986 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1987 client->addr << 1, client->adapter->name);
1988
1989 return 0;
1990
1991 err_work_queues:
1992 if (!bt1120->hdmirx_irq)
1993 flush_work(&bt1120->work_i2c_poll);
1994 cancel_delayed_work(&bt1120->delayed_work_enable_hotplug);
1995 cancel_delayed_work(&bt1120->delayed_work_res_change);
1996 rk628_hdmirx_audio_destroy(bt1120->audio_info);
1997 err_hdl:
1998 mutex_destroy(&bt1120->confctl_mutex);
1999 media_entity_cleanup(&sd->entity);
2000 v4l2_ctrl_handler_free(&bt1120->hdl);
2001 return err;
2002 }
2003
rk628_bt1120_remove(struct i2c_client * client)2004 static int rk628_bt1120_remove(struct i2c_client *client)
2005 {
2006 struct rk628_bt1120 *bt1120 = i2c_get_clientdata(client);
2007
2008 if (!bt1120->hdmirx_irq) {
2009 del_timer_sync(&bt1120->timer);
2010 flush_work(&bt1120->work_i2c_poll);
2011 }
2012 cancel_delayed_work_sync(&bt1120->delayed_work_enable_hotplug);
2013 cancel_delayed_work_sync(&bt1120->delayed_work_res_change);
2014 rk628_hdmirx_audio_cancel_work_audio(bt1120->audio_info, true);
2015 rk628_hdmirx_audio_cancel_work_rate_change(bt1120->audio_info, true);
2016
2017 if (bt1120->rxphy_pwron)
2018 rk628_rxphy_power_off(bt1120->rk628);
2019
2020 mutex_destroy(&bt1120->confctl_mutex);
2021
2022 rk628_control_assert(bt1120->rk628, RGU_HDMIRX);
2023 rk628_control_assert(bt1120->rk628, RGU_HDMIRX_PON);
2024 rk628_control_assert(bt1120->rk628, RGU_DECODER);
2025 rk628_control_assert(bt1120->rk628, RGU_CLK_RX);
2026 rk628_control_assert(bt1120->rk628, RGU_VOP);
2027 rk628_control_assert(bt1120->rk628, RGU_BT1120DEC);
2028
2029 return 0;
2030 }
2031
2032 static const struct i2c_device_id rk628_bt1120_i2c_id[] = {
2033 { "rk628-bt1120-v4l2", 0 },
2034 { }
2035 };
2036
2037 MODULE_DEVICE_TABLE(i2c, rk628_bt1120_i2c_id);
2038
2039 static const struct of_device_id rk628_bt1120_of_match[] = {
2040 { .compatible = "rockchip,rk628-bt1120-v4l2" },
2041 {}
2042 };
2043 MODULE_DEVICE_TABLE(of, rk628_bt1120_of_match);
2044
2045 static struct i2c_driver rk628_bt1120_i2c_driver = {
2046 .driver = {
2047 .name = "rk628-bt1120-v4l2",
2048 .of_match_table = of_match_ptr(rk628_bt1120_of_match),
2049 },
2050 .id_table = rk628_bt1120_i2c_id,
2051 .probe = rk628_bt1120_probe,
2052 .remove = rk628_bt1120_remove,
2053 };
2054
2055 module_i2c_driver(rk628_bt1120_i2c_driver);
2056
2057 MODULE_DESCRIPTION("Rockchip RK628 HDMI to BT120 bridge I2C driver");
2058 MODULE_AUTHOR("Shunqing Chen <csq@rock-chips.com>");
2059 MODULE_LICENSE("GPL");
2060