xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/rj54n1cb0c.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for RJ54N1CB0C CMOS Image Sensor from Sharp
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2018, Jacopo Mondi <jacopo@jmondi.org>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/v4l2-mediabus.h>
17*4882a593Smuzhiyun #include <linux/videodev2.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <media/i2c/rj54n1cb0c.h>
20*4882a593Smuzhiyun #include <media/v4l2-device.h>
21*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
22*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define RJ54N1_DEV_CODE			0x0400
25*4882a593Smuzhiyun #define RJ54N1_DEV_CODE2		0x0401
26*4882a593Smuzhiyun #define RJ54N1_OUT_SEL			0x0403
27*4882a593Smuzhiyun #define RJ54N1_XY_OUTPUT_SIZE_S_H	0x0404
28*4882a593Smuzhiyun #define RJ54N1_X_OUTPUT_SIZE_S_L	0x0405
29*4882a593Smuzhiyun #define RJ54N1_Y_OUTPUT_SIZE_S_L	0x0406
30*4882a593Smuzhiyun #define RJ54N1_XY_OUTPUT_SIZE_P_H	0x0407
31*4882a593Smuzhiyun #define RJ54N1_X_OUTPUT_SIZE_P_L	0x0408
32*4882a593Smuzhiyun #define RJ54N1_Y_OUTPUT_SIZE_P_L	0x0409
33*4882a593Smuzhiyun #define RJ54N1_LINE_LENGTH_PCK_S_H	0x040a
34*4882a593Smuzhiyun #define RJ54N1_LINE_LENGTH_PCK_S_L	0x040b
35*4882a593Smuzhiyun #define RJ54N1_LINE_LENGTH_PCK_P_H	0x040c
36*4882a593Smuzhiyun #define RJ54N1_LINE_LENGTH_PCK_P_L	0x040d
37*4882a593Smuzhiyun #define RJ54N1_RESIZE_N			0x040e
38*4882a593Smuzhiyun #define RJ54N1_RESIZE_N_STEP		0x040f
39*4882a593Smuzhiyun #define RJ54N1_RESIZE_STEP		0x0410
40*4882a593Smuzhiyun #define RJ54N1_RESIZE_HOLD_H		0x0411
41*4882a593Smuzhiyun #define RJ54N1_RESIZE_HOLD_L		0x0412
42*4882a593Smuzhiyun #define RJ54N1_H_OBEN_OFS		0x0413
43*4882a593Smuzhiyun #define RJ54N1_V_OBEN_OFS		0x0414
44*4882a593Smuzhiyun #define RJ54N1_RESIZE_CONTROL		0x0415
45*4882a593Smuzhiyun #define RJ54N1_STILL_CONTROL		0x0417
46*4882a593Smuzhiyun #define RJ54N1_INC_USE_SEL_H		0x0425
47*4882a593Smuzhiyun #define RJ54N1_INC_USE_SEL_L		0x0426
48*4882a593Smuzhiyun #define RJ54N1_MIRROR_STILL_MODE	0x0427
49*4882a593Smuzhiyun #define RJ54N1_INIT_START		0x0428
50*4882a593Smuzhiyun #define RJ54N1_SCALE_1_2_LEV		0x0429
51*4882a593Smuzhiyun #define RJ54N1_SCALE_4_LEV		0x042a
52*4882a593Smuzhiyun #define RJ54N1_Y_GAIN			0x04d8
53*4882a593Smuzhiyun #define RJ54N1_APT_GAIN_UP		0x04fa
54*4882a593Smuzhiyun #define RJ54N1_RA_SEL_UL		0x0530
55*4882a593Smuzhiyun #define RJ54N1_BYTE_SWAP		0x0531
56*4882a593Smuzhiyun #define RJ54N1_OUT_SIGPO		0x053b
57*4882a593Smuzhiyun #define RJ54N1_WB_SEL_WEIGHT_I		0x054e
58*4882a593Smuzhiyun #define RJ54N1_BIT8_WB			0x0569
59*4882a593Smuzhiyun #define RJ54N1_HCAPS_WB			0x056a
60*4882a593Smuzhiyun #define RJ54N1_VCAPS_WB			0x056b
61*4882a593Smuzhiyun #define RJ54N1_HCAPE_WB			0x056c
62*4882a593Smuzhiyun #define RJ54N1_VCAPE_WB			0x056d
63*4882a593Smuzhiyun #define RJ54N1_EXPOSURE_CONTROL		0x058c
64*4882a593Smuzhiyun #define RJ54N1_FRAME_LENGTH_S_H		0x0595
65*4882a593Smuzhiyun #define RJ54N1_FRAME_LENGTH_S_L		0x0596
66*4882a593Smuzhiyun #define RJ54N1_FRAME_LENGTH_P_H		0x0597
67*4882a593Smuzhiyun #define RJ54N1_FRAME_LENGTH_P_L		0x0598
68*4882a593Smuzhiyun #define RJ54N1_PEAK_H			0x05b7
69*4882a593Smuzhiyun #define RJ54N1_PEAK_50			0x05b8
70*4882a593Smuzhiyun #define RJ54N1_PEAK_60			0x05b9
71*4882a593Smuzhiyun #define RJ54N1_PEAK_DIFF		0x05ba
72*4882a593Smuzhiyun #define RJ54N1_IOC			0x05ef
73*4882a593Smuzhiyun #define RJ54N1_TG_BYPASS		0x0700
74*4882a593Smuzhiyun #define RJ54N1_PLL_L			0x0701
75*4882a593Smuzhiyun #define RJ54N1_PLL_N			0x0702
76*4882a593Smuzhiyun #define RJ54N1_PLL_EN			0x0704
77*4882a593Smuzhiyun #define RJ54N1_RATIO_TG			0x0706
78*4882a593Smuzhiyun #define RJ54N1_RATIO_T			0x0707
79*4882a593Smuzhiyun #define RJ54N1_RATIO_R			0x0708
80*4882a593Smuzhiyun #define RJ54N1_RAMP_TGCLK_EN		0x0709
81*4882a593Smuzhiyun #define RJ54N1_OCLK_DSP			0x0710
82*4882a593Smuzhiyun #define RJ54N1_RATIO_OP			0x0711
83*4882a593Smuzhiyun #define RJ54N1_RATIO_O			0x0712
84*4882a593Smuzhiyun #define RJ54N1_OCLK_SEL_EN		0x0713
85*4882a593Smuzhiyun #define RJ54N1_CLK_RST			0x0717
86*4882a593Smuzhiyun #define RJ54N1_RESET_STANDBY		0x0718
87*4882a593Smuzhiyun #define RJ54N1_FWFLG			0x07fe
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun #define E_EXCLK				(1 << 7)
90*4882a593Smuzhiyun #define SOFT_STDBY			(1 << 4)
91*4882a593Smuzhiyun #define SEN_RSTX			(1 << 2)
92*4882a593Smuzhiyun #define TG_RSTX				(1 << 1)
93*4882a593Smuzhiyun #define DSP_RSTX			(1 << 0)
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun #define RESIZE_HOLD_SEL			(1 << 2)
96*4882a593Smuzhiyun #define RESIZE_GO			(1 << 1)
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /*
99*4882a593Smuzhiyun  * When cropping, the camera automatically centers the cropped region, there
100*4882a593Smuzhiyun  * doesn't seem to be a way to specify an explicit location of the rectangle.
101*4882a593Smuzhiyun  */
102*4882a593Smuzhiyun #define RJ54N1_COLUMN_SKIP		0
103*4882a593Smuzhiyun #define RJ54N1_ROW_SKIP			0
104*4882a593Smuzhiyun #define RJ54N1_MAX_WIDTH		1600
105*4882a593Smuzhiyun #define RJ54N1_MAX_HEIGHT		1200
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #define PLL_L				2
108*4882a593Smuzhiyun #define PLL_N				0x31
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun /* I2C addresses: 0x50, 0x51, 0x60, 0x61 */
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* RJ54N1CB0C has only one fixed colorspace per pixelcode */
113*4882a593Smuzhiyun struct rj54n1_datafmt {
114*4882a593Smuzhiyun 	u32	code;
115*4882a593Smuzhiyun 	enum v4l2_colorspace		colorspace;
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* Find a data format by a pixel code in an array */
rj54n1_find_datafmt(u32 code,const struct rj54n1_datafmt * fmt,int n)119*4882a593Smuzhiyun static const struct rj54n1_datafmt *rj54n1_find_datafmt(
120*4882a593Smuzhiyun 	u32 code, const struct rj54n1_datafmt *fmt,
121*4882a593Smuzhiyun 	int n)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun 	int i;
124*4882a593Smuzhiyun 	for (i = 0; i < n; i++)
125*4882a593Smuzhiyun 		if (fmt[i].code == code)
126*4882a593Smuzhiyun 			return fmt + i;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	return NULL;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun static const struct rj54n1_datafmt rj54n1_colour_fmts[] = {
132*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
133*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
134*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
135*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
136*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
137*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE, V4L2_COLORSPACE_SRGB},
138*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
139*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE, V4L2_COLORSPACE_SRGB},
140*4882a593Smuzhiyun 	{MEDIA_BUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun struct rj54n1_clock_div {
144*4882a593Smuzhiyun 	u8 ratio_tg;	/* can be 0 or an odd number */
145*4882a593Smuzhiyun 	u8 ratio_t;
146*4882a593Smuzhiyun 	u8 ratio_r;
147*4882a593Smuzhiyun 	u8 ratio_op;
148*4882a593Smuzhiyun 	u8 ratio_o;
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun struct rj54n1 {
152*4882a593Smuzhiyun 	struct v4l2_subdev subdev;
153*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
154*4882a593Smuzhiyun 	struct clk *clk;
155*4882a593Smuzhiyun 	struct gpio_desc *pwup_gpio;
156*4882a593Smuzhiyun 	struct gpio_desc *enable_gpio;
157*4882a593Smuzhiyun 	struct rj54n1_clock_div clk_div;
158*4882a593Smuzhiyun 	const struct rj54n1_datafmt *fmt;
159*4882a593Smuzhiyun 	struct v4l2_rect rect;	/* Sensor window */
160*4882a593Smuzhiyun 	unsigned int tgclk_mhz;
161*4882a593Smuzhiyun 	bool auto_wb;
162*4882a593Smuzhiyun 	unsigned short width;	/* Output window */
163*4882a593Smuzhiyun 	unsigned short height;
164*4882a593Smuzhiyun 	unsigned short resize;	/* Sensor * 1024 / resize = Output */
165*4882a593Smuzhiyun 	unsigned short scale;
166*4882a593Smuzhiyun 	u8 bank;
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun struct rj54n1_reg_val {
170*4882a593Smuzhiyun 	u16 reg;
171*4882a593Smuzhiyun 	u8 val;
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun static const struct rj54n1_reg_val bank_4[] = {
175*4882a593Smuzhiyun 	{0x417, 0},
176*4882a593Smuzhiyun 	{0x42c, 0},
177*4882a593Smuzhiyun 	{0x42d, 0xf0},
178*4882a593Smuzhiyun 	{0x42e, 0},
179*4882a593Smuzhiyun 	{0x42f, 0x50},
180*4882a593Smuzhiyun 	{0x430, 0xf5},
181*4882a593Smuzhiyun 	{0x431, 0x16},
182*4882a593Smuzhiyun 	{0x432, 0x20},
183*4882a593Smuzhiyun 	{0x433, 0},
184*4882a593Smuzhiyun 	{0x434, 0xc8},
185*4882a593Smuzhiyun 	{0x43c, 8},
186*4882a593Smuzhiyun 	{0x43e, 0x90},
187*4882a593Smuzhiyun 	{0x445, 0x83},
188*4882a593Smuzhiyun 	{0x4ba, 0x58},
189*4882a593Smuzhiyun 	{0x4bb, 4},
190*4882a593Smuzhiyun 	{0x4bc, 0x20},
191*4882a593Smuzhiyun 	{0x4db, 4},
192*4882a593Smuzhiyun 	{0x4fe, 2},
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun static const struct rj54n1_reg_val bank_5[] = {
196*4882a593Smuzhiyun 	{0x514, 0},
197*4882a593Smuzhiyun 	{0x516, 0},
198*4882a593Smuzhiyun 	{0x518, 0},
199*4882a593Smuzhiyun 	{0x51a, 0},
200*4882a593Smuzhiyun 	{0x51d, 0xff},
201*4882a593Smuzhiyun 	{0x56f, 0x28},
202*4882a593Smuzhiyun 	{0x575, 0x40},
203*4882a593Smuzhiyun 	{0x5bc, 0x48},
204*4882a593Smuzhiyun 	{0x5c1, 6},
205*4882a593Smuzhiyun 	{0x5e5, 0x11},
206*4882a593Smuzhiyun 	{0x5e6, 0x43},
207*4882a593Smuzhiyun 	{0x5e7, 0x33},
208*4882a593Smuzhiyun 	{0x5e8, 0x21},
209*4882a593Smuzhiyun 	{0x5e9, 0x30},
210*4882a593Smuzhiyun 	{0x5ea, 0x0},
211*4882a593Smuzhiyun 	{0x5eb, 0xa5},
212*4882a593Smuzhiyun 	{0x5ec, 0xff},
213*4882a593Smuzhiyun 	{0x5fe, 2},
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static const struct rj54n1_reg_val bank_7[] = {
217*4882a593Smuzhiyun 	{0x70a, 0},
218*4882a593Smuzhiyun 	{0x714, 0xff},
219*4882a593Smuzhiyun 	{0x715, 0xff},
220*4882a593Smuzhiyun 	{0x716, 0x1f},
221*4882a593Smuzhiyun 	{0x7FE, 2},
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun static const struct rj54n1_reg_val bank_8[] = {
225*4882a593Smuzhiyun 	{0x800, 0x00},
226*4882a593Smuzhiyun 	{0x801, 0x01},
227*4882a593Smuzhiyun 	{0x802, 0x61},
228*4882a593Smuzhiyun 	{0x805, 0x00},
229*4882a593Smuzhiyun 	{0x806, 0x00},
230*4882a593Smuzhiyun 	{0x807, 0x00},
231*4882a593Smuzhiyun 	{0x808, 0x00},
232*4882a593Smuzhiyun 	{0x809, 0x01},
233*4882a593Smuzhiyun 	{0x80A, 0x61},
234*4882a593Smuzhiyun 	{0x80B, 0x00},
235*4882a593Smuzhiyun 	{0x80C, 0x01},
236*4882a593Smuzhiyun 	{0x80D, 0x00},
237*4882a593Smuzhiyun 	{0x80E, 0x00},
238*4882a593Smuzhiyun 	{0x80F, 0x00},
239*4882a593Smuzhiyun 	{0x810, 0x00},
240*4882a593Smuzhiyun 	{0x811, 0x01},
241*4882a593Smuzhiyun 	{0x812, 0x61},
242*4882a593Smuzhiyun 	{0x813, 0x00},
243*4882a593Smuzhiyun 	{0x814, 0x11},
244*4882a593Smuzhiyun 	{0x815, 0x00},
245*4882a593Smuzhiyun 	{0x816, 0x41},
246*4882a593Smuzhiyun 	{0x817, 0x00},
247*4882a593Smuzhiyun 	{0x818, 0x51},
248*4882a593Smuzhiyun 	{0x819, 0x01},
249*4882a593Smuzhiyun 	{0x81A, 0x1F},
250*4882a593Smuzhiyun 	{0x81B, 0x00},
251*4882a593Smuzhiyun 	{0x81C, 0x01},
252*4882a593Smuzhiyun 	{0x81D, 0x00},
253*4882a593Smuzhiyun 	{0x81E, 0x11},
254*4882a593Smuzhiyun 	{0x81F, 0x00},
255*4882a593Smuzhiyun 	{0x820, 0x41},
256*4882a593Smuzhiyun 	{0x821, 0x00},
257*4882a593Smuzhiyun 	{0x822, 0x51},
258*4882a593Smuzhiyun 	{0x823, 0x00},
259*4882a593Smuzhiyun 	{0x824, 0x00},
260*4882a593Smuzhiyun 	{0x825, 0x00},
261*4882a593Smuzhiyun 	{0x826, 0x47},
262*4882a593Smuzhiyun 	{0x827, 0x01},
263*4882a593Smuzhiyun 	{0x828, 0x4F},
264*4882a593Smuzhiyun 	{0x829, 0x00},
265*4882a593Smuzhiyun 	{0x82A, 0x00},
266*4882a593Smuzhiyun 	{0x82B, 0x00},
267*4882a593Smuzhiyun 	{0x82C, 0x30},
268*4882a593Smuzhiyun 	{0x82D, 0x00},
269*4882a593Smuzhiyun 	{0x82E, 0x40},
270*4882a593Smuzhiyun 	{0x82F, 0x00},
271*4882a593Smuzhiyun 	{0x830, 0xB3},
272*4882a593Smuzhiyun 	{0x831, 0x00},
273*4882a593Smuzhiyun 	{0x832, 0xE3},
274*4882a593Smuzhiyun 	{0x833, 0x00},
275*4882a593Smuzhiyun 	{0x834, 0x00},
276*4882a593Smuzhiyun 	{0x835, 0x00},
277*4882a593Smuzhiyun 	{0x836, 0x00},
278*4882a593Smuzhiyun 	{0x837, 0x00},
279*4882a593Smuzhiyun 	{0x838, 0x00},
280*4882a593Smuzhiyun 	{0x839, 0x01},
281*4882a593Smuzhiyun 	{0x83A, 0x61},
282*4882a593Smuzhiyun 	{0x83B, 0x00},
283*4882a593Smuzhiyun 	{0x83C, 0x01},
284*4882a593Smuzhiyun 	{0x83D, 0x00},
285*4882a593Smuzhiyun 	{0x83E, 0x00},
286*4882a593Smuzhiyun 	{0x83F, 0x00},
287*4882a593Smuzhiyun 	{0x840, 0x00},
288*4882a593Smuzhiyun 	{0x841, 0x01},
289*4882a593Smuzhiyun 	{0x842, 0x61},
290*4882a593Smuzhiyun 	{0x843, 0x00},
291*4882a593Smuzhiyun 	{0x844, 0x1D},
292*4882a593Smuzhiyun 	{0x845, 0x00},
293*4882a593Smuzhiyun 	{0x846, 0x00},
294*4882a593Smuzhiyun 	{0x847, 0x00},
295*4882a593Smuzhiyun 	{0x848, 0x00},
296*4882a593Smuzhiyun 	{0x849, 0x01},
297*4882a593Smuzhiyun 	{0x84A, 0x1F},
298*4882a593Smuzhiyun 	{0x84B, 0x00},
299*4882a593Smuzhiyun 	{0x84C, 0x05},
300*4882a593Smuzhiyun 	{0x84D, 0x00},
301*4882a593Smuzhiyun 	{0x84E, 0x19},
302*4882a593Smuzhiyun 	{0x84F, 0x01},
303*4882a593Smuzhiyun 	{0x850, 0x21},
304*4882a593Smuzhiyun 	{0x851, 0x01},
305*4882a593Smuzhiyun 	{0x852, 0x5D},
306*4882a593Smuzhiyun 	{0x853, 0x00},
307*4882a593Smuzhiyun 	{0x854, 0x00},
308*4882a593Smuzhiyun 	{0x855, 0x00},
309*4882a593Smuzhiyun 	{0x856, 0x19},
310*4882a593Smuzhiyun 	{0x857, 0x01},
311*4882a593Smuzhiyun 	{0x858, 0x21},
312*4882a593Smuzhiyun 	{0x859, 0x00},
313*4882a593Smuzhiyun 	{0x85A, 0x00},
314*4882a593Smuzhiyun 	{0x85B, 0x00},
315*4882a593Smuzhiyun 	{0x85C, 0x00},
316*4882a593Smuzhiyun 	{0x85D, 0x00},
317*4882a593Smuzhiyun 	{0x85E, 0x00},
318*4882a593Smuzhiyun 	{0x85F, 0x00},
319*4882a593Smuzhiyun 	{0x860, 0xB3},
320*4882a593Smuzhiyun 	{0x861, 0x00},
321*4882a593Smuzhiyun 	{0x862, 0xE3},
322*4882a593Smuzhiyun 	{0x863, 0x00},
323*4882a593Smuzhiyun 	{0x864, 0x00},
324*4882a593Smuzhiyun 	{0x865, 0x00},
325*4882a593Smuzhiyun 	{0x866, 0x00},
326*4882a593Smuzhiyun 	{0x867, 0x00},
327*4882a593Smuzhiyun 	{0x868, 0x00},
328*4882a593Smuzhiyun 	{0x869, 0xE2},
329*4882a593Smuzhiyun 	{0x86A, 0x00},
330*4882a593Smuzhiyun 	{0x86B, 0x01},
331*4882a593Smuzhiyun 	{0x86C, 0x06},
332*4882a593Smuzhiyun 	{0x86D, 0x00},
333*4882a593Smuzhiyun 	{0x86E, 0x00},
334*4882a593Smuzhiyun 	{0x86F, 0x00},
335*4882a593Smuzhiyun 	{0x870, 0x60},
336*4882a593Smuzhiyun 	{0x871, 0x8C},
337*4882a593Smuzhiyun 	{0x872, 0x10},
338*4882a593Smuzhiyun 	{0x873, 0x00},
339*4882a593Smuzhiyun 	{0x874, 0xE0},
340*4882a593Smuzhiyun 	{0x875, 0x00},
341*4882a593Smuzhiyun 	{0x876, 0x27},
342*4882a593Smuzhiyun 	{0x877, 0x01},
343*4882a593Smuzhiyun 	{0x878, 0x00},
344*4882a593Smuzhiyun 	{0x879, 0x00},
345*4882a593Smuzhiyun 	{0x87A, 0x00},
346*4882a593Smuzhiyun 	{0x87B, 0x03},
347*4882a593Smuzhiyun 	{0x87C, 0x00},
348*4882a593Smuzhiyun 	{0x87D, 0x00},
349*4882a593Smuzhiyun 	{0x87E, 0x00},
350*4882a593Smuzhiyun 	{0x87F, 0x00},
351*4882a593Smuzhiyun 	{0x880, 0x00},
352*4882a593Smuzhiyun 	{0x881, 0x00},
353*4882a593Smuzhiyun 	{0x882, 0x00},
354*4882a593Smuzhiyun 	{0x883, 0x00},
355*4882a593Smuzhiyun 	{0x884, 0x00},
356*4882a593Smuzhiyun 	{0x885, 0x00},
357*4882a593Smuzhiyun 	{0x886, 0xF8},
358*4882a593Smuzhiyun 	{0x887, 0x00},
359*4882a593Smuzhiyun 	{0x888, 0x03},
360*4882a593Smuzhiyun 	{0x889, 0x00},
361*4882a593Smuzhiyun 	{0x88A, 0x64},
362*4882a593Smuzhiyun 	{0x88B, 0x00},
363*4882a593Smuzhiyun 	{0x88C, 0x03},
364*4882a593Smuzhiyun 	{0x88D, 0x00},
365*4882a593Smuzhiyun 	{0x88E, 0xB1},
366*4882a593Smuzhiyun 	{0x88F, 0x00},
367*4882a593Smuzhiyun 	{0x890, 0x03},
368*4882a593Smuzhiyun 	{0x891, 0x01},
369*4882a593Smuzhiyun 	{0x892, 0x1D},
370*4882a593Smuzhiyun 	{0x893, 0x00},
371*4882a593Smuzhiyun 	{0x894, 0x03},
372*4882a593Smuzhiyun 	{0x895, 0x01},
373*4882a593Smuzhiyun 	{0x896, 0x4B},
374*4882a593Smuzhiyun 	{0x897, 0x00},
375*4882a593Smuzhiyun 	{0x898, 0xE5},
376*4882a593Smuzhiyun 	{0x899, 0x00},
377*4882a593Smuzhiyun 	{0x89A, 0x01},
378*4882a593Smuzhiyun 	{0x89B, 0x00},
379*4882a593Smuzhiyun 	{0x89C, 0x01},
380*4882a593Smuzhiyun 	{0x89D, 0x04},
381*4882a593Smuzhiyun 	{0x89E, 0xC8},
382*4882a593Smuzhiyun 	{0x89F, 0x00},
383*4882a593Smuzhiyun 	{0x8A0, 0x01},
384*4882a593Smuzhiyun 	{0x8A1, 0x01},
385*4882a593Smuzhiyun 	{0x8A2, 0x61},
386*4882a593Smuzhiyun 	{0x8A3, 0x00},
387*4882a593Smuzhiyun 	{0x8A4, 0x01},
388*4882a593Smuzhiyun 	{0x8A5, 0x00},
389*4882a593Smuzhiyun 	{0x8A6, 0x00},
390*4882a593Smuzhiyun 	{0x8A7, 0x00},
391*4882a593Smuzhiyun 	{0x8A8, 0x00},
392*4882a593Smuzhiyun 	{0x8A9, 0x00},
393*4882a593Smuzhiyun 	{0x8AA, 0x7F},
394*4882a593Smuzhiyun 	{0x8AB, 0x03},
395*4882a593Smuzhiyun 	{0x8AC, 0x00},
396*4882a593Smuzhiyun 	{0x8AD, 0x00},
397*4882a593Smuzhiyun 	{0x8AE, 0x00},
398*4882a593Smuzhiyun 	{0x8AF, 0x00},
399*4882a593Smuzhiyun 	{0x8B0, 0x00},
400*4882a593Smuzhiyun 	{0x8B1, 0x00},
401*4882a593Smuzhiyun 	{0x8B6, 0x00},
402*4882a593Smuzhiyun 	{0x8B7, 0x01},
403*4882a593Smuzhiyun 	{0x8B8, 0x00},
404*4882a593Smuzhiyun 	{0x8B9, 0x00},
405*4882a593Smuzhiyun 	{0x8BA, 0x02},
406*4882a593Smuzhiyun 	{0x8BB, 0x00},
407*4882a593Smuzhiyun 	{0x8BC, 0xFF},
408*4882a593Smuzhiyun 	{0x8BD, 0x00},
409*4882a593Smuzhiyun 	{0x8FE, 2},
410*4882a593Smuzhiyun };
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun static const struct rj54n1_reg_val bank_10[] = {
413*4882a593Smuzhiyun 	{0x10bf, 0x69}
414*4882a593Smuzhiyun };
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun /* Clock dividers - these are default register values, divider = register + 1 */
417*4882a593Smuzhiyun static const struct rj54n1_clock_div clk_div = {
418*4882a593Smuzhiyun 	.ratio_tg	= 3 /* default: 5 */,
419*4882a593Smuzhiyun 	.ratio_t	= 4 /* default: 1 */,
420*4882a593Smuzhiyun 	.ratio_r	= 4 /* default: 0 */,
421*4882a593Smuzhiyun 	.ratio_op	= 1 /* default: 5 */,
422*4882a593Smuzhiyun 	.ratio_o	= 9 /* default: 0 */,
423*4882a593Smuzhiyun };
424*4882a593Smuzhiyun 
to_rj54n1(const struct i2c_client * client)425*4882a593Smuzhiyun static struct rj54n1 *to_rj54n1(const struct i2c_client *client)
426*4882a593Smuzhiyun {
427*4882a593Smuzhiyun 	return container_of(i2c_get_clientdata(client), struct rj54n1, subdev);
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun 
reg_read(struct i2c_client * client,const u16 reg)430*4882a593Smuzhiyun static int reg_read(struct i2c_client *client, const u16 reg)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
433*4882a593Smuzhiyun 	int ret;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	/* set bank */
436*4882a593Smuzhiyun 	if (rj54n1->bank != reg >> 8) {
437*4882a593Smuzhiyun 		dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
438*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
439*4882a593Smuzhiyun 		if (ret < 0)
440*4882a593Smuzhiyun 			return ret;
441*4882a593Smuzhiyun 		rj54n1->bank = reg >> 8;
442*4882a593Smuzhiyun 	}
443*4882a593Smuzhiyun 	return i2c_smbus_read_byte_data(client, reg & 0xff);
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun 
reg_write(struct i2c_client * client,const u16 reg,const u8 data)446*4882a593Smuzhiyun static int reg_write(struct i2c_client *client, const u16 reg,
447*4882a593Smuzhiyun 		     const u8 data)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
450*4882a593Smuzhiyun 	int ret;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	/* set bank */
453*4882a593Smuzhiyun 	if (rj54n1->bank != reg >> 8) {
454*4882a593Smuzhiyun 		dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
455*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
456*4882a593Smuzhiyun 		if (ret < 0)
457*4882a593Smuzhiyun 			return ret;
458*4882a593Smuzhiyun 		rj54n1->bank = reg >> 8;
459*4882a593Smuzhiyun 	}
460*4882a593Smuzhiyun 	dev_dbg(&client->dev, "[0x%x] = 0x%x\n", reg & 0xff, data);
461*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(client, reg & 0xff, data);
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun 
reg_set(struct i2c_client * client,const u16 reg,const u8 data,const u8 mask)464*4882a593Smuzhiyun static int reg_set(struct i2c_client *client, const u16 reg,
465*4882a593Smuzhiyun 		   const u8 data, const u8 mask)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 	int ret;
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	ret = reg_read(client, reg);
470*4882a593Smuzhiyun 	if (ret < 0)
471*4882a593Smuzhiyun 		return ret;
472*4882a593Smuzhiyun 	return reg_write(client, reg, (ret & ~mask) | (data & mask));
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun 
reg_write_multiple(struct i2c_client * client,const struct rj54n1_reg_val * rv,const int n)475*4882a593Smuzhiyun static int reg_write_multiple(struct i2c_client *client,
476*4882a593Smuzhiyun 			      const struct rj54n1_reg_val *rv, const int n)
477*4882a593Smuzhiyun {
478*4882a593Smuzhiyun 	int i, ret;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	for (i = 0; i < n; i++) {
481*4882a593Smuzhiyun 		ret = reg_write(client, rv->reg, rv->val);
482*4882a593Smuzhiyun 		if (ret < 0)
483*4882a593Smuzhiyun 			return ret;
484*4882a593Smuzhiyun 		rv++;
485*4882a593Smuzhiyun 	}
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 	return 0;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun 
rj54n1_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)490*4882a593Smuzhiyun static int rj54n1_enum_mbus_code(struct v4l2_subdev *sd,
491*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
492*4882a593Smuzhiyun 		struct v4l2_subdev_mbus_code_enum *code)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun 	if (code->pad || code->index >= ARRAY_SIZE(rj54n1_colour_fmts))
495*4882a593Smuzhiyun 		return -EINVAL;
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	code->code = rj54n1_colour_fmts[code->index].code;
498*4882a593Smuzhiyun 	return 0;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun 
rj54n1_s_stream(struct v4l2_subdev * sd,int enable)501*4882a593Smuzhiyun static int rj54n1_s_stream(struct v4l2_subdev *sd, int enable)
502*4882a593Smuzhiyun {
503*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	/* Switch between preview and still shot modes */
506*4882a593Smuzhiyun 	return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80);
507*4882a593Smuzhiyun }
508*4882a593Smuzhiyun 
rj54n1_set_rect(struct i2c_client * client,u16 reg_x,u16 reg_y,u16 reg_xy,u32 width,u32 height)509*4882a593Smuzhiyun static int rj54n1_set_rect(struct i2c_client *client,
510*4882a593Smuzhiyun 			   u16 reg_x, u16 reg_y, u16 reg_xy,
511*4882a593Smuzhiyun 			   u32 width, u32 height)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun 	int ret;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	ret = reg_write(client, reg_xy,
516*4882a593Smuzhiyun 			((width >> 4) & 0x70) |
517*4882a593Smuzhiyun 			((height >> 8) & 7));
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	if (!ret)
520*4882a593Smuzhiyun 		ret = reg_write(client, reg_x, width & 0xff);
521*4882a593Smuzhiyun 	if (!ret)
522*4882a593Smuzhiyun 		ret = reg_write(client, reg_y, height & 0xff);
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	return ret;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun /*
528*4882a593Smuzhiyun  * Some commands, specifically certain initialisation sequences, require
529*4882a593Smuzhiyun  * a commit operation.
530*4882a593Smuzhiyun  */
rj54n1_commit(struct i2c_client * client)531*4882a593Smuzhiyun static int rj54n1_commit(struct i2c_client *client)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	int ret = reg_write(client, RJ54N1_INIT_START, 1);
534*4882a593Smuzhiyun 	msleep(10);
535*4882a593Smuzhiyun 	if (!ret)
536*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_INIT_START, 0);
537*4882a593Smuzhiyun 	return ret;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
541*4882a593Smuzhiyun 			       s32 *out_w, s32 *out_h);
542*4882a593Smuzhiyun 
rj54n1_set_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)543*4882a593Smuzhiyun static int rj54n1_set_selection(struct v4l2_subdev *sd,
544*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
545*4882a593Smuzhiyun 				struct v4l2_subdev_selection *sel)
546*4882a593Smuzhiyun {
547*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
548*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
549*4882a593Smuzhiyun 	const struct v4l2_rect *rect = &sel->r;
550*4882a593Smuzhiyun 	int output_w, output_h, input_w = rect->width, input_h = rect->height;
551*4882a593Smuzhiyun 	int ret;
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
554*4882a593Smuzhiyun 	    sel->target != V4L2_SEL_TGT_CROP)
555*4882a593Smuzhiyun 		return -EINVAL;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	/* arbitrary minimum width and height, edges unimportant */
558*4882a593Smuzhiyun 	v4l_bound_align_image(&input_w, 8, RJ54N1_MAX_WIDTH, 0,
559*4882a593Smuzhiyun 			      &input_h, 8, RJ54N1_MAX_HEIGHT, 0, 0);
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	output_w = (input_w * 1024 + rj54n1->resize / 2) / rj54n1->resize;
562*4882a593Smuzhiyun 	output_h = (input_h * 1024 + rj54n1->resize / 2) / rj54n1->resize;
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	dev_dbg(&client->dev, "Scaling for %dx%d : %u = %dx%d\n",
565*4882a593Smuzhiyun 		input_w, input_h, rj54n1->resize, output_w, output_h);
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
568*4882a593Smuzhiyun 	if (ret < 0)
569*4882a593Smuzhiyun 		return ret;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	rj54n1->width		= output_w;
572*4882a593Smuzhiyun 	rj54n1->height		= output_h;
573*4882a593Smuzhiyun 	rj54n1->resize		= ret;
574*4882a593Smuzhiyun 	rj54n1->rect.width	= input_w;
575*4882a593Smuzhiyun 	rj54n1->rect.height	= input_h;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	return 0;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun 
rj54n1_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)580*4882a593Smuzhiyun static int rj54n1_get_selection(struct v4l2_subdev *sd,
581*4882a593Smuzhiyun 				struct v4l2_subdev_pad_config *cfg,
582*4882a593Smuzhiyun 				struct v4l2_subdev_selection *sel)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
585*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
588*4882a593Smuzhiyun 		return -EINVAL;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	switch (sel->target) {
591*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP_BOUNDS:
592*4882a593Smuzhiyun 		sel->r.left = RJ54N1_COLUMN_SKIP;
593*4882a593Smuzhiyun 		sel->r.top = RJ54N1_ROW_SKIP;
594*4882a593Smuzhiyun 		sel->r.width = RJ54N1_MAX_WIDTH;
595*4882a593Smuzhiyun 		sel->r.height = RJ54N1_MAX_HEIGHT;
596*4882a593Smuzhiyun 		return 0;
597*4882a593Smuzhiyun 	case V4L2_SEL_TGT_CROP:
598*4882a593Smuzhiyun 		sel->r = rj54n1->rect;
599*4882a593Smuzhiyun 		return 0;
600*4882a593Smuzhiyun 	default:
601*4882a593Smuzhiyun 		return -EINVAL;
602*4882a593Smuzhiyun 	}
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun 
rj54n1_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)605*4882a593Smuzhiyun static int rj54n1_get_fmt(struct v4l2_subdev *sd,
606*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
607*4882a593Smuzhiyun 		struct v4l2_subdev_format *format)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &format->format;
610*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
611*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun 	if (format->pad)
614*4882a593Smuzhiyun 		return -EINVAL;
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	mf->code	= rj54n1->fmt->code;
617*4882a593Smuzhiyun 	mf->colorspace	= rj54n1->fmt->colorspace;
618*4882a593Smuzhiyun 	mf->ycbcr_enc	= V4L2_YCBCR_ENC_601;
619*4882a593Smuzhiyun 	mf->xfer_func	= V4L2_XFER_FUNC_SRGB;
620*4882a593Smuzhiyun 	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
621*4882a593Smuzhiyun 	mf->field	= V4L2_FIELD_NONE;
622*4882a593Smuzhiyun 	mf->width	= rj54n1->width;
623*4882a593Smuzhiyun 	mf->height	= rj54n1->height;
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	return 0;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun /*
629*4882a593Smuzhiyun  * The actual geometry configuration routine. It scales the input window into
630*4882a593Smuzhiyun  * the output one, updates the window sizes and returns an error or the resize
631*4882a593Smuzhiyun  * coefficient on success. Note: we only use the "Fixed Scaling" on this camera.
632*4882a593Smuzhiyun  */
rj54n1_sensor_scale(struct v4l2_subdev * sd,s32 * in_w,s32 * in_h,s32 * out_w,s32 * out_h)633*4882a593Smuzhiyun static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
634*4882a593Smuzhiyun 			       s32 *out_w, s32 *out_h)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
637*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
638*4882a593Smuzhiyun 	unsigned int skip, resize, input_w = *in_w, input_h = *in_h,
639*4882a593Smuzhiyun 		output_w = *out_w, output_h = *out_h;
640*4882a593Smuzhiyun 	u16 inc_sel, wb_bit8, wb_left, wb_right, wb_top, wb_bottom;
641*4882a593Smuzhiyun 	unsigned int peak, peak_50, peak_60;
642*4882a593Smuzhiyun 	int ret;
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	/*
645*4882a593Smuzhiyun 	 * We have a problem with crops, where the window is larger than 512x384
646*4882a593Smuzhiyun 	 * and output window is larger than a half of the input one. In this
647*4882a593Smuzhiyun 	 * case we have to either reduce the input window to equal or below
648*4882a593Smuzhiyun 	 * 512x384 or the output window to equal or below 1/2 of the input.
649*4882a593Smuzhiyun 	 */
650*4882a593Smuzhiyun 	if (output_w > max(512U, input_w / 2)) {
651*4882a593Smuzhiyun 		if (2 * output_w > RJ54N1_MAX_WIDTH) {
652*4882a593Smuzhiyun 			input_w = RJ54N1_MAX_WIDTH;
653*4882a593Smuzhiyun 			output_w = RJ54N1_MAX_WIDTH / 2;
654*4882a593Smuzhiyun 		} else {
655*4882a593Smuzhiyun 			input_w = output_w * 2;
656*4882a593Smuzhiyun 		}
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 		dev_dbg(&client->dev, "Adjusted output width: in %u, out %u\n",
659*4882a593Smuzhiyun 			input_w, output_w);
660*4882a593Smuzhiyun 	}
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	if (output_h > max(384U, input_h / 2)) {
663*4882a593Smuzhiyun 		if (2 * output_h > RJ54N1_MAX_HEIGHT) {
664*4882a593Smuzhiyun 			input_h = RJ54N1_MAX_HEIGHT;
665*4882a593Smuzhiyun 			output_h = RJ54N1_MAX_HEIGHT / 2;
666*4882a593Smuzhiyun 		} else {
667*4882a593Smuzhiyun 			input_h = output_h * 2;
668*4882a593Smuzhiyun 		}
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun 		dev_dbg(&client->dev, "Adjusted output height: in %u, out %u\n",
671*4882a593Smuzhiyun 			input_h, output_h);
672*4882a593Smuzhiyun 	}
673*4882a593Smuzhiyun 
674*4882a593Smuzhiyun 	/* Idea: use the read mode for snapshots, handle separate geometries */
675*4882a593Smuzhiyun 	ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_S_L,
676*4882a593Smuzhiyun 			      RJ54N1_Y_OUTPUT_SIZE_S_L,
677*4882a593Smuzhiyun 			      RJ54N1_XY_OUTPUT_SIZE_S_H, output_w, output_h);
678*4882a593Smuzhiyun 	if (!ret)
679*4882a593Smuzhiyun 		ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_P_L,
680*4882a593Smuzhiyun 			      RJ54N1_Y_OUTPUT_SIZE_P_L,
681*4882a593Smuzhiyun 			      RJ54N1_XY_OUTPUT_SIZE_P_H, output_w, output_h);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	if (ret < 0)
684*4882a593Smuzhiyun 		return ret;
685*4882a593Smuzhiyun 
686*4882a593Smuzhiyun 	if (output_w > input_w && output_h > input_h) {
687*4882a593Smuzhiyun 		input_w = output_w;
688*4882a593Smuzhiyun 		input_h = output_h;
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 		resize = 1024;
691*4882a593Smuzhiyun 	} else {
692*4882a593Smuzhiyun 		unsigned int resize_x, resize_y;
693*4882a593Smuzhiyun 		resize_x = (input_w * 1024 + output_w / 2) / output_w;
694*4882a593Smuzhiyun 		resize_y = (input_h * 1024 + output_h / 2) / output_h;
695*4882a593Smuzhiyun 
696*4882a593Smuzhiyun 		/* We want max(resize_x, resize_y), check if it still fits */
697*4882a593Smuzhiyun 		if (resize_x > resize_y &&
698*4882a593Smuzhiyun 		    (output_h * resize_x + 512) / 1024 > RJ54N1_MAX_HEIGHT)
699*4882a593Smuzhiyun 			resize = (RJ54N1_MAX_HEIGHT * 1024 + output_h / 2) /
700*4882a593Smuzhiyun 				output_h;
701*4882a593Smuzhiyun 		else if (resize_y > resize_x &&
702*4882a593Smuzhiyun 			 (output_w * resize_y + 512) / 1024 > RJ54N1_MAX_WIDTH)
703*4882a593Smuzhiyun 			resize = (RJ54N1_MAX_WIDTH * 1024 + output_w / 2) /
704*4882a593Smuzhiyun 				output_w;
705*4882a593Smuzhiyun 		else
706*4882a593Smuzhiyun 			resize = max(resize_x, resize_y);
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 		/* Prohibited value ranges */
709*4882a593Smuzhiyun 		switch (resize) {
710*4882a593Smuzhiyun 		case 2040 ... 2047:
711*4882a593Smuzhiyun 			resize = 2039;
712*4882a593Smuzhiyun 			break;
713*4882a593Smuzhiyun 		case 4080 ... 4095:
714*4882a593Smuzhiyun 			resize = 4079;
715*4882a593Smuzhiyun 			break;
716*4882a593Smuzhiyun 		case 8160 ... 8191:
717*4882a593Smuzhiyun 			resize = 8159;
718*4882a593Smuzhiyun 			break;
719*4882a593Smuzhiyun 		case 16320 ... 16384:
720*4882a593Smuzhiyun 			resize = 16319;
721*4882a593Smuzhiyun 		}
722*4882a593Smuzhiyun 	}
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	/* Set scaling */
725*4882a593Smuzhiyun 	ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff);
726*4882a593Smuzhiyun 	if (!ret)
727*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8);
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	if (ret < 0)
730*4882a593Smuzhiyun 		return ret;
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	/*
733*4882a593Smuzhiyun 	 * Configure a skipping bitmask. The sensor will select a skipping value
734*4882a593Smuzhiyun 	 * among set bits automatically. This is very unclear in the datasheet
735*4882a593Smuzhiyun 	 * too. I was told, in this register one enables all skipping values,
736*4882a593Smuzhiyun 	 * that are required for a specific resize, and the camera selects
737*4882a593Smuzhiyun 	 * automatically, which ones to use. But it is unclear how to identify,
738*4882a593Smuzhiyun 	 * which cropping values are needed. Secondly, why don't we just set all
739*4882a593Smuzhiyun 	 * bits and let the camera choose? Would it increase processing time and
740*4882a593Smuzhiyun 	 * reduce the framerate? Using 0xfffc for INC_USE_SEL doesn't seem to
741*4882a593Smuzhiyun 	 * improve the image quality or stability for larger frames (see comment
742*4882a593Smuzhiyun 	 * above), but I didn't check the framerate.
743*4882a593Smuzhiyun 	 */
744*4882a593Smuzhiyun 	skip = min(resize / 1024, 15U);
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun 	inc_sel = 1 << skip;
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun 	if (inc_sel <= 2)
749*4882a593Smuzhiyun 		inc_sel = 0xc;
750*4882a593Smuzhiyun 	else if (resize & 1023 && skip < 15)
751*4882a593Smuzhiyun 		inc_sel |= 1 << (skip + 1);
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun 	ret = reg_write(client, RJ54N1_INC_USE_SEL_L, inc_sel & 0xfc);
754*4882a593Smuzhiyun 	if (!ret)
755*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_INC_USE_SEL_H, inc_sel >> 8);
756*4882a593Smuzhiyun 
757*4882a593Smuzhiyun 	if (!rj54n1->auto_wb) {
758*4882a593Smuzhiyun 		/* Auto white balance window */
759*4882a593Smuzhiyun 		wb_left	  = output_w / 16;
760*4882a593Smuzhiyun 		wb_right  = (3 * output_w / 4 - 3) / 4;
761*4882a593Smuzhiyun 		wb_top	  = output_h / 16;
762*4882a593Smuzhiyun 		wb_bottom = (3 * output_h / 4 - 3) / 4;
763*4882a593Smuzhiyun 		wb_bit8	  = ((wb_left >> 2) & 0x40) | ((wb_top >> 4) & 0x10) |
764*4882a593Smuzhiyun 			((wb_right >> 6) & 4) | ((wb_bottom >> 8) & 1);
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 		if (!ret)
767*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_BIT8_WB, wb_bit8);
768*4882a593Smuzhiyun 		if (!ret)
769*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_HCAPS_WB, wb_left);
770*4882a593Smuzhiyun 		if (!ret)
771*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_VCAPS_WB, wb_top);
772*4882a593Smuzhiyun 		if (!ret)
773*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_HCAPE_WB, wb_right);
774*4882a593Smuzhiyun 		if (!ret)
775*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_VCAPE_WB, wb_bottom);
776*4882a593Smuzhiyun 	}
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun 	/* Antiflicker */
779*4882a593Smuzhiyun 	peak = 12 * RJ54N1_MAX_WIDTH * (1 << 14) * resize / rj54n1->tgclk_mhz /
780*4882a593Smuzhiyun 		10000;
781*4882a593Smuzhiyun 	peak_50 = peak / 6;
782*4882a593Smuzhiyun 	peak_60 = peak / 5;
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	if (!ret)
785*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_PEAK_H,
786*4882a593Smuzhiyun 				((peak_50 >> 4) & 0xf0) | (peak_60 >> 8));
787*4882a593Smuzhiyun 	if (!ret)
788*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_PEAK_50, peak_50);
789*4882a593Smuzhiyun 	if (!ret)
790*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_PEAK_60, peak_60);
791*4882a593Smuzhiyun 	if (!ret)
792*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_PEAK_DIFF, peak / 150);
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	/* Start resizing */
795*4882a593Smuzhiyun 	if (!ret)
796*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
797*4882a593Smuzhiyun 				RESIZE_HOLD_SEL | RESIZE_GO | 1);
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	if (ret < 0)
800*4882a593Smuzhiyun 		return ret;
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	/* Constant taken from manufacturer's example */
803*4882a593Smuzhiyun 	msleep(230);
804*4882a593Smuzhiyun 
805*4882a593Smuzhiyun 	ret = reg_write(client, RJ54N1_RESIZE_CONTROL, RESIZE_HOLD_SEL | 1);
806*4882a593Smuzhiyun 	if (ret < 0)
807*4882a593Smuzhiyun 		return ret;
808*4882a593Smuzhiyun 
809*4882a593Smuzhiyun 	*in_w = (output_w * resize + 512) / 1024;
810*4882a593Smuzhiyun 	*in_h = (output_h * resize + 512) / 1024;
811*4882a593Smuzhiyun 	*out_w = output_w;
812*4882a593Smuzhiyun 	*out_h = output_h;
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	dev_dbg(&client->dev, "Scaled for %dx%d : %u = %ux%u, skip %u\n",
815*4882a593Smuzhiyun 		*in_w, *in_h, resize, output_w, output_h, skip);
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	return resize;
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun 
rj54n1_set_clock(struct i2c_client * client)820*4882a593Smuzhiyun static int rj54n1_set_clock(struct i2c_client *client)
821*4882a593Smuzhiyun {
822*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
823*4882a593Smuzhiyun 	int ret;
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	/* Enable external clock */
826*4882a593Smuzhiyun 	ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK | SOFT_STDBY);
827*4882a593Smuzhiyun 	/* Leave stand-by. Note: use this when implementing suspend / resume */
828*4882a593Smuzhiyun 	if (!ret)
829*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK);
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 	if (!ret)
832*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_PLL_L, PLL_L);
833*4882a593Smuzhiyun 	if (!ret)
834*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_PLL_N, PLL_N);
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	/* TGCLK dividers */
837*4882a593Smuzhiyun 	if (!ret)
838*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RATIO_TG,
839*4882a593Smuzhiyun 				rj54n1->clk_div.ratio_tg);
840*4882a593Smuzhiyun 	if (!ret)
841*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RATIO_T,
842*4882a593Smuzhiyun 				rj54n1->clk_div.ratio_t);
843*4882a593Smuzhiyun 	if (!ret)
844*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RATIO_R,
845*4882a593Smuzhiyun 				rj54n1->clk_div.ratio_r);
846*4882a593Smuzhiyun 
847*4882a593Smuzhiyun 	/* Enable TGCLK & RAMP */
848*4882a593Smuzhiyun 	if (!ret)
849*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RAMP_TGCLK_EN, 3);
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	/* Disable clock output */
852*4882a593Smuzhiyun 	if (!ret)
853*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OCLK_DSP, 0);
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun 	/* Set divisors */
856*4882a593Smuzhiyun 	if (!ret)
857*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RATIO_OP,
858*4882a593Smuzhiyun 				rj54n1->clk_div.ratio_op);
859*4882a593Smuzhiyun 	if (!ret)
860*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RATIO_O,
861*4882a593Smuzhiyun 				rj54n1->clk_div.ratio_o);
862*4882a593Smuzhiyun 
863*4882a593Smuzhiyun 	/* Enable OCLK */
864*4882a593Smuzhiyun 	if (!ret)
865*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	/* Use PLL for Timing Generator, write 2 to reserved bits */
868*4882a593Smuzhiyun 	if (!ret)
869*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_TG_BYPASS, 2);
870*4882a593Smuzhiyun 
871*4882a593Smuzhiyun 	/* Take sensor out of reset */
872*4882a593Smuzhiyun 	if (!ret)
873*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RESET_STANDBY,
874*4882a593Smuzhiyun 				E_EXCLK | SEN_RSTX);
875*4882a593Smuzhiyun 	/* Enable PLL */
876*4882a593Smuzhiyun 	if (!ret)
877*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_PLL_EN, 1);
878*4882a593Smuzhiyun 
879*4882a593Smuzhiyun 	/* Wait for PLL to stabilise */
880*4882a593Smuzhiyun 	msleep(10);
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 	/* Enable clock to frequency divider */
883*4882a593Smuzhiyun 	if (!ret)
884*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_CLK_RST, 1);
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun 	if (!ret)
887*4882a593Smuzhiyun 		ret = reg_read(client, RJ54N1_CLK_RST);
888*4882a593Smuzhiyun 	if (ret != 1) {
889*4882a593Smuzhiyun 		dev_err(&client->dev,
890*4882a593Smuzhiyun 			"Resetting RJ54N1CB0C clock failed: %d!\n", ret);
891*4882a593Smuzhiyun 		return -EIO;
892*4882a593Smuzhiyun 	}
893*4882a593Smuzhiyun 
894*4882a593Smuzhiyun 	/* Start the PLL */
895*4882a593Smuzhiyun 	ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1);
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun 	/* Enable OCLK */
898*4882a593Smuzhiyun 	if (!ret)
899*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
900*4882a593Smuzhiyun 
901*4882a593Smuzhiyun 	return ret;
902*4882a593Smuzhiyun }
903*4882a593Smuzhiyun 
rj54n1_reg_init(struct i2c_client * client)904*4882a593Smuzhiyun static int rj54n1_reg_init(struct i2c_client *client)
905*4882a593Smuzhiyun {
906*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
907*4882a593Smuzhiyun 	int ret = rj54n1_set_clock(client);
908*4882a593Smuzhiyun 
909*4882a593Smuzhiyun 	if (!ret)
910*4882a593Smuzhiyun 		ret = reg_write_multiple(client, bank_7, ARRAY_SIZE(bank_7));
911*4882a593Smuzhiyun 	if (!ret)
912*4882a593Smuzhiyun 		ret = reg_write_multiple(client, bank_10, ARRAY_SIZE(bank_10));
913*4882a593Smuzhiyun 
914*4882a593Smuzhiyun 	/* Set binning divisors */
915*4882a593Smuzhiyun 	if (!ret)
916*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_SCALE_1_2_LEV, 3 | (7 << 4));
917*4882a593Smuzhiyun 	if (!ret)
918*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_SCALE_4_LEV, 0xf);
919*4882a593Smuzhiyun 
920*4882a593Smuzhiyun 	/* Switch to fixed resize mode */
921*4882a593Smuzhiyun 	if (!ret)
922*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
923*4882a593Smuzhiyun 				RESIZE_HOLD_SEL | 1);
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	/* Set gain */
926*4882a593Smuzhiyun 	if (!ret)
927*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_Y_GAIN, 0x84);
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	/*
930*4882a593Smuzhiyun 	 * Mirror the image back: default is upside down and left-to-right...
931*4882a593Smuzhiyun 	 * Set manual preview / still shot switching
932*4882a593Smuzhiyun 	 */
933*4882a593Smuzhiyun 	if (!ret)
934*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_MIRROR_STILL_MODE, 0x27);
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	if (!ret)
937*4882a593Smuzhiyun 		ret = reg_write_multiple(client, bank_4, ARRAY_SIZE(bank_4));
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun 	/* Auto exposure area */
940*4882a593Smuzhiyun 	if (!ret)
941*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_EXPOSURE_CONTROL, 0x80);
942*4882a593Smuzhiyun 	/* Check current auto WB config */
943*4882a593Smuzhiyun 	if (!ret)
944*4882a593Smuzhiyun 		ret = reg_read(client, RJ54N1_WB_SEL_WEIGHT_I);
945*4882a593Smuzhiyun 	if (ret >= 0) {
946*4882a593Smuzhiyun 		rj54n1->auto_wb = ret & 0x80;
947*4882a593Smuzhiyun 		ret = reg_write_multiple(client, bank_5, ARRAY_SIZE(bank_5));
948*4882a593Smuzhiyun 	}
949*4882a593Smuzhiyun 	if (!ret)
950*4882a593Smuzhiyun 		ret = reg_write_multiple(client, bank_8, ARRAY_SIZE(bank_8));
951*4882a593Smuzhiyun 
952*4882a593Smuzhiyun 	if (!ret)
953*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RESET_STANDBY,
954*4882a593Smuzhiyun 				E_EXCLK | DSP_RSTX | SEN_RSTX);
955*4882a593Smuzhiyun 
956*4882a593Smuzhiyun 	/* Commit init */
957*4882a593Smuzhiyun 	if (!ret)
958*4882a593Smuzhiyun 		ret = rj54n1_commit(client);
959*4882a593Smuzhiyun 
960*4882a593Smuzhiyun 	/* Take DSP, TG, sensor out of reset */
961*4882a593Smuzhiyun 	if (!ret)
962*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_RESET_STANDBY,
963*4882a593Smuzhiyun 				E_EXCLK | DSP_RSTX | TG_RSTX | SEN_RSTX);
964*4882a593Smuzhiyun 
965*4882a593Smuzhiyun 	/* Start register update? Same register as 0x?FE in many bank_* sets */
966*4882a593Smuzhiyun 	if (!ret)
967*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_FWFLG, 2);
968*4882a593Smuzhiyun 
969*4882a593Smuzhiyun 	/* Constant taken from manufacturer's example */
970*4882a593Smuzhiyun 	msleep(700);
971*4882a593Smuzhiyun 
972*4882a593Smuzhiyun 	return ret;
973*4882a593Smuzhiyun }
974*4882a593Smuzhiyun 
rj54n1_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)975*4882a593Smuzhiyun static int rj54n1_set_fmt(struct v4l2_subdev *sd,
976*4882a593Smuzhiyun 		struct v4l2_subdev_pad_config *cfg,
977*4882a593Smuzhiyun 		struct v4l2_subdev_format *format)
978*4882a593Smuzhiyun {
979*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = &format->format;
980*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
981*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
982*4882a593Smuzhiyun 	const struct rj54n1_datafmt *fmt;
983*4882a593Smuzhiyun 	int output_w, output_h, max_w, max_h,
984*4882a593Smuzhiyun 		input_w = rj54n1->rect.width, input_h = rj54n1->rect.height;
985*4882a593Smuzhiyun 	int align = mf->code == MEDIA_BUS_FMT_SBGGR10_1X10 ||
986*4882a593Smuzhiyun 		mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE ||
987*4882a593Smuzhiyun 		mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE ||
988*4882a593Smuzhiyun 		mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE ||
989*4882a593Smuzhiyun 		mf->code == MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE;
990*4882a593Smuzhiyun 	int ret;
991*4882a593Smuzhiyun 
992*4882a593Smuzhiyun 	if (format->pad)
993*4882a593Smuzhiyun 		return -EINVAL;
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	dev_dbg(&client->dev, "%s: code = %d, width = %u, height = %u\n",
996*4882a593Smuzhiyun 		__func__, mf->code, mf->width, mf->height);
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
999*4882a593Smuzhiyun 				  ARRAY_SIZE(rj54n1_colour_fmts));
1000*4882a593Smuzhiyun 	if (!fmt) {
1001*4882a593Smuzhiyun 		fmt = rj54n1->fmt;
1002*4882a593Smuzhiyun 		mf->code = fmt->code;
1003*4882a593Smuzhiyun 	}
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 	mf->field	= V4L2_FIELD_NONE;
1006*4882a593Smuzhiyun 	mf->colorspace	= fmt->colorspace;
1007*4882a593Smuzhiyun 
1008*4882a593Smuzhiyun 	v4l_bound_align_image(&mf->width, 112, RJ54N1_MAX_WIDTH, align,
1009*4882a593Smuzhiyun 			      &mf->height, 84, RJ54N1_MAX_HEIGHT, align, 0);
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1012*4882a593Smuzhiyun 		cfg->try_fmt = *mf;
1013*4882a593Smuzhiyun 		return 0;
1014*4882a593Smuzhiyun 	}
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	/*
1017*4882a593Smuzhiyun 	 * Verify if the sensor has just been powered on. TODO: replace this
1018*4882a593Smuzhiyun 	 * with proper PM, when a suitable API is available.
1019*4882a593Smuzhiyun 	 */
1020*4882a593Smuzhiyun 	ret = reg_read(client, RJ54N1_RESET_STANDBY);
1021*4882a593Smuzhiyun 	if (ret < 0)
1022*4882a593Smuzhiyun 		return ret;
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	if (!(ret & E_EXCLK)) {
1025*4882a593Smuzhiyun 		ret = rj54n1_reg_init(client);
1026*4882a593Smuzhiyun 		if (ret < 0)
1027*4882a593Smuzhiyun 			return ret;
1028*4882a593Smuzhiyun 	}
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun 	/* RA_SEL_UL is only relevant for raw modes, ignored otherwise. */
1031*4882a593Smuzhiyun 	switch (mf->code) {
1032*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_YUYV8_2X8:
1033*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1034*4882a593Smuzhiyun 		if (!ret)
1035*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1036*4882a593Smuzhiyun 		break;
1037*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_YVYU8_2X8:
1038*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1039*4882a593Smuzhiyun 		if (!ret)
1040*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1041*4882a593Smuzhiyun 		break;
1042*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB565_2X8_LE:
1043*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1044*4882a593Smuzhiyun 		if (!ret)
1045*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1046*4882a593Smuzhiyun 		break;
1047*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB565_2X8_BE:
1048*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1049*4882a593Smuzhiyun 		if (!ret)
1050*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1051*4882a593Smuzhiyun 		break;
1052*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
1053*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1054*4882a593Smuzhiyun 		if (!ret)
1055*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1056*4882a593Smuzhiyun 		if (!ret)
1057*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1058*4882a593Smuzhiyun 		break;
1059*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
1060*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1061*4882a593Smuzhiyun 		if (!ret)
1062*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1063*4882a593Smuzhiyun 		if (!ret)
1064*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1065*4882a593Smuzhiyun 		break;
1066*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
1067*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1068*4882a593Smuzhiyun 		if (!ret)
1069*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1070*4882a593Smuzhiyun 		if (!ret)
1071*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1072*4882a593Smuzhiyun 		break;
1073*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
1074*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1075*4882a593Smuzhiyun 		if (!ret)
1076*4882a593Smuzhiyun 			ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1077*4882a593Smuzhiyun 		if (!ret)
1078*4882a593Smuzhiyun 			ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1079*4882a593Smuzhiyun 		break;
1080*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR10_1X10:
1081*4882a593Smuzhiyun 		ret = reg_write(client, RJ54N1_OUT_SEL, 5);
1082*4882a593Smuzhiyun 		break;
1083*4882a593Smuzhiyun 	default:
1084*4882a593Smuzhiyun 		ret = -EINVAL;
1085*4882a593Smuzhiyun 	}
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	/* Special case: a raw mode with 10 bits of data per clock tick */
1088*4882a593Smuzhiyun 	if (!ret)
1089*4882a593Smuzhiyun 		ret = reg_set(client, RJ54N1_OCLK_SEL_EN,
1090*4882a593Smuzhiyun 			      (mf->code == MEDIA_BUS_FMT_SBGGR10_1X10) << 1, 2);
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	if (ret < 0)
1093*4882a593Smuzhiyun 		return ret;
1094*4882a593Smuzhiyun 
1095*4882a593Smuzhiyun 	/* Supported scales 1:1 >= scale > 1:16 */
1096*4882a593Smuzhiyun 	max_w = mf->width * (16 * 1024 - 1) / 1024;
1097*4882a593Smuzhiyun 	if (input_w > max_w)
1098*4882a593Smuzhiyun 		input_w = max_w;
1099*4882a593Smuzhiyun 	max_h = mf->height * (16 * 1024 - 1) / 1024;
1100*4882a593Smuzhiyun 	if (input_h > max_h)
1101*4882a593Smuzhiyun 		input_h = max_h;
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	output_w = mf->width;
1104*4882a593Smuzhiyun 	output_h = mf->height;
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
1107*4882a593Smuzhiyun 	if (ret < 0)
1108*4882a593Smuzhiyun 		return ret;
1109*4882a593Smuzhiyun 
1110*4882a593Smuzhiyun 	fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
1111*4882a593Smuzhiyun 				  ARRAY_SIZE(rj54n1_colour_fmts));
1112*4882a593Smuzhiyun 
1113*4882a593Smuzhiyun 	rj54n1->fmt		= fmt;
1114*4882a593Smuzhiyun 	rj54n1->resize		= ret;
1115*4882a593Smuzhiyun 	rj54n1->rect.width	= input_w;
1116*4882a593Smuzhiyun 	rj54n1->rect.height	= input_h;
1117*4882a593Smuzhiyun 	rj54n1->width		= output_w;
1118*4882a593Smuzhiyun 	rj54n1->height		= output_h;
1119*4882a593Smuzhiyun 
1120*4882a593Smuzhiyun 	mf->width		= output_w;
1121*4882a593Smuzhiyun 	mf->height		= output_h;
1122*4882a593Smuzhiyun 	mf->field		= V4L2_FIELD_NONE;
1123*4882a593Smuzhiyun 	mf->colorspace		= fmt->colorspace;
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 	return 0;
1126*4882a593Smuzhiyun }
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
rj54n1_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)1129*4882a593Smuzhiyun static int rj54n1_g_register(struct v4l2_subdev *sd,
1130*4882a593Smuzhiyun 			     struct v4l2_dbg_register *reg)
1131*4882a593Smuzhiyun {
1132*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
1133*4882a593Smuzhiyun 
1134*4882a593Smuzhiyun 	if (reg->reg < 0x400 || reg->reg > 0x1fff)
1135*4882a593Smuzhiyun 		/* Registers > 0x0800 are only available from Sharp support */
1136*4882a593Smuzhiyun 		return -EINVAL;
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	reg->size = 1;
1139*4882a593Smuzhiyun 	reg->val = reg_read(client, reg->reg);
1140*4882a593Smuzhiyun 
1141*4882a593Smuzhiyun 	if (reg->val > 0xff)
1142*4882a593Smuzhiyun 		return -EIO;
1143*4882a593Smuzhiyun 
1144*4882a593Smuzhiyun 	return 0;
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun 
rj54n1_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)1147*4882a593Smuzhiyun static int rj54n1_s_register(struct v4l2_subdev *sd,
1148*4882a593Smuzhiyun 			     const struct v4l2_dbg_register *reg)
1149*4882a593Smuzhiyun {
1150*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
1151*4882a593Smuzhiyun 
1152*4882a593Smuzhiyun 	if (reg->reg < 0x400 || reg->reg > 0x1fff)
1153*4882a593Smuzhiyun 		/* Registers >= 0x0800 are only available from Sharp support */
1154*4882a593Smuzhiyun 		return -EINVAL;
1155*4882a593Smuzhiyun 
1156*4882a593Smuzhiyun 	if (reg_write(client, reg->reg, reg->val) < 0)
1157*4882a593Smuzhiyun 		return -EIO;
1158*4882a593Smuzhiyun 
1159*4882a593Smuzhiyun 	return 0;
1160*4882a593Smuzhiyun }
1161*4882a593Smuzhiyun #endif
1162*4882a593Smuzhiyun 
rj54n1_s_power(struct v4l2_subdev * sd,int on)1163*4882a593Smuzhiyun static int rj54n1_s_power(struct v4l2_subdev *sd, int on)
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
1166*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun 	if (on) {
1169*4882a593Smuzhiyun 		if (rj54n1->pwup_gpio)
1170*4882a593Smuzhiyun 			gpiod_set_value(rj54n1->pwup_gpio, 1);
1171*4882a593Smuzhiyun 		if (rj54n1->enable_gpio)
1172*4882a593Smuzhiyun 			gpiod_set_value(rj54n1->enable_gpio, 1);
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun 		msleep(1);
1175*4882a593Smuzhiyun 
1176*4882a593Smuzhiyun 		return clk_prepare_enable(rj54n1->clk);
1177*4882a593Smuzhiyun 	}
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun 	clk_disable_unprepare(rj54n1->clk);
1180*4882a593Smuzhiyun 
1181*4882a593Smuzhiyun 	if (rj54n1->enable_gpio)
1182*4882a593Smuzhiyun 		gpiod_set_value(rj54n1->enable_gpio, 0);
1183*4882a593Smuzhiyun 	if (rj54n1->pwup_gpio)
1184*4882a593Smuzhiyun 		gpiod_set_value(rj54n1->pwup_gpio, 0);
1185*4882a593Smuzhiyun 
1186*4882a593Smuzhiyun 	return 0;
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun 
rj54n1_s_ctrl(struct v4l2_ctrl * ctrl)1189*4882a593Smuzhiyun static int rj54n1_s_ctrl(struct v4l2_ctrl *ctrl)
1190*4882a593Smuzhiyun {
1191*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = container_of(ctrl->handler, struct rj54n1, hdl);
1192*4882a593Smuzhiyun 	struct v4l2_subdev *sd = &rj54n1->subdev;
1193*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
1194*4882a593Smuzhiyun 	int data;
1195*4882a593Smuzhiyun 
1196*4882a593Smuzhiyun 	switch (ctrl->id) {
1197*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
1198*4882a593Smuzhiyun 		if (ctrl->val)
1199*4882a593Smuzhiyun 			data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 1);
1200*4882a593Smuzhiyun 		else
1201*4882a593Smuzhiyun 			data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 1, 1);
1202*4882a593Smuzhiyun 		if (data < 0)
1203*4882a593Smuzhiyun 			return -EIO;
1204*4882a593Smuzhiyun 		return 0;
1205*4882a593Smuzhiyun 	case V4L2_CID_HFLIP:
1206*4882a593Smuzhiyun 		if (ctrl->val)
1207*4882a593Smuzhiyun 			data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 2);
1208*4882a593Smuzhiyun 		else
1209*4882a593Smuzhiyun 			data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 2, 2);
1210*4882a593Smuzhiyun 		if (data < 0)
1211*4882a593Smuzhiyun 			return -EIO;
1212*4882a593Smuzhiyun 		return 0;
1213*4882a593Smuzhiyun 	case V4L2_CID_GAIN:
1214*4882a593Smuzhiyun 		if (reg_write(client, RJ54N1_Y_GAIN, ctrl->val * 2) < 0)
1215*4882a593Smuzhiyun 			return -EIO;
1216*4882a593Smuzhiyun 		return 0;
1217*4882a593Smuzhiyun 	case V4L2_CID_AUTO_WHITE_BALANCE:
1218*4882a593Smuzhiyun 		/* Auto WB area - whole image */
1219*4882a593Smuzhiyun 		if (reg_set(client, RJ54N1_WB_SEL_WEIGHT_I, ctrl->val << 7,
1220*4882a593Smuzhiyun 			    0x80) < 0)
1221*4882a593Smuzhiyun 			return -EIO;
1222*4882a593Smuzhiyun 		rj54n1->auto_wb = ctrl->val;
1223*4882a593Smuzhiyun 		return 0;
1224*4882a593Smuzhiyun 	}
1225*4882a593Smuzhiyun 
1226*4882a593Smuzhiyun 	return -EINVAL;
1227*4882a593Smuzhiyun }
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun static const struct v4l2_ctrl_ops rj54n1_ctrl_ops = {
1230*4882a593Smuzhiyun 	.s_ctrl = rj54n1_s_ctrl,
1231*4882a593Smuzhiyun };
1232*4882a593Smuzhiyun 
1233*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops rj54n1_subdev_core_ops = {
1234*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_ADV_DEBUG
1235*4882a593Smuzhiyun 	.g_register	= rj54n1_g_register,
1236*4882a593Smuzhiyun 	.s_register	= rj54n1_s_register,
1237*4882a593Smuzhiyun #endif
1238*4882a593Smuzhiyun 	.s_power	= rj54n1_s_power,
1239*4882a593Smuzhiyun };
1240*4882a593Smuzhiyun 
1241*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops rj54n1_subdev_video_ops = {
1242*4882a593Smuzhiyun 	.s_stream	= rj54n1_s_stream,
1243*4882a593Smuzhiyun };
1244*4882a593Smuzhiyun 
1245*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops rj54n1_subdev_pad_ops = {
1246*4882a593Smuzhiyun 	.enum_mbus_code = rj54n1_enum_mbus_code,
1247*4882a593Smuzhiyun 	.get_selection	= rj54n1_get_selection,
1248*4882a593Smuzhiyun 	.set_selection	= rj54n1_set_selection,
1249*4882a593Smuzhiyun 	.get_fmt	= rj54n1_get_fmt,
1250*4882a593Smuzhiyun 	.set_fmt	= rj54n1_set_fmt,
1251*4882a593Smuzhiyun };
1252*4882a593Smuzhiyun 
1253*4882a593Smuzhiyun static const struct v4l2_subdev_ops rj54n1_subdev_ops = {
1254*4882a593Smuzhiyun 	.core	= &rj54n1_subdev_core_ops,
1255*4882a593Smuzhiyun 	.video	= &rj54n1_subdev_video_ops,
1256*4882a593Smuzhiyun 	.pad	= &rj54n1_subdev_pad_ops,
1257*4882a593Smuzhiyun };
1258*4882a593Smuzhiyun 
1259*4882a593Smuzhiyun /*
1260*4882a593Smuzhiyun  * Interface active, can use i2c. If it fails, it can indeed mean, that
1261*4882a593Smuzhiyun  * this wasn't our capture interface, so, we wait for the right one
1262*4882a593Smuzhiyun  */
rj54n1_video_probe(struct i2c_client * client,struct rj54n1_pdata * priv)1263*4882a593Smuzhiyun static int rj54n1_video_probe(struct i2c_client *client,
1264*4882a593Smuzhiyun 			      struct rj54n1_pdata *priv)
1265*4882a593Smuzhiyun {
1266*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
1267*4882a593Smuzhiyun 	int data1, data2;
1268*4882a593Smuzhiyun 	int ret;
1269*4882a593Smuzhiyun 
1270*4882a593Smuzhiyun 	ret = rj54n1_s_power(&rj54n1->subdev, 1);
1271*4882a593Smuzhiyun 	if (ret < 0)
1272*4882a593Smuzhiyun 		return ret;
1273*4882a593Smuzhiyun 
1274*4882a593Smuzhiyun 	/* Read out the chip version register */
1275*4882a593Smuzhiyun 	data1 = reg_read(client, RJ54N1_DEV_CODE);
1276*4882a593Smuzhiyun 	data2 = reg_read(client, RJ54N1_DEV_CODE2);
1277*4882a593Smuzhiyun 
1278*4882a593Smuzhiyun 	if (data1 != 0x51 || data2 != 0x10) {
1279*4882a593Smuzhiyun 		ret = -ENODEV;
1280*4882a593Smuzhiyun 		dev_info(&client->dev, "No RJ54N1CB0C found, read 0x%x:0x%x\n",
1281*4882a593Smuzhiyun 			 data1, data2);
1282*4882a593Smuzhiyun 		goto done;
1283*4882a593Smuzhiyun 	}
1284*4882a593Smuzhiyun 
1285*4882a593Smuzhiyun 	/* Configure IOCTL polarity from the platform data: 0 or 1 << 7. */
1286*4882a593Smuzhiyun 	ret = reg_write(client, RJ54N1_IOC, priv->ioctl_high << 7);
1287*4882a593Smuzhiyun 	if (ret < 0)
1288*4882a593Smuzhiyun 		goto done;
1289*4882a593Smuzhiyun 
1290*4882a593Smuzhiyun 	dev_info(&client->dev, "Detected a RJ54N1CB0C chip ID 0x%x:0x%x\n",
1291*4882a593Smuzhiyun 		 data1, data2);
1292*4882a593Smuzhiyun 
1293*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_setup(&rj54n1->hdl);
1294*4882a593Smuzhiyun 
1295*4882a593Smuzhiyun done:
1296*4882a593Smuzhiyun 	rj54n1_s_power(&rj54n1->subdev, 0);
1297*4882a593Smuzhiyun 	return ret;
1298*4882a593Smuzhiyun }
1299*4882a593Smuzhiyun 
rj54n1_probe(struct i2c_client * client,const struct i2c_device_id * did)1300*4882a593Smuzhiyun static int rj54n1_probe(struct i2c_client *client,
1301*4882a593Smuzhiyun 			const struct i2c_device_id *did)
1302*4882a593Smuzhiyun {
1303*4882a593Smuzhiyun 	struct rj54n1 *rj54n1;
1304*4882a593Smuzhiyun 	struct i2c_adapter *adapter = client->adapter;
1305*4882a593Smuzhiyun 	struct rj54n1_pdata *rj54n1_priv;
1306*4882a593Smuzhiyun 	int ret;
1307*4882a593Smuzhiyun 
1308*4882a593Smuzhiyun 	if (!client->dev.platform_data) {
1309*4882a593Smuzhiyun 		dev_err(&client->dev, "RJ54N1CB0C: missing platform data!\n");
1310*4882a593Smuzhiyun 		return -EINVAL;
1311*4882a593Smuzhiyun 	}
1312*4882a593Smuzhiyun 
1313*4882a593Smuzhiyun 	rj54n1_priv = client->dev.platform_data;
1314*4882a593Smuzhiyun 
1315*4882a593Smuzhiyun 	if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1316*4882a593Smuzhiyun 		dev_warn(&adapter->dev,
1317*4882a593Smuzhiyun 			 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
1318*4882a593Smuzhiyun 		return -EIO;
1319*4882a593Smuzhiyun 	}
1320*4882a593Smuzhiyun 
1321*4882a593Smuzhiyun 	rj54n1 = devm_kzalloc(&client->dev, sizeof(struct rj54n1), GFP_KERNEL);
1322*4882a593Smuzhiyun 	if (!rj54n1)
1323*4882a593Smuzhiyun 		return -ENOMEM;
1324*4882a593Smuzhiyun 
1325*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(&rj54n1->subdev, client, &rj54n1_subdev_ops);
1326*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&rj54n1->hdl, 4);
1327*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1328*4882a593Smuzhiyun 			V4L2_CID_VFLIP, 0, 1, 1, 0);
1329*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1330*4882a593Smuzhiyun 			V4L2_CID_HFLIP, 0, 1, 1, 0);
1331*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1332*4882a593Smuzhiyun 			V4L2_CID_GAIN, 0, 127, 1, 66);
1333*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1334*4882a593Smuzhiyun 			V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1335*4882a593Smuzhiyun 	rj54n1->subdev.ctrl_handler = &rj54n1->hdl;
1336*4882a593Smuzhiyun 	if (rj54n1->hdl.error)
1337*4882a593Smuzhiyun 		return rj54n1->hdl.error;
1338*4882a593Smuzhiyun 
1339*4882a593Smuzhiyun 	rj54n1->clk_div		= clk_div;
1340*4882a593Smuzhiyun 	rj54n1->rect.left	= RJ54N1_COLUMN_SKIP;
1341*4882a593Smuzhiyun 	rj54n1->rect.top	= RJ54N1_ROW_SKIP;
1342*4882a593Smuzhiyun 	rj54n1->rect.width	= RJ54N1_MAX_WIDTH;
1343*4882a593Smuzhiyun 	rj54n1->rect.height	= RJ54N1_MAX_HEIGHT;
1344*4882a593Smuzhiyun 	rj54n1->width		= RJ54N1_MAX_WIDTH;
1345*4882a593Smuzhiyun 	rj54n1->height		= RJ54N1_MAX_HEIGHT;
1346*4882a593Smuzhiyun 	rj54n1->fmt		= &rj54n1_colour_fmts[0];
1347*4882a593Smuzhiyun 	rj54n1->resize		= 1024;
1348*4882a593Smuzhiyun 	rj54n1->tgclk_mhz	= (rj54n1_priv->mclk_freq / PLL_L * PLL_N) /
1349*4882a593Smuzhiyun 		(clk_div.ratio_tg + 1) / (clk_div.ratio_t + 1);
1350*4882a593Smuzhiyun 
1351*4882a593Smuzhiyun 	rj54n1->clk = clk_get(&client->dev, NULL);
1352*4882a593Smuzhiyun 	if (IS_ERR(rj54n1->clk)) {
1353*4882a593Smuzhiyun 		ret = PTR_ERR(rj54n1->clk);
1354*4882a593Smuzhiyun 		goto err_free_ctrl;
1355*4882a593Smuzhiyun 	}
1356*4882a593Smuzhiyun 
1357*4882a593Smuzhiyun 	rj54n1->pwup_gpio = gpiod_get_optional(&client->dev, "powerup",
1358*4882a593Smuzhiyun 					       GPIOD_OUT_LOW);
1359*4882a593Smuzhiyun 	if (IS_ERR(rj54n1->pwup_gpio)) {
1360*4882a593Smuzhiyun 		dev_info(&client->dev, "Unable to get GPIO \"powerup\": %ld\n",
1361*4882a593Smuzhiyun 			 PTR_ERR(rj54n1->pwup_gpio));
1362*4882a593Smuzhiyun 		ret = PTR_ERR(rj54n1->pwup_gpio);
1363*4882a593Smuzhiyun 		goto err_clk_put;
1364*4882a593Smuzhiyun 	}
1365*4882a593Smuzhiyun 
1366*4882a593Smuzhiyun 	rj54n1->enable_gpio = gpiod_get_optional(&client->dev, "enable",
1367*4882a593Smuzhiyun 						 GPIOD_OUT_LOW);
1368*4882a593Smuzhiyun 	if (IS_ERR(rj54n1->enable_gpio)) {
1369*4882a593Smuzhiyun 		dev_info(&client->dev, "Unable to get GPIO \"enable\": %ld\n",
1370*4882a593Smuzhiyun 			 PTR_ERR(rj54n1->enable_gpio));
1371*4882a593Smuzhiyun 		ret = PTR_ERR(rj54n1->enable_gpio);
1372*4882a593Smuzhiyun 		goto err_gpio_put;
1373*4882a593Smuzhiyun 	}
1374*4882a593Smuzhiyun 
1375*4882a593Smuzhiyun 	ret = rj54n1_video_probe(client, rj54n1_priv);
1376*4882a593Smuzhiyun 	if (ret < 0)
1377*4882a593Smuzhiyun 		goto err_gpio_put;
1378*4882a593Smuzhiyun 
1379*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev(&rj54n1->subdev);
1380*4882a593Smuzhiyun 	if (ret)
1381*4882a593Smuzhiyun 		goto err_gpio_put;
1382*4882a593Smuzhiyun 
1383*4882a593Smuzhiyun 	return 0;
1384*4882a593Smuzhiyun 
1385*4882a593Smuzhiyun err_gpio_put:
1386*4882a593Smuzhiyun 	if (rj54n1->enable_gpio)
1387*4882a593Smuzhiyun 		gpiod_put(rj54n1->enable_gpio);
1388*4882a593Smuzhiyun 
1389*4882a593Smuzhiyun 	if (rj54n1->pwup_gpio)
1390*4882a593Smuzhiyun 		gpiod_put(rj54n1->pwup_gpio);
1391*4882a593Smuzhiyun 
1392*4882a593Smuzhiyun err_clk_put:
1393*4882a593Smuzhiyun 	clk_put(rj54n1->clk);
1394*4882a593Smuzhiyun 
1395*4882a593Smuzhiyun err_free_ctrl:
1396*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&rj54n1->hdl);
1397*4882a593Smuzhiyun 
1398*4882a593Smuzhiyun 	return ret;
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun 
rj54n1_remove(struct i2c_client * client)1401*4882a593Smuzhiyun static int rj54n1_remove(struct i2c_client *client)
1402*4882a593Smuzhiyun {
1403*4882a593Smuzhiyun 	struct rj54n1 *rj54n1 = to_rj54n1(client);
1404*4882a593Smuzhiyun 
1405*4882a593Smuzhiyun 	if (rj54n1->enable_gpio)
1406*4882a593Smuzhiyun 		gpiod_put(rj54n1->enable_gpio);
1407*4882a593Smuzhiyun 	if (rj54n1->pwup_gpio)
1408*4882a593Smuzhiyun 		gpiod_put(rj54n1->pwup_gpio);
1409*4882a593Smuzhiyun 
1410*4882a593Smuzhiyun 	clk_put(rj54n1->clk);
1411*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&rj54n1->hdl);
1412*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(&rj54n1->subdev);
1413*4882a593Smuzhiyun 
1414*4882a593Smuzhiyun 	return 0;
1415*4882a593Smuzhiyun }
1416*4882a593Smuzhiyun 
1417*4882a593Smuzhiyun static const struct i2c_device_id rj54n1_id[] = {
1418*4882a593Smuzhiyun 	{ "rj54n1cb0c", 0 },
1419*4882a593Smuzhiyun 	{ }
1420*4882a593Smuzhiyun };
1421*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, rj54n1_id);
1422*4882a593Smuzhiyun 
1423*4882a593Smuzhiyun static struct i2c_driver rj54n1_i2c_driver = {
1424*4882a593Smuzhiyun 	.driver = {
1425*4882a593Smuzhiyun 		.name = "rj54n1cb0c",
1426*4882a593Smuzhiyun 	},
1427*4882a593Smuzhiyun 	.probe		= rj54n1_probe,
1428*4882a593Smuzhiyun 	.remove		= rj54n1_remove,
1429*4882a593Smuzhiyun 	.id_table	= rj54n1_id,
1430*4882a593Smuzhiyun };
1431*4882a593Smuzhiyun 
1432*4882a593Smuzhiyun module_i2c_driver(rj54n1_i2c_driver);
1433*4882a593Smuzhiyun 
1434*4882a593Smuzhiyun MODULE_DESCRIPTION("Sharp RJ54N1CB0C Camera driver");
1435*4882a593Smuzhiyun MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1436*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1437