1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * OmniVision OV96xx Camera Header File 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__ 9*4882a593Smuzhiyun #define __DRIVERS_MEDIA_VIDEO_OV9640_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* Register definitions */ 12*4882a593Smuzhiyun #define OV9640_GAIN 0x00 13*4882a593Smuzhiyun #define OV9640_BLUE 0x01 14*4882a593Smuzhiyun #define OV9640_RED 0x02 15*4882a593Smuzhiyun #define OV9640_VFER 0x03 16*4882a593Smuzhiyun #define OV9640_COM1 0x04 17*4882a593Smuzhiyun #define OV9640_BAVE 0x05 18*4882a593Smuzhiyun #define OV9640_GEAVE 0x06 19*4882a593Smuzhiyun #define OV9640_RSID 0x07 20*4882a593Smuzhiyun #define OV9640_RAVE 0x08 21*4882a593Smuzhiyun #define OV9640_COM2 0x09 22*4882a593Smuzhiyun #define OV9640_PID 0x0a 23*4882a593Smuzhiyun #define OV9640_VER 0x0b 24*4882a593Smuzhiyun #define OV9640_COM3 0x0c 25*4882a593Smuzhiyun #define OV9640_COM4 0x0d 26*4882a593Smuzhiyun #define OV9640_COM5 0x0e 27*4882a593Smuzhiyun #define OV9640_COM6 0x0f 28*4882a593Smuzhiyun #define OV9640_AECH 0x10 29*4882a593Smuzhiyun #define OV9640_CLKRC 0x11 30*4882a593Smuzhiyun #define OV9640_COM7 0x12 31*4882a593Smuzhiyun #define OV9640_COM8 0x13 32*4882a593Smuzhiyun #define OV9640_COM9 0x14 33*4882a593Smuzhiyun #define OV9640_COM10 0x15 34*4882a593Smuzhiyun /* 0x16 - RESERVED */ 35*4882a593Smuzhiyun #define OV9640_HSTART 0x17 36*4882a593Smuzhiyun #define OV9640_HSTOP 0x18 37*4882a593Smuzhiyun #define OV9640_VSTART 0x19 38*4882a593Smuzhiyun #define OV9640_VSTOP 0x1a 39*4882a593Smuzhiyun #define OV9640_PSHFT 0x1b 40*4882a593Smuzhiyun #define OV9640_MIDH 0x1c 41*4882a593Smuzhiyun #define OV9640_MIDL 0x1d 42*4882a593Smuzhiyun #define OV9640_MVFP 0x1e 43*4882a593Smuzhiyun #define OV9640_LAEC 0x1f 44*4882a593Smuzhiyun #define OV9640_BOS 0x20 45*4882a593Smuzhiyun #define OV9640_GBOS 0x21 46*4882a593Smuzhiyun #define OV9640_GROS 0x22 47*4882a593Smuzhiyun #define OV9640_ROS 0x23 48*4882a593Smuzhiyun #define OV9640_AEW 0x24 49*4882a593Smuzhiyun #define OV9640_AEB 0x25 50*4882a593Smuzhiyun #define OV9640_VPT 0x26 51*4882a593Smuzhiyun #define OV9640_BBIAS 0x27 52*4882a593Smuzhiyun #define OV9640_GBBIAS 0x28 53*4882a593Smuzhiyun /* 0x29 - RESERVED */ 54*4882a593Smuzhiyun #define OV9640_EXHCH 0x2a 55*4882a593Smuzhiyun #define OV9640_EXHCL 0x2b 56*4882a593Smuzhiyun #define OV9640_RBIAS 0x2c 57*4882a593Smuzhiyun #define OV9640_ADVFL 0x2d 58*4882a593Smuzhiyun #define OV9640_ADVFH 0x2e 59*4882a593Smuzhiyun #define OV9640_YAVE 0x2f 60*4882a593Smuzhiyun #define OV9640_HSYST 0x30 61*4882a593Smuzhiyun #define OV9640_HSYEN 0x31 62*4882a593Smuzhiyun #define OV9640_HREF 0x32 63*4882a593Smuzhiyun #define OV9640_CHLF 0x33 64*4882a593Smuzhiyun #define OV9640_ARBLM 0x34 65*4882a593Smuzhiyun /* 0x35..0x36 - RESERVED */ 66*4882a593Smuzhiyun #define OV9640_ADC 0x37 67*4882a593Smuzhiyun #define OV9640_ACOM 0x38 68*4882a593Smuzhiyun #define OV9640_OFON 0x39 69*4882a593Smuzhiyun #define OV9640_TSLB 0x3a 70*4882a593Smuzhiyun #define OV9640_COM11 0x3b 71*4882a593Smuzhiyun #define OV9640_COM12 0x3c 72*4882a593Smuzhiyun #define OV9640_COM13 0x3d 73*4882a593Smuzhiyun #define OV9640_COM14 0x3e 74*4882a593Smuzhiyun #define OV9640_EDGE 0x3f 75*4882a593Smuzhiyun #define OV9640_COM15 0x40 76*4882a593Smuzhiyun #define OV9640_COM16 0x41 77*4882a593Smuzhiyun #define OV9640_COM17 0x42 78*4882a593Smuzhiyun /* 0x43..0x4e - RESERVED */ 79*4882a593Smuzhiyun #define OV9640_MTX1 0x4f 80*4882a593Smuzhiyun #define OV9640_MTX2 0x50 81*4882a593Smuzhiyun #define OV9640_MTX3 0x51 82*4882a593Smuzhiyun #define OV9640_MTX4 0x52 83*4882a593Smuzhiyun #define OV9640_MTX5 0x53 84*4882a593Smuzhiyun #define OV9640_MTX6 0x54 85*4882a593Smuzhiyun #define OV9640_MTX7 0x55 86*4882a593Smuzhiyun #define OV9640_MTX8 0x56 87*4882a593Smuzhiyun #define OV9640_MTX9 0x57 88*4882a593Smuzhiyun #define OV9640_MTXS 0x58 89*4882a593Smuzhiyun /* 0x59..0x61 - RESERVED */ 90*4882a593Smuzhiyun #define OV9640_LCC1 0x62 91*4882a593Smuzhiyun #define OV9640_LCC2 0x63 92*4882a593Smuzhiyun #define OV9640_LCC3 0x64 93*4882a593Smuzhiyun #define OV9640_LCC4 0x65 94*4882a593Smuzhiyun #define OV9640_LCC5 0x66 95*4882a593Smuzhiyun #define OV9640_MANU 0x67 96*4882a593Smuzhiyun #define OV9640_MANV 0x68 97*4882a593Smuzhiyun #define OV9640_HV 0x69 98*4882a593Smuzhiyun #define OV9640_MBD 0x6a 99*4882a593Smuzhiyun #define OV9640_DBLV 0x6b 100*4882a593Smuzhiyun #define OV9640_GSP 0x6c /* ... till 0x7b */ 101*4882a593Smuzhiyun #define OV9640_GST 0x7c /* ... till 0x8a */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #define OV9640_CLKRC_DPLL_EN 0x80 104*4882a593Smuzhiyun #define OV9640_CLKRC_DIRECT 0x40 105*4882a593Smuzhiyun #define OV9640_CLKRC_DIV(x) ((x) & 0x3f) 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define OV9640_PSHFT_VAL(x) ((x) & 0xff) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define OV9640_ACOM_2X_ANALOG 0x80 110*4882a593Smuzhiyun #define OV9640_ACOM_RSVD 0x12 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define OV9640_MVFP_V 0x10 113*4882a593Smuzhiyun #define OV9640_MVFP_H 0x20 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define OV9640_COM1_HREF_NOSKIP 0x00 116*4882a593Smuzhiyun #define OV9640_COM1_HREF_2SKIP 0x04 117*4882a593Smuzhiyun #define OV9640_COM1_HREF_3SKIP 0x08 118*4882a593Smuzhiyun #define OV9640_COM1_QQFMT 0x20 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define OV9640_COM2_SSM 0x10 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun #define OV9640_COM3_VP 0x04 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define OV9640_COM4_QQ_VP 0x80 125*4882a593Smuzhiyun #define OV9640_COM4_RSVD 0x40 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define OV9640_COM5_SYSCLK 0x80 128*4882a593Smuzhiyun #define OV9640_COM5_LONGEXP 0x01 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define OV9640_COM6_OPT_BLC 0x40 131*4882a593Smuzhiyun #define OV9640_COM6_ADBLC_BIAS 0x08 132*4882a593Smuzhiyun #define OV9640_COM6_FMT_RST 0x82 133*4882a593Smuzhiyun #define OV9640_COM6_ADBLC_OPTEN 0x01 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define OV9640_COM7_RAW_RGB 0x01 136*4882a593Smuzhiyun #define OV9640_COM7_RGB 0x04 137*4882a593Smuzhiyun #define OV9640_COM7_QCIF 0x08 138*4882a593Smuzhiyun #define OV9640_COM7_QVGA 0x10 139*4882a593Smuzhiyun #define OV9640_COM7_CIF 0x20 140*4882a593Smuzhiyun #define OV9640_COM7_VGA 0x40 141*4882a593Smuzhiyun #define OV9640_COM7_SCCB_RESET 0x80 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #define OV9640_TSLB_YVYU_YUYV 0x04 144*4882a593Smuzhiyun #define OV9640_TSLB_YUYV_UYVY 0x08 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define OV9640_COM12_YUV_AVG 0x04 147*4882a593Smuzhiyun #define OV9640_COM12_RSVD 0x40 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define OV9640_COM13_GAMMA_NONE 0x00 150*4882a593Smuzhiyun #define OV9640_COM13_GAMMA_Y 0x40 151*4882a593Smuzhiyun #define OV9640_COM13_GAMMA_RAW 0x80 152*4882a593Smuzhiyun #define OV9640_COM13_RGB_AVG 0x20 153*4882a593Smuzhiyun #define OV9640_COM13_MATRIX_EN 0x10 154*4882a593Smuzhiyun #define OV9640_COM13_Y_DELAY_EN 0x08 155*4882a593Smuzhiyun #define OV9640_COM13_YUV_DLY(x) ((x) & 0x07) 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #define OV9640_COM15_OR_00FF 0x00 158*4882a593Smuzhiyun #define OV9640_COM15_OR_01FE 0x40 159*4882a593Smuzhiyun #define OV9640_COM15_OR_10F0 0xc0 160*4882a593Smuzhiyun #define OV9640_COM15_RGB_NORM 0x00 161*4882a593Smuzhiyun #define OV9640_COM15_RGB_565 0x10 162*4882a593Smuzhiyun #define OV9640_COM15_RGB_555 0x30 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define OV9640_COM16_RB_AVG 0x01 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* IDs */ 167*4882a593Smuzhiyun #define OV9640_V2 0x9648 168*4882a593Smuzhiyun #define OV9640_V3 0x9649 169*4882a593Smuzhiyun #define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF)) 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* supported resolutions */ 172*4882a593Smuzhiyun enum { 173*4882a593Smuzhiyun W_QQCIF = 88, 174*4882a593Smuzhiyun W_QQVGA = 160, 175*4882a593Smuzhiyun W_QCIF = 176, 176*4882a593Smuzhiyun W_QVGA = 320, 177*4882a593Smuzhiyun W_CIF = 352, 178*4882a593Smuzhiyun W_VGA = 640, 179*4882a593Smuzhiyun W_SXGA = 1280 180*4882a593Smuzhiyun }; 181*4882a593Smuzhiyun #define H_SXGA 960 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* Misc. structures */ 184*4882a593Smuzhiyun struct ov9640_reg_alt { 185*4882a593Smuzhiyun u8 com7; 186*4882a593Smuzhiyun u8 com12; 187*4882a593Smuzhiyun u8 com13; 188*4882a593Smuzhiyun u8 com15; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun struct ov9640_reg { 192*4882a593Smuzhiyun u8 reg; 193*4882a593Smuzhiyun u8 val; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun struct ov9640_priv { 197*4882a593Smuzhiyun struct v4l2_subdev subdev; 198*4882a593Smuzhiyun struct v4l2_ctrl_handler hdl; 199*4882a593Smuzhiyun struct v4l2_clk *clk; 200*4882a593Smuzhiyun struct gpio_desc *gpio_power; 201*4882a593Smuzhiyun struct gpio_desc *gpio_reset; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun int model; 204*4882a593Smuzhiyun int revision; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */ 208