1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2019 Intel Corporation.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <asm/unaligned.h>
5*4882a593Smuzhiyun #include <linux/acpi.h>
6*4882a593Smuzhiyun #include <linux/clk.h>
7*4882a593Smuzhiyun #include <linux/delay.h>
8*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/pm_runtime.h>
12*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
13*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
14*4882a593Smuzhiyun #include <media/v4l2-device.h>
15*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define OV8856_REG_VALUE_08BIT 1
18*4882a593Smuzhiyun #define OV8856_REG_VALUE_16BIT 2
19*4882a593Smuzhiyun #define OV8856_REG_VALUE_24BIT 3
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define OV8856_LINK_FREQ_360MHZ 360000000ULL
22*4882a593Smuzhiyun #define OV8856_LINK_FREQ_180MHZ 180000000ULL
23*4882a593Smuzhiyun #define OV8856_SCLK 144000000ULL
24*4882a593Smuzhiyun #define OV8856_XVCLK_19_2 19200000
25*4882a593Smuzhiyun #define OV8856_DATA_LANES 4
26*4882a593Smuzhiyun #define OV8856_RGB_DEPTH 10
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define OV8856_REG_CHIP_ID 0x300a
29*4882a593Smuzhiyun #define OV8856_CHIP_ID 0x00885a
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define OV8856_REG_MODE_SELECT 0x0100
32*4882a593Smuzhiyun #define OV8856_MODE_STANDBY 0x00
33*4882a593Smuzhiyun #define OV8856_MODE_STREAMING 0x01
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* module revisions */
36*4882a593Smuzhiyun #define OV8856_2A_MODULE 0x01
37*4882a593Smuzhiyun #define OV8856_1B_MODULE 0x02
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* the OTP read-out buffer is at 0x7000 and 0xf is the offset
40*4882a593Smuzhiyun * of the byte in the OTP that means the module revision
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun #define OV8856_MODULE_REVISION 0x700f
43*4882a593Smuzhiyun #define OV8856_OTP_MODE_CTRL 0x3d84
44*4882a593Smuzhiyun #define OV8856_OTP_LOAD_CTRL 0x3d81
45*4882a593Smuzhiyun #define OV8856_OTP_MODE_AUTO 0x00
46*4882a593Smuzhiyun #define OV8856_OTP_LOAD_CTRL_ENABLE BIT(0)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* vertical-timings from sensor */
49*4882a593Smuzhiyun #define OV8856_REG_VTS 0x380e
50*4882a593Smuzhiyun #define OV8856_VTS_MAX 0x7fff
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* horizontal-timings from sensor */
53*4882a593Smuzhiyun #define OV8856_REG_HTS 0x380c
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Exposure controls from sensor */
56*4882a593Smuzhiyun #define OV8856_REG_EXPOSURE 0x3500
57*4882a593Smuzhiyun #define OV8856_EXPOSURE_MIN 6
58*4882a593Smuzhiyun #define OV8856_EXPOSURE_MAX_MARGIN 6
59*4882a593Smuzhiyun #define OV8856_EXPOSURE_STEP 1
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Analog gain controls from sensor */
62*4882a593Smuzhiyun #define OV8856_REG_ANALOG_GAIN 0x3508
63*4882a593Smuzhiyun #define OV8856_ANAL_GAIN_MIN 128
64*4882a593Smuzhiyun #define OV8856_ANAL_GAIN_MAX 2047
65*4882a593Smuzhiyun #define OV8856_ANAL_GAIN_STEP 1
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Digital gain controls from sensor */
68*4882a593Smuzhiyun #define OV8856_REG_MWB_R_GAIN 0x5019
69*4882a593Smuzhiyun #define OV8856_REG_MWB_G_GAIN 0x501b
70*4882a593Smuzhiyun #define OV8856_REG_MWB_B_GAIN 0x501d
71*4882a593Smuzhiyun #define OV8856_DGTL_GAIN_MIN 0
72*4882a593Smuzhiyun #define OV8856_DGTL_GAIN_MAX 4095
73*4882a593Smuzhiyun #define OV8856_DGTL_GAIN_STEP 1
74*4882a593Smuzhiyun #define OV8856_DGTL_GAIN_DEFAULT 1024
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Test Pattern Control */
77*4882a593Smuzhiyun #define OV8856_REG_TEST_PATTERN 0x5e00
78*4882a593Smuzhiyun #define OV8856_TEST_PATTERN_ENABLE BIT(7)
79*4882a593Smuzhiyun #define OV8856_TEST_PATTERN_BAR_SHIFT 2
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define to_ov8856(_sd) container_of(_sd, struct ov8856, sd)
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun static const char * const ov8856_supply_names[] = {
84*4882a593Smuzhiyun "dovdd", /* Digital I/O power */
85*4882a593Smuzhiyun "avdd", /* Analog power */
86*4882a593Smuzhiyun "dvdd", /* Digital core power */
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun enum {
90*4882a593Smuzhiyun OV8856_LINK_FREQ_720MBPS,
91*4882a593Smuzhiyun OV8856_LINK_FREQ_360MBPS,
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun struct ov8856_reg {
95*4882a593Smuzhiyun u16 address;
96*4882a593Smuzhiyun u8 val;
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct ov8856_reg_list {
100*4882a593Smuzhiyun u32 num_of_regs;
101*4882a593Smuzhiyun const struct ov8856_reg *regs;
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun struct ov8856_link_freq_config {
105*4882a593Smuzhiyun const struct ov8856_reg_list reg_list;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun struct ov8856_mode {
109*4882a593Smuzhiyun /* Frame width in pixels */
110*4882a593Smuzhiyun u32 width;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Frame height in pixels */
113*4882a593Smuzhiyun u32 height;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun /* Horizontal timining size */
116*4882a593Smuzhiyun u32 hts;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* Default vertical timining size */
119*4882a593Smuzhiyun u32 vts_def;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /* Min vertical timining size */
122*4882a593Smuzhiyun u32 vts_min;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* Link frequency needed for this resolution */
125*4882a593Smuzhiyun u32 link_freq_index;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* Sensor register settings for this resolution */
128*4882a593Smuzhiyun const struct ov8856_reg_list reg_list;
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun static const struct ov8856_reg mipi_data_rate_720mbps[] = {
132*4882a593Smuzhiyun {0x0103, 0x01},
133*4882a593Smuzhiyun {0x0100, 0x00},
134*4882a593Smuzhiyun {0x0302, 0x4b},
135*4882a593Smuzhiyun {0x0303, 0x01},
136*4882a593Smuzhiyun {0x030b, 0x02},
137*4882a593Smuzhiyun {0x030d, 0x4b},
138*4882a593Smuzhiyun {0x031e, 0x0c},
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun static const struct ov8856_reg mipi_data_rate_360mbps[] = {
142*4882a593Smuzhiyun {0x0103, 0x01},
143*4882a593Smuzhiyun {0x0100, 0x00},
144*4882a593Smuzhiyun {0x0302, 0x4b},
145*4882a593Smuzhiyun {0x0303, 0x03},
146*4882a593Smuzhiyun {0x030b, 0x02},
147*4882a593Smuzhiyun {0x030d, 0x4b},
148*4882a593Smuzhiyun {0x031e, 0x0c},
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct ov8856_reg mode_3280x2464_regs[] = {
152*4882a593Smuzhiyun {0x3000, 0x20},
153*4882a593Smuzhiyun {0x3003, 0x08},
154*4882a593Smuzhiyun {0x300e, 0x20},
155*4882a593Smuzhiyun {0x3010, 0x00},
156*4882a593Smuzhiyun {0x3015, 0x84},
157*4882a593Smuzhiyun {0x3018, 0x72},
158*4882a593Smuzhiyun {0x3021, 0x23},
159*4882a593Smuzhiyun {0x3033, 0x24},
160*4882a593Smuzhiyun {0x3500, 0x00},
161*4882a593Smuzhiyun {0x3501, 0x9a},
162*4882a593Smuzhiyun {0x3502, 0x20},
163*4882a593Smuzhiyun {0x3503, 0x08},
164*4882a593Smuzhiyun {0x3505, 0x83},
165*4882a593Smuzhiyun {0x3508, 0x01},
166*4882a593Smuzhiyun {0x3509, 0x80},
167*4882a593Smuzhiyun {0x350c, 0x00},
168*4882a593Smuzhiyun {0x350d, 0x80},
169*4882a593Smuzhiyun {0x350e, 0x04},
170*4882a593Smuzhiyun {0x350f, 0x00},
171*4882a593Smuzhiyun {0x3510, 0x00},
172*4882a593Smuzhiyun {0x3511, 0x02},
173*4882a593Smuzhiyun {0x3512, 0x00},
174*4882a593Smuzhiyun {0x3600, 0x72},
175*4882a593Smuzhiyun {0x3601, 0x40},
176*4882a593Smuzhiyun {0x3602, 0x30},
177*4882a593Smuzhiyun {0x3610, 0xc5},
178*4882a593Smuzhiyun {0x3611, 0x58},
179*4882a593Smuzhiyun {0x3612, 0x5c},
180*4882a593Smuzhiyun {0x3613, 0xca},
181*4882a593Smuzhiyun {0x3614, 0x20},
182*4882a593Smuzhiyun {0x3628, 0xff},
183*4882a593Smuzhiyun {0x3629, 0xff},
184*4882a593Smuzhiyun {0x362a, 0xff},
185*4882a593Smuzhiyun {0x3633, 0x10},
186*4882a593Smuzhiyun {0x3634, 0x10},
187*4882a593Smuzhiyun {0x3635, 0x10},
188*4882a593Smuzhiyun {0x3636, 0x10},
189*4882a593Smuzhiyun {0x3663, 0x08},
190*4882a593Smuzhiyun {0x3669, 0x34},
191*4882a593Smuzhiyun {0x366e, 0x10},
192*4882a593Smuzhiyun {0x3706, 0x86},
193*4882a593Smuzhiyun {0x370b, 0x7e},
194*4882a593Smuzhiyun {0x3714, 0x23},
195*4882a593Smuzhiyun {0x3730, 0x12},
196*4882a593Smuzhiyun {0x3733, 0x10},
197*4882a593Smuzhiyun {0x3764, 0x00},
198*4882a593Smuzhiyun {0x3765, 0x00},
199*4882a593Smuzhiyun {0x3769, 0x62},
200*4882a593Smuzhiyun {0x376a, 0x2a},
201*4882a593Smuzhiyun {0x376b, 0x30},
202*4882a593Smuzhiyun {0x3780, 0x00},
203*4882a593Smuzhiyun {0x3781, 0x24},
204*4882a593Smuzhiyun {0x3782, 0x00},
205*4882a593Smuzhiyun {0x3783, 0x23},
206*4882a593Smuzhiyun {0x3798, 0x2f},
207*4882a593Smuzhiyun {0x37a1, 0x60},
208*4882a593Smuzhiyun {0x37a8, 0x6a},
209*4882a593Smuzhiyun {0x37ab, 0x3f},
210*4882a593Smuzhiyun {0x37c2, 0x04},
211*4882a593Smuzhiyun {0x37c3, 0xf1},
212*4882a593Smuzhiyun {0x37c9, 0x80},
213*4882a593Smuzhiyun {0x37cb, 0x16},
214*4882a593Smuzhiyun {0x37cc, 0x16},
215*4882a593Smuzhiyun {0x37cd, 0x16},
216*4882a593Smuzhiyun {0x37ce, 0x16},
217*4882a593Smuzhiyun {0x3800, 0x00},
218*4882a593Smuzhiyun {0x3801, 0x00},
219*4882a593Smuzhiyun {0x3802, 0x00},
220*4882a593Smuzhiyun {0x3803, 0x06},
221*4882a593Smuzhiyun {0x3804, 0x0c},
222*4882a593Smuzhiyun {0x3805, 0xdf},
223*4882a593Smuzhiyun {0x3806, 0x09},
224*4882a593Smuzhiyun {0x3807, 0xa7},
225*4882a593Smuzhiyun {0x3808, 0x0c},
226*4882a593Smuzhiyun {0x3809, 0xd0},
227*4882a593Smuzhiyun {0x380a, 0x09},
228*4882a593Smuzhiyun {0x380b, 0xa0},
229*4882a593Smuzhiyun {0x380c, 0x07},
230*4882a593Smuzhiyun {0x380d, 0x88},
231*4882a593Smuzhiyun {0x380e, 0x09},
232*4882a593Smuzhiyun {0x380f, 0xb8},
233*4882a593Smuzhiyun {0x3810, 0x00},
234*4882a593Smuzhiyun {0x3811, 0x00},
235*4882a593Smuzhiyun {0x3812, 0x00},
236*4882a593Smuzhiyun {0x3813, 0x01},
237*4882a593Smuzhiyun {0x3814, 0x01},
238*4882a593Smuzhiyun {0x3815, 0x01},
239*4882a593Smuzhiyun {0x3816, 0x00},
240*4882a593Smuzhiyun {0x3817, 0x00},
241*4882a593Smuzhiyun {0x3818, 0x00},
242*4882a593Smuzhiyun {0x3819, 0x10},
243*4882a593Smuzhiyun {0x3820, 0x80},
244*4882a593Smuzhiyun {0x3821, 0x46},
245*4882a593Smuzhiyun {0x382a, 0x01},
246*4882a593Smuzhiyun {0x382b, 0x01},
247*4882a593Smuzhiyun {0x3830, 0x06},
248*4882a593Smuzhiyun {0x3836, 0x02},
249*4882a593Smuzhiyun {0x3862, 0x04},
250*4882a593Smuzhiyun {0x3863, 0x08},
251*4882a593Smuzhiyun {0x3cc0, 0x33},
252*4882a593Smuzhiyun {0x3d85, 0x17},
253*4882a593Smuzhiyun {0x3d8c, 0x73},
254*4882a593Smuzhiyun {0x3d8d, 0xde},
255*4882a593Smuzhiyun {0x4001, 0xe0},
256*4882a593Smuzhiyun {0x4003, 0x40},
257*4882a593Smuzhiyun {0x4008, 0x00},
258*4882a593Smuzhiyun {0x4009, 0x0b},
259*4882a593Smuzhiyun {0x400a, 0x00},
260*4882a593Smuzhiyun {0x400b, 0x84},
261*4882a593Smuzhiyun {0x400f, 0x80},
262*4882a593Smuzhiyun {0x4010, 0xf0},
263*4882a593Smuzhiyun {0x4011, 0xff},
264*4882a593Smuzhiyun {0x4012, 0x02},
265*4882a593Smuzhiyun {0x4013, 0x01},
266*4882a593Smuzhiyun {0x4014, 0x01},
267*4882a593Smuzhiyun {0x4015, 0x01},
268*4882a593Smuzhiyun {0x4042, 0x00},
269*4882a593Smuzhiyun {0x4043, 0x80},
270*4882a593Smuzhiyun {0x4044, 0x00},
271*4882a593Smuzhiyun {0x4045, 0x80},
272*4882a593Smuzhiyun {0x4046, 0x00},
273*4882a593Smuzhiyun {0x4047, 0x80},
274*4882a593Smuzhiyun {0x4048, 0x00},
275*4882a593Smuzhiyun {0x4049, 0x80},
276*4882a593Smuzhiyun {0x4041, 0x03},
277*4882a593Smuzhiyun {0x404c, 0x20},
278*4882a593Smuzhiyun {0x404d, 0x00},
279*4882a593Smuzhiyun {0x404e, 0x20},
280*4882a593Smuzhiyun {0x4203, 0x80},
281*4882a593Smuzhiyun {0x4307, 0x30},
282*4882a593Smuzhiyun {0x4317, 0x00},
283*4882a593Smuzhiyun {0x4503, 0x08},
284*4882a593Smuzhiyun {0x4601, 0x80},
285*4882a593Smuzhiyun {0x4800, 0x44},
286*4882a593Smuzhiyun {0x4816, 0x53},
287*4882a593Smuzhiyun {0x481b, 0x58},
288*4882a593Smuzhiyun {0x481f, 0x27},
289*4882a593Smuzhiyun {0x4837, 0x16},
290*4882a593Smuzhiyun {0x483c, 0x0f},
291*4882a593Smuzhiyun {0x484b, 0x05},
292*4882a593Smuzhiyun {0x5000, 0x57},
293*4882a593Smuzhiyun {0x5001, 0x0a},
294*4882a593Smuzhiyun {0x5004, 0x04},
295*4882a593Smuzhiyun {0x502e, 0x03},
296*4882a593Smuzhiyun {0x5030, 0x41},
297*4882a593Smuzhiyun {0x5780, 0x14},
298*4882a593Smuzhiyun {0x5781, 0x0f},
299*4882a593Smuzhiyun {0x5782, 0x44},
300*4882a593Smuzhiyun {0x5783, 0x02},
301*4882a593Smuzhiyun {0x5784, 0x01},
302*4882a593Smuzhiyun {0x5785, 0x01},
303*4882a593Smuzhiyun {0x5786, 0x00},
304*4882a593Smuzhiyun {0x5787, 0x04},
305*4882a593Smuzhiyun {0x5788, 0x02},
306*4882a593Smuzhiyun {0x5789, 0x0f},
307*4882a593Smuzhiyun {0x578a, 0xfd},
308*4882a593Smuzhiyun {0x578b, 0xf5},
309*4882a593Smuzhiyun {0x578c, 0xf5},
310*4882a593Smuzhiyun {0x578d, 0x03},
311*4882a593Smuzhiyun {0x578e, 0x08},
312*4882a593Smuzhiyun {0x578f, 0x0c},
313*4882a593Smuzhiyun {0x5790, 0x08},
314*4882a593Smuzhiyun {0x5791, 0x04},
315*4882a593Smuzhiyun {0x5792, 0x00},
316*4882a593Smuzhiyun {0x5793, 0x52},
317*4882a593Smuzhiyun {0x5794, 0xa3},
318*4882a593Smuzhiyun {0x5795, 0x02},
319*4882a593Smuzhiyun {0x5796, 0x20},
320*4882a593Smuzhiyun {0x5797, 0x20},
321*4882a593Smuzhiyun {0x5798, 0xd5},
322*4882a593Smuzhiyun {0x5799, 0xd5},
323*4882a593Smuzhiyun {0x579a, 0x00},
324*4882a593Smuzhiyun {0x579b, 0x50},
325*4882a593Smuzhiyun {0x579c, 0x00},
326*4882a593Smuzhiyun {0x579d, 0x2c},
327*4882a593Smuzhiyun {0x579e, 0x0c},
328*4882a593Smuzhiyun {0x579f, 0x40},
329*4882a593Smuzhiyun {0x57a0, 0x09},
330*4882a593Smuzhiyun {0x57a1, 0x40},
331*4882a593Smuzhiyun {0x59f8, 0x3d},
332*4882a593Smuzhiyun {0x5a08, 0x02},
333*4882a593Smuzhiyun {0x5b00, 0x02},
334*4882a593Smuzhiyun {0x5b01, 0x10},
335*4882a593Smuzhiyun {0x5b02, 0x03},
336*4882a593Smuzhiyun {0x5b03, 0xcf},
337*4882a593Smuzhiyun {0x5b05, 0x6c},
338*4882a593Smuzhiyun {0x5e00, 0x00}
339*4882a593Smuzhiyun };
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun static const struct ov8856_reg mode_3264x2448_regs[] = {
342*4882a593Smuzhiyun {0x0103, 0x01},
343*4882a593Smuzhiyun {0x0302, 0x3c},
344*4882a593Smuzhiyun {0x0303, 0x01},
345*4882a593Smuzhiyun {0x031e, 0x0c},
346*4882a593Smuzhiyun {0x3000, 0x20},
347*4882a593Smuzhiyun {0x3003, 0x08},
348*4882a593Smuzhiyun {0x300e, 0x20},
349*4882a593Smuzhiyun {0x3010, 0x00},
350*4882a593Smuzhiyun {0x3015, 0x84},
351*4882a593Smuzhiyun {0x3018, 0x72},
352*4882a593Smuzhiyun {0x3021, 0x23},
353*4882a593Smuzhiyun {0x3033, 0x24},
354*4882a593Smuzhiyun {0x3500, 0x00},
355*4882a593Smuzhiyun {0x3501, 0x9a},
356*4882a593Smuzhiyun {0x3502, 0x20},
357*4882a593Smuzhiyun {0x3503, 0x08},
358*4882a593Smuzhiyun {0x3505, 0x83},
359*4882a593Smuzhiyun {0x3508, 0x01},
360*4882a593Smuzhiyun {0x3509, 0x80},
361*4882a593Smuzhiyun {0x350c, 0x00},
362*4882a593Smuzhiyun {0x350d, 0x80},
363*4882a593Smuzhiyun {0x350e, 0x04},
364*4882a593Smuzhiyun {0x350f, 0x00},
365*4882a593Smuzhiyun {0x3510, 0x00},
366*4882a593Smuzhiyun {0x3511, 0x02},
367*4882a593Smuzhiyun {0x3512, 0x00},
368*4882a593Smuzhiyun {0x3600, 0x72},
369*4882a593Smuzhiyun {0x3601, 0x40},
370*4882a593Smuzhiyun {0x3602, 0x30},
371*4882a593Smuzhiyun {0x3610, 0xc5},
372*4882a593Smuzhiyun {0x3611, 0x58},
373*4882a593Smuzhiyun {0x3612, 0x5c},
374*4882a593Smuzhiyun {0x3613, 0xca},
375*4882a593Smuzhiyun {0x3614, 0x60},
376*4882a593Smuzhiyun {0x3628, 0xff},
377*4882a593Smuzhiyun {0x3629, 0xff},
378*4882a593Smuzhiyun {0x362a, 0xff},
379*4882a593Smuzhiyun {0x3633, 0x10},
380*4882a593Smuzhiyun {0x3634, 0x10},
381*4882a593Smuzhiyun {0x3635, 0x10},
382*4882a593Smuzhiyun {0x3636, 0x10},
383*4882a593Smuzhiyun {0x3663, 0x08},
384*4882a593Smuzhiyun {0x3669, 0x34},
385*4882a593Smuzhiyun {0x366d, 0x00},
386*4882a593Smuzhiyun {0x366e, 0x10},
387*4882a593Smuzhiyun {0x3706, 0x86},
388*4882a593Smuzhiyun {0x370b, 0x7e},
389*4882a593Smuzhiyun {0x3714, 0x23},
390*4882a593Smuzhiyun {0x3730, 0x12},
391*4882a593Smuzhiyun {0x3733, 0x10},
392*4882a593Smuzhiyun {0x3764, 0x00},
393*4882a593Smuzhiyun {0x3765, 0x00},
394*4882a593Smuzhiyun {0x3769, 0x62},
395*4882a593Smuzhiyun {0x376a, 0x2a},
396*4882a593Smuzhiyun {0x376b, 0x30},
397*4882a593Smuzhiyun {0x3780, 0x00},
398*4882a593Smuzhiyun {0x3781, 0x24},
399*4882a593Smuzhiyun {0x3782, 0x00},
400*4882a593Smuzhiyun {0x3783, 0x23},
401*4882a593Smuzhiyun {0x3798, 0x2f},
402*4882a593Smuzhiyun {0x37a1, 0x60},
403*4882a593Smuzhiyun {0x37a8, 0x6a},
404*4882a593Smuzhiyun {0x37ab, 0x3f},
405*4882a593Smuzhiyun {0x37c2, 0x04},
406*4882a593Smuzhiyun {0x37c3, 0xf1},
407*4882a593Smuzhiyun {0x37c9, 0x80},
408*4882a593Smuzhiyun {0x37cb, 0x16},
409*4882a593Smuzhiyun {0x37cc, 0x16},
410*4882a593Smuzhiyun {0x37cd, 0x16},
411*4882a593Smuzhiyun {0x37ce, 0x16},
412*4882a593Smuzhiyun {0x3800, 0x00},
413*4882a593Smuzhiyun {0x3801, 0x00},
414*4882a593Smuzhiyun {0x3802, 0x00},
415*4882a593Smuzhiyun {0x3803, 0x0c},
416*4882a593Smuzhiyun {0x3804, 0x0c},
417*4882a593Smuzhiyun {0x3805, 0xdf},
418*4882a593Smuzhiyun {0x3806, 0x09},
419*4882a593Smuzhiyun {0x3807, 0xa3},
420*4882a593Smuzhiyun {0x3808, 0x0c},
421*4882a593Smuzhiyun {0x3809, 0xc0},
422*4882a593Smuzhiyun {0x380a, 0x09},
423*4882a593Smuzhiyun {0x380b, 0x90},
424*4882a593Smuzhiyun {0x380c, 0x07},
425*4882a593Smuzhiyun {0x380d, 0x8c},
426*4882a593Smuzhiyun {0x380e, 0x09},
427*4882a593Smuzhiyun {0x380f, 0xb2},
428*4882a593Smuzhiyun {0x3810, 0x00},
429*4882a593Smuzhiyun {0x3811, 0x04},
430*4882a593Smuzhiyun {0x3812, 0x00},
431*4882a593Smuzhiyun {0x3813, 0x02},
432*4882a593Smuzhiyun {0x3814, 0x01},
433*4882a593Smuzhiyun {0x3815, 0x01},
434*4882a593Smuzhiyun {0x3816, 0x00},
435*4882a593Smuzhiyun {0x3817, 0x00},
436*4882a593Smuzhiyun {0x3818, 0x00},
437*4882a593Smuzhiyun {0x3819, 0x10},
438*4882a593Smuzhiyun {0x3820, 0x80},
439*4882a593Smuzhiyun {0x3821, 0x46},
440*4882a593Smuzhiyun {0x382a, 0x01},
441*4882a593Smuzhiyun {0x382b, 0x01},
442*4882a593Smuzhiyun {0x3830, 0x06},
443*4882a593Smuzhiyun {0x3836, 0x02},
444*4882a593Smuzhiyun {0x3862, 0x04},
445*4882a593Smuzhiyun {0x3863, 0x08},
446*4882a593Smuzhiyun {0x3cc0, 0x33},
447*4882a593Smuzhiyun {0x3d85, 0x17},
448*4882a593Smuzhiyun {0x3d8c, 0x73},
449*4882a593Smuzhiyun {0x3d8d, 0xde},
450*4882a593Smuzhiyun {0x4001, 0xe0},
451*4882a593Smuzhiyun {0x4003, 0x40},
452*4882a593Smuzhiyun {0x4008, 0x00},
453*4882a593Smuzhiyun {0x4009, 0x0b},
454*4882a593Smuzhiyun {0x400a, 0x00},
455*4882a593Smuzhiyun {0x400b, 0x84},
456*4882a593Smuzhiyun {0x400f, 0x80},
457*4882a593Smuzhiyun {0x4010, 0xf0},
458*4882a593Smuzhiyun {0x4011, 0xff},
459*4882a593Smuzhiyun {0x4012, 0x02},
460*4882a593Smuzhiyun {0x4013, 0x01},
461*4882a593Smuzhiyun {0x4014, 0x01},
462*4882a593Smuzhiyun {0x4015, 0x01},
463*4882a593Smuzhiyun {0x4042, 0x00},
464*4882a593Smuzhiyun {0x4043, 0x80},
465*4882a593Smuzhiyun {0x4044, 0x00},
466*4882a593Smuzhiyun {0x4045, 0x80},
467*4882a593Smuzhiyun {0x4046, 0x00},
468*4882a593Smuzhiyun {0x4047, 0x80},
469*4882a593Smuzhiyun {0x4048, 0x00},
470*4882a593Smuzhiyun {0x4049, 0x80},
471*4882a593Smuzhiyun {0x4041, 0x03},
472*4882a593Smuzhiyun {0x404c, 0x20},
473*4882a593Smuzhiyun {0x404d, 0x00},
474*4882a593Smuzhiyun {0x404e, 0x20},
475*4882a593Smuzhiyun {0x4203, 0x80},
476*4882a593Smuzhiyun {0x4307, 0x30},
477*4882a593Smuzhiyun {0x4317, 0x00},
478*4882a593Smuzhiyun {0x4502, 0x50},
479*4882a593Smuzhiyun {0x4503, 0x08},
480*4882a593Smuzhiyun {0x4601, 0x80},
481*4882a593Smuzhiyun {0x4800, 0x44},
482*4882a593Smuzhiyun {0x4816, 0x53},
483*4882a593Smuzhiyun {0x481b, 0x50},
484*4882a593Smuzhiyun {0x481f, 0x27},
485*4882a593Smuzhiyun {0x4823, 0x3c},
486*4882a593Smuzhiyun {0x482b, 0x00},
487*4882a593Smuzhiyun {0x4831, 0x66},
488*4882a593Smuzhiyun {0x4837, 0x16},
489*4882a593Smuzhiyun {0x483c, 0x0f},
490*4882a593Smuzhiyun {0x484b, 0x05},
491*4882a593Smuzhiyun {0x5000, 0x77},
492*4882a593Smuzhiyun {0x5001, 0x0a},
493*4882a593Smuzhiyun {0x5003, 0xc8},
494*4882a593Smuzhiyun {0x5004, 0x04},
495*4882a593Smuzhiyun {0x5006, 0x00},
496*4882a593Smuzhiyun {0x5007, 0x00},
497*4882a593Smuzhiyun {0x502e, 0x03},
498*4882a593Smuzhiyun {0x5030, 0x41},
499*4882a593Smuzhiyun {0x5780, 0x14},
500*4882a593Smuzhiyun {0x5781, 0x0f},
501*4882a593Smuzhiyun {0x5782, 0x44},
502*4882a593Smuzhiyun {0x5783, 0x02},
503*4882a593Smuzhiyun {0x5784, 0x01},
504*4882a593Smuzhiyun {0x5785, 0x01},
505*4882a593Smuzhiyun {0x5786, 0x00},
506*4882a593Smuzhiyun {0x5787, 0x04},
507*4882a593Smuzhiyun {0x5788, 0x02},
508*4882a593Smuzhiyun {0x5789, 0x0f},
509*4882a593Smuzhiyun {0x578a, 0xfd},
510*4882a593Smuzhiyun {0x578b, 0xf5},
511*4882a593Smuzhiyun {0x578c, 0xf5},
512*4882a593Smuzhiyun {0x578d, 0x03},
513*4882a593Smuzhiyun {0x578e, 0x08},
514*4882a593Smuzhiyun {0x578f, 0x0c},
515*4882a593Smuzhiyun {0x5790, 0x08},
516*4882a593Smuzhiyun {0x5791, 0x04},
517*4882a593Smuzhiyun {0x5792, 0x00},
518*4882a593Smuzhiyun {0x5793, 0x52},
519*4882a593Smuzhiyun {0x5794, 0xa3},
520*4882a593Smuzhiyun {0x5795, 0x02},
521*4882a593Smuzhiyun {0x5796, 0x20},
522*4882a593Smuzhiyun {0x5797, 0x20},
523*4882a593Smuzhiyun {0x5798, 0xd5},
524*4882a593Smuzhiyun {0x5799, 0xd5},
525*4882a593Smuzhiyun {0x579a, 0x00},
526*4882a593Smuzhiyun {0x579b, 0x50},
527*4882a593Smuzhiyun {0x579c, 0x00},
528*4882a593Smuzhiyun {0x579d, 0x2c},
529*4882a593Smuzhiyun {0x579e, 0x0c},
530*4882a593Smuzhiyun {0x579f, 0x40},
531*4882a593Smuzhiyun {0x57a0, 0x09},
532*4882a593Smuzhiyun {0x57a1, 0x40},
533*4882a593Smuzhiyun {0x59f8, 0x3d},
534*4882a593Smuzhiyun {0x5a08, 0x02},
535*4882a593Smuzhiyun {0x5b00, 0x02},
536*4882a593Smuzhiyun {0x5b01, 0x10},
537*4882a593Smuzhiyun {0x5b02, 0x03},
538*4882a593Smuzhiyun {0x5b03, 0xcf},
539*4882a593Smuzhiyun {0x5b05, 0x6c},
540*4882a593Smuzhiyun {0x5e00, 0x00},
541*4882a593Smuzhiyun {0x5e10, 0xfc}
542*4882a593Smuzhiyun };
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun static const struct ov8856_reg mode_1640x1232_regs[] = {
545*4882a593Smuzhiyun {0x3000, 0x20},
546*4882a593Smuzhiyun {0x3003, 0x08},
547*4882a593Smuzhiyun {0x300e, 0x20},
548*4882a593Smuzhiyun {0x3010, 0x00},
549*4882a593Smuzhiyun {0x3015, 0x84},
550*4882a593Smuzhiyun {0x3018, 0x72},
551*4882a593Smuzhiyun {0x3021, 0x23},
552*4882a593Smuzhiyun {0x3033, 0x24},
553*4882a593Smuzhiyun {0x3500, 0x00},
554*4882a593Smuzhiyun {0x3501, 0x4c},
555*4882a593Smuzhiyun {0x3502, 0xe0},
556*4882a593Smuzhiyun {0x3503, 0x08},
557*4882a593Smuzhiyun {0x3505, 0x83},
558*4882a593Smuzhiyun {0x3508, 0x01},
559*4882a593Smuzhiyun {0x3509, 0x80},
560*4882a593Smuzhiyun {0x350c, 0x00},
561*4882a593Smuzhiyun {0x350d, 0x80},
562*4882a593Smuzhiyun {0x350e, 0x04},
563*4882a593Smuzhiyun {0x350f, 0x00},
564*4882a593Smuzhiyun {0x3510, 0x00},
565*4882a593Smuzhiyun {0x3511, 0x02},
566*4882a593Smuzhiyun {0x3512, 0x00},
567*4882a593Smuzhiyun {0x3600, 0x72},
568*4882a593Smuzhiyun {0x3601, 0x40},
569*4882a593Smuzhiyun {0x3602, 0x30},
570*4882a593Smuzhiyun {0x3610, 0xc5},
571*4882a593Smuzhiyun {0x3611, 0x58},
572*4882a593Smuzhiyun {0x3612, 0x5c},
573*4882a593Smuzhiyun {0x3613, 0xca},
574*4882a593Smuzhiyun {0x3614, 0x20},
575*4882a593Smuzhiyun {0x3628, 0xff},
576*4882a593Smuzhiyun {0x3629, 0xff},
577*4882a593Smuzhiyun {0x362a, 0xff},
578*4882a593Smuzhiyun {0x3633, 0x10},
579*4882a593Smuzhiyun {0x3634, 0x10},
580*4882a593Smuzhiyun {0x3635, 0x10},
581*4882a593Smuzhiyun {0x3636, 0x10},
582*4882a593Smuzhiyun {0x3663, 0x08},
583*4882a593Smuzhiyun {0x3669, 0x34},
584*4882a593Smuzhiyun {0x366e, 0x08},
585*4882a593Smuzhiyun {0x3706, 0x86},
586*4882a593Smuzhiyun {0x370b, 0x7e},
587*4882a593Smuzhiyun {0x3714, 0x27},
588*4882a593Smuzhiyun {0x3730, 0x12},
589*4882a593Smuzhiyun {0x3733, 0x10},
590*4882a593Smuzhiyun {0x3764, 0x00},
591*4882a593Smuzhiyun {0x3765, 0x00},
592*4882a593Smuzhiyun {0x3769, 0x62},
593*4882a593Smuzhiyun {0x376a, 0x2a},
594*4882a593Smuzhiyun {0x376b, 0x30},
595*4882a593Smuzhiyun {0x3780, 0x00},
596*4882a593Smuzhiyun {0x3781, 0x24},
597*4882a593Smuzhiyun {0x3782, 0x00},
598*4882a593Smuzhiyun {0x3783, 0x23},
599*4882a593Smuzhiyun {0x3798, 0x2f},
600*4882a593Smuzhiyun {0x37a1, 0x60},
601*4882a593Smuzhiyun {0x37a8, 0x6a},
602*4882a593Smuzhiyun {0x37ab, 0x3f},
603*4882a593Smuzhiyun {0x37c2, 0x14},
604*4882a593Smuzhiyun {0x37c3, 0xf1},
605*4882a593Smuzhiyun {0x37c9, 0x80},
606*4882a593Smuzhiyun {0x37cb, 0x16},
607*4882a593Smuzhiyun {0x37cc, 0x16},
608*4882a593Smuzhiyun {0x37cd, 0x16},
609*4882a593Smuzhiyun {0x37ce, 0x16},
610*4882a593Smuzhiyun {0x3800, 0x00},
611*4882a593Smuzhiyun {0x3801, 0x00},
612*4882a593Smuzhiyun {0x3802, 0x00},
613*4882a593Smuzhiyun {0x3803, 0x06},
614*4882a593Smuzhiyun {0x3804, 0x0c},
615*4882a593Smuzhiyun {0x3805, 0xdf},
616*4882a593Smuzhiyun {0x3806, 0x09},
617*4882a593Smuzhiyun {0x3807, 0xa7},
618*4882a593Smuzhiyun {0x3808, 0x06},
619*4882a593Smuzhiyun {0x3809, 0x68},
620*4882a593Smuzhiyun {0x380a, 0x04},
621*4882a593Smuzhiyun {0x380b, 0xd0},
622*4882a593Smuzhiyun {0x380c, 0x0e},
623*4882a593Smuzhiyun {0x380d, 0xec},
624*4882a593Smuzhiyun {0x380e, 0x04},
625*4882a593Smuzhiyun {0x380f, 0xe8},
626*4882a593Smuzhiyun {0x3810, 0x00},
627*4882a593Smuzhiyun {0x3811, 0x00},
628*4882a593Smuzhiyun {0x3812, 0x00},
629*4882a593Smuzhiyun {0x3813, 0x01},
630*4882a593Smuzhiyun {0x3814, 0x03},
631*4882a593Smuzhiyun {0x3815, 0x01},
632*4882a593Smuzhiyun {0x3816, 0x00},
633*4882a593Smuzhiyun {0x3817, 0x00},
634*4882a593Smuzhiyun {0x3818, 0x00},
635*4882a593Smuzhiyun {0x3819, 0x10},
636*4882a593Smuzhiyun {0x3820, 0x90},
637*4882a593Smuzhiyun {0x3821, 0x67},
638*4882a593Smuzhiyun {0x382a, 0x03},
639*4882a593Smuzhiyun {0x382b, 0x01},
640*4882a593Smuzhiyun {0x3830, 0x06},
641*4882a593Smuzhiyun {0x3836, 0x02},
642*4882a593Smuzhiyun {0x3862, 0x04},
643*4882a593Smuzhiyun {0x3863, 0x08},
644*4882a593Smuzhiyun {0x3cc0, 0x33},
645*4882a593Smuzhiyun {0x3d85, 0x17},
646*4882a593Smuzhiyun {0x3d8c, 0x73},
647*4882a593Smuzhiyun {0x3d8d, 0xde},
648*4882a593Smuzhiyun {0x4001, 0xe0},
649*4882a593Smuzhiyun {0x4003, 0x40},
650*4882a593Smuzhiyun {0x4008, 0x00},
651*4882a593Smuzhiyun {0x4009, 0x05},
652*4882a593Smuzhiyun {0x400a, 0x00},
653*4882a593Smuzhiyun {0x400b, 0x84},
654*4882a593Smuzhiyun {0x400f, 0x80},
655*4882a593Smuzhiyun {0x4010, 0xf0},
656*4882a593Smuzhiyun {0x4011, 0xff},
657*4882a593Smuzhiyun {0x4012, 0x02},
658*4882a593Smuzhiyun {0x4013, 0x01},
659*4882a593Smuzhiyun {0x4014, 0x01},
660*4882a593Smuzhiyun {0x4015, 0x01},
661*4882a593Smuzhiyun {0x4042, 0x00},
662*4882a593Smuzhiyun {0x4043, 0x80},
663*4882a593Smuzhiyun {0x4044, 0x00},
664*4882a593Smuzhiyun {0x4045, 0x80},
665*4882a593Smuzhiyun {0x4046, 0x00},
666*4882a593Smuzhiyun {0x4047, 0x80},
667*4882a593Smuzhiyun {0x4048, 0x00},
668*4882a593Smuzhiyun {0x4049, 0x80},
669*4882a593Smuzhiyun {0x4041, 0x03},
670*4882a593Smuzhiyun {0x404c, 0x20},
671*4882a593Smuzhiyun {0x404d, 0x00},
672*4882a593Smuzhiyun {0x404e, 0x20},
673*4882a593Smuzhiyun {0x4203, 0x80},
674*4882a593Smuzhiyun {0x4307, 0x30},
675*4882a593Smuzhiyun {0x4317, 0x00},
676*4882a593Smuzhiyun {0x4503, 0x08},
677*4882a593Smuzhiyun {0x4601, 0x80},
678*4882a593Smuzhiyun {0x4800, 0x44},
679*4882a593Smuzhiyun {0x4816, 0x53},
680*4882a593Smuzhiyun {0x481b, 0x58},
681*4882a593Smuzhiyun {0x481f, 0x27},
682*4882a593Smuzhiyun {0x4837, 0x16},
683*4882a593Smuzhiyun {0x483c, 0x0f},
684*4882a593Smuzhiyun {0x484b, 0x05},
685*4882a593Smuzhiyun {0x5000, 0x57},
686*4882a593Smuzhiyun {0x5001, 0x0a},
687*4882a593Smuzhiyun {0x5004, 0x04},
688*4882a593Smuzhiyun {0x502e, 0x03},
689*4882a593Smuzhiyun {0x5030, 0x41},
690*4882a593Smuzhiyun {0x5780, 0x14},
691*4882a593Smuzhiyun {0x5781, 0x0f},
692*4882a593Smuzhiyun {0x5782, 0x44},
693*4882a593Smuzhiyun {0x5783, 0x02},
694*4882a593Smuzhiyun {0x5784, 0x01},
695*4882a593Smuzhiyun {0x5785, 0x01},
696*4882a593Smuzhiyun {0x5786, 0x00},
697*4882a593Smuzhiyun {0x5787, 0x04},
698*4882a593Smuzhiyun {0x5788, 0x02},
699*4882a593Smuzhiyun {0x5789, 0x0f},
700*4882a593Smuzhiyun {0x578a, 0xfd},
701*4882a593Smuzhiyun {0x578b, 0xf5},
702*4882a593Smuzhiyun {0x578c, 0xf5},
703*4882a593Smuzhiyun {0x578d, 0x03},
704*4882a593Smuzhiyun {0x578e, 0x08},
705*4882a593Smuzhiyun {0x578f, 0x0c},
706*4882a593Smuzhiyun {0x5790, 0x08},
707*4882a593Smuzhiyun {0x5791, 0x04},
708*4882a593Smuzhiyun {0x5792, 0x00},
709*4882a593Smuzhiyun {0x5793, 0x52},
710*4882a593Smuzhiyun {0x5794, 0xa3},
711*4882a593Smuzhiyun {0x5795, 0x00},
712*4882a593Smuzhiyun {0x5796, 0x10},
713*4882a593Smuzhiyun {0x5797, 0x10},
714*4882a593Smuzhiyun {0x5798, 0x73},
715*4882a593Smuzhiyun {0x5799, 0x73},
716*4882a593Smuzhiyun {0x579a, 0x00},
717*4882a593Smuzhiyun {0x579b, 0x28},
718*4882a593Smuzhiyun {0x579c, 0x00},
719*4882a593Smuzhiyun {0x579d, 0x16},
720*4882a593Smuzhiyun {0x579e, 0x06},
721*4882a593Smuzhiyun {0x579f, 0x20},
722*4882a593Smuzhiyun {0x57a0, 0x04},
723*4882a593Smuzhiyun {0x57a1, 0xa0},
724*4882a593Smuzhiyun {0x59f8, 0x3d},
725*4882a593Smuzhiyun {0x5a08, 0x02},
726*4882a593Smuzhiyun {0x5b00, 0x02},
727*4882a593Smuzhiyun {0x5b01, 0x10},
728*4882a593Smuzhiyun {0x5b02, 0x03},
729*4882a593Smuzhiyun {0x5b03, 0xcf},
730*4882a593Smuzhiyun {0x5b05, 0x6c},
731*4882a593Smuzhiyun {0x5e00, 0x00}
732*4882a593Smuzhiyun };
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun static const struct ov8856_reg mode_1632x1224_regs[] = {
735*4882a593Smuzhiyun {0x0103, 0x01},
736*4882a593Smuzhiyun {0x0302, 0x3c},
737*4882a593Smuzhiyun {0x0303, 0x01},
738*4882a593Smuzhiyun {0x031e, 0x0c},
739*4882a593Smuzhiyun {0x3000, 0x20},
740*4882a593Smuzhiyun {0x3003, 0x08},
741*4882a593Smuzhiyun {0x300e, 0x20},
742*4882a593Smuzhiyun {0x3010, 0x00},
743*4882a593Smuzhiyun {0x3015, 0x84},
744*4882a593Smuzhiyun {0x3018, 0x72},
745*4882a593Smuzhiyun {0x3021, 0x23},
746*4882a593Smuzhiyun {0x3033, 0x24},
747*4882a593Smuzhiyun {0x3500, 0x00},
748*4882a593Smuzhiyun {0x3501, 0x4c},
749*4882a593Smuzhiyun {0x3502, 0xe0},
750*4882a593Smuzhiyun {0x3503, 0x08},
751*4882a593Smuzhiyun {0x3505, 0x83},
752*4882a593Smuzhiyun {0x3508, 0x01},
753*4882a593Smuzhiyun {0x3509, 0x80},
754*4882a593Smuzhiyun {0x350c, 0x00},
755*4882a593Smuzhiyun {0x350d, 0x80},
756*4882a593Smuzhiyun {0x350e, 0x04},
757*4882a593Smuzhiyun {0x350f, 0x00},
758*4882a593Smuzhiyun {0x3510, 0x00},
759*4882a593Smuzhiyun {0x3511, 0x02},
760*4882a593Smuzhiyun {0x3512, 0x00},
761*4882a593Smuzhiyun {0x3600, 0x72},
762*4882a593Smuzhiyun {0x3601, 0x40},
763*4882a593Smuzhiyun {0x3602, 0x30},
764*4882a593Smuzhiyun {0x3610, 0xc5},
765*4882a593Smuzhiyun {0x3611, 0x58},
766*4882a593Smuzhiyun {0x3612, 0x5c},
767*4882a593Smuzhiyun {0x3613, 0xca},
768*4882a593Smuzhiyun {0x3614, 0x60},
769*4882a593Smuzhiyun {0x3628, 0xff},
770*4882a593Smuzhiyun {0x3629, 0xff},
771*4882a593Smuzhiyun {0x362a, 0xff},
772*4882a593Smuzhiyun {0x3633, 0x10},
773*4882a593Smuzhiyun {0x3634, 0x10},
774*4882a593Smuzhiyun {0x3635, 0x10},
775*4882a593Smuzhiyun {0x3636, 0x10},
776*4882a593Smuzhiyun {0x3663, 0x08},
777*4882a593Smuzhiyun {0x3669, 0x34},
778*4882a593Smuzhiyun {0x366d, 0x00},
779*4882a593Smuzhiyun {0x366e, 0x08},
780*4882a593Smuzhiyun {0x3706, 0x86},
781*4882a593Smuzhiyun {0x370b, 0x7e},
782*4882a593Smuzhiyun {0x3714, 0x27},
783*4882a593Smuzhiyun {0x3730, 0x12},
784*4882a593Smuzhiyun {0x3733, 0x10},
785*4882a593Smuzhiyun {0x3764, 0x00},
786*4882a593Smuzhiyun {0x3765, 0x00},
787*4882a593Smuzhiyun {0x3769, 0x62},
788*4882a593Smuzhiyun {0x376a, 0x2a},
789*4882a593Smuzhiyun {0x376b, 0x30},
790*4882a593Smuzhiyun {0x3780, 0x00},
791*4882a593Smuzhiyun {0x3781, 0x24},
792*4882a593Smuzhiyun {0x3782, 0x00},
793*4882a593Smuzhiyun {0x3783, 0x23},
794*4882a593Smuzhiyun {0x3798, 0x2f},
795*4882a593Smuzhiyun {0x37a1, 0x60},
796*4882a593Smuzhiyun {0x37a8, 0x6a},
797*4882a593Smuzhiyun {0x37ab, 0x3f},
798*4882a593Smuzhiyun {0x37c2, 0x14},
799*4882a593Smuzhiyun {0x37c3, 0xf1},
800*4882a593Smuzhiyun {0x37c9, 0x80},
801*4882a593Smuzhiyun {0x37cb, 0x16},
802*4882a593Smuzhiyun {0x37cc, 0x16},
803*4882a593Smuzhiyun {0x37cd, 0x16},
804*4882a593Smuzhiyun {0x37ce, 0x16},
805*4882a593Smuzhiyun {0x3800, 0x00},
806*4882a593Smuzhiyun {0x3801, 0x00},
807*4882a593Smuzhiyun {0x3802, 0x00},
808*4882a593Smuzhiyun {0x3803, 0x0c},
809*4882a593Smuzhiyun {0x3804, 0x0c},
810*4882a593Smuzhiyun {0x3805, 0xdf},
811*4882a593Smuzhiyun {0x3806, 0x09},
812*4882a593Smuzhiyun {0x3807, 0xa3},
813*4882a593Smuzhiyun {0x3808, 0x06},
814*4882a593Smuzhiyun {0x3809, 0x60},
815*4882a593Smuzhiyun {0x380a, 0x04},
816*4882a593Smuzhiyun {0x380b, 0xc8},
817*4882a593Smuzhiyun {0x380c, 0x07},
818*4882a593Smuzhiyun {0x380d, 0x8c},
819*4882a593Smuzhiyun {0x380e, 0x09},
820*4882a593Smuzhiyun {0x380f, 0xb2},
821*4882a593Smuzhiyun {0x3810, 0x00},
822*4882a593Smuzhiyun {0x3811, 0x02},
823*4882a593Smuzhiyun {0x3812, 0x00},
824*4882a593Smuzhiyun {0x3813, 0x02},
825*4882a593Smuzhiyun {0x3814, 0x03},
826*4882a593Smuzhiyun {0x3815, 0x01},
827*4882a593Smuzhiyun {0x3816, 0x00},
828*4882a593Smuzhiyun {0x3817, 0x00},
829*4882a593Smuzhiyun {0x3818, 0x00},
830*4882a593Smuzhiyun {0x3819, 0x10},
831*4882a593Smuzhiyun {0x3820, 0x80},
832*4882a593Smuzhiyun {0x3821, 0x47},
833*4882a593Smuzhiyun {0x382a, 0x03},
834*4882a593Smuzhiyun {0x382b, 0x01},
835*4882a593Smuzhiyun {0x3830, 0x06},
836*4882a593Smuzhiyun {0x3836, 0x02},
837*4882a593Smuzhiyun {0x3862, 0x04},
838*4882a593Smuzhiyun {0x3863, 0x08},
839*4882a593Smuzhiyun {0x3cc0, 0x33},
840*4882a593Smuzhiyun {0x3d85, 0x17},
841*4882a593Smuzhiyun {0x3d8c, 0x73},
842*4882a593Smuzhiyun {0x3d8d, 0xde},
843*4882a593Smuzhiyun {0x4001, 0xe0},
844*4882a593Smuzhiyun {0x4003, 0x40},
845*4882a593Smuzhiyun {0x4008, 0x00},
846*4882a593Smuzhiyun {0x4009, 0x05},
847*4882a593Smuzhiyun {0x400a, 0x00},
848*4882a593Smuzhiyun {0x400b, 0x84},
849*4882a593Smuzhiyun {0x400f, 0x80},
850*4882a593Smuzhiyun {0x4010, 0xf0},
851*4882a593Smuzhiyun {0x4011, 0xff},
852*4882a593Smuzhiyun {0x4012, 0x02},
853*4882a593Smuzhiyun {0x4013, 0x01},
854*4882a593Smuzhiyun {0x4014, 0x01},
855*4882a593Smuzhiyun {0x4015, 0x01},
856*4882a593Smuzhiyun {0x4042, 0x00},
857*4882a593Smuzhiyun {0x4043, 0x80},
858*4882a593Smuzhiyun {0x4044, 0x00},
859*4882a593Smuzhiyun {0x4045, 0x80},
860*4882a593Smuzhiyun {0x4046, 0x00},
861*4882a593Smuzhiyun {0x4047, 0x80},
862*4882a593Smuzhiyun {0x4048, 0x00},
863*4882a593Smuzhiyun {0x4049, 0x80},
864*4882a593Smuzhiyun {0x4041, 0x03},
865*4882a593Smuzhiyun {0x404c, 0x20},
866*4882a593Smuzhiyun {0x404d, 0x00},
867*4882a593Smuzhiyun {0x404e, 0x20},
868*4882a593Smuzhiyun {0x4203, 0x80},
869*4882a593Smuzhiyun {0x4307, 0x30},
870*4882a593Smuzhiyun {0x4317, 0x00},
871*4882a593Smuzhiyun {0x4502, 0x50},
872*4882a593Smuzhiyun {0x4503, 0x08},
873*4882a593Smuzhiyun {0x4601, 0x80},
874*4882a593Smuzhiyun {0x4800, 0x44},
875*4882a593Smuzhiyun {0x4816, 0x53},
876*4882a593Smuzhiyun {0x481b, 0x50},
877*4882a593Smuzhiyun {0x481f, 0x27},
878*4882a593Smuzhiyun {0x4823, 0x3c},
879*4882a593Smuzhiyun {0x482b, 0x00},
880*4882a593Smuzhiyun {0x4831, 0x66},
881*4882a593Smuzhiyun {0x4837, 0x16},
882*4882a593Smuzhiyun {0x483c, 0x0f},
883*4882a593Smuzhiyun {0x484b, 0x05},
884*4882a593Smuzhiyun {0x5000, 0x77},
885*4882a593Smuzhiyun {0x5001, 0x0a},
886*4882a593Smuzhiyun {0x5003, 0xc8},
887*4882a593Smuzhiyun {0x5004, 0x04},
888*4882a593Smuzhiyun {0x5006, 0x00},
889*4882a593Smuzhiyun {0x5007, 0x00},
890*4882a593Smuzhiyun {0x502e, 0x03},
891*4882a593Smuzhiyun {0x5030, 0x41},
892*4882a593Smuzhiyun {0x5795, 0x00},
893*4882a593Smuzhiyun {0x5796, 0x10},
894*4882a593Smuzhiyun {0x5797, 0x10},
895*4882a593Smuzhiyun {0x5798, 0x73},
896*4882a593Smuzhiyun {0x5799, 0x73},
897*4882a593Smuzhiyun {0x579a, 0x00},
898*4882a593Smuzhiyun {0x579b, 0x28},
899*4882a593Smuzhiyun {0x579c, 0x00},
900*4882a593Smuzhiyun {0x579d, 0x16},
901*4882a593Smuzhiyun {0x579e, 0x06},
902*4882a593Smuzhiyun {0x579f, 0x20},
903*4882a593Smuzhiyun {0x57a0, 0x04},
904*4882a593Smuzhiyun {0x57a1, 0xa0},
905*4882a593Smuzhiyun {0x5780, 0x14},
906*4882a593Smuzhiyun {0x5781, 0x0f},
907*4882a593Smuzhiyun {0x5782, 0x44},
908*4882a593Smuzhiyun {0x5783, 0x02},
909*4882a593Smuzhiyun {0x5784, 0x01},
910*4882a593Smuzhiyun {0x5785, 0x01},
911*4882a593Smuzhiyun {0x5786, 0x00},
912*4882a593Smuzhiyun {0x5787, 0x04},
913*4882a593Smuzhiyun {0x5788, 0x02},
914*4882a593Smuzhiyun {0x5789, 0x0f},
915*4882a593Smuzhiyun {0x578a, 0xfd},
916*4882a593Smuzhiyun {0x578b, 0xf5},
917*4882a593Smuzhiyun {0x578c, 0xf5},
918*4882a593Smuzhiyun {0x578d, 0x03},
919*4882a593Smuzhiyun {0x578e, 0x08},
920*4882a593Smuzhiyun {0x578f, 0x0c},
921*4882a593Smuzhiyun {0x5790, 0x08},
922*4882a593Smuzhiyun {0x5791, 0x04},
923*4882a593Smuzhiyun {0x5792, 0x00},
924*4882a593Smuzhiyun {0x5793, 0x52},
925*4882a593Smuzhiyun {0x5794, 0xa3},
926*4882a593Smuzhiyun {0x59f8, 0x3d},
927*4882a593Smuzhiyun {0x5a08, 0x02},
928*4882a593Smuzhiyun {0x5b00, 0x02},
929*4882a593Smuzhiyun {0x5b01, 0x10},
930*4882a593Smuzhiyun {0x5b02, 0x03},
931*4882a593Smuzhiyun {0x5b03, 0xcf},
932*4882a593Smuzhiyun {0x5b05, 0x6c},
933*4882a593Smuzhiyun {0x5e00, 0x00},
934*4882a593Smuzhiyun {0x5e10, 0xfc}
935*4882a593Smuzhiyun };
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun static const char * const ov8856_test_pattern_menu[] = {
938*4882a593Smuzhiyun "Disabled",
939*4882a593Smuzhiyun "Standard Color Bar",
940*4882a593Smuzhiyun "Top-Bottom Darker Color Bar",
941*4882a593Smuzhiyun "Right-Left Darker Color Bar",
942*4882a593Smuzhiyun "Bottom-Top Darker Color Bar"
943*4882a593Smuzhiyun };
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
946*4882a593Smuzhiyun OV8856_LINK_FREQ_360MHZ,
947*4882a593Smuzhiyun OV8856_LINK_FREQ_180MHZ
948*4882a593Smuzhiyun };
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun static const struct ov8856_link_freq_config link_freq_configs[] = {
951*4882a593Smuzhiyun [OV8856_LINK_FREQ_720MBPS] = {
952*4882a593Smuzhiyun .reg_list = {
953*4882a593Smuzhiyun .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
954*4882a593Smuzhiyun .regs = mipi_data_rate_720mbps,
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun },
957*4882a593Smuzhiyun [OV8856_LINK_FREQ_360MBPS] = {
958*4882a593Smuzhiyun .reg_list = {
959*4882a593Smuzhiyun .num_of_regs = ARRAY_SIZE(mipi_data_rate_360mbps),
960*4882a593Smuzhiyun .regs = mipi_data_rate_360mbps,
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun }
963*4882a593Smuzhiyun };
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun static const struct ov8856_mode supported_modes[] = {
966*4882a593Smuzhiyun {
967*4882a593Smuzhiyun .width = 3280,
968*4882a593Smuzhiyun .height = 2464,
969*4882a593Smuzhiyun .hts = 1928,
970*4882a593Smuzhiyun .vts_def = 2488,
971*4882a593Smuzhiyun .vts_min = 2488,
972*4882a593Smuzhiyun .reg_list = {
973*4882a593Smuzhiyun .num_of_regs = ARRAY_SIZE(mode_3280x2464_regs),
974*4882a593Smuzhiyun .regs = mode_3280x2464_regs,
975*4882a593Smuzhiyun },
976*4882a593Smuzhiyun .link_freq_index = OV8856_LINK_FREQ_720MBPS,
977*4882a593Smuzhiyun },
978*4882a593Smuzhiyun {
979*4882a593Smuzhiyun .width = 3264,
980*4882a593Smuzhiyun .height = 2448,
981*4882a593Smuzhiyun .hts = 1932,
982*4882a593Smuzhiyun .vts_def = 2482,
983*4882a593Smuzhiyun .vts_min = 2482,
984*4882a593Smuzhiyun .reg_list = {
985*4882a593Smuzhiyun .num_of_regs = ARRAY_SIZE(mode_3264x2448_regs),
986*4882a593Smuzhiyun .regs = mode_3264x2448_regs,
987*4882a593Smuzhiyun },
988*4882a593Smuzhiyun .link_freq_index = OV8856_LINK_FREQ_720MBPS,
989*4882a593Smuzhiyun },
990*4882a593Smuzhiyun {
991*4882a593Smuzhiyun .width = 1640,
992*4882a593Smuzhiyun .height = 1232,
993*4882a593Smuzhiyun .hts = 3820,
994*4882a593Smuzhiyun .vts_def = 1256,
995*4882a593Smuzhiyun .vts_min = 1256,
996*4882a593Smuzhiyun .reg_list = {
997*4882a593Smuzhiyun .num_of_regs = ARRAY_SIZE(mode_1640x1232_regs),
998*4882a593Smuzhiyun .regs = mode_1640x1232_regs,
999*4882a593Smuzhiyun },
1000*4882a593Smuzhiyun .link_freq_index = OV8856_LINK_FREQ_360MBPS,
1001*4882a593Smuzhiyun },
1002*4882a593Smuzhiyun {
1003*4882a593Smuzhiyun .width = 1632,
1004*4882a593Smuzhiyun .height = 1224,
1005*4882a593Smuzhiyun .hts = 1932,
1006*4882a593Smuzhiyun .vts_def = 2482,
1007*4882a593Smuzhiyun .vts_min = 2482,
1008*4882a593Smuzhiyun .reg_list = {
1009*4882a593Smuzhiyun .num_of_regs = ARRAY_SIZE(mode_1632x1224_regs),
1010*4882a593Smuzhiyun .regs = mode_1632x1224_regs,
1011*4882a593Smuzhiyun },
1012*4882a593Smuzhiyun .link_freq_index = OV8856_LINK_FREQ_360MBPS,
1013*4882a593Smuzhiyun }
1014*4882a593Smuzhiyun };
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun struct ov8856 {
1017*4882a593Smuzhiyun struct v4l2_subdev sd;
1018*4882a593Smuzhiyun struct media_pad pad;
1019*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
1020*4882a593Smuzhiyun
1021*4882a593Smuzhiyun struct clk *xvclk;
1022*4882a593Smuzhiyun struct gpio_desc *reset_gpio;
1023*4882a593Smuzhiyun struct regulator_bulk_data supplies[ARRAY_SIZE(ov8856_supply_names)];
1024*4882a593Smuzhiyun
1025*4882a593Smuzhiyun /* V4L2 Controls */
1026*4882a593Smuzhiyun struct v4l2_ctrl *link_freq;
1027*4882a593Smuzhiyun struct v4l2_ctrl *pixel_rate;
1028*4882a593Smuzhiyun struct v4l2_ctrl *vblank;
1029*4882a593Smuzhiyun struct v4l2_ctrl *hblank;
1030*4882a593Smuzhiyun struct v4l2_ctrl *exposure;
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun /* Current mode */
1033*4882a593Smuzhiyun const struct ov8856_mode *cur_mode;
1034*4882a593Smuzhiyun
1035*4882a593Smuzhiyun /* To serialize asynchronus callbacks */
1036*4882a593Smuzhiyun struct mutex mutex;
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun /* Streaming on/off */
1039*4882a593Smuzhiyun bool streaming;
1040*4882a593Smuzhiyun };
1041*4882a593Smuzhiyun
to_pixel_rate(u32 f_index)1042*4882a593Smuzhiyun static u64 to_pixel_rate(u32 f_index)
1043*4882a593Smuzhiyun {
1044*4882a593Smuzhiyun u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV8856_DATA_LANES;
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun do_div(pixel_rate, OV8856_RGB_DEPTH);
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun return pixel_rate;
1049*4882a593Smuzhiyun }
1050*4882a593Smuzhiyun
to_pixels_per_line(u32 hts,u32 f_index)1051*4882a593Smuzhiyun static u64 to_pixels_per_line(u32 hts, u32 f_index)
1052*4882a593Smuzhiyun {
1053*4882a593Smuzhiyun u64 ppl = hts * to_pixel_rate(f_index);
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun do_div(ppl, OV8856_SCLK);
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun return ppl;
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun
ov8856_read_reg(struct ov8856 * ov8856,u16 reg,u16 len,u32 * val)1060*4882a593Smuzhiyun static int ov8856_read_reg(struct ov8856 *ov8856, u16 reg, u16 len, u32 *val)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1063*4882a593Smuzhiyun struct i2c_msg msgs[2];
1064*4882a593Smuzhiyun u8 addr_buf[2];
1065*4882a593Smuzhiyun u8 data_buf[4] = {0};
1066*4882a593Smuzhiyun int ret;
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun if (len > 4)
1069*4882a593Smuzhiyun return -EINVAL;
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun put_unaligned_be16(reg, addr_buf);
1072*4882a593Smuzhiyun msgs[0].addr = client->addr;
1073*4882a593Smuzhiyun msgs[0].flags = 0;
1074*4882a593Smuzhiyun msgs[0].len = sizeof(addr_buf);
1075*4882a593Smuzhiyun msgs[0].buf = addr_buf;
1076*4882a593Smuzhiyun msgs[1].addr = client->addr;
1077*4882a593Smuzhiyun msgs[1].flags = I2C_M_RD;
1078*4882a593Smuzhiyun msgs[1].len = len;
1079*4882a593Smuzhiyun msgs[1].buf = &data_buf[4 - len];
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
1082*4882a593Smuzhiyun if (ret != ARRAY_SIZE(msgs))
1083*4882a593Smuzhiyun return -EIO;
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun *val = get_unaligned_be32(data_buf);
1086*4882a593Smuzhiyun
1087*4882a593Smuzhiyun return 0;
1088*4882a593Smuzhiyun }
1089*4882a593Smuzhiyun
ov8856_write_reg(struct ov8856 * ov8856,u16 reg,u16 len,u32 val)1090*4882a593Smuzhiyun static int ov8856_write_reg(struct ov8856 *ov8856, u16 reg, u16 len, u32 val)
1091*4882a593Smuzhiyun {
1092*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1093*4882a593Smuzhiyun u8 buf[6];
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun if (len > 4)
1096*4882a593Smuzhiyun return -EINVAL;
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun put_unaligned_be16(reg, buf);
1099*4882a593Smuzhiyun put_unaligned_be32(val << 8 * (4 - len), buf + 2);
1100*4882a593Smuzhiyun if (i2c_master_send(client, buf, len + 2) != len + 2)
1101*4882a593Smuzhiyun return -EIO;
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun return 0;
1104*4882a593Smuzhiyun }
1105*4882a593Smuzhiyun
ov8856_write_reg_list(struct ov8856 * ov8856,const struct ov8856_reg_list * r_list)1106*4882a593Smuzhiyun static int ov8856_write_reg_list(struct ov8856 *ov8856,
1107*4882a593Smuzhiyun const struct ov8856_reg_list *r_list)
1108*4882a593Smuzhiyun {
1109*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1110*4882a593Smuzhiyun unsigned int i;
1111*4882a593Smuzhiyun int ret;
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun for (i = 0; i < r_list->num_of_regs; i++) {
1114*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, r_list->regs[i].address, 1,
1115*4882a593Smuzhiyun r_list->regs[i].val);
1116*4882a593Smuzhiyun if (ret) {
1117*4882a593Smuzhiyun dev_err_ratelimited(&client->dev,
1118*4882a593Smuzhiyun "failed to write reg 0x%4.4x. error = %d",
1119*4882a593Smuzhiyun r_list->regs[i].address, ret);
1120*4882a593Smuzhiyun return ret;
1121*4882a593Smuzhiyun }
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun return 0;
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun
ov8856_update_digital_gain(struct ov8856 * ov8856,u32 d_gain)1127*4882a593Smuzhiyun static int ov8856_update_digital_gain(struct ov8856 *ov8856, u32 d_gain)
1128*4882a593Smuzhiyun {
1129*4882a593Smuzhiyun int ret;
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_MWB_R_GAIN,
1132*4882a593Smuzhiyun OV8856_REG_VALUE_16BIT, d_gain);
1133*4882a593Smuzhiyun if (ret)
1134*4882a593Smuzhiyun return ret;
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_MWB_G_GAIN,
1137*4882a593Smuzhiyun OV8856_REG_VALUE_16BIT, d_gain);
1138*4882a593Smuzhiyun if (ret)
1139*4882a593Smuzhiyun return ret;
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun return ov8856_write_reg(ov8856, OV8856_REG_MWB_B_GAIN,
1142*4882a593Smuzhiyun OV8856_REG_VALUE_16BIT, d_gain);
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun
ov8856_test_pattern(struct ov8856 * ov8856,u32 pattern)1145*4882a593Smuzhiyun static int ov8856_test_pattern(struct ov8856 *ov8856, u32 pattern)
1146*4882a593Smuzhiyun {
1147*4882a593Smuzhiyun if (pattern)
1148*4882a593Smuzhiyun pattern = (pattern - 1) << OV8856_TEST_PATTERN_BAR_SHIFT |
1149*4882a593Smuzhiyun OV8856_TEST_PATTERN_ENABLE;
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun return ov8856_write_reg(ov8856, OV8856_REG_TEST_PATTERN,
1152*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT, pattern);
1153*4882a593Smuzhiyun }
1154*4882a593Smuzhiyun
ov8856_set_ctrl(struct v4l2_ctrl * ctrl)1155*4882a593Smuzhiyun static int ov8856_set_ctrl(struct v4l2_ctrl *ctrl)
1156*4882a593Smuzhiyun {
1157*4882a593Smuzhiyun struct ov8856 *ov8856 = container_of(ctrl->handler,
1158*4882a593Smuzhiyun struct ov8856, ctrl_handler);
1159*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1160*4882a593Smuzhiyun s64 exposure_max;
1161*4882a593Smuzhiyun int ret = 0;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun /* Propagate change of current control to all related controls */
1164*4882a593Smuzhiyun if (ctrl->id == V4L2_CID_VBLANK) {
1165*4882a593Smuzhiyun /* Update max exposure while meeting expected vblanking */
1166*4882a593Smuzhiyun exposure_max = ov8856->cur_mode->height + ctrl->val -
1167*4882a593Smuzhiyun OV8856_EXPOSURE_MAX_MARGIN;
1168*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov8856->exposure,
1169*4882a593Smuzhiyun ov8856->exposure->minimum,
1170*4882a593Smuzhiyun exposure_max, ov8856->exposure->step,
1171*4882a593Smuzhiyun exposure_max);
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun /* V4L2 controls values will be applied only when power is already up */
1175*4882a593Smuzhiyun if (!pm_runtime_get_if_in_use(&client->dev))
1176*4882a593Smuzhiyun return 0;
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun switch (ctrl->id) {
1179*4882a593Smuzhiyun case V4L2_CID_ANALOGUE_GAIN:
1180*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_ANALOG_GAIN,
1181*4882a593Smuzhiyun OV8856_REG_VALUE_16BIT, ctrl->val);
1182*4882a593Smuzhiyun break;
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun case V4L2_CID_DIGITAL_GAIN:
1185*4882a593Smuzhiyun ret = ov8856_update_digital_gain(ov8856, ctrl->val);
1186*4882a593Smuzhiyun break;
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun case V4L2_CID_EXPOSURE:
1189*4882a593Smuzhiyun /* 4 least significant bits of expsoure are fractional part */
1190*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_EXPOSURE,
1191*4882a593Smuzhiyun OV8856_REG_VALUE_24BIT, ctrl->val << 4);
1192*4882a593Smuzhiyun break;
1193*4882a593Smuzhiyun
1194*4882a593Smuzhiyun case V4L2_CID_VBLANK:
1195*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_VTS,
1196*4882a593Smuzhiyun OV8856_REG_VALUE_16BIT,
1197*4882a593Smuzhiyun ov8856->cur_mode->height + ctrl->val);
1198*4882a593Smuzhiyun break;
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun case V4L2_CID_TEST_PATTERN:
1201*4882a593Smuzhiyun ret = ov8856_test_pattern(ov8856, ctrl->val);
1202*4882a593Smuzhiyun break;
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun default:
1205*4882a593Smuzhiyun ret = -EINVAL;
1206*4882a593Smuzhiyun break;
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun return ret;
1212*4882a593Smuzhiyun }
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun static const struct v4l2_ctrl_ops ov8856_ctrl_ops = {
1215*4882a593Smuzhiyun .s_ctrl = ov8856_set_ctrl,
1216*4882a593Smuzhiyun };
1217*4882a593Smuzhiyun
ov8856_init_controls(struct ov8856 * ov8856)1218*4882a593Smuzhiyun static int ov8856_init_controls(struct ov8856 *ov8856)
1219*4882a593Smuzhiyun {
1220*4882a593Smuzhiyun struct v4l2_ctrl_handler *ctrl_hdlr;
1221*4882a593Smuzhiyun s64 exposure_max, h_blank;
1222*4882a593Smuzhiyun int ret;
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun ctrl_hdlr = &ov8856->ctrl_handler;
1225*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
1226*4882a593Smuzhiyun if (ret)
1227*4882a593Smuzhiyun return ret;
1228*4882a593Smuzhiyun
1229*4882a593Smuzhiyun ctrl_hdlr->lock = &ov8856->mutex;
1230*4882a593Smuzhiyun ov8856->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov8856_ctrl_ops,
1231*4882a593Smuzhiyun V4L2_CID_LINK_FREQ,
1232*4882a593Smuzhiyun ARRAY_SIZE(link_freq_menu_items) - 1,
1233*4882a593Smuzhiyun 0, link_freq_menu_items);
1234*4882a593Smuzhiyun if (ov8856->link_freq)
1235*4882a593Smuzhiyun ov8856->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun ov8856->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov8856_ctrl_ops,
1238*4882a593Smuzhiyun V4L2_CID_PIXEL_RATE, 0,
1239*4882a593Smuzhiyun to_pixel_rate(OV8856_LINK_FREQ_720MBPS),
1240*4882a593Smuzhiyun 1,
1241*4882a593Smuzhiyun to_pixel_rate(OV8856_LINK_FREQ_720MBPS));
1242*4882a593Smuzhiyun ov8856->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov8856_ctrl_ops,
1243*4882a593Smuzhiyun V4L2_CID_VBLANK,
1244*4882a593Smuzhiyun ov8856->cur_mode->vts_min - ov8856->cur_mode->height,
1245*4882a593Smuzhiyun OV8856_VTS_MAX - ov8856->cur_mode->height, 1,
1246*4882a593Smuzhiyun ov8856->cur_mode->vts_def - ov8856->cur_mode->height);
1247*4882a593Smuzhiyun h_blank = to_pixels_per_line(ov8856->cur_mode->hts,
1248*4882a593Smuzhiyun ov8856->cur_mode->link_freq_index) - ov8856->cur_mode->width;
1249*4882a593Smuzhiyun ov8856->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov8856_ctrl_ops,
1250*4882a593Smuzhiyun V4L2_CID_HBLANK, h_blank, h_blank, 1,
1251*4882a593Smuzhiyun h_blank);
1252*4882a593Smuzhiyun if (ov8856->hblank)
1253*4882a593Smuzhiyun ov8856->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1254*4882a593Smuzhiyun
1255*4882a593Smuzhiyun v4l2_ctrl_new_std(ctrl_hdlr, &ov8856_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
1256*4882a593Smuzhiyun OV8856_ANAL_GAIN_MIN, OV8856_ANAL_GAIN_MAX,
1257*4882a593Smuzhiyun OV8856_ANAL_GAIN_STEP, OV8856_ANAL_GAIN_MIN);
1258*4882a593Smuzhiyun v4l2_ctrl_new_std(ctrl_hdlr, &ov8856_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
1259*4882a593Smuzhiyun OV8856_DGTL_GAIN_MIN, OV8856_DGTL_GAIN_MAX,
1260*4882a593Smuzhiyun OV8856_DGTL_GAIN_STEP, OV8856_DGTL_GAIN_DEFAULT);
1261*4882a593Smuzhiyun exposure_max = ov8856->cur_mode->vts_def - OV8856_EXPOSURE_MAX_MARGIN;
1262*4882a593Smuzhiyun ov8856->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov8856_ctrl_ops,
1263*4882a593Smuzhiyun V4L2_CID_EXPOSURE,
1264*4882a593Smuzhiyun OV8856_EXPOSURE_MIN, exposure_max,
1265*4882a593Smuzhiyun OV8856_EXPOSURE_STEP,
1266*4882a593Smuzhiyun exposure_max);
1267*4882a593Smuzhiyun v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov8856_ctrl_ops,
1268*4882a593Smuzhiyun V4L2_CID_TEST_PATTERN,
1269*4882a593Smuzhiyun ARRAY_SIZE(ov8856_test_pattern_menu) - 1,
1270*4882a593Smuzhiyun 0, 0, ov8856_test_pattern_menu);
1271*4882a593Smuzhiyun if (ctrl_hdlr->error)
1272*4882a593Smuzhiyun return ctrl_hdlr->error;
1273*4882a593Smuzhiyun
1274*4882a593Smuzhiyun ov8856->sd.ctrl_handler = ctrl_hdlr;
1275*4882a593Smuzhiyun
1276*4882a593Smuzhiyun return 0;
1277*4882a593Smuzhiyun }
1278*4882a593Smuzhiyun
ov8856_update_pad_format(const struct ov8856_mode * mode,struct v4l2_mbus_framefmt * fmt)1279*4882a593Smuzhiyun static void ov8856_update_pad_format(const struct ov8856_mode *mode,
1280*4882a593Smuzhiyun struct v4l2_mbus_framefmt *fmt)
1281*4882a593Smuzhiyun {
1282*4882a593Smuzhiyun fmt->width = mode->width;
1283*4882a593Smuzhiyun fmt->height = mode->height;
1284*4882a593Smuzhiyun fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1285*4882a593Smuzhiyun fmt->field = V4L2_FIELD_NONE;
1286*4882a593Smuzhiyun }
1287*4882a593Smuzhiyun
ov8856_start_streaming(struct ov8856 * ov8856)1288*4882a593Smuzhiyun static int ov8856_start_streaming(struct ov8856 *ov8856)
1289*4882a593Smuzhiyun {
1290*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1291*4882a593Smuzhiyun const struct ov8856_reg_list *reg_list;
1292*4882a593Smuzhiyun int link_freq_index, ret;
1293*4882a593Smuzhiyun
1294*4882a593Smuzhiyun link_freq_index = ov8856->cur_mode->link_freq_index;
1295*4882a593Smuzhiyun reg_list = &link_freq_configs[link_freq_index].reg_list;
1296*4882a593Smuzhiyun ret = ov8856_write_reg_list(ov8856, reg_list);
1297*4882a593Smuzhiyun if (ret) {
1298*4882a593Smuzhiyun dev_err(&client->dev, "failed to set plls");
1299*4882a593Smuzhiyun return ret;
1300*4882a593Smuzhiyun }
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun reg_list = &ov8856->cur_mode->reg_list;
1303*4882a593Smuzhiyun ret = ov8856_write_reg_list(ov8856, reg_list);
1304*4882a593Smuzhiyun if (ret) {
1305*4882a593Smuzhiyun dev_err(&client->dev, "failed to set mode");
1306*4882a593Smuzhiyun return ret;
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun ret = __v4l2_ctrl_handler_setup(ov8856->sd.ctrl_handler);
1310*4882a593Smuzhiyun if (ret)
1311*4882a593Smuzhiyun return ret;
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_MODE_SELECT,
1314*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT, OV8856_MODE_STREAMING);
1315*4882a593Smuzhiyun if (ret) {
1316*4882a593Smuzhiyun dev_err(&client->dev, "failed to set stream");
1317*4882a593Smuzhiyun return ret;
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun return 0;
1321*4882a593Smuzhiyun }
1322*4882a593Smuzhiyun
ov8856_stop_streaming(struct ov8856 * ov8856)1323*4882a593Smuzhiyun static void ov8856_stop_streaming(struct ov8856 *ov8856)
1324*4882a593Smuzhiyun {
1325*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun if (ov8856_write_reg(ov8856, OV8856_REG_MODE_SELECT,
1328*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT, OV8856_MODE_STANDBY))
1329*4882a593Smuzhiyun dev_err(&client->dev, "failed to set stream");
1330*4882a593Smuzhiyun }
1331*4882a593Smuzhiyun
ov8856_set_stream(struct v4l2_subdev * sd,int enable)1332*4882a593Smuzhiyun static int ov8856_set_stream(struct v4l2_subdev *sd, int enable)
1333*4882a593Smuzhiyun {
1334*4882a593Smuzhiyun struct ov8856 *ov8856 = to_ov8856(sd);
1335*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
1336*4882a593Smuzhiyun int ret = 0;
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun if (ov8856->streaming == enable)
1339*4882a593Smuzhiyun return 0;
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun mutex_lock(&ov8856->mutex);
1342*4882a593Smuzhiyun if (enable) {
1343*4882a593Smuzhiyun ret = pm_runtime_get_sync(&client->dev);
1344*4882a593Smuzhiyun if (ret < 0) {
1345*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1346*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1347*4882a593Smuzhiyun return ret;
1348*4882a593Smuzhiyun }
1349*4882a593Smuzhiyun
1350*4882a593Smuzhiyun ret = ov8856_start_streaming(ov8856);
1351*4882a593Smuzhiyun if (ret) {
1352*4882a593Smuzhiyun enable = 0;
1353*4882a593Smuzhiyun ov8856_stop_streaming(ov8856);
1354*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1355*4882a593Smuzhiyun }
1356*4882a593Smuzhiyun } else {
1357*4882a593Smuzhiyun ov8856_stop_streaming(ov8856);
1358*4882a593Smuzhiyun pm_runtime_put(&client->dev);
1359*4882a593Smuzhiyun }
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun ov8856->streaming = enable;
1362*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun return ret;
1365*4882a593Smuzhiyun }
1366*4882a593Smuzhiyun
__ov8856_power_on(struct ov8856 * ov8856)1367*4882a593Smuzhiyun static int __ov8856_power_on(struct ov8856 *ov8856)
1368*4882a593Smuzhiyun {
1369*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1370*4882a593Smuzhiyun int ret;
1371*4882a593Smuzhiyun
1372*4882a593Smuzhiyun if (is_acpi_node(dev_fwnode(&client->dev)))
1373*4882a593Smuzhiyun return 0;
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun ret = clk_prepare_enable(ov8856->xvclk);
1376*4882a593Smuzhiyun if (ret < 0) {
1377*4882a593Smuzhiyun dev_err(&client->dev, "failed to enable xvclk\n");
1378*4882a593Smuzhiyun return ret;
1379*4882a593Smuzhiyun }
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun if (ov8856->reset_gpio) {
1382*4882a593Smuzhiyun gpiod_set_value_cansleep(ov8856->reset_gpio, 1);
1383*4882a593Smuzhiyun usleep_range(1000, 2000);
1384*4882a593Smuzhiyun }
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun ret = regulator_bulk_enable(ARRAY_SIZE(ov8856_supply_names),
1387*4882a593Smuzhiyun ov8856->supplies);
1388*4882a593Smuzhiyun if (ret < 0) {
1389*4882a593Smuzhiyun dev_err(&client->dev, "failed to enable regulators\n");
1390*4882a593Smuzhiyun goto disable_clk;
1391*4882a593Smuzhiyun }
1392*4882a593Smuzhiyun
1393*4882a593Smuzhiyun gpiod_set_value_cansleep(ov8856->reset_gpio, 0);
1394*4882a593Smuzhiyun usleep_range(1500, 1800);
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun return 0;
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun disable_clk:
1399*4882a593Smuzhiyun gpiod_set_value_cansleep(ov8856->reset_gpio, 1);
1400*4882a593Smuzhiyun clk_disable_unprepare(ov8856->xvclk);
1401*4882a593Smuzhiyun
1402*4882a593Smuzhiyun return ret;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
__ov8856_power_off(struct ov8856 * ov8856)1405*4882a593Smuzhiyun static void __ov8856_power_off(struct ov8856 *ov8856)
1406*4882a593Smuzhiyun {
1407*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1408*4882a593Smuzhiyun
1409*4882a593Smuzhiyun if (is_acpi_node(dev_fwnode(&client->dev)))
1410*4882a593Smuzhiyun return;
1411*4882a593Smuzhiyun
1412*4882a593Smuzhiyun gpiod_set_value_cansleep(ov8856->reset_gpio, 1);
1413*4882a593Smuzhiyun regulator_bulk_disable(ARRAY_SIZE(ov8856_supply_names),
1414*4882a593Smuzhiyun ov8856->supplies);
1415*4882a593Smuzhiyun clk_disable_unprepare(ov8856->xvclk);
1416*4882a593Smuzhiyun }
1417*4882a593Smuzhiyun
ov8856_suspend(struct device * dev)1418*4882a593Smuzhiyun static int __maybe_unused ov8856_suspend(struct device *dev)
1419*4882a593Smuzhiyun {
1420*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1421*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1422*4882a593Smuzhiyun struct ov8856 *ov8856 = to_ov8856(sd);
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun mutex_lock(&ov8856->mutex);
1425*4882a593Smuzhiyun if (ov8856->streaming)
1426*4882a593Smuzhiyun ov8856_stop_streaming(ov8856);
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun __ov8856_power_off(ov8856);
1429*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1430*4882a593Smuzhiyun
1431*4882a593Smuzhiyun return 0;
1432*4882a593Smuzhiyun }
1433*4882a593Smuzhiyun
ov8856_resume(struct device * dev)1434*4882a593Smuzhiyun static int __maybe_unused ov8856_resume(struct device *dev)
1435*4882a593Smuzhiyun {
1436*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1437*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1438*4882a593Smuzhiyun struct ov8856 *ov8856 = to_ov8856(sd);
1439*4882a593Smuzhiyun int ret;
1440*4882a593Smuzhiyun
1441*4882a593Smuzhiyun mutex_lock(&ov8856->mutex);
1442*4882a593Smuzhiyun
1443*4882a593Smuzhiyun __ov8856_power_on(ov8856);
1444*4882a593Smuzhiyun if (ov8856->streaming) {
1445*4882a593Smuzhiyun ret = ov8856_start_streaming(ov8856);
1446*4882a593Smuzhiyun if (ret) {
1447*4882a593Smuzhiyun ov8856->streaming = false;
1448*4882a593Smuzhiyun ov8856_stop_streaming(ov8856);
1449*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1450*4882a593Smuzhiyun return ret;
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun }
1453*4882a593Smuzhiyun
1454*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1455*4882a593Smuzhiyun
1456*4882a593Smuzhiyun return 0;
1457*4882a593Smuzhiyun }
1458*4882a593Smuzhiyun
ov8856_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1459*4882a593Smuzhiyun static int ov8856_set_format(struct v4l2_subdev *sd,
1460*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1461*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
1462*4882a593Smuzhiyun {
1463*4882a593Smuzhiyun struct ov8856 *ov8856 = to_ov8856(sd);
1464*4882a593Smuzhiyun const struct ov8856_mode *mode;
1465*4882a593Smuzhiyun s32 vblank_def, h_blank;
1466*4882a593Smuzhiyun
1467*4882a593Smuzhiyun mode = v4l2_find_nearest_size(supported_modes,
1468*4882a593Smuzhiyun ARRAY_SIZE(supported_modes), width,
1469*4882a593Smuzhiyun height, fmt->format.width,
1470*4882a593Smuzhiyun fmt->format.height);
1471*4882a593Smuzhiyun
1472*4882a593Smuzhiyun mutex_lock(&ov8856->mutex);
1473*4882a593Smuzhiyun ov8856_update_pad_format(mode, &fmt->format);
1474*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1475*4882a593Smuzhiyun *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
1476*4882a593Smuzhiyun } else {
1477*4882a593Smuzhiyun ov8856->cur_mode = mode;
1478*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(ov8856->link_freq, mode->link_freq_index);
1479*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl_int64(ov8856->pixel_rate,
1480*4882a593Smuzhiyun to_pixel_rate(mode->link_freq_index));
1481*4882a593Smuzhiyun
1482*4882a593Smuzhiyun /* Update limits and set FPS to default */
1483*4882a593Smuzhiyun vblank_def = mode->vts_def - mode->height;
1484*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov8856->vblank,
1485*4882a593Smuzhiyun mode->vts_min - mode->height,
1486*4882a593Smuzhiyun OV8856_VTS_MAX - mode->height, 1,
1487*4882a593Smuzhiyun vblank_def);
1488*4882a593Smuzhiyun __v4l2_ctrl_s_ctrl(ov8856->vblank, vblank_def);
1489*4882a593Smuzhiyun h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
1490*4882a593Smuzhiyun mode->width;
1491*4882a593Smuzhiyun __v4l2_ctrl_modify_range(ov8856->hblank, h_blank, h_blank, 1,
1492*4882a593Smuzhiyun h_blank);
1493*4882a593Smuzhiyun }
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun return 0;
1498*4882a593Smuzhiyun }
1499*4882a593Smuzhiyun
ov8856_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)1500*4882a593Smuzhiyun static int ov8856_get_format(struct v4l2_subdev *sd,
1501*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1502*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
1503*4882a593Smuzhiyun {
1504*4882a593Smuzhiyun struct ov8856 *ov8856 = to_ov8856(sd);
1505*4882a593Smuzhiyun
1506*4882a593Smuzhiyun mutex_lock(&ov8856->mutex);
1507*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
1508*4882a593Smuzhiyun fmt->format = *v4l2_subdev_get_try_format(&ov8856->sd, cfg,
1509*4882a593Smuzhiyun fmt->pad);
1510*4882a593Smuzhiyun else
1511*4882a593Smuzhiyun ov8856_update_pad_format(ov8856->cur_mode, &fmt->format);
1512*4882a593Smuzhiyun
1513*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun return 0;
1516*4882a593Smuzhiyun }
1517*4882a593Smuzhiyun
ov8856_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)1518*4882a593Smuzhiyun static int ov8856_enum_mbus_code(struct v4l2_subdev *sd,
1519*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1520*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
1521*4882a593Smuzhiyun {
1522*4882a593Smuzhiyun /* Only one bayer order GRBG is supported */
1523*4882a593Smuzhiyun if (code->index > 0)
1524*4882a593Smuzhiyun return -EINVAL;
1525*4882a593Smuzhiyun
1526*4882a593Smuzhiyun code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1527*4882a593Smuzhiyun
1528*4882a593Smuzhiyun return 0;
1529*4882a593Smuzhiyun }
1530*4882a593Smuzhiyun
ov8856_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)1531*4882a593Smuzhiyun static int ov8856_enum_frame_size(struct v4l2_subdev *sd,
1532*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
1533*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
1534*4882a593Smuzhiyun {
1535*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(supported_modes))
1536*4882a593Smuzhiyun return -EINVAL;
1537*4882a593Smuzhiyun
1538*4882a593Smuzhiyun if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1539*4882a593Smuzhiyun return -EINVAL;
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun fse->min_width = supported_modes[fse->index].width;
1542*4882a593Smuzhiyun fse->max_width = fse->min_width;
1543*4882a593Smuzhiyun fse->min_height = supported_modes[fse->index].height;
1544*4882a593Smuzhiyun fse->max_height = fse->min_height;
1545*4882a593Smuzhiyun
1546*4882a593Smuzhiyun return 0;
1547*4882a593Smuzhiyun }
1548*4882a593Smuzhiyun
ov8856_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1549*4882a593Smuzhiyun static int ov8856_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1550*4882a593Smuzhiyun {
1551*4882a593Smuzhiyun struct ov8856 *ov8856 = to_ov8856(sd);
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun mutex_lock(&ov8856->mutex);
1554*4882a593Smuzhiyun ov8856_update_pad_format(&supported_modes[0],
1555*4882a593Smuzhiyun v4l2_subdev_get_try_format(sd, fh->pad, 0));
1556*4882a593Smuzhiyun mutex_unlock(&ov8856->mutex);
1557*4882a593Smuzhiyun
1558*4882a593Smuzhiyun return 0;
1559*4882a593Smuzhiyun }
1560*4882a593Smuzhiyun
1561*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops ov8856_video_ops = {
1562*4882a593Smuzhiyun .s_stream = ov8856_set_stream,
1563*4882a593Smuzhiyun };
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops ov8856_pad_ops = {
1566*4882a593Smuzhiyun .set_fmt = ov8856_set_format,
1567*4882a593Smuzhiyun .get_fmt = ov8856_get_format,
1568*4882a593Smuzhiyun .enum_mbus_code = ov8856_enum_mbus_code,
1569*4882a593Smuzhiyun .enum_frame_size = ov8856_enum_frame_size,
1570*4882a593Smuzhiyun };
1571*4882a593Smuzhiyun
1572*4882a593Smuzhiyun static const struct v4l2_subdev_ops ov8856_subdev_ops = {
1573*4882a593Smuzhiyun .video = &ov8856_video_ops,
1574*4882a593Smuzhiyun .pad = &ov8856_pad_ops,
1575*4882a593Smuzhiyun };
1576*4882a593Smuzhiyun
1577*4882a593Smuzhiyun static const struct media_entity_operations ov8856_subdev_entity_ops = {
1578*4882a593Smuzhiyun .link_validate = v4l2_subdev_link_validate,
1579*4882a593Smuzhiyun };
1580*4882a593Smuzhiyun
1581*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops ov8856_internal_ops = {
1582*4882a593Smuzhiyun .open = ov8856_open,
1583*4882a593Smuzhiyun };
1584*4882a593Smuzhiyun
ov8856_identify_module(struct ov8856 * ov8856)1585*4882a593Smuzhiyun static int ov8856_identify_module(struct ov8856 *ov8856)
1586*4882a593Smuzhiyun {
1587*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(&ov8856->sd);
1588*4882a593Smuzhiyun int ret;
1589*4882a593Smuzhiyun u32 val;
1590*4882a593Smuzhiyun
1591*4882a593Smuzhiyun ret = ov8856_read_reg(ov8856, OV8856_REG_CHIP_ID,
1592*4882a593Smuzhiyun OV8856_REG_VALUE_24BIT, &val);
1593*4882a593Smuzhiyun if (ret)
1594*4882a593Smuzhiyun return ret;
1595*4882a593Smuzhiyun
1596*4882a593Smuzhiyun if (val != OV8856_CHIP_ID) {
1597*4882a593Smuzhiyun dev_err(&client->dev, "chip id mismatch: %x!=%x",
1598*4882a593Smuzhiyun OV8856_CHIP_ID, val);
1599*4882a593Smuzhiyun return -ENXIO;
1600*4882a593Smuzhiyun }
1601*4882a593Smuzhiyun
1602*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_MODE_SELECT,
1603*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT, OV8856_MODE_STREAMING);
1604*4882a593Smuzhiyun if (ret)
1605*4882a593Smuzhiyun return ret;
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_OTP_MODE_CTRL,
1608*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT, OV8856_OTP_MODE_AUTO);
1609*4882a593Smuzhiyun if (ret) {
1610*4882a593Smuzhiyun dev_err(&client->dev, "failed to set otp mode");
1611*4882a593Smuzhiyun return ret;
1612*4882a593Smuzhiyun }
1613*4882a593Smuzhiyun
1614*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_OTP_LOAD_CTRL,
1615*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT,
1616*4882a593Smuzhiyun OV8856_OTP_LOAD_CTRL_ENABLE);
1617*4882a593Smuzhiyun if (ret) {
1618*4882a593Smuzhiyun dev_err(&client->dev, "failed to enable load control");
1619*4882a593Smuzhiyun return ret;
1620*4882a593Smuzhiyun }
1621*4882a593Smuzhiyun
1622*4882a593Smuzhiyun ret = ov8856_read_reg(ov8856, OV8856_MODULE_REVISION,
1623*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT, &val);
1624*4882a593Smuzhiyun if (ret) {
1625*4882a593Smuzhiyun dev_err(&client->dev, "failed to read module revision");
1626*4882a593Smuzhiyun return ret;
1627*4882a593Smuzhiyun }
1628*4882a593Smuzhiyun
1629*4882a593Smuzhiyun dev_info(&client->dev, "OV8856 revision %x (%s) at address 0x%02x\n",
1630*4882a593Smuzhiyun val,
1631*4882a593Smuzhiyun val == OV8856_2A_MODULE ? "2A" :
1632*4882a593Smuzhiyun val == OV8856_1B_MODULE ? "1B" : "unknown revision",
1633*4882a593Smuzhiyun client->addr);
1634*4882a593Smuzhiyun
1635*4882a593Smuzhiyun ret = ov8856_write_reg(ov8856, OV8856_REG_MODE_SELECT,
1636*4882a593Smuzhiyun OV8856_REG_VALUE_08BIT, OV8856_MODE_STANDBY);
1637*4882a593Smuzhiyun if (ret) {
1638*4882a593Smuzhiyun dev_err(&client->dev, "failed to exit streaming mode");
1639*4882a593Smuzhiyun return ret;
1640*4882a593Smuzhiyun }
1641*4882a593Smuzhiyun
1642*4882a593Smuzhiyun return 0;
1643*4882a593Smuzhiyun }
1644*4882a593Smuzhiyun
ov8856_get_hwcfg(struct ov8856 * ov8856,struct device * dev)1645*4882a593Smuzhiyun static int ov8856_get_hwcfg(struct ov8856 *ov8856, struct device *dev)
1646*4882a593Smuzhiyun {
1647*4882a593Smuzhiyun struct fwnode_handle *ep;
1648*4882a593Smuzhiyun struct fwnode_handle *fwnode = dev_fwnode(dev);
1649*4882a593Smuzhiyun struct v4l2_fwnode_endpoint bus_cfg = {
1650*4882a593Smuzhiyun .bus_type = V4L2_MBUS_CSI2_DPHY
1651*4882a593Smuzhiyun };
1652*4882a593Smuzhiyun u32 xvclk_rate;
1653*4882a593Smuzhiyun int ret;
1654*4882a593Smuzhiyun unsigned int i, j;
1655*4882a593Smuzhiyun
1656*4882a593Smuzhiyun if (!fwnode)
1657*4882a593Smuzhiyun return -ENXIO;
1658*4882a593Smuzhiyun
1659*4882a593Smuzhiyun ret = fwnode_property_read_u32(fwnode, "clock-frequency", &xvclk_rate);
1660*4882a593Smuzhiyun if (ret)
1661*4882a593Smuzhiyun return ret;
1662*4882a593Smuzhiyun
1663*4882a593Smuzhiyun if (!is_acpi_node(fwnode)) {
1664*4882a593Smuzhiyun ov8856->xvclk = devm_clk_get(dev, "xvclk");
1665*4882a593Smuzhiyun if (IS_ERR(ov8856->xvclk)) {
1666*4882a593Smuzhiyun dev_err(dev, "could not get xvclk clock (%pe)\n",
1667*4882a593Smuzhiyun ov8856->xvclk);
1668*4882a593Smuzhiyun return PTR_ERR(ov8856->xvclk);
1669*4882a593Smuzhiyun }
1670*4882a593Smuzhiyun
1671*4882a593Smuzhiyun clk_set_rate(ov8856->xvclk, xvclk_rate);
1672*4882a593Smuzhiyun xvclk_rate = clk_get_rate(ov8856->xvclk);
1673*4882a593Smuzhiyun }
1674*4882a593Smuzhiyun
1675*4882a593Smuzhiyun if (xvclk_rate != OV8856_XVCLK_19_2)
1676*4882a593Smuzhiyun dev_warn(dev, "external clock rate %u is unsupported",
1677*4882a593Smuzhiyun xvclk_rate);
1678*4882a593Smuzhiyun
1679*4882a593Smuzhiyun ov8856->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1680*4882a593Smuzhiyun GPIOD_OUT_LOW);
1681*4882a593Smuzhiyun if (IS_ERR(ov8856->reset_gpio))
1682*4882a593Smuzhiyun return PTR_ERR(ov8856->reset_gpio);
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(ov8856_supply_names); i++)
1685*4882a593Smuzhiyun ov8856->supplies[i].supply = ov8856_supply_names[i];
1686*4882a593Smuzhiyun
1687*4882a593Smuzhiyun ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov8856_supply_names),
1688*4882a593Smuzhiyun ov8856->supplies);
1689*4882a593Smuzhiyun if (ret)
1690*4882a593Smuzhiyun return ret;
1691*4882a593Smuzhiyun
1692*4882a593Smuzhiyun ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1693*4882a593Smuzhiyun if (!ep)
1694*4882a593Smuzhiyun return -ENXIO;
1695*4882a593Smuzhiyun
1696*4882a593Smuzhiyun ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1697*4882a593Smuzhiyun fwnode_handle_put(ep);
1698*4882a593Smuzhiyun if (ret)
1699*4882a593Smuzhiyun return ret;
1700*4882a593Smuzhiyun
1701*4882a593Smuzhiyun if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV8856_DATA_LANES) {
1702*4882a593Smuzhiyun dev_err(dev, "number of CSI2 data lanes %d is not supported",
1703*4882a593Smuzhiyun bus_cfg.bus.mipi_csi2.num_data_lanes);
1704*4882a593Smuzhiyun ret = -EINVAL;
1705*4882a593Smuzhiyun goto check_hwcfg_error;
1706*4882a593Smuzhiyun }
1707*4882a593Smuzhiyun
1708*4882a593Smuzhiyun if (!bus_cfg.nr_of_link_frequencies) {
1709*4882a593Smuzhiyun dev_err(dev, "no link frequencies defined");
1710*4882a593Smuzhiyun ret = -EINVAL;
1711*4882a593Smuzhiyun goto check_hwcfg_error;
1712*4882a593Smuzhiyun }
1713*4882a593Smuzhiyun
1714*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1715*4882a593Smuzhiyun for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1716*4882a593Smuzhiyun if (link_freq_menu_items[i] ==
1717*4882a593Smuzhiyun bus_cfg.link_frequencies[j])
1718*4882a593Smuzhiyun break;
1719*4882a593Smuzhiyun }
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun if (j == bus_cfg.nr_of_link_frequencies) {
1722*4882a593Smuzhiyun dev_err(dev, "no link frequency %lld supported",
1723*4882a593Smuzhiyun link_freq_menu_items[i]);
1724*4882a593Smuzhiyun ret = -EINVAL;
1725*4882a593Smuzhiyun goto check_hwcfg_error;
1726*4882a593Smuzhiyun }
1727*4882a593Smuzhiyun }
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun check_hwcfg_error:
1730*4882a593Smuzhiyun v4l2_fwnode_endpoint_free(&bus_cfg);
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun return ret;
1733*4882a593Smuzhiyun }
1734*4882a593Smuzhiyun
ov8856_remove(struct i2c_client * client)1735*4882a593Smuzhiyun static int ov8856_remove(struct i2c_client *client)
1736*4882a593Smuzhiyun {
1737*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1738*4882a593Smuzhiyun struct ov8856 *ov8856 = to_ov8856(sd);
1739*4882a593Smuzhiyun
1740*4882a593Smuzhiyun v4l2_async_unregister_subdev(sd);
1741*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1742*4882a593Smuzhiyun v4l2_ctrl_handler_free(sd->ctrl_handler);
1743*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1744*4882a593Smuzhiyun mutex_destroy(&ov8856->mutex);
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun __ov8856_power_off(ov8856);
1747*4882a593Smuzhiyun
1748*4882a593Smuzhiyun return 0;
1749*4882a593Smuzhiyun }
1750*4882a593Smuzhiyun
ov8856_probe(struct i2c_client * client)1751*4882a593Smuzhiyun static int ov8856_probe(struct i2c_client *client)
1752*4882a593Smuzhiyun {
1753*4882a593Smuzhiyun struct ov8856 *ov8856;
1754*4882a593Smuzhiyun int ret;
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun ov8856 = devm_kzalloc(&client->dev, sizeof(*ov8856), GFP_KERNEL);
1757*4882a593Smuzhiyun if (!ov8856)
1758*4882a593Smuzhiyun return -ENOMEM;
1759*4882a593Smuzhiyun
1760*4882a593Smuzhiyun ret = ov8856_get_hwcfg(ov8856, &client->dev);
1761*4882a593Smuzhiyun if (ret) {
1762*4882a593Smuzhiyun dev_err(&client->dev, "failed to get HW configuration: %d",
1763*4882a593Smuzhiyun ret);
1764*4882a593Smuzhiyun return ret;
1765*4882a593Smuzhiyun }
1766*4882a593Smuzhiyun
1767*4882a593Smuzhiyun v4l2_i2c_subdev_init(&ov8856->sd, client, &ov8856_subdev_ops);
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun ret = __ov8856_power_on(ov8856);
1770*4882a593Smuzhiyun if (ret) {
1771*4882a593Smuzhiyun dev_err(&client->dev, "failed to power on\n");
1772*4882a593Smuzhiyun return ret;
1773*4882a593Smuzhiyun }
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun ret = ov8856_identify_module(ov8856);
1776*4882a593Smuzhiyun if (ret) {
1777*4882a593Smuzhiyun dev_err(&client->dev, "failed to find sensor: %d", ret);
1778*4882a593Smuzhiyun goto probe_power_off;
1779*4882a593Smuzhiyun }
1780*4882a593Smuzhiyun
1781*4882a593Smuzhiyun mutex_init(&ov8856->mutex);
1782*4882a593Smuzhiyun ov8856->cur_mode = &supported_modes[0];
1783*4882a593Smuzhiyun ret = ov8856_init_controls(ov8856);
1784*4882a593Smuzhiyun if (ret) {
1785*4882a593Smuzhiyun dev_err(&client->dev, "failed to init controls: %d", ret);
1786*4882a593Smuzhiyun goto probe_error_v4l2_ctrl_handler_free;
1787*4882a593Smuzhiyun }
1788*4882a593Smuzhiyun
1789*4882a593Smuzhiyun ov8856->sd.internal_ops = &ov8856_internal_ops;
1790*4882a593Smuzhiyun ov8856->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1791*4882a593Smuzhiyun ov8856->sd.entity.ops = &ov8856_subdev_entity_ops;
1792*4882a593Smuzhiyun ov8856->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1793*4882a593Smuzhiyun ov8856->pad.flags = MEDIA_PAD_FL_SOURCE;
1794*4882a593Smuzhiyun ret = media_entity_pads_init(&ov8856->sd.entity, 1, &ov8856->pad);
1795*4882a593Smuzhiyun if (ret) {
1796*4882a593Smuzhiyun dev_err(&client->dev, "failed to init entity pads: %d", ret);
1797*4882a593Smuzhiyun goto probe_error_v4l2_ctrl_handler_free;
1798*4882a593Smuzhiyun }
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(&ov8856->sd);
1801*4882a593Smuzhiyun if (ret < 0) {
1802*4882a593Smuzhiyun dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1803*4882a593Smuzhiyun ret);
1804*4882a593Smuzhiyun goto probe_error_media_entity_cleanup;
1805*4882a593Smuzhiyun }
1806*4882a593Smuzhiyun
1807*4882a593Smuzhiyun /*
1808*4882a593Smuzhiyun * Device is already turned on by i2c-core with ACPI domain PM.
1809*4882a593Smuzhiyun * Enable runtime PM and turn off the device.
1810*4882a593Smuzhiyun */
1811*4882a593Smuzhiyun pm_runtime_set_active(&client->dev);
1812*4882a593Smuzhiyun pm_runtime_enable(&client->dev);
1813*4882a593Smuzhiyun pm_runtime_idle(&client->dev);
1814*4882a593Smuzhiyun
1815*4882a593Smuzhiyun return 0;
1816*4882a593Smuzhiyun
1817*4882a593Smuzhiyun probe_error_media_entity_cleanup:
1818*4882a593Smuzhiyun media_entity_cleanup(&ov8856->sd.entity);
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun probe_error_v4l2_ctrl_handler_free:
1821*4882a593Smuzhiyun v4l2_ctrl_handler_free(ov8856->sd.ctrl_handler);
1822*4882a593Smuzhiyun mutex_destroy(&ov8856->mutex);
1823*4882a593Smuzhiyun
1824*4882a593Smuzhiyun probe_power_off:
1825*4882a593Smuzhiyun __ov8856_power_off(ov8856);
1826*4882a593Smuzhiyun
1827*4882a593Smuzhiyun return ret;
1828*4882a593Smuzhiyun }
1829*4882a593Smuzhiyun
1830*4882a593Smuzhiyun static const struct dev_pm_ops ov8856_pm_ops = {
1831*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(ov8856_suspend, ov8856_resume)
1832*4882a593Smuzhiyun };
1833*4882a593Smuzhiyun
1834*4882a593Smuzhiyun #ifdef CONFIG_ACPI
1835*4882a593Smuzhiyun static const struct acpi_device_id ov8856_acpi_ids[] = {
1836*4882a593Smuzhiyun {"OVTI8856"},
1837*4882a593Smuzhiyun {}
1838*4882a593Smuzhiyun };
1839*4882a593Smuzhiyun
1840*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, ov8856_acpi_ids);
1841*4882a593Smuzhiyun #endif
1842*4882a593Smuzhiyun
1843*4882a593Smuzhiyun static const struct of_device_id ov8856_of_match[] = {
1844*4882a593Smuzhiyun { .compatible = "ovti,ov8856" },
1845*4882a593Smuzhiyun { /* sentinel */ }
1846*4882a593Smuzhiyun };
1847*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ov8856_of_match);
1848*4882a593Smuzhiyun
1849*4882a593Smuzhiyun static struct i2c_driver ov8856_i2c_driver = {
1850*4882a593Smuzhiyun .driver = {
1851*4882a593Smuzhiyun .name = "ov8856",
1852*4882a593Smuzhiyun .pm = &ov8856_pm_ops,
1853*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(ov8856_acpi_ids),
1854*4882a593Smuzhiyun .of_match_table = ov8856_of_match,
1855*4882a593Smuzhiyun },
1856*4882a593Smuzhiyun .probe_new = ov8856_probe,
1857*4882a593Smuzhiyun .remove = ov8856_remove,
1858*4882a593Smuzhiyun };
1859*4882a593Smuzhiyun
1860*4882a593Smuzhiyun module_i2c_driver(ov8856_i2c_driver);
1861*4882a593Smuzhiyun
1862*4882a593Smuzhiyun MODULE_AUTHOR("Ben Kao <ben.kao@intel.com>");
1863*4882a593Smuzhiyun MODULE_DESCRIPTION("OmniVision OV8856 sensor driver");
1864*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1865