xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/ov5675.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (c) 2019 Intel Corporation.
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun #include <asm/unaligned.h>
5*4882a593Smuzhiyun #include <linux/acpi.h>
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/i2c.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/pm_runtime.h>
10*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
11*4882a593Smuzhiyun #include <media/v4l2-device.h>
12*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #define OV5675_REG_VALUE_08BIT		1
15*4882a593Smuzhiyun #define OV5675_REG_VALUE_16BIT		2
16*4882a593Smuzhiyun #define OV5675_REG_VALUE_24BIT		3
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define OV5675_LINK_FREQ_450MHZ		450000000ULL
19*4882a593Smuzhiyun #define OV5675_SCLK			90000000LL
20*4882a593Smuzhiyun #define OV5675_MCLK			19200000
21*4882a593Smuzhiyun #define OV5675_DATA_LANES		2
22*4882a593Smuzhiyun #define OV5675_RGB_DEPTH		10
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #define OV5675_REG_CHIP_ID		0x300a
25*4882a593Smuzhiyun #define OV5675_CHIP_ID			0x5675
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define OV5675_REG_MODE_SELECT		0x0100
28*4882a593Smuzhiyun #define OV5675_MODE_STANDBY		0x00
29*4882a593Smuzhiyun #define OV5675_MODE_STREAMING		0x01
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /* vertical-timings from sensor */
32*4882a593Smuzhiyun #define OV5675_REG_VTS			0x380e
33*4882a593Smuzhiyun #define OV5675_VTS_30FPS		0x07e4
34*4882a593Smuzhiyun #define OV5675_VTS_30FPS_MIN		0x07e4
35*4882a593Smuzhiyun #define OV5675_VTS_MAX			0x7fff
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /* horizontal-timings from sensor */
38*4882a593Smuzhiyun #define OV5675_REG_HTS			0x380c
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /* Exposure controls from sensor */
41*4882a593Smuzhiyun #define OV5675_REG_EXPOSURE		0x3500
42*4882a593Smuzhiyun #define	OV5675_EXPOSURE_MIN		4
43*4882a593Smuzhiyun #define OV5675_EXPOSURE_MAX_MARGIN	4
44*4882a593Smuzhiyun #define	OV5675_EXPOSURE_STEP		1
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* Analog gain controls from sensor */
47*4882a593Smuzhiyun #define OV5675_REG_ANALOG_GAIN		0x3508
48*4882a593Smuzhiyun #define	OV5675_ANAL_GAIN_MIN		128
49*4882a593Smuzhiyun #define	OV5675_ANAL_GAIN_MAX		2047
50*4882a593Smuzhiyun #define	OV5675_ANAL_GAIN_STEP		1
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* Digital gain controls from sensor */
53*4882a593Smuzhiyun #define OV5675_REG_MWB_R_GAIN		0x5019
54*4882a593Smuzhiyun #define OV5675_REG_MWB_G_GAIN		0x501b
55*4882a593Smuzhiyun #define OV5675_REG_MWB_B_GAIN		0x501d
56*4882a593Smuzhiyun #define OV5675_DGTL_GAIN_MIN		0
57*4882a593Smuzhiyun #define OV5675_DGTL_GAIN_MAX		4095
58*4882a593Smuzhiyun #define OV5675_DGTL_GAIN_STEP		1
59*4882a593Smuzhiyun #define OV5675_DGTL_GAIN_DEFAULT	1024
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* Test Pattern Control */
62*4882a593Smuzhiyun #define OV5675_REG_TEST_PATTERN		0x4503
63*4882a593Smuzhiyun #define OV5675_TEST_PATTERN_ENABLE	BIT(7)
64*4882a593Smuzhiyun #define OV5675_TEST_PATTERN_BAR_SHIFT	2
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /* Flip Mirror Controls from sensor */
67*4882a593Smuzhiyun #define OV5675_REG_FORMAT1		0x3820
68*4882a593Smuzhiyun #define OV5675_REG_FORMAT2		0x373d
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun #define to_ov5675(_sd)			container_of(_sd, struct ov5675, sd)
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun enum {
73*4882a593Smuzhiyun 	OV5675_LINK_FREQ_900MBPS,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun struct ov5675_reg {
77*4882a593Smuzhiyun 	u16 address;
78*4882a593Smuzhiyun 	u8 val;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun struct ov5675_reg_list {
82*4882a593Smuzhiyun 	u32 num_of_regs;
83*4882a593Smuzhiyun 	const struct ov5675_reg *regs;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun struct ov5675_link_freq_config {
87*4882a593Smuzhiyun 	const struct ov5675_reg_list reg_list;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun struct ov5675_mode {
91*4882a593Smuzhiyun 	/* Frame width in pixels */
92*4882a593Smuzhiyun 	u32 width;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	/* Frame height in pixels */
95*4882a593Smuzhiyun 	u32 height;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	/* Horizontal timining size */
98*4882a593Smuzhiyun 	u32 hts;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	/* Default vertical timining size */
101*4882a593Smuzhiyun 	u32 vts_def;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	/* Min vertical timining size */
104*4882a593Smuzhiyun 	u32 vts_min;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	/* Link frequency needed for this resolution */
107*4882a593Smuzhiyun 	u32 link_freq_index;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	/* Sensor register settings for this resolution */
110*4882a593Smuzhiyun 	const struct ov5675_reg_list reg_list;
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static const struct ov5675_reg mipi_data_rate_900mbps[] = {
114*4882a593Smuzhiyun 	{0x0103, 0x01},
115*4882a593Smuzhiyun 	{0x0100, 0x00},
116*4882a593Smuzhiyun 	{0x0300, 0x04},
117*4882a593Smuzhiyun 	{0x0302, 0x8d},
118*4882a593Smuzhiyun 	{0x0303, 0x00},
119*4882a593Smuzhiyun 	{0x030d, 0x26},
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static const struct ov5675_reg mode_2592x1944_regs[] = {
123*4882a593Smuzhiyun 	{0x3002, 0x21},
124*4882a593Smuzhiyun 	{0x3107, 0x23},
125*4882a593Smuzhiyun 	{0x3501, 0x20},
126*4882a593Smuzhiyun 	{0x3503, 0x0c},
127*4882a593Smuzhiyun 	{0x3508, 0x03},
128*4882a593Smuzhiyun 	{0x3509, 0x00},
129*4882a593Smuzhiyun 	{0x3600, 0x66},
130*4882a593Smuzhiyun 	{0x3602, 0x30},
131*4882a593Smuzhiyun 	{0x3610, 0xa5},
132*4882a593Smuzhiyun 	{0x3612, 0x93},
133*4882a593Smuzhiyun 	{0x3620, 0x80},
134*4882a593Smuzhiyun 	{0x3642, 0x0e},
135*4882a593Smuzhiyun 	{0x3661, 0x00},
136*4882a593Smuzhiyun 	{0x3662, 0x10},
137*4882a593Smuzhiyun 	{0x3664, 0xf3},
138*4882a593Smuzhiyun 	{0x3665, 0x9e},
139*4882a593Smuzhiyun 	{0x3667, 0xa5},
140*4882a593Smuzhiyun 	{0x366e, 0x55},
141*4882a593Smuzhiyun 	{0x366f, 0x55},
142*4882a593Smuzhiyun 	{0x3670, 0x11},
143*4882a593Smuzhiyun 	{0x3671, 0x11},
144*4882a593Smuzhiyun 	{0x3672, 0x11},
145*4882a593Smuzhiyun 	{0x3673, 0x11},
146*4882a593Smuzhiyun 	{0x3714, 0x24},
147*4882a593Smuzhiyun 	{0x371a, 0x3e},
148*4882a593Smuzhiyun 	{0x3733, 0x10},
149*4882a593Smuzhiyun 	{0x3734, 0x00},
150*4882a593Smuzhiyun 	{0x373d, 0x24},
151*4882a593Smuzhiyun 	{0x3764, 0x20},
152*4882a593Smuzhiyun 	{0x3765, 0x20},
153*4882a593Smuzhiyun 	{0x3766, 0x12},
154*4882a593Smuzhiyun 	{0x37a1, 0x14},
155*4882a593Smuzhiyun 	{0x37a8, 0x1c},
156*4882a593Smuzhiyun 	{0x37ab, 0x0f},
157*4882a593Smuzhiyun 	{0x37c2, 0x04},
158*4882a593Smuzhiyun 	{0x37cb, 0x00},
159*4882a593Smuzhiyun 	{0x37cc, 0x00},
160*4882a593Smuzhiyun 	{0x37cd, 0x00},
161*4882a593Smuzhiyun 	{0x37ce, 0x00},
162*4882a593Smuzhiyun 	{0x37d8, 0x02},
163*4882a593Smuzhiyun 	{0x37d9, 0x08},
164*4882a593Smuzhiyun 	{0x37dc, 0x04},
165*4882a593Smuzhiyun 	{0x3800, 0x00},
166*4882a593Smuzhiyun 	{0x3801, 0x00},
167*4882a593Smuzhiyun 	{0x3802, 0x00},
168*4882a593Smuzhiyun 	{0x3803, 0x04},
169*4882a593Smuzhiyun 	{0x3804, 0x0a},
170*4882a593Smuzhiyun 	{0x3805, 0x3f},
171*4882a593Smuzhiyun 	{0x3806, 0x07},
172*4882a593Smuzhiyun 	{0x3807, 0xb3},
173*4882a593Smuzhiyun 	{0x3808, 0x0a},
174*4882a593Smuzhiyun 	{0x3809, 0x20},
175*4882a593Smuzhiyun 	{0x380a, 0x07},
176*4882a593Smuzhiyun 	{0x380b, 0x98},
177*4882a593Smuzhiyun 	{0x380c, 0x02},
178*4882a593Smuzhiyun 	{0x380d, 0xee},
179*4882a593Smuzhiyun 	{0x380e, 0x07},
180*4882a593Smuzhiyun 	{0x380f, 0xe4},
181*4882a593Smuzhiyun 	{0x3811, 0x10},
182*4882a593Smuzhiyun 	{0x3813, 0x0d},
183*4882a593Smuzhiyun 	{0x3814, 0x01},
184*4882a593Smuzhiyun 	{0x3815, 0x01},
185*4882a593Smuzhiyun 	{0x3816, 0x01},
186*4882a593Smuzhiyun 	{0x3817, 0x01},
187*4882a593Smuzhiyun 	{0x381e, 0x02},
188*4882a593Smuzhiyun 	{0x3820, 0x88},
189*4882a593Smuzhiyun 	{0x3821, 0x01},
190*4882a593Smuzhiyun 	{0x3832, 0x04},
191*4882a593Smuzhiyun 	{0x3c80, 0x01},
192*4882a593Smuzhiyun 	{0x3c82, 0x00},
193*4882a593Smuzhiyun 	{0x3c83, 0xc8},
194*4882a593Smuzhiyun 	{0x3c8c, 0x0f},
195*4882a593Smuzhiyun 	{0x3c8d, 0xa0},
196*4882a593Smuzhiyun 	{0x3c90, 0x07},
197*4882a593Smuzhiyun 	{0x3c91, 0x00},
198*4882a593Smuzhiyun 	{0x3c92, 0x00},
199*4882a593Smuzhiyun 	{0x3c93, 0x00},
200*4882a593Smuzhiyun 	{0x3c94, 0xd0},
201*4882a593Smuzhiyun 	{0x3c95, 0x50},
202*4882a593Smuzhiyun 	{0x3c96, 0x35},
203*4882a593Smuzhiyun 	{0x3c97, 0x00},
204*4882a593Smuzhiyun 	{0x4001, 0xe0},
205*4882a593Smuzhiyun 	{0x4008, 0x02},
206*4882a593Smuzhiyun 	{0x4009, 0x0d},
207*4882a593Smuzhiyun 	{0x400f, 0x80},
208*4882a593Smuzhiyun 	{0x4013, 0x02},
209*4882a593Smuzhiyun 	{0x4040, 0x00},
210*4882a593Smuzhiyun 	{0x4041, 0x07},
211*4882a593Smuzhiyun 	{0x404c, 0x50},
212*4882a593Smuzhiyun 	{0x404e, 0x20},
213*4882a593Smuzhiyun 	{0x4500, 0x06},
214*4882a593Smuzhiyun 	{0x4503, 0x00},
215*4882a593Smuzhiyun 	{0x450a, 0x04},
216*4882a593Smuzhiyun 	{0x4809, 0x04},
217*4882a593Smuzhiyun 	{0x480c, 0x12},
218*4882a593Smuzhiyun 	{0x4819, 0x70},
219*4882a593Smuzhiyun 	{0x4825, 0x32},
220*4882a593Smuzhiyun 	{0x4826, 0x32},
221*4882a593Smuzhiyun 	{0x482a, 0x06},
222*4882a593Smuzhiyun 	{0x4833, 0x08},
223*4882a593Smuzhiyun 	{0x4837, 0x0d},
224*4882a593Smuzhiyun 	{0x5000, 0x77},
225*4882a593Smuzhiyun 	{0x5b00, 0x01},
226*4882a593Smuzhiyun 	{0x5b01, 0x10},
227*4882a593Smuzhiyun 	{0x5b02, 0x01},
228*4882a593Smuzhiyun 	{0x5b03, 0xdb},
229*4882a593Smuzhiyun 	{0x5b05, 0x6c},
230*4882a593Smuzhiyun 	{0x5e10, 0xfc},
231*4882a593Smuzhiyun 	{0x3500, 0x00},
232*4882a593Smuzhiyun 	{0x3501, 0x3E},
233*4882a593Smuzhiyun 	{0x3502, 0x60},
234*4882a593Smuzhiyun 	{0x3503, 0x08},
235*4882a593Smuzhiyun 	{0x3508, 0x04},
236*4882a593Smuzhiyun 	{0x3509, 0x00},
237*4882a593Smuzhiyun 	{0x3832, 0x48},
238*4882a593Smuzhiyun 	{0x5780, 0x3e},
239*4882a593Smuzhiyun 	{0x5781, 0x0f},
240*4882a593Smuzhiyun 	{0x5782, 0x44},
241*4882a593Smuzhiyun 	{0x5783, 0x02},
242*4882a593Smuzhiyun 	{0x5784, 0x01},
243*4882a593Smuzhiyun 	{0x5785, 0x01},
244*4882a593Smuzhiyun 	{0x5786, 0x00},
245*4882a593Smuzhiyun 	{0x5787, 0x04},
246*4882a593Smuzhiyun 	{0x5788, 0x02},
247*4882a593Smuzhiyun 	{0x5789, 0x0f},
248*4882a593Smuzhiyun 	{0x578a, 0xfd},
249*4882a593Smuzhiyun 	{0x578b, 0xf5},
250*4882a593Smuzhiyun 	{0x578c, 0xf5},
251*4882a593Smuzhiyun 	{0x578d, 0x03},
252*4882a593Smuzhiyun 	{0x578e, 0x08},
253*4882a593Smuzhiyun 	{0x578f, 0x0c},
254*4882a593Smuzhiyun 	{0x5790, 0x08},
255*4882a593Smuzhiyun 	{0x5791, 0x06},
256*4882a593Smuzhiyun 	{0x5792, 0x00},
257*4882a593Smuzhiyun 	{0x5793, 0x52},
258*4882a593Smuzhiyun 	{0x5794, 0xa3},
259*4882a593Smuzhiyun 	{0x4003, 0x40},
260*4882a593Smuzhiyun 	{0x3107, 0x01},
261*4882a593Smuzhiyun 	{0x3c80, 0x08},
262*4882a593Smuzhiyun 	{0x3c83, 0xb1},
263*4882a593Smuzhiyun 	{0x3c8c, 0x10},
264*4882a593Smuzhiyun 	{0x3c8d, 0x00},
265*4882a593Smuzhiyun 	{0x3c90, 0x00},
266*4882a593Smuzhiyun 	{0x3c94, 0x00},
267*4882a593Smuzhiyun 	{0x3c95, 0x00},
268*4882a593Smuzhiyun 	{0x3c96, 0x00},
269*4882a593Smuzhiyun 	{0x37cb, 0x09},
270*4882a593Smuzhiyun 	{0x37cc, 0x15},
271*4882a593Smuzhiyun 	{0x37cd, 0x1f},
272*4882a593Smuzhiyun 	{0x37ce, 0x1f},
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun static const struct ov5675_reg mode_1296x972_regs[] = {
276*4882a593Smuzhiyun 	{0x3002, 0x21},
277*4882a593Smuzhiyun 	{0x3107, 0x23},
278*4882a593Smuzhiyun 	{0x3501, 0x20},
279*4882a593Smuzhiyun 	{0x3503, 0x0c},
280*4882a593Smuzhiyun 	{0x3508, 0x03},
281*4882a593Smuzhiyun 	{0x3509, 0x00},
282*4882a593Smuzhiyun 	{0x3600, 0x66},
283*4882a593Smuzhiyun 	{0x3602, 0x30},
284*4882a593Smuzhiyun 	{0x3610, 0xa5},
285*4882a593Smuzhiyun 	{0x3612, 0x93},
286*4882a593Smuzhiyun 	{0x3620, 0x80},
287*4882a593Smuzhiyun 	{0x3642, 0x0e},
288*4882a593Smuzhiyun 	{0x3661, 0x00},
289*4882a593Smuzhiyun 	{0x3662, 0x08},
290*4882a593Smuzhiyun 	{0x3664, 0xf3},
291*4882a593Smuzhiyun 	{0x3665, 0x9e},
292*4882a593Smuzhiyun 	{0x3667, 0xa5},
293*4882a593Smuzhiyun 	{0x366e, 0x55},
294*4882a593Smuzhiyun 	{0x366f, 0x55},
295*4882a593Smuzhiyun 	{0x3670, 0x11},
296*4882a593Smuzhiyun 	{0x3671, 0x11},
297*4882a593Smuzhiyun 	{0x3672, 0x11},
298*4882a593Smuzhiyun 	{0x3673, 0x11},
299*4882a593Smuzhiyun 	{0x3714, 0x28},
300*4882a593Smuzhiyun 	{0x371a, 0x3e},
301*4882a593Smuzhiyun 	{0x3733, 0x10},
302*4882a593Smuzhiyun 	{0x3734, 0x00},
303*4882a593Smuzhiyun 	{0x373d, 0x24},
304*4882a593Smuzhiyun 	{0x3764, 0x20},
305*4882a593Smuzhiyun 	{0x3765, 0x20},
306*4882a593Smuzhiyun 	{0x3766, 0x12},
307*4882a593Smuzhiyun 	{0x37a1, 0x14},
308*4882a593Smuzhiyun 	{0x37a8, 0x1c},
309*4882a593Smuzhiyun 	{0x37ab, 0x0f},
310*4882a593Smuzhiyun 	{0x37c2, 0x14},
311*4882a593Smuzhiyun 	{0x37cb, 0x00},
312*4882a593Smuzhiyun 	{0x37cc, 0x00},
313*4882a593Smuzhiyun 	{0x37cd, 0x00},
314*4882a593Smuzhiyun 	{0x37ce, 0x00},
315*4882a593Smuzhiyun 	{0x37d8, 0x02},
316*4882a593Smuzhiyun 	{0x37d9, 0x04},
317*4882a593Smuzhiyun 	{0x37dc, 0x04},
318*4882a593Smuzhiyun 	{0x3800, 0x00},
319*4882a593Smuzhiyun 	{0x3801, 0x00},
320*4882a593Smuzhiyun 	{0x3802, 0x00},
321*4882a593Smuzhiyun 	{0x3803, 0x00},
322*4882a593Smuzhiyun 	{0x3804, 0x0a},
323*4882a593Smuzhiyun 	{0x3805, 0x3f},
324*4882a593Smuzhiyun 	{0x3806, 0x07},
325*4882a593Smuzhiyun 	{0x3807, 0xb7},
326*4882a593Smuzhiyun 	{0x3808, 0x05},
327*4882a593Smuzhiyun 	{0x3809, 0x10},
328*4882a593Smuzhiyun 	{0x380a, 0x03},
329*4882a593Smuzhiyun 	{0x380b, 0xcc},
330*4882a593Smuzhiyun 	{0x380c, 0x02},
331*4882a593Smuzhiyun 	{0x380d, 0xee},
332*4882a593Smuzhiyun 	{0x380e, 0x07},
333*4882a593Smuzhiyun 	{0x380f, 0xd0},
334*4882a593Smuzhiyun 	{0x3811, 0x08},
335*4882a593Smuzhiyun 	{0x3813, 0x0d},
336*4882a593Smuzhiyun 	{0x3814, 0x03},
337*4882a593Smuzhiyun 	{0x3815, 0x01},
338*4882a593Smuzhiyun 	{0x3816, 0x03},
339*4882a593Smuzhiyun 	{0x3817, 0x01},
340*4882a593Smuzhiyun 	{0x381e, 0x02},
341*4882a593Smuzhiyun 	{0x3820, 0x8b},
342*4882a593Smuzhiyun 	{0x3821, 0x01},
343*4882a593Smuzhiyun 	{0x3832, 0x04},
344*4882a593Smuzhiyun 	{0x3c80, 0x01},
345*4882a593Smuzhiyun 	{0x3c82, 0x00},
346*4882a593Smuzhiyun 	{0x3c83, 0xc8},
347*4882a593Smuzhiyun 	{0x3c8c, 0x0f},
348*4882a593Smuzhiyun 	{0x3c8d, 0xa0},
349*4882a593Smuzhiyun 	{0x3c90, 0x07},
350*4882a593Smuzhiyun 	{0x3c91, 0x00},
351*4882a593Smuzhiyun 	{0x3c92, 0x00},
352*4882a593Smuzhiyun 	{0x3c93, 0x00},
353*4882a593Smuzhiyun 	{0x3c94, 0xd0},
354*4882a593Smuzhiyun 	{0x3c95, 0x50},
355*4882a593Smuzhiyun 	{0x3c96, 0x35},
356*4882a593Smuzhiyun 	{0x3c97, 0x00},
357*4882a593Smuzhiyun 	{0x4001, 0xe0},
358*4882a593Smuzhiyun 	{0x4008, 0x00},
359*4882a593Smuzhiyun 	{0x4009, 0x07},
360*4882a593Smuzhiyun 	{0x400f, 0x80},
361*4882a593Smuzhiyun 	{0x4013, 0x02},
362*4882a593Smuzhiyun 	{0x4040, 0x00},
363*4882a593Smuzhiyun 	{0x4041, 0x03},
364*4882a593Smuzhiyun 	{0x404c, 0x50},
365*4882a593Smuzhiyun 	{0x404e, 0x20},
366*4882a593Smuzhiyun 	{0x4500, 0x06},
367*4882a593Smuzhiyun 	{0x4503, 0x00},
368*4882a593Smuzhiyun 	{0x450a, 0x04},
369*4882a593Smuzhiyun 	{0x4809, 0x04},
370*4882a593Smuzhiyun 	{0x480c, 0x12},
371*4882a593Smuzhiyun 	{0x4819, 0x70},
372*4882a593Smuzhiyun 	{0x4825, 0x32},
373*4882a593Smuzhiyun 	{0x4826, 0x32},
374*4882a593Smuzhiyun 	{0x482a, 0x06},
375*4882a593Smuzhiyun 	{0x4833, 0x08},
376*4882a593Smuzhiyun 	{0x4837, 0x0d},
377*4882a593Smuzhiyun 	{0x5000, 0x77},
378*4882a593Smuzhiyun 	{0x5b00, 0x01},
379*4882a593Smuzhiyun 	{0x5b01, 0x10},
380*4882a593Smuzhiyun 	{0x5b02, 0x01},
381*4882a593Smuzhiyun 	{0x5b03, 0xdb},
382*4882a593Smuzhiyun 	{0x5b05, 0x6c},
383*4882a593Smuzhiyun 	{0x5e10, 0xfc},
384*4882a593Smuzhiyun 	{0x3500, 0x00},
385*4882a593Smuzhiyun 	{0x3501, 0x1F},
386*4882a593Smuzhiyun 	{0x3502, 0x20},
387*4882a593Smuzhiyun 	{0x3503, 0x08},
388*4882a593Smuzhiyun 	{0x3508, 0x04},
389*4882a593Smuzhiyun 	{0x3509, 0x00},
390*4882a593Smuzhiyun 	{0x3832, 0x48},
391*4882a593Smuzhiyun 	{0x5780, 0x3e},
392*4882a593Smuzhiyun 	{0x5781, 0x0f},
393*4882a593Smuzhiyun 	{0x5782, 0x44},
394*4882a593Smuzhiyun 	{0x5783, 0x02},
395*4882a593Smuzhiyun 	{0x5784, 0x01},
396*4882a593Smuzhiyun 	{0x5785, 0x01},
397*4882a593Smuzhiyun 	{0x5786, 0x00},
398*4882a593Smuzhiyun 	{0x5787, 0x04},
399*4882a593Smuzhiyun 	{0x5788, 0x02},
400*4882a593Smuzhiyun 	{0x5789, 0x0f},
401*4882a593Smuzhiyun 	{0x578a, 0xfd},
402*4882a593Smuzhiyun 	{0x578b, 0xf5},
403*4882a593Smuzhiyun 	{0x578c, 0xf5},
404*4882a593Smuzhiyun 	{0x578d, 0x03},
405*4882a593Smuzhiyun 	{0x578e, 0x08},
406*4882a593Smuzhiyun 	{0x578f, 0x0c},
407*4882a593Smuzhiyun 	{0x5790, 0x08},
408*4882a593Smuzhiyun 	{0x5791, 0x06},
409*4882a593Smuzhiyun 	{0x5792, 0x00},
410*4882a593Smuzhiyun 	{0x5793, 0x52},
411*4882a593Smuzhiyun 	{0x5794, 0xa3},
412*4882a593Smuzhiyun 	{0x4003, 0x40},
413*4882a593Smuzhiyun 	{0x3107, 0x01},
414*4882a593Smuzhiyun 	{0x3c80, 0x08},
415*4882a593Smuzhiyun 	{0x3c83, 0xb1},
416*4882a593Smuzhiyun 	{0x3c8c, 0x10},
417*4882a593Smuzhiyun 	{0x3c8d, 0x00},
418*4882a593Smuzhiyun 	{0x3c90, 0x00},
419*4882a593Smuzhiyun 	{0x3c94, 0x00},
420*4882a593Smuzhiyun 	{0x3c95, 0x00},
421*4882a593Smuzhiyun 	{0x3c96, 0x00},
422*4882a593Smuzhiyun 	{0x37cb, 0x09},
423*4882a593Smuzhiyun 	{0x37cc, 0x15},
424*4882a593Smuzhiyun 	{0x37cd, 0x1f},
425*4882a593Smuzhiyun 	{0x37ce, 0x1f},
426*4882a593Smuzhiyun };
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun static const char * const ov5675_test_pattern_menu[] = {
429*4882a593Smuzhiyun 	"Disabled",
430*4882a593Smuzhiyun 	"Standard Color Bar",
431*4882a593Smuzhiyun 	"Top-Bottom Darker Color Bar",
432*4882a593Smuzhiyun 	"Right-Left Darker Color Bar",
433*4882a593Smuzhiyun 	"Bottom-Top Darker Color Bar"
434*4882a593Smuzhiyun };
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun static const s64 link_freq_menu_items[] = {
437*4882a593Smuzhiyun 	OV5675_LINK_FREQ_450MHZ,
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun static const struct ov5675_link_freq_config link_freq_configs[] = {
441*4882a593Smuzhiyun 	[OV5675_LINK_FREQ_900MBPS] = {
442*4882a593Smuzhiyun 		.reg_list = {
443*4882a593Smuzhiyun 			.num_of_regs = ARRAY_SIZE(mipi_data_rate_900mbps),
444*4882a593Smuzhiyun 			.regs = mipi_data_rate_900mbps,
445*4882a593Smuzhiyun 		}
446*4882a593Smuzhiyun 	}
447*4882a593Smuzhiyun };
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun static const struct ov5675_mode supported_modes[] = {
450*4882a593Smuzhiyun 	{
451*4882a593Smuzhiyun 		.width = 2592,
452*4882a593Smuzhiyun 		.height = 1944,
453*4882a593Smuzhiyun 		.hts = 1500,
454*4882a593Smuzhiyun 		.vts_def = OV5675_VTS_30FPS,
455*4882a593Smuzhiyun 		.vts_min = OV5675_VTS_30FPS_MIN,
456*4882a593Smuzhiyun 		.reg_list = {
457*4882a593Smuzhiyun 			.num_of_regs = ARRAY_SIZE(mode_2592x1944_regs),
458*4882a593Smuzhiyun 			.regs = mode_2592x1944_regs,
459*4882a593Smuzhiyun 		},
460*4882a593Smuzhiyun 		.link_freq_index = OV5675_LINK_FREQ_900MBPS,
461*4882a593Smuzhiyun 	},
462*4882a593Smuzhiyun 	{
463*4882a593Smuzhiyun 		.width = 1296,
464*4882a593Smuzhiyun 		.height = 972,
465*4882a593Smuzhiyun 		.hts = 1500,
466*4882a593Smuzhiyun 		.vts_def = OV5675_VTS_30FPS,
467*4882a593Smuzhiyun 		.vts_min = OV5675_VTS_30FPS_MIN,
468*4882a593Smuzhiyun 		.reg_list = {
469*4882a593Smuzhiyun 			.num_of_regs = ARRAY_SIZE(mode_1296x972_regs),
470*4882a593Smuzhiyun 			.regs = mode_1296x972_regs,
471*4882a593Smuzhiyun 		},
472*4882a593Smuzhiyun 		.link_freq_index = OV5675_LINK_FREQ_900MBPS,
473*4882a593Smuzhiyun 	}
474*4882a593Smuzhiyun };
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun struct ov5675 {
477*4882a593Smuzhiyun 	struct v4l2_subdev sd;
478*4882a593Smuzhiyun 	struct media_pad pad;
479*4882a593Smuzhiyun 	struct v4l2_ctrl_handler ctrl_handler;
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	/* V4L2 Controls */
482*4882a593Smuzhiyun 	struct v4l2_ctrl *link_freq;
483*4882a593Smuzhiyun 	struct v4l2_ctrl *pixel_rate;
484*4882a593Smuzhiyun 	struct v4l2_ctrl *vblank;
485*4882a593Smuzhiyun 	struct v4l2_ctrl *hblank;
486*4882a593Smuzhiyun 	struct v4l2_ctrl *exposure;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	/* Current mode */
489*4882a593Smuzhiyun 	const struct ov5675_mode *cur_mode;
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	/* To serialize asynchronus callbacks */
492*4882a593Smuzhiyun 	struct mutex mutex;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	/* Streaming on/off */
495*4882a593Smuzhiyun 	bool streaming;
496*4882a593Smuzhiyun };
497*4882a593Smuzhiyun 
to_pixel_rate(u32 f_index)498*4882a593Smuzhiyun static u64 to_pixel_rate(u32 f_index)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun 	u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV5675_DATA_LANES;
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	do_div(pixel_rate, OV5675_RGB_DEPTH);
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	return pixel_rate;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun 
to_pixels_per_line(u32 hts,u32 f_index)507*4882a593Smuzhiyun static u64 to_pixels_per_line(u32 hts, u32 f_index)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	u64 ppl = hts * to_pixel_rate(f_index);
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	do_div(ppl, OV5675_SCLK);
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	return ppl;
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun 
ov5675_read_reg(struct ov5675 * ov5675,u16 reg,u16 len,u32 * val)516*4882a593Smuzhiyun static int ov5675_read_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 *val)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
519*4882a593Smuzhiyun 	struct i2c_msg msgs[2];
520*4882a593Smuzhiyun 	u8 addr_buf[2];
521*4882a593Smuzhiyun 	u8 data_buf[4] = {0};
522*4882a593Smuzhiyun 	int ret;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	if (len > 4)
525*4882a593Smuzhiyun 		return -EINVAL;
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	put_unaligned_be16(reg, addr_buf);
528*4882a593Smuzhiyun 	msgs[0].addr = client->addr;
529*4882a593Smuzhiyun 	msgs[0].flags = 0;
530*4882a593Smuzhiyun 	msgs[0].len = sizeof(addr_buf);
531*4882a593Smuzhiyun 	msgs[0].buf = addr_buf;
532*4882a593Smuzhiyun 	msgs[1].addr = client->addr;
533*4882a593Smuzhiyun 	msgs[1].flags = I2C_M_RD;
534*4882a593Smuzhiyun 	msgs[1].len = len;
535*4882a593Smuzhiyun 	msgs[1].buf = &data_buf[4 - len];
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
538*4882a593Smuzhiyun 	if (ret != ARRAY_SIZE(msgs))
539*4882a593Smuzhiyun 		return -EIO;
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	*val = get_unaligned_be32(data_buf);
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	return 0;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun 
ov5675_write_reg(struct ov5675 * ov5675,u16 reg,u16 len,u32 val)546*4882a593Smuzhiyun static int ov5675_write_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 val)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
549*4882a593Smuzhiyun 	u8 buf[6];
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	if (len > 4)
552*4882a593Smuzhiyun 		return -EINVAL;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	put_unaligned_be16(reg, buf);
555*4882a593Smuzhiyun 	put_unaligned_be32(val << 8 * (4 - len), buf + 2);
556*4882a593Smuzhiyun 	if (i2c_master_send(client, buf, len + 2) != len + 2)
557*4882a593Smuzhiyun 		return -EIO;
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	return 0;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun 
ov5675_write_reg_list(struct ov5675 * ov5675,const struct ov5675_reg_list * r_list)562*4882a593Smuzhiyun static int ov5675_write_reg_list(struct ov5675 *ov5675,
563*4882a593Smuzhiyun 				 const struct ov5675_reg_list *r_list)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
566*4882a593Smuzhiyun 	unsigned int i;
567*4882a593Smuzhiyun 	int ret;
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	for (i = 0; i < r_list->num_of_regs; i++) {
570*4882a593Smuzhiyun 		ret = ov5675_write_reg(ov5675, r_list->regs[i].address, 1,
571*4882a593Smuzhiyun 				       r_list->regs[i].val);
572*4882a593Smuzhiyun 		if (ret) {
573*4882a593Smuzhiyun 			dev_err_ratelimited(&client->dev,
574*4882a593Smuzhiyun 				    "failed to write reg 0x%4.4x. error = %d",
575*4882a593Smuzhiyun 				    r_list->regs[i].address, ret);
576*4882a593Smuzhiyun 			return ret;
577*4882a593Smuzhiyun 		}
578*4882a593Smuzhiyun 	}
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	return 0;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun 
ov5675_update_digital_gain(struct ov5675 * ov5675,u32 d_gain)583*4882a593Smuzhiyun static int ov5675_update_digital_gain(struct ov5675 *ov5675, u32 d_gain)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun 	int ret;
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_R_GAIN,
588*4882a593Smuzhiyun 			       OV5675_REG_VALUE_16BIT, d_gain);
589*4882a593Smuzhiyun 	if (ret)
590*4882a593Smuzhiyun 		return ret;
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_G_GAIN,
593*4882a593Smuzhiyun 			       OV5675_REG_VALUE_16BIT, d_gain);
594*4882a593Smuzhiyun 	if (ret)
595*4882a593Smuzhiyun 		return ret;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	return ov5675_write_reg(ov5675, OV5675_REG_MWB_B_GAIN,
598*4882a593Smuzhiyun 				OV5675_REG_VALUE_16BIT, d_gain);
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun 
ov5675_test_pattern(struct ov5675 * ov5675,u32 pattern)601*4882a593Smuzhiyun static int ov5675_test_pattern(struct ov5675 *ov5675, u32 pattern)
602*4882a593Smuzhiyun {
603*4882a593Smuzhiyun 	if (pattern)
604*4882a593Smuzhiyun 		pattern = (pattern - 1) << OV5675_TEST_PATTERN_BAR_SHIFT |
605*4882a593Smuzhiyun 			  OV5675_TEST_PATTERN_ENABLE;
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	return ov5675_write_reg(ov5675, OV5675_REG_TEST_PATTERN,
608*4882a593Smuzhiyun 				OV5675_REG_VALUE_08BIT, pattern);
609*4882a593Smuzhiyun }
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun /*
612*4882a593Smuzhiyun  * OV5675 supports keeping the pixel order by mirror and flip function
613*4882a593Smuzhiyun  * The Bayer order isn't affected by the flip controls
614*4882a593Smuzhiyun  */
ov5675_set_ctrl_hflip(struct ov5675 * ov5675,u32 ctrl_val)615*4882a593Smuzhiyun static int ov5675_set_ctrl_hflip(struct ov5675 *ov5675, u32 ctrl_val)
616*4882a593Smuzhiyun {
617*4882a593Smuzhiyun 	int ret;
618*4882a593Smuzhiyun 	u32 val;
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun 	ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1,
621*4882a593Smuzhiyun 			      OV5675_REG_VALUE_08BIT, &val);
622*4882a593Smuzhiyun 	if (ret)
623*4882a593Smuzhiyun 		return ret;
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun 	return ov5675_write_reg(ov5675, OV5675_REG_FORMAT1,
626*4882a593Smuzhiyun 				OV5675_REG_VALUE_08BIT,
627*4882a593Smuzhiyun 				ctrl_val ? val & ~BIT(3) : val);
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun 
ov5675_set_ctrl_vflip(struct ov5675 * ov5675,u8 ctrl_val)630*4882a593Smuzhiyun static int ov5675_set_ctrl_vflip(struct ov5675 *ov5675, u8 ctrl_val)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun 	int ret;
633*4882a593Smuzhiyun 	u32 val;
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 	ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1,
636*4882a593Smuzhiyun 			      OV5675_REG_VALUE_08BIT, &val);
637*4882a593Smuzhiyun 	if (ret)
638*4882a593Smuzhiyun 		return ret;
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	ret = ov5675_write_reg(ov5675, OV5675_REG_FORMAT1,
641*4882a593Smuzhiyun 			       OV5675_REG_VALUE_08BIT,
642*4882a593Smuzhiyun 			       ctrl_val ? val | BIT(4) | BIT(5)  : val);
643*4882a593Smuzhiyun 
644*4882a593Smuzhiyun 	if (ret)
645*4882a593Smuzhiyun 		return ret;
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT2,
648*4882a593Smuzhiyun 			      OV5675_REG_VALUE_08BIT, &val);
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	if (ret)
651*4882a593Smuzhiyun 		return ret;
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	return ov5675_write_reg(ov5675, OV5675_REG_FORMAT2,
654*4882a593Smuzhiyun 				OV5675_REG_VALUE_08BIT,
655*4882a593Smuzhiyun 				ctrl_val ? val | BIT(1) : val);
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun 
ov5675_set_ctrl(struct v4l2_ctrl * ctrl)658*4882a593Smuzhiyun static int ov5675_set_ctrl(struct v4l2_ctrl *ctrl)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun 	struct ov5675 *ov5675 = container_of(ctrl->handler,
661*4882a593Smuzhiyun 					     struct ov5675, ctrl_handler);
662*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
663*4882a593Smuzhiyun 	s64 exposure_max;
664*4882a593Smuzhiyun 	int ret = 0;
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	/* Propagate change of current control to all related controls */
667*4882a593Smuzhiyun 	if (ctrl->id == V4L2_CID_VBLANK) {
668*4882a593Smuzhiyun 		/* Update max exposure while meeting expected vblanking */
669*4882a593Smuzhiyun 		exposure_max = ov5675->cur_mode->height + ctrl->val -
670*4882a593Smuzhiyun 			OV5675_EXPOSURE_MAX_MARGIN;
671*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(ov5675->exposure,
672*4882a593Smuzhiyun 					 ov5675->exposure->minimum,
673*4882a593Smuzhiyun 					 exposure_max, ov5675->exposure->step,
674*4882a593Smuzhiyun 					 exposure_max);
675*4882a593Smuzhiyun 	}
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun 	/* V4L2 controls values will be applied only when power is already up */
678*4882a593Smuzhiyun 	if (!pm_runtime_get_if_in_use(&client->dev))
679*4882a593Smuzhiyun 		return 0;
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun 	switch (ctrl->id) {
682*4882a593Smuzhiyun 	case V4L2_CID_ANALOGUE_GAIN:
683*4882a593Smuzhiyun 		ret = ov5675_write_reg(ov5675, OV5675_REG_ANALOG_GAIN,
684*4882a593Smuzhiyun 				       OV5675_REG_VALUE_16BIT, ctrl->val);
685*4882a593Smuzhiyun 		break;
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 	case V4L2_CID_DIGITAL_GAIN:
688*4882a593Smuzhiyun 		ret = ov5675_update_digital_gain(ov5675, ctrl->val);
689*4882a593Smuzhiyun 		break;
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE:
692*4882a593Smuzhiyun 		/* 4 least significant bits of expsoure are fractional part
693*4882a593Smuzhiyun 		 * val = val << 4
694*4882a593Smuzhiyun 		 * for ov5675, the unit of exposure is differnt from other
695*4882a593Smuzhiyun 		 * OmniVision sensors, its exposure value is twice of the
696*4882a593Smuzhiyun 		 * register value, the exposure should be divided by 2 before
697*4882a593Smuzhiyun 		 * set register, e.g. val << 3.
698*4882a593Smuzhiyun 		 */
699*4882a593Smuzhiyun 		ret = ov5675_write_reg(ov5675, OV5675_REG_EXPOSURE,
700*4882a593Smuzhiyun 				       OV5675_REG_VALUE_24BIT, ctrl->val << 3);
701*4882a593Smuzhiyun 		break;
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	case V4L2_CID_VBLANK:
704*4882a593Smuzhiyun 		ret = ov5675_write_reg(ov5675, OV5675_REG_VTS,
705*4882a593Smuzhiyun 				       OV5675_REG_VALUE_16BIT,
706*4882a593Smuzhiyun 				       ov5675->cur_mode->height + ctrl->val +
707*4882a593Smuzhiyun 				       10);
708*4882a593Smuzhiyun 		break;
709*4882a593Smuzhiyun 
710*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
711*4882a593Smuzhiyun 		ret = ov5675_test_pattern(ov5675, ctrl->val);
712*4882a593Smuzhiyun 		break;
713*4882a593Smuzhiyun 
714*4882a593Smuzhiyun 	case V4L2_CID_HFLIP:
715*4882a593Smuzhiyun 		ov5675_set_ctrl_hflip(ov5675, ctrl->val);
716*4882a593Smuzhiyun 		break;
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
719*4882a593Smuzhiyun 		ov5675_set_ctrl_vflip(ov5675, ctrl->val);
720*4882a593Smuzhiyun 		break;
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun 	default:
723*4882a593Smuzhiyun 		ret = -EINVAL;
724*4882a593Smuzhiyun 		break;
725*4882a593Smuzhiyun 	}
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	pm_runtime_put(&client->dev);
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun 	return ret;
730*4882a593Smuzhiyun }
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun static const struct v4l2_ctrl_ops ov5675_ctrl_ops = {
733*4882a593Smuzhiyun 	.s_ctrl = ov5675_set_ctrl,
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun 
ov5675_init_controls(struct ov5675 * ov5675)736*4882a593Smuzhiyun static int ov5675_init_controls(struct ov5675 *ov5675)
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *ctrl_hdlr;
739*4882a593Smuzhiyun 	s64 exposure_max, h_blank;
740*4882a593Smuzhiyun 	int ret;
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 	ctrl_hdlr = &ov5675->ctrl_handler;
743*4882a593Smuzhiyun 	ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
744*4882a593Smuzhiyun 	if (ret)
745*4882a593Smuzhiyun 		return ret;
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	ctrl_hdlr->lock = &ov5675->mutex;
748*4882a593Smuzhiyun 	ov5675->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov5675_ctrl_ops,
749*4882a593Smuzhiyun 					   V4L2_CID_LINK_FREQ,
750*4882a593Smuzhiyun 					   ARRAY_SIZE(link_freq_menu_items) - 1,
751*4882a593Smuzhiyun 					   0, link_freq_menu_items);
752*4882a593Smuzhiyun 	if (ov5675->link_freq)
753*4882a593Smuzhiyun 		ov5675->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	ov5675->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
756*4882a593Smuzhiyun 				       V4L2_CID_PIXEL_RATE, 0,
757*4882a593Smuzhiyun 				       to_pixel_rate(OV5675_LINK_FREQ_900MBPS),
758*4882a593Smuzhiyun 				       1,
759*4882a593Smuzhiyun 				       to_pixel_rate(OV5675_LINK_FREQ_900MBPS));
760*4882a593Smuzhiyun 	ov5675->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
761*4882a593Smuzhiyun 			  V4L2_CID_VBLANK,
762*4882a593Smuzhiyun 			  ov5675->cur_mode->vts_min - ov5675->cur_mode->height,
763*4882a593Smuzhiyun 			  OV5675_VTS_MAX - ov5675->cur_mode->height, 1,
764*4882a593Smuzhiyun 			  ov5675->cur_mode->vts_def - ov5675->cur_mode->height);
765*4882a593Smuzhiyun 	h_blank = to_pixels_per_line(ov5675->cur_mode->hts,
766*4882a593Smuzhiyun 		  ov5675->cur_mode->link_freq_index) - ov5675->cur_mode->width;
767*4882a593Smuzhiyun 	ov5675->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
768*4882a593Smuzhiyun 					   V4L2_CID_HBLANK, h_blank, h_blank, 1,
769*4882a593Smuzhiyun 					   h_blank);
770*4882a593Smuzhiyun 	if (ov5675->hblank)
771*4882a593Smuzhiyun 		ov5675->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
774*4882a593Smuzhiyun 			  OV5675_ANAL_GAIN_MIN, OV5675_ANAL_GAIN_MAX,
775*4882a593Smuzhiyun 			  OV5675_ANAL_GAIN_STEP, OV5675_ANAL_GAIN_MIN);
776*4882a593Smuzhiyun 	v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
777*4882a593Smuzhiyun 			  OV5675_DGTL_GAIN_MIN, OV5675_DGTL_GAIN_MAX,
778*4882a593Smuzhiyun 			  OV5675_DGTL_GAIN_STEP, OV5675_DGTL_GAIN_DEFAULT);
779*4882a593Smuzhiyun 	exposure_max = (ov5675->cur_mode->vts_def - OV5675_EXPOSURE_MAX_MARGIN);
780*4882a593Smuzhiyun 	ov5675->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
781*4882a593Smuzhiyun 					     V4L2_CID_EXPOSURE,
782*4882a593Smuzhiyun 					     OV5675_EXPOSURE_MIN, exposure_max,
783*4882a593Smuzhiyun 					     OV5675_EXPOSURE_STEP,
784*4882a593Smuzhiyun 					     exposure_max);
785*4882a593Smuzhiyun 	v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov5675_ctrl_ops,
786*4882a593Smuzhiyun 				     V4L2_CID_TEST_PATTERN,
787*4882a593Smuzhiyun 				     ARRAY_SIZE(ov5675_test_pattern_menu) - 1,
788*4882a593Smuzhiyun 				     0, 0, ov5675_test_pattern_menu);
789*4882a593Smuzhiyun 	v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
790*4882a593Smuzhiyun 			  V4L2_CID_HFLIP, 0, 1, 1, 0);
791*4882a593Smuzhiyun 	v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
792*4882a593Smuzhiyun 			  V4L2_CID_VFLIP, 0, 1, 1, 0);
793*4882a593Smuzhiyun 
794*4882a593Smuzhiyun 	if (ctrl_hdlr->error)
795*4882a593Smuzhiyun 		return ctrl_hdlr->error;
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun 	ov5675->sd.ctrl_handler = ctrl_hdlr;
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	return 0;
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun 
ov5675_update_pad_format(const struct ov5675_mode * mode,struct v4l2_mbus_framefmt * fmt)802*4882a593Smuzhiyun static void ov5675_update_pad_format(const struct ov5675_mode *mode,
803*4882a593Smuzhiyun 				     struct v4l2_mbus_framefmt *fmt)
804*4882a593Smuzhiyun {
805*4882a593Smuzhiyun 	fmt->width = mode->width;
806*4882a593Smuzhiyun 	fmt->height = mode->height;
807*4882a593Smuzhiyun 	fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
808*4882a593Smuzhiyun 	fmt->field = V4L2_FIELD_NONE;
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun 
ov5675_start_streaming(struct ov5675 * ov5675)811*4882a593Smuzhiyun static int ov5675_start_streaming(struct ov5675 *ov5675)
812*4882a593Smuzhiyun {
813*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
814*4882a593Smuzhiyun 	const struct ov5675_reg_list *reg_list;
815*4882a593Smuzhiyun 	int link_freq_index, ret;
816*4882a593Smuzhiyun 
817*4882a593Smuzhiyun 	link_freq_index = ov5675->cur_mode->link_freq_index;
818*4882a593Smuzhiyun 	reg_list = &link_freq_configs[link_freq_index].reg_list;
819*4882a593Smuzhiyun 	ret = ov5675_write_reg_list(ov5675, reg_list);
820*4882a593Smuzhiyun 	if (ret) {
821*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to set plls");
822*4882a593Smuzhiyun 		return ret;
823*4882a593Smuzhiyun 	}
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	reg_list = &ov5675->cur_mode->reg_list;
826*4882a593Smuzhiyun 	ret = ov5675_write_reg_list(ov5675, reg_list);
827*4882a593Smuzhiyun 	if (ret) {
828*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to set mode");
829*4882a593Smuzhiyun 		return ret;
830*4882a593Smuzhiyun 	}
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun 	ret = __v4l2_ctrl_handler_setup(ov5675->sd.ctrl_handler);
833*4882a593Smuzhiyun 	if (ret)
834*4882a593Smuzhiyun 		return ret;
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	ret = ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT,
837*4882a593Smuzhiyun 			       OV5675_REG_VALUE_08BIT, OV5675_MODE_STREAMING);
838*4882a593Smuzhiyun 	if (ret) {
839*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to set stream");
840*4882a593Smuzhiyun 		return ret;
841*4882a593Smuzhiyun 	}
842*4882a593Smuzhiyun 
843*4882a593Smuzhiyun 	return 0;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun 
ov5675_stop_streaming(struct ov5675 * ov5675)846*4882a593Smuzhiyun static void ov5675_stop_streaming(struct ov5675 *ov5675)
847*4882a593Smuzhiyun {
848*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
849*4882a593Smuzhiyun 
850*4882a593Smuzhiyun 	if (ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT,
851*4882a593Smuzhiyun 			     OV5675_REG_VALUE_08BIT, OV5675_MODE_STANDBY))
852*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to set stream");
853*4882a593Smuzhiyun }
854*4882a593Smuzhiyun 
ov5675_set_stream(struct v4l2_subdev * sd,int enable)855*4882a593Smuzhiyun static int ov5675_set_stream(struct v4l2_subdev *sd, int enable)
856*4882a593Smuzhiyun {
857*4882a593Smuzhiyun 	struct ov5675 *ov5675 = to_ov5675(sd);
858*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
859*4882a593Smuzhiyun 	int ret = 0;
860*4882a593Smuzhiyun 
861*4882a593Smuzhiyun 	if (ov5675->streaming == enable)
862*4882a593Smuzhiyun 		return 0;
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	mutex_lock(&ov5675->mutex);
865*4882a593Smuzhiyun 	if (enable) {
866*4882a593Smuzhiyun 		ret = pm_runtime_get_sync(&client->dev);
867*4882a593Smuzhiyun 		if (ret < 0) {
868*4882a593Smuzhiyun 			pm_runtime_put_noidle(&client->dev);
869*4882a593Smuzhiyun 			mutex_unlock(&ov5675->mutex);
870*4882a593Smuzhiyun 			return ret;
871*4882a593Smuzhiyun 		}
872*4882a593Smuzhiyun 
873*4882a593Smuzhiyun 		ret = ov5675_start_streaming(ov5675);
874*4882a593Smuzhiyun 		if (ret) {
875*4882a593Smuzhiyun 			enable = 0;
876*4882a593Smuzhiyun 			ov5675_stop_streaming(ov5675);
877*4882a593Smuzhiyun 			pm_runtime_put(&client->dev);
878*4882a593Smuzhiyun 		}
879*4882a593Smuzhiyun 	} else {
880*4882a593Smuzhiyun 		ov5675_stop_streaming(ov5675);
881*4882a593Smuzhiyun 		pm_runtime_put(&client->dev);
882*4882a593Smuzhiyun 	}
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun 	ov5675->streaming = enable;
885*4882a593Smuzhiyun 	mutex_unlock(&ov5675->mutex);
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	return ret;
888*4882a593Smuzhiyun }
889*4882a593Smuzhiyun 
ov5675_suspend(struct device * dev)890*4882a593Smuzhiyun static int __maybe_unused ov5675_suspend(struct device *dev)
891*4882a593Smuzhiyun {
892*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
893*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
894*4882a593Smuzhiyun 	struct ov5675 *ov5675 = to_ov5675(sd);
895*4882a593Smuzhiyun 
896*4882a593Smuzhiyun 	mutex_lock(&ov5675->mutex);
897*4882a593Smuzhiyun 	if (ov5675->streaming)
898*4882a593Smuzhiyun 		ov5675_stop_streaming(ov5675);
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 	mutex_unlock(&ov5675->mutex);
901*4882a593Smuzhiyun 
902*4882a593Smuzhiyun 	return 0;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun 
ov5675_resume(struct device * dev)905*4882a593Smuzhiyun static int __maybe_unused ov5675_resume(struct device *dev)
906*4882a593Smuzhiyun {
907*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(dev);
908*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
909*4882a593Smuzhiyun 	struct ov5675 *ov5675 = to_ov5675(sd);
910*4882a593Smuzhiyun 	int ret;
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun 	mutex_lock(&ov5675->mutex);
913*4882a593Smuzhiyun 	if (ov5675->streaming) {
914*4882a593Smuzhiyun 		ret = ov5675_start_streaming(ov5675);
915*4882a593Smuzhiyun 		if (ret) {
916*4882a593Smuzhiyun 			ov5675->streaming = false;
917*4882a593Smuzhiyun 			ov5675_stop_streaming(ov5675);
918*4882a593Smuzhiyun 			mutex_unlock(&ov5675->mutex);
919*4882a593Smuzhiyun 			return ret;
920*4882a593Smuzhiyun 		}
921*4882a593Smuzhiyun 	}
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun 	mutex_unlock(&ov5675->mutex);
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	return 0;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun 
ov5675_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)928*4882a593Smuzhiyun static int ov5675_set_format(struct v4l2_subdev *sd,
929*4882a593Smuzhiyun 			     struct v4l2_subdev_pad_config *cfg,
930*4882a593Smuzhiyun 			     struct v4l2_subdev_format *fmt)
931*4882a593Smuzhiyun {
932*4882a593Smuzhiyun 	struct ov5675 *ov5675 = to_ov5675(sd);
933*4882a593Smuzhiyun 	const struct ov5675_mode *mode;
934*4882a593Smuzhiyun 	s32 vblank_def, h_blank;
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	mode = v4l2_find_nearest_size(supported_modes,
937*4882a593Smuzhiyun 				      ARRAY_SIZE(supported_modes), width,
938*4882a593Smuzhiyun 				      height, fmt->format.width,
939*4882a593Smuzhiyun 				      fmt->format.height);
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	mutex_lock(&ov5675->mutex);
942*4882a593Smuzhiyun 	ov5675_update_pad_format(mode, &fmt->format);
943*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
944*4882a593Smuzhiyun 		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
945*4882a593Smuzhiyun 	} else {
946*4882a593Smuzhiyun 		ov5675->cur_mode = mode;
947*4882a593Smuzhiyun 		__v4l2_ctrl_s_ctrl(ov5675->link_freq, mode->link_freq_index);
948*4882a593Smuzhiyun 		__v4l2_ctrl_s_ctrl_int64(ov5675->pixel_rate,
949*4882a593Smuzhiyun 					 to_pixel_rate(mode->link_freq_index));
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun 		/* Update limits and set FPS to default */
952*4882a593Smuzhiyun 		vblank_def = mode->vts_def - mode->height;
953*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(ov5675->vblank,
954*4882a593Smuzhiyun 					 mode->vts_min - mode->height,
955*4882a593Smuzhiyun 					 OV5675_VTS_MAX - mode->height, 1,
956*4882a593Smuzhiyun 					 vblank_def);
957*4882a593Smuzhiyun 		__v4l2_ctrl_s_ctrl(ov5675->vblank, vblank_def);
958*4882a593Smuzhiyun 		h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
959*4882a593Smuzhiyun 			  mode->width;
960*4882a593Smuzhiyun 		__v4l2_ctrl_modify_range(ov5675->hblank, h_blank, h_blank, 1,
961*4882a593Smuzhiyun 					 h_blank);
962*4882a593Smuzhiyun 	}
963*4882a593Smuzhiyun 
964*4882a593Smuzhiyun 	mutex_unlock(&ov5675->mutex);
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 	return 0;
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun 
ov5675_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)969*4882a593Smuzhiyun static int ov5675_get_format(struct v4l2_subdev *sd,
970*4882a593Smuzhiyun 			     struct v4l2_subdev_pad_config *cfg,
971*4882a593Smuzhiyun 			     struct v4l2_subdev_format *fmt)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun 	struct ov5675 *ov5675 = to_ov5675(sd);
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	mutex_lock(&ov5675->mutex);
976*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
977*4882a593Smuzhiyun 		fmt->format = *v4l2_subdev_get_try_format(&ov5675->sd, cfg,
978*4882a593Smuzhiyun 							  fmt->pad);
979*4882a593Smuzhiyun 	else
980*4882a593Smuzhiyun 		ov5675_update_pad_format(ov5675->cur_mode, &fmt->format);
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun 	mutex_unlock(&ov5675->mutex);
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 	return 0;
985*4882a593Smuzhiyun }
986*4882a593Smuzhiyun 
ov5675_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)987*4882a593Smuzhiyun static int ov5675_enum_mbus_code(struct v4l2_subdev *sd,
988*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
989*4882a593Smuzhiyun 				 struct v4l2_subdev_mbus_code_enum *code)
990*4882a593Smuzhiyun {
991*4882a593Smuzhiyun 	if (code->index > 0)
992*4882a593Smuzhiyun 		return -EINVAL;
993*4882a593Smuzhiyun 
994*4882a593Smuzhiyun 	code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
995*4882a593Smuzhiyun 
996*4882a593Smuzhiyun 	return 0;
997*4882a593Smuzhiyun }
998*4882a593Smuzhiyun 
ov5675_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)999*4882a593Smuzhiyun static int ov5675_enum_frame_size(struct v4l2_subdev *sd,
1000*4882a593Smuzhiyun 				  struct v4l2_subdev_pad_config *cfg,
1001*4882a593Smuzhiyun 				  struct v4l2_subdev_frame_size_enum *fse)
1002*4882a593Smuzhiyun {
1003*4882a593Smuzhiyun 	if (fse->index >= ARRAY_SIZE(supported_modes))
1004*4882a593Smuzhiyun 		return -EINVAL;
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1007*4882a593Smuzhiyun 		return -EINVAL;
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun 	fse->min_width = supported_modes[fse->index].width;
1010*4882a593Smuzhiyun 	fse->max_width = fse->min_width;
1011*4882a593Smuzhiyun 	fse->min_height = supported_modes[fse->index].height;
1012*4882a593Smuzhiyun 	fse->max_height = fse->min_height;
1013*4882a593Smuzhiyun 
1014*4882a593Smuzhiyun 	return 0;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun 
ov5675_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1017*4882a593Smuzhiyun static int ov5675_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1018*4882a593Smuzhiyun {
1019*4882a593Smuzhiyun 	struct ov5675 *ov5675 = to_ov5675(sd);
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun 	mutex_lock(&ov5675->mutex);
1022*4882a593Smuzhiyun 	ov5675_update_pad_format(&supported_modes[0],
1023*4882a593Smuzhiyun 				 v4l2_subdev_get_try_format(sd, fh->pad, 0));
1024*4882a593Smuzhiyun 	mutex_unlock(&ov5675->mutex);
1025*4882a593Smuzhiyun 
1026*4882a593Smuzhiyun 	return 0;
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun 
1029*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops ov5675_video_ops = {
1030*4882a593Smuzhiyun 	.s_stream = ov5675_set_stream,
1031*4882a593Smuzhiyun };
1032*4882a593Smuzhiyun 
1033*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops ov5675_pad_ops = {
1034*4882a593Smuzhiyun 	.set_fmt = ov5675_set_format,
1035*4882a593Smuzhiyun 	.get_fmt = ov5675_get_format,
1036*4882a593Smuzhiyun 	.enum_mbus_code = ov5675_enum_mbus_code,
1037*4882a593Smuzhiyun 	.enum_frame_size = ov5675_enum_frame_size,
1038*4882a593Smuzhiyun };
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun static const struct v4l2_subdev_ops ov5675_subdev_ops = {
1041*4882a593Smuzhiyun 	.video = &ov5675_video_ops,
1042*4882a593Smuzhiyun 	.pad = &ov5675_pad_ops,
1043*4882a593Smuzhiyun };
1044*4882a593Smuzhiyun 
1045*4882a593Smuzhiyun static const struct media_entity_operations ov5675_subdev_entity_ops = {
1046*4882a593Smuzhiyun 	.link_validate = v4l2_subdev_link_validate,
1047*4882a593Smuzhiyun };
1048*4882a593Smuzhiyun 
1049*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops ov5675_internal_ops = {
1050*4882a593Smuzhiyun 	.open = ov5675_open,
1051*4882a593Smuzhiyun };
1052*4882a593Smuzhiyun 
ov5675_identify_module(struct ov5675 * ov5675)1053*4882a593Smuzhiyun static int ov5675_identify_module(struct ov5675 *ov5675)
1054*4882a593Smuzhiyun {
1055*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
1056*4882a593Smuzhiyun 	int ret;
1057*4882a593Smuzhiyun 	u32 val;
1058*4882a593Smuzhiyun 
1059*4882a593Smuzhiyun 	ret = ov5675_read_reg(ov5675, OV5675_REG_CHIP_ID,
1060*4882a593Smuzhiyun 			      OV5675_REG_VALUE_24BIT, &val);
1061*4882a593Smuzhiyun 	if (ret)
1062*4882a593Smuzhiyun 		return ret;
1063*4882a593Smuzhiyun 
1064*4882a593Smuzhiyun 	if (val != OV5675_CHIP_ID) {
1065*4882a593Smuzhiyun 		dev_err(&client->dev, "chip id mismatch: %x!=%x",
1066*4882a593Smuzhiyun 			OV5675_CHIP_ID, val);
1067*4882a593Smuzhiyun 		return -ENXIO;
1068*4882a593Smuzhiyun 	}
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	return 0;
1071*4882a593Smuzhiyun }
1072*4882a593Smuzhiyun 
ov5675_check_hwcfg(struct device * dev)1073*4882a593Smuzhiyun static int ov5675_check_hwcfg(struct device *dev)
1074*4882a593Smuzhiyun {
1075*4882a593Smuzhiyun 	struct fwnode_handle *ep;
1076*4882a593Smuzhiyun 	struct fwnode_handle *fwnode = dev_fwnode(dev);
1077*4882a593Smuzhiyun 	struct v4l2_fwnode_endpoint bus_cfg = {
1078*4882a593Smuzhiyun 		.bus_type = V4L2_MBUS_CSI2_DPHY
1079*4882a593Smuzhiyun 	};
1080*4882a593Smuzhiyun 	u32 mclk;
1081*4882a593Smuzhiyun 	int ret;
1082*4882a593Smuzhiyun 	unsigned int i, j;
1083*4882a593Smuzhiyun 
1084*4882a593Smuzhiyun 	if (!fwnode)
1085*4882a593Smuzhiyun 		return -ENXIO;
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
1088*4882a593Smuzhiyun 
1089*4882a593Smuzhiyun 	if (ret) {
1090*4882a593Smuzhiyun 		dev_err(dev, "can't get clock frequency");
1091*4882a593Smuzhiyun 		return ret;
1092*4882a593Smuzhiyun 	}
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun 	if (mclk != OV5675_MCLK) {
1095*4882a593Smuzhiyun 		dev_err(dev, "external clock %d is not supported", mclk);
1096*4882a593Smuzhiyun 		return -EINVAL;
1097*4882a593Smuzhiyun 	}
1098*4882a593Smuzhiyun 
1099*4882a593Smuzhiyun 	ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1100*4882a593Smuzhiyun 	if (!ep)
1101*4882a593Smuzhiyun 		return -ENXIO;
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun 	ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1104*4882a593Smuzhiyun 	fwnode_handle_put(ep);
1105*4882a593Smuzhiyun 	if (ret)
1106*4882a593Smuzhiyun 		return ret;
1107*4882a593Smuzhiyun 
1108*4882a593Smuzhiyun 	if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV5675_DATA_LANES) {
1109*4882a593Smuzhiyun 		dev_err(dev, "number of CSI2 data lanes %d is not supported",
1110*4882a593Smuzhiyun 			bus_cfg.bus.mipi_csi2.num_data_lanes);
1111*4882a593Smuzhiyun 		ret = -EINVAL;
1112*4882a593Smuzhiyun 		goto check_hwcfg_error;
1113*4882a593Smuzhiyun 	}
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	if (!bus_cfg.nr_of_link_frequencies) {
1116*4882a593Smuzhiyun 		dev_err(dev, "no link frequencies defined");
1117*4882a593Smuzhiyun 		ret = -EINVAL;
1118*4882a593Smuzhiyun 		goto check_hwcfg_error;
1119*4882a593Smuzhiyun 	}
1120*4882a593Smuzhiyun 
1121*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1122*4882a593Smuzhiyun 		for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1123*4882a593Smuzhiyun 			if (link_freq_menu_items[i] ==
1124*4882a593Smuzhiyun 				bus_cfg.link_frequencies[j])
1125*4882a593Smuzhiyun 				break;
1126*4882a593Smuzhiyun 		}
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun 		if (j == bus_cfg.nr_of_link_frequencies) {
1129*4882a593Smuzhiyun 			dev_err(dev, "no link frequency %lld supported",
1130*4882a593Smuzhiyun 				link_freq_menu_items[i]);
1131*4882a593Smuzhiyun 			ret = -EINVAL;
1132*4882a593Smuzhiyun 			goto check_hwcfg_error;
1133*4882a593Smuzhiyun 		}
1134*4882a593Smuzhiyun 	}
1135*4882a593Smuzhiyun 
1136*4882a593Smuzhiyun check_hwcfg_error:
1137*4882a593Smuzhiyun 	v4l2_fwnode_endpoint_free(&bus_cfg);
1138*4882a593Smuzhiyun 
1139*4882a593Smuzhiyun 	return ret;
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun 
ov5675_remove(struct i2c_client * client)1142*4882a593Smuzhiyun static int ov5675_remove(struct i2c_client *client)
1143*4882a593Smuzhiyun {
1144*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
1145*4882a593Smuzhiyun 	struct ov5675 *ov5675 = to_ov5675(sd);
1146*4882a593Smuzhiyun 
1147*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(sd);
1148*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
1149*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(sd->ctrl_handler);
1150*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
1151*4882a593Smuzhiyun 	mutex_destroy(&ov5675->mutex);
1152*4882a593Smuzhiyun 
1153*4882a593Smuzhiyun 	return 0;
1154*4882a593Smuzhiyun }
1155*4882a593Smuzhiyun 
ov5675_probe(struct i2c_client * client)1156*4882a593Smuzhiyun static int ov5675_probe(struct i2c_client *client)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun 	struct ov5675 *ov5675;
1159*4882a593Smuzhiyun 	int ret;
1160*4882a593Smuzhiyun 
1161*4882a593Smuzhiyun 	ret = ov5675_check_hwcfg(&client->dev);
1162*4882a593Smuzhiyun 	if (ret) {
1163*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to check HW configuration: %d",
1164*4882a593Smuzhiyun 			ret);
1165*4882a593Smuzhiyun 		return ret;
1166*4882a593Smuzhiyun 	}
1167*4882a593Smuzhiyun 
1168*4882a593Smuzhiyun 	ov5675 = devm_kzalloc(&client->dev, sizeof(*ov5675), GFP_KERNEL);
1169*4882a593Smuzhiyun 	if (!ov5675)
1170*4882a593Smuzhiyun 		return -ENOMEM;
1171*4882a593Smuzhiyun 
1172*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(&ov5675->sd, client, &ov5675_subdev_ops);
1173*4882a593Smuzhiyun 	ret = ov5675_identify_module(ov5675);
1174*4882a593Smuzhiyun 	if (ret) {
1175*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to find sensor: %d", ret);
1176*4882a593Smuzhiyun 		return ret;
1177*4882a593Smuzhiyun 	}
1178*4882a593Smuzhiyun 
1179*4882a593Smuzhiyun 	mutex_init(&ov5675->mutex);
1180*4882a593Smuzhiyun 	ov5675->cur_mode = &supported_modes[0];
1181*4882a593Smuzhiyun 	ret = ov5675_init_controls(ov5675);
1182*4882a593Smuzhiyun 	if (ret) {
1183*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to init controls: %d", ret);
1184*4882a593Smuzhiyun 		goto probe_error_v4l2_ctrl_handler_free;
1185*4882a593Smuzhiyun 	}
1186*4882a593Smuzhiyun 
1187*4882a593Smuzhiyun 	ov5675->sd.internal_ops = &ov5675_internal_ops;
1188*4882a593Smuzhiyun 	ov5675->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1189*4882a593Smuzhiyun 	ov5675->sd.entity.ops = &ov5675_subdev_entity_ops;
1190*4882a593Smuzhiyun 	ov5675->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1191*4882a593Smuzhiyun 	ov5675->pad.flags = MEDIA_PAD_FL_SOURCE;
1192*4882a593Smuzhiyun 	ret = media_entity_pads_init(&ov5675->sd.entity, 1, &ov5675->pad);
1193*4882a593Smuzhiyun 	if (ret) {
1194*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to init entity pads: %d", ret);
1195*4882a593Smuzhiyun 		goto probe_error_v4l2_ctrl_handler_free;
1196*4882a593Smuzhiyun 	}
1197*4882a593Smuzhiyun 
1198*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev_sensor_common(&ov5675->sd);
1199*4882a593Smuzhiyun 	if (ret < 0) {
1200*4882a593Smuzhiyun 		dev_err(&client->dev, "failed to register V4L2 subdev: %d",
1201*4882a593Smuzhiyun 			ret);
1202*4882a593Smuzhiyun 		goto probe_error_media_entity_cleanup;
1203*4882a593Smuzhiyun 	}
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun 	/*
1206*4882a593Smuzhiyun 	 * Device is already turned on by i2c-core with ACPI domain PM.
1207*4882a593Smuzhiyun 	 * Enable runtime PM and turn off the device.
1208*4882a593Smuzhiyun 	 */
1209*4882a593Smuzhiyun 	pm_runtime_set_active(&client->dev);
1210*4882a593Smuzhiyun 	pm_runtime_enable(&client->dev);
1211*4882a593Smuzhiyun 	pm_runtime_idle(&client->dev);
1212*4882a593Smuzhiyun 
1213*4882a593Smuzhiyun 	return 0;
1214*4882a593Smuzhiyun 
1215*4882a593Smuzhiyun probe_error_media_entity_cleanup:
1216*4882a593Smuzhiyun 	media_entity_cleanup(&ov5675->sd.entity);
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun probe_error_v4l2_ctrl_handler_free:
1219*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(ov5675->sd.ctrl_handler);
1220*4882a593Smuzhiyun 	mutex_destroy(&ov5675->mutex);
1221*4882a593Smuzhiyun 
1222*4882a593Smuzhiyun 	return ret;
1223*4882a593Smuzhiyun }
1224*4882a593Smuzhiyun 
1225*4882a593Smuzhiyun static const struct dev_pm_ops ov5675_pm_ops = {
1226*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(ov5675_suspend, ov5675_resume)
1227*4882a593Smuzhiyun };
1228*4882a593Smuzhiyun 
1229*4882a593Smuzhiyun #ifdef CONFIG_ACPI
1230*4882a593Smuzhiyun static const struct acpi_device_id ov5675_acpi_ids[] = {
1231*4882a593Smuzhiyun 	{"OVTI5675"},
1232*4882a593Smuzhiyun 	{}
1233*4882a593Smuzhiyun };
1234*4882a593Smuzhiyun 
1235*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, ov5675_acpi_ids);
1236*4882a593Smuzhiyun #endif
1237*4882a593Smuzhiyun 
1238*4882a593Smuzhiyun static struct i2c_driver ov5675_i2c_driver = {
1239*4882a593Smuzhiyun 	.driver = {
1240*4882a593Smuzhiyun 		.name = "ov5675",
1241*4882a593Smuzhiyun 		.pm = &ov5675_pm_ops,
1242*4882a593Smuzhiyun 		.acpi_match_table = ACPI_PTR(ov5675_acpi_ids),
1243*4882a593Smuzhiyun 	},
1244*4882a593Smuzhiyun 	.probe_new = ov5675_probe,
1245*4882a593Smuzhiyun 	.remove = ov5675_remove,
1246*4882a593Smuzhiyun };
1247*4882a593Smuzhiyun 
1248*4882a593Smuzhiyun module_i2c_driver(ov5675_i2c_driver);
1249*4882a593Smuzhiyun 
1250*4882a593Smuzhiyun MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1251*4882a593Smuzhiyun MODULE_DESCRIPTION("OmniVision OV5675 sensor driver");
1252*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1253