1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Driver for the OV5645 camera sensor.
4 *
5 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
6 * Copyright (C) 2015 By Tech Design S.L. All Rights Reserved.
7 * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
8 *
9 * Based on:
10 * - the OV5645 driver from QC msm-3.10 kernel on codeaurora.org:
11 * https://us.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/
12 * media/platform/msm/camera_v2/sensor/ov5645.c?h=LA.BR.1.2.4_rb1.41
13 * - the OV5640 driver posted on linux-media:
14 * https://www.mail-archive.com/linux-media%40vger.kernel.org/msg92671.html
15 */
16
17 /*
18 */
19
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/gpio/consumer.h>
25 #include <linux/i2c.h>
26 #include <linux/init.h>
27 #include <linux/module.h>
28 #include <linux/of.h>
29 #include <linux/of_graph.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
33 #include <media/v4l2-ctrls.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-subdev.h>
36 #include <linux/rk-camera-module.h>
37
38
39 #define OV5645_SYSTEM_CTRL0 0x3008
40 #define OV5645_SYSTEM_CTRL0_START 0x02
41 #define OV5645_SYSTEM_CTRL0_STOP 0x42
42 #define OV5645_CHIP_ID_HIGH 0x300a
43 #define OV5645_CHIP_ID_HIGH_BYTE 0x56
44 #define OV5645_CHIP_ID_LOW 0x300b
45 #define OV5645_CHIP_ID_LOW_BYTE 0x45
46 #define OV5645_IO_MIPI_CTRL00 0x300e
47 #define OV5645_PAD_OUTPUT00 0x3019
48 #define OV5645_AWB_MANUAL_CONTROL 0x3406
49 #define OV5645_AWB_MANUAL_ENABLE BIT(0)
50 #define OV5645_AEC_PK_MANUAL 0x3503
51 #define OV5645_AEC_MANUAL_ENABLE BIT(0)
52 #define OV5645_AGC_MANUAL_ENABLE BIT(1)
53 #define OV5645_TIMING_TC_REG20 0x3820
54 #define OV5645_SENSOR_VFLIP BIT(1)
55 #define OV5645_ISP_VFLIP BIT(2)
56 #define OV5645_TIMING_TC_REG21 0x3821
57 #define OV5645_SENSOR_MIRROR BIT(1)
58 #define OV5645_MIPI_CTRL00 0x4800
59 #define OV5645_PRE_ISP_TEST_SETTING_1 0x503d
60 #define OV5645_TEST_PATTERN_MASK 0x3
61 #define OV5645_SET_TEST_PATTERN(x) ((x) & OV5645_TEST_PATTERN_MASK)
62 #define OV5645_TEST_PATTERN_ENABLE BIT(7)
63 #define OV5645_SDE_SAT_U 0x5583
64 #define OV5645_SDE_SAT_V 0x5584
65
66 /* regulator supplies */
67 static const char * const ov5645_supply_name[] = {
68 "vdddo", /* Digital I/O (1.8V) supply */
69 "vdda", /* Analog (2.8V) supply */
70 "vddd", /* Digital Core (1.5V) supply */
71 };
72
73 #define OV5645_NUM_SUPPLIES ARRAY_SIZE(ov5645_supply_name)
74
75 struct reg_value {
76 u16 reg;
77 u8 val;
78 };
79
80 struct ov5645_mode_info {
81 u32 width;
82 u32 height;
83 const struct reg_value *data;
84 struct v4l2_fract max_fps;
85 u32 data_size;
86 u32 pixel_clock;
87 u32 link_freq;
88 };
89
90 struct ov5645 {
91 struct i2c_client *i2c_client;
92 struct device *dev;
93 struct v4l2_subdev sd;
94 struct media_pad pad;
95 struct v4l2_fwnode_endpoint ep;
96 struct v4l2_mbus_framefmt fmt;
97 struct v4l2_rect crop;
98 struct clk *xclk;
99
100 struct regulator_bulk_data supplies[OV5645_NUM_SUPPLIES];
101
102 const struct ov5645_mode_info *current_mode;
103
104 struct v4l2_ctrl_handler ctrls;
105 struct v4l2_ctrl *pixel_clock;
106 struct v4l2_ctrl *link_freq;
107
108 /* Cached register values */
109 u8 aec_pk_manual;
110 u8 timing_tc_reg20;
111 u8 timing_tc_reg21;
112
113 struct mutex power_lock; /* lock to protect power state */
114 int power_count;
115
116 struct gpio_desc *enable_gpio;
117 struct gpio_desc *rst_gpio;
118
119 u32 module_index;
120 const char *module_facing;
121 const char *module_name;
122 const char *len_name;
123 u32 lane_data_num;
124 };
125
to_ov5645(struct v4l2_subdev * sd)126 static inline struct ov5645 *to_ov5645(struct v4l2_subdev *sd)
127 {
128 return container_of(sd, struct ov5645, sd);
129 }
130
131 static const struct reg_value ov5645_check_aec[] = {
132 { 0x3500, 0x00 },
133 { 0x3501, 0x45 },
134 { 0x3502, 0xc0 },
135 { 0x350a, 0x00 },
136 { 0x350b, 0x36 }
137 };
138
139 static const struct reg_value ov5645_global_init_setting[] = {
140 { 0x3103, 0x11 },
141 { 0x3008, 0x82 },
142 { 0x3008, 0x42 },
143 { 0x3103, 0x03 },
144 { 0x3503, 0x07 },
145 { 0x3002, 0x1c },
146 { 0x3006, 0xc3 },
147 { 0x3017, 0x00 },
148 { 0x3018, 0x00 },
149 { 0x302e, 0x0b },
150 { 0x3037, 0x13 },
151 { 0x3108, 0x01 },
152 { 0x3611, 0x06 },
153 { 0x3500, 0x00 },
154 { 0x3501, 0x01 },
155 { 0x3502, 0x00 },
156 { 0x350a, 0x00 },
157 { 0x350b, 0x3f },
158 { 0x3620, 0x33 },
159 { 0x3621, 0xe0 },
160 { 0x3622, 0x01 },
161 { 0x3630, 0x2e },
162 { 0x3631, 0x00 },
163 { 0x3632, 0x32 },
164 { 0x3633, 0x52 },
165 { 0x3634, 0x70 },
166 { 0x3635, 0x13 },
167 { 0x3636, 0x03 },
168 { 0x3703, 0x5a },
169 { 0x3704, 0xa0 },
170 { 0x3705, 0x1a },
171 { 0x3709, 0x12 },
172 { 0x370b, 0x61 },
173 { 0x370f, 0x10 },
174 { 0x3715, 0x78 },
175 { 0x3717, 0x01 },
176 { 0x371b, 0x20 },
177 { 0x3731, 0x12 },
178 { 0x3901, 0x0a },
179 { 0x3905, 0x02 },
180 { 0x3906, 0x10 },
181 { 0x3719, 0x86 },
182 { 0x3810, 0x00 },
183 { 0x3811, 0x10 },
184 { 0x3812, 0x00 },
185 { 0x3821, 0x01 },
186 { 0x3824, 0x01 },
187 { 0x3826, 0x03 },
188 { 0x3828, 0x08 },
189 { 0x3a19, 0xf8 },
190 { 0x3c01, 0x34 },
191 { 0x3c04, 0x28 },
192 { 0x3c05, 0x98 },
193 { 0x3c07, 0x07 },
194 { 0x3c09, 0xc2 },
195 { 0x3c0a, 0x9c },
196 { 0x3c0b, 0x40 },
197 { 0x3c01, 0x34 },
198 { 0x4001, 0x02 },
199 { 0x4514, 0x00 },
200 { 0x4520, 0xb0 },
201 { 0x460b, 0x37 },
202 { 0x460c, 0x20 },
203 { 0x4818, 0x01 },
204 { 0x481d, 0xf0 },
205 { 0x481f, 0x50 },
206 { 0x4823, 0x70 },
207 { 0x4831, 0x14 },
208 { 0x5000, 0xa7 },
209 { 0x5001, 0x83 },
210 { 0x501d, 0x00 },
211 { 0x501f, 0x00 },
212 { 0x503d, 0x00 },
213 { 0x505c, 0x30 },
214 { 0x5181, 0x59 },
215 { 0x5183, 0x00 },
216 { 0x5191, 0xf0 },
217 { 0x5192, 0x03 },
218 { 0x5684, 0x10 },
219 { 0x5685, 0xa0 },
220 { 0x5686, 0x0c },
221 { 0x5687, 0x78 },
222 { 0x5a00, 0x08 },
223 { 0x5a21, 0x00 },
224 { 0x5a24, 0x00 },
225 { 0x3008, 0x02 },
226 { 0x3503, 0x00 },
227 { 0x5180, 0xff },
228 { 0x5181, 0xf2 },
229 { 0x5182, 0x00 },
230 { 0x5183, 0x14 },
231 { 0x5184, 0x25 },
232 { 0x5185, 0x24 },
233 { 0x5186, 0x09 },
234 { 0x5187, 0x09 },
235 { 0x5188, 0x0a },
236 { 0x5189, 0x75 },
237 { 0x518a, 0x52 },
238 { 0x518b, 0xea },
239 { 0x518c, 0xa8 },
240 { 0x518d, 0x42 },
241 { 0x518e, 0x38 },
242 { 0x518f, 0x56 },
243 { 0x5190, 0x42 },
244 { 0x5191, 0xf8 },
245 { 0x5192, 0x04 },
246 { 0x5193, 0xfd },
247 { 0x5194, 0xa7 },
248 { 0x5195, 0xfc },
249 { 0x5196, 0x03 },
250 { 0x5197, 0x01 },
251 { 0x5198, 0x04 },
252 { 0x5199, 0x12 },
253 { 0x519a, 0x04 },
254 { 0x519b, 0x00 },
255 { 0x519c, 0x06 },
256 { 0x519d, 0x82 },
257 { 0x519e, 0x38 },
258 { 0x5381, 0x1e },
259 { 0x5382, 0x5b },
260 { 0x5383, 0x08 },
261 { 0x5384, 0x0a },
262 { 0x5385, 0x7e },
263 { 0x5386, 0x88 },
264 { 0x5387, 0x7c },
265 { 0x5388, 0x6c },
266 { 0x5389, 0x10 },
267 { 0x538a, 0x01 },
268 { 0x538b, 0x98 },
269 { 0x5300, 0x08 },
270 { 0x5301, 0x30 },
271 { 0x5302, 0x10 },
272 { 0x5303, 0x00 },
273 { 0x5304, 0x08 },
274 { 0x5305, 0x30 },
275 { 0x5306, 0x08 },
276 { 0x5307, 0x16 },
277 { 0x5309, 0x08 },
278 { 0x530a, 0x30 },
279 { 0x530b, 0x04 },
280 { 0x530c, 0x06 },
281 { 0x5480, 0x01 },
282 { 0x5481, 0x08 },
283 { 0x5482, 0x14 },
284 { 0x5483, 0x28 },
285 { 0x5484, 0x51 },
286 { 0x5485, 0x65 },
287 { 0x5486, 0x71 },
288 { 0x5487, 0x7d },
289 { 0x5488, 0x87 },
290 { 0x5489, 0x91 },
291 { 0x548a, 0x9a },
292 { 0x548b, 0xaa },
293 { 0x548c, 0xb8 },
294 { 0x548d, 0xcd },
295 { 0x548e, 0xdd },
296 { 0x548f, 0xea },
297 { 0x5490, 0x1d },
298 { 0x5580, 0x02 },
299 { 0x5583, 0x40 },
300 { 0x5584, 0x10 },
301 { 0x5589, 0x10 },
302 { 0x558a, 0x00 },
303 { 0x558b, 0xf8 },
304 { 0x5800, 0x3f },
305 { 0x5801, 0x16 },
306 { 0x5802, 0x0e },
307 { 0x5803, 0x0d },
308 { 0x5804, 0x17 },
309 { 0x5805, 0x3f },
310 { 0x5806, 0x0b },
311 { 0x5807, 0x06 },
312 { 0x5808, 0x04 },
313 { 0x5809, 0x04 },
314 { 0x580a, 0x06 },
315 { 0x580b, 0x0b },
316 { 0x580c, 0x09 },
317 { 0x580d, 0x03 },
318 { 0x580e, 0x00 },
319 { 0x580f, 0x00 },
320 { 0x5810, 0x03 },
321 { 0x5811, 0x08 },
322 { 0x5812, 0x0a },
323 { 0x5813, 0x03 },
324 { 0x5814, 0x00 },
325 { 0x5815, 0x00 },
326 { 0x5816, 0x04 },
327 { 0x5817, 0x09 },
328 { 0x5818, 0x0f },
329 { 0x5819, 0x08 },
330 { 0x581a, 0x06 },
331 { 0x581b, 0x06 },
332 { 0x581c, 0x08 },
333 { 0x581d, 0x0c },
334 { 0x581e, 0x3f },
335 { 0x581f, 0x1e },
336 { 0x5820, 0x12 },
337 { 0x5821, 0x13 },
338 { 0x5822, 0x21 },
339 { 0x5823, 0x3f },
340 { 0x5824, 0x68 },
341 { 0x5825, 0x28 },
342 { 0x5826, 0x2c },
343 { 0x5827, 0x28 },
344 { 0x5828, 0x08 },
345 { 0x5829, 0x48 },
346 { 0x582a, 0x64 },
347 { 0x582b, 0x62 },
348 { 0x582c, 0x64 },
349 { 0x582d, 0x28 },
350 { 0x582e, 0x46 },
351 { 0x582f, 0x62 },
352 { 0x5830, 0x60 },
353 { 0x5831, 0x62 },
354 { 0x5832, 0x26 },
355 { 0x5833, 0x48 },
356 { 0x5834, 0x66 },
357 { 0x5835, 0x44 },
358 { 0x5836, 0x64 },
359 { 0x5837, 0x28 },
360 { 0x5838, 0x66 },
361 { 0x5839, 0x48 },
362 { 0x583a, 0x2c },
363 { 0x583b, 0x28 },
364 { 0x583c, 0x26 },
365 { 0x583d, 0xae },
366 { 0x5025, 0x00 },
367 { 0x3a0f, 0x30 },
368 { 0x3a10, 0x28 },
369 { 0x3a1b, 0x30 },
370 { 0x3a1e, 0x26 },
371 { 0x3a11, 0x60 },
372 { 0x3a1f, 0x14 },
373 { 0x0601, 0x02 },
374 { 0x3008, 0x42 },
375 { 0x3008, 0x02 },
376 { OV5645_IO_MIPI_CTRL00, 0x40 },
377 { OV5645_MIPI_CTRL00, 0x24 },
378 { OV5645_PAD_OUTPUT00, 0x70 }
379 };
380
381 static const struct reg_value ov5645_setting_sxga[] = {
382 { 0x3612, 0xa9 },
383 { 0x3614, 0x50 },
384 { 0x3618, 0x00 },
385 { 0x3034, 0x18 },
386 { 0x3035, 0x21 },
387 { 0x3036, 0x70 },
388 { 0x3600, 0x09 },
389 { 0x3601, 0x43 },
390 { 0x3708, 0x66 },
391 { 0x370c, 0xc3 },
392 { 0x3800, 0x00 },
393 { 0x3801, 0x00 },
394 { 0x3802, 0x00 },
395 { 0x3803, 0x06 },
396 { 0x3804, 0x0a },
397 { 0x3805, 0x3f },
398 { 0x3806, 0x07 },
399 { 0x3807, 0x9d },
400 { 0x3808, 0x05 },
401 { 0x3809, 0x00 },
402 { 0x380a, 0x03 },
403 { 0x380b, 0xc0 },
404 { 0x380c, 0x07 },
405 { 0x380d, 0x68 },
406 { 0x380e, 0x03 },
407 { 0x380f, 0xd8 },
408 { 0x3813, 0x06 },
409 { 0x3814, 0x31 },
410 { 0x3815, 0x31 },
411 { 0x3820, 0x47 },
412 { 0x3a02, 0x03 },
413 { 0x3a03, 0xd8 },
414 { 0x3a08, 0x01 },
415 { 0x3a09, 0xf8 },
416 { 0x3a0a, 0x01 },
417 { 0x3a0b, 0xa4 },
418 { 0x3a0e, 0x02 },
419 { 0x3a0d, 0x02 },
420 { 0x3a14, 0x03 },
421 { 0x3a15, 0xd8 },
422 { 0x3a18, 0x00 },
423 { 0x4004, 0x02 },
424 { 0x4005, 0x18 },
425 { 0x4300, 0x32 },
426 { 0x4202, 0x00 }
427 };
428
429 static const struct reg_value ov5645_setting_1080p[] = {
430 { 0x3612, 0xab },
431 { 0x3614, 0x50 },
432 { 0x3618, 0x04 },
433 { 0x3034, 0x18 },
434 { 0x3035, 0x11 },
435 { 0x3036, 0x54 },
436 { 0x3600, 0x08 },
437 { 0x3601, 0x33 },
438 { 0x3708, 0x63 },
439 { 0x370c, 0xc0 },
440 { 0x3800, 0x01 },
441 { 0x3801, 0x50 },
442 { 0x3802, 0x01 },
443 { 0x3803, 0xb2 },
444 { 0x3804, 0x08 },
445 { 0x3805, 0xef },
446 { 0x3806, 0x05 },
447 { 0x3807, 0xf1 },
448 { 0x3808, 0x07 },
449 { 0x3809, 0x80 },
450 { 0x380a, 0x04 },
451 { 0x380b, 0x38 },
452 { 0x380c, 0x09 },
453 { 0x380d, 0xc4 },
454 { 0x380e, 0x04 },
455 { 0x380f, 0x60 },
456 { 0x3813, 0x04 },
457 { 0x3814, 0x11 },
458 { 0x3815, 0x11 },
459 { 0x3820, 0x47 },
460 { 0x4514, 0x88 },
461 { 0x3a02, 0x04 },
462 { 0x3a03, 0x60 },
463 { 0x3a08, 0x01 },
464 { 0x3a09, 0x50 },
465 { 0x3a0a, 0x01 },
466 { 0x3a0b, 0x18 },
467 { 0x3a0e, 0x03 },
468 { 0x3a0d, 0x04 },
469 { 0x3a14, 0x04 },
470 { 0x3a15, 0x60 },
471 { 0x3a18, 0x00 },
472 { 0x4004, 0x06 },
473 { 0x4005, 0x18 },
474 { 0x4300, 0x32 },
475 { 0x4202, 0x00 },
476 { 0x4837, 0x0b }
477 };
478
479 static const struct reg_value ov5645_setting_full[] = {
480 { 0x3612, 0xab },
481 { 0x3614, 0x50 },
482 { 0x3618, 0x04 },
483 { 0x3034, 0x18 },
484 { 0x3035, 0x11 },
485 { 0x3036, 0x54 },
486 { 0x3600, 0x08 },
487 { 0x3601, 0x33 },
488 { 0x3708, 0x63 },
489 { 0x370c, 0xc0 },
490 { 0x3800, 0x00 },
491 { 0x3801, 0x00 },
492 { 0x3802, 0x00 },
493 { 0x3803, 0x00 },
494 { 0x3804, 0x0a },
495 { 0x3805, 0x3f },
496 { 0x3806, 0x07 },
497 { 0x3807, 0x9f },
498 { 0x3808, 0x0a },
499 { 0x3809, 0x20 },
500 { 0x380a, 0x07 },
501 { 0x380b, 0x98 },
502 { 0x380c, 0x0b },
503 { 0x380d, 0x1c },
504 { 0x380e, 0x07 },
505 { 0x380f, 0xb0 },
506 { 0x3813, 0x06 },
507 { 0x3814, 0x11 },
508 { 0x3815, 0x11 },
509 { 0x3820, 0x47 },
510 { 0x4514, 0x88 },
511 { 0x3a02, 0x07 },
512 { 0x3a03, 0xb0 },
513 { 0x3a08, 0x01 },
514 { 0x3a09, 0x27 },
515 { 0x3a0a, 0x00 },
516 { 0x3a0b, 0xf6 },
517 { 0x3a0e, 0x06 },
518 { 0x3a0d, 0x08 },
519 { 0x3a14, 0x07 },
520 { 0x3a15, 0xb0 },
521 { 0x3a18, 0x01 },
522 { 0x4004, 0x06 },
523 { 0x4005, 0x18 },
524 { 0x4300, 0x32 },
525 { 0x4837, 0x0b },
526 { 0x4202, 0x00 }
527 };
528
529 static const s64 link_freq[] = {
530 224000000,
531 336000000
532 };
533
534 static const struct ov5645_mode_info ov5645_mode_info_data[] = {
535 {
536 .width = 1280,
537 .height = 960,
538 .max_fps = {
539 .numerator = 10000,
540 .denominator = 300000,
541 },
542 .data = ov5645_setting_sxga,
543 .data_size = ARRAY_SIZE(ov5645_setting_sxga),
544 .pixel_clock = 112000000,
545 .link_freq = 0 /* an index in link_freq[] */
546 },
547 {
548 .width = 1920,
549 .height = 1080,
550 .max_fps = {
551 .numerator = 10000,
552 .denominator = 300000,
553 },
554 .data = ov5645_setting_1080p,
555 .data_size = ARRAY_SIZE(ov5645_setting_1080p),
556 .pixel_clock = 168000000,
557 .link_freq = 1 /* an index in link_freq[] */
558 },
559 {
560 .width = 2592,
561 .height = 1944,
562 .max_fps = {
563 .numerator = 10000,
564 .denominator = 300000,
565 },
566 .data = ov5645_setting_full,
567 .data_size = ARRAY_SIZE(ov5645_setting_full),
568 .pixel_clock = 168000000,
569 .link_freq = 1 /* an index in link_freq[] */
570 },
571 };
572
ov5645_write_reg(struct ov5645 * ov5645,u16 reg,u8 val)573 static int ov5645_write_reg(struct ov5645 *ov5645, u16 reg, u8 val)
574 {
575 u8 regbuf[3];
576 int ret;
577
578 regbuf[0] = reg >> 8;
579 regbuf[1] = reg & 0xff;
580 regbuf[2] = val;
581
582 ret = i2c_master_send(ov5645->i2c_client, regbuf, 3);
583 if (ret < 0) {
584 dev_err(ov5645->dev, "%s: write reg error %d: reg=%x, val=%x\n",
585 __func__, ret, reg, val);
586 return ret;
587 }
588
589 return 0;
590 }
591
ov5645_read_reg(struct ov5645 * ov5645,u16 reg,u8 * val)592 static int ov5645_read_reg(struct ov5645 *ov5645, u16 reg, u8 *val)
593 {
594 u8 regbuf[2];
595 int ret;
596
597 regbuf[0] = reg >> 8;
598 regbuf[1] = reg & 0xff;
599
600 ret = i2c_master_send(ov5645->i2c_client, regbuf, 2);
601 if (ret < 0) {
602 dev_err(ov5645->dev, "%s: write reg error %d: reg=%x\n",
603 __func__, ret, reg);
604 return ret;
605 }
606
607 ret = i2c_master_recv(ov5645->i2c_client, val, 1);
608 if (ret < 0) {
609 dev_err(ov5645->dev, "%s: read reg error %d: reg=%x\n",
610 __func__, ret, reg);
611 return ret;
612 }
613
614 return 0;
615 }
616
ov5645_set_aec_mode(struct ov5645 * ov5645,u32 mode)617 static int ov5645_set_aec_mode(struct ov5645 *ov5645, u32 mode)
618 {
619 u8 val = ov5645->aec_pk_manual;
620 int ret;
621
622 if (mode == V4L2_EXPOSURE_AUTO)
623 val &= ~OV5645_AEC_MANUAL_ENABLE;
624 else /* V4L2_EXPOSURE_MANUAL */
625 val |= OV5645_AEC_MANUAL_ENABLE;
626
627 ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
628 if (!ret)
629 ov5645->aec_pk_manual = val;
630
631 return ret;
632 }
633
ov5645_set_agc_mode(struct ov5645 * ov5645,u32 enable)634 static int ov5645_set_agc_mode(struct ov5645 *ov5645, u32 enable)
635 {
636 u8 val = ov5645->aec_pk_manual;
637 int ret;
638
639 if (enable)
640 val &= ~OV5645_AGC_MANUAL_ENABLE;
641 else
642 val |= OV5645_AGC_MANUAL_ENABLE;
643
644 ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
645 if (!ret)
646 ov5645->aec_pk_manual = val;
647
648 return ret;
649 }
650
ov5645_set_register_array(struct ov5645 * ov5645,const struct reg_value * settings,unsigned int num_settings)651 static int ov5645_set_register_array(struct ov5645 *ov5645,
652 const struct reg_value *settings,
653 unsigned int num_settings)
654 {
655 unsigned int i;
656 int ret;
657 u8 tmp;
658
659 for (i = 0; i < num_settings; ++i, ++settings) {
660 ret = ov5645_write_reg(ov5645, settings->reg, settings->val);
661 if (ret < 0)
662 return ret;
663 if (settings->reg == OV5645_SYSTEM_CTRL0)
664 usleep_range(10000, 15000);
665 if ((settings->reg >= 0x3500) && (settings->reg <= 0x350b)) { //AEC
666 do {
667 ov5645_read_reg(ov5645, settings->reg, &tmp);
668 if (tmp != settings->val)
669 usleep_range(5000, 10000);
670 else
671 break;
672 ov5645_write_reg(ov5645, settings->reg, settings->val);
673 }while (1);
674 }
675 }
676
677 return 0;
678 }
679
ov5645_set_power_on(struct ov5645 * ov5645)680 static int ov5645_set_power_on(struct ov5645 *ov5645)
681 {
682 int ret;
683 /*
684 ret = regulator_bulk_enable(OV5645_NUM_SUPPLIES, ov5645->supplies);
685 if (ret < 0)
686 return ret;
687 */
688
689 ret = clk_prepare_enable(ov5645->xclk);
690 if (ret < 0) {
691 dev_err(ov5645->dev, "clk prepare enable failed\n");
692 // regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
693 return ret;
694 }
695
696 usleep_range(5000, 15000);
697 gpiod_set_value_cansleep(ov5645->enable_gpio, 1);
698
699 usleep_range(1000, 2000);
700 gpiod_set_value_cansleep(ov5645->rst_gpio, 0);
701
702 msleep(20);
703
704 return 0;
705 }
706
ov5645_set_power_off(struct ov5645 * ov5645)707 static void ov5645_set_power_off(struct ov5645 *ov5645)
708 {
709 gpiod_set_value_cansleep(ov5645->rst_gpio, 1);
710 gpiod_set_value_cansleep(ov5645->enable_gpio, 0);
711 clk_disable_unprepare(ov5645->xclk);
712 //regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
713 }
714
ov5645_s_power(struct v4l2_subdev * sd,int on)715 static int ov5645_s_power(struct v4l2_subdev *sd, int on)
716 {
717 struct ov5645 *ov5645 = to_ov5645(sd);
718 int ret = 0;
719
720 mutex_lock(&ov5645->power_lock);
721
722 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
723 * update the power state.
724 */
725 if (ov5645->power_count == !on) {
726 if (on) {
727 ret = ov5645_set_power_on(ov5645);
728 if (ret < 0)
729 goto exit;
730
731 ret = ov5645_set_register_array(ov5645,
732 ov5645_global_init_setting,
733 ARRAY_SIZE(ov5645_global_init_setting));
734 if (ret < 0) {
735 dev_err(ov5645->dev,
736 "could not set init registers\n");
737 ov5645_set_power_off(ov5645);
738 goto exit;
739 }
740
741 usleep_range(500, 1000);
742
743 } else {
744 ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x58);
745 ov5645_set_power_off(ov5645);
746 }
747 }
748
749 /* Update the power count. */
750 ov5645->power_count += on ? 1 : -1;
751 WARN_ON(ov5645->power_count < 0);
752
753 exit:
754 mutex_unlock(&ov5645->power_lock);
755
756 return ret;
757 }
758
ov5645_set_saturation(struct ov5645 * ov5645,s32 value)759 static int ov5645_set_saturation(struct ov5645 *ov5645, s32 value)
760 {
761 u32 reg_value = (value * 0x10) + 0x40;
762 int ret;
763
764 ret = ov5645_write_reg(ov5645, OV5645_SDE_SAT_U, reg_value);
765 if (ret < 0)
766 return ret;
767
768 return ov5645_write_reg(ov5645, OV5645_SDE_SAT_V, reg_value);
769 }
770
ov5645_set_hflip(struct ov5645 * ov5645,s32 value)771 static int ov5645_set_hflip(struct ov5645 *ov5645, s32 value)
772 {
773 u8 val = ov5645->timing_tc_reg21;
774 int ret;
775
776 if (value == 0)
777 val &= ~(OV5645_SENSOR_MIRROR);
778 else
779 val |= (OV5645_SENSOR_MIRROR);
780
781 ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG21, val);
782 if (!ret)
783 ov5645->timing_tc_reg21 = val;
784
785 return ret;
786 }
787
ov5645_set_vflip(struct ov5645 * ov5645,s32 value)788 static int ov5645_set_vflip(struct ov5645 *ov5645, s32 value)
789 {
790 u8 val = ov5645->timing_tc_reg20;
791 int ret;
792
793 if (value == 0)
794 val |= (OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
795 else
796 val &= ~(OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
797
798 ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG20, val);
799 if (!ret)
800 ov5645->timing_tc_reg20 = val;
801
802 return ret;
803 }
804
ov5645_set_test_pattern(struct ov5645 * ov5645,s32 value)805 static int ov5645_set_test_pattern(struct ov5645 *ov5645, s32 value)
806 {
807 u8 val = 0;
808
809 if (value) {
810 val = OV5645_SET_TEST_PATTERN(value - 1);
811 val |= OV5645_TEST_PATTERN_ENABLE;
812 }
813
814 return ov5645_write_reg(ov5645, OV5645_PRE_ISP_TEST_SETTING_1, val);
815 }
816
817 static const char * const ov5645_test_pattern_menu[] = {
818 "Disabled",
819 "Vertical Color Bars",
820 "Pseudo-Random Data",
821 "Color Square",
822 "Black Image",
823 };
824
ov5645_set_awb(struct ov5645 * ov5645,s32 enable_auto)825 static int ov5645_set_awb(struct ov5645 *ov5645, s32 enable_auto)
826 {
827 u8 val = 0;
828
829 if (!enable_auto)
830 val = OV5645_AWB_MANUAL_ENABLE;
831
832 return ov5645_write_reg(ov5645, OV5645_AWB_MANUAL_CONTROL, val);
833 }
834
ov5645_s_ctrl(struct v4l2_ctrl * ctrl)835 static int ov5645_s_ctrl(struct v4l2_ctrl *ctrl)
836 {
837 struct ov5645 *ov5645 = container_of(ctrl->handler,
838 struct ov5645, ctrls);
839 int ret = 0;
840
841 mutex_lock(&ov5645->power_lock);
842 if (!ov5645->power_count) {
843 mutex_unlock(&ov5645->power_lock);
844 return 0;
845 }
846
847 switch (ctrl->id) {
848 case V4L2_CID_SATURATION:
849 ret = ov5645_set_saturation(ov5645, ctrl->val);
850 break;
851 case V4L2_CID_AUTO_WHITE_BALANCE:
852 ret = ov5645_set_awb(ov5645, ctrl->val);
853 break;
854 case V4L2_CID_AUTOGAIN:
855 ret = ov5645_set_agc_mode(ov5645, ctrl->val);
856 break;
857 case V4L2_CID_EXPOSURE_AUTO:
858 ret = ov5645_set_aec_mode(ov5645, ctrl->val);
859 break;
860 case V4L2_CID_TEST_PATTERN:
861 ret = ov5645_set_test_pattern(ov5645, ctrl->val);
862 break;
863 case V4L2_CID_HFLIP:
864 ret = ov5645_set_hflip(ov5645, ctrl->val);
865 break;
866 case V4L2_CID_VFLIP:
867 ret = ov5645_set_vflip(ov5645, ctrl->val);
868 break;
869 default:
870 ret = -EINVAL;
871 break;
872 }
873
874 mutex_unlock(&ov5645->power_lock);
875
876 return ret;
877 }
878
879 static const struct v4l2_ctrl_ops ov5645_ctrl_ops = {
880 .s_ctrl = ov5645_s_ctrl,
881 };
882
ov5645_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)883 static int ov5645_enum_mbus_code(struct v4l2_subdev *sd,
884 struct v4l2_subdev_pad_config *cfg,
885 struct v4l2_subdev_mbus_code_enum *code)
886 {
887 if (code->index > 0)
888 return -EINVAL;
889
890 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
891
892 return 0;
893 }
894
ov5645_enum_frame_size(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)895 static int ov5645_enum_frame_size(struct v4l2_subdev *subdev,
896 struct v4l2_subdev_pad_config *cfg,
897 struct v4l2_subdev_frame_size_enum *fse)
898 {
899 if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
900 return -EINVAL;
901
902 if (fse->index >= ARRAY_SIZE(ov5645_mode_info_data))
903 return -EINVAL;
904
905 fse->min_width = ov5645_mode_info_data[fse->index].width;
906 fse->max_width = ov5645_mode_info_data[fse->index].width;
907 fse->min_height = ov5645_mode_info_data[fse->index].height;
908 fse->max_height = ov5645_mode_info_data[fse->index].height;
909
910 return 0;
911 }
912
ov5645_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)913 static int ov5645_enum_frame_interval(struct v4l2_subdev *sd,
914 struct v4l2_subdev_pad_config *cfg,
915 struct v4l2_subdev_frame_interval_enum *fie)
916 {
917 if (fie->index >= ARRAY_SIZE(ov5645_mode_info_data))
918 return -EINVAL;
919 fie->code = MEDIA_BUS_FMT_UYVY8_2X8;
920 fie->width = ov5645_mode_info_data[fie->index].width;
921 fie->height = ov5645_mode_info_data[fie->index].height;
922 fie->interval = ov5645_mode_info_data[fie->index].max_fps;
923 fie->reserved[0] = NO_HDR;
924 return 0;
925 }
926
927
928 static struct v4l2_mbus_framefmt *
__ov5645_get_pad_format(struct ov5645 * ov5645,struct v4l2_subdev_pad_config * cfg,unsigned int pad,enum v4l2_subdev_format_whence which)929 __ov5645_get_pad_format(struct ov5645 *ov5645,
930 struct v4l2_subdev_pad_config *cfg,
931 unsigned int pad,
932 enum v4l2_subdev_format_whence which)
933 {
934 switch (which) {
935 case V4L2_SUBDEV_FORMAT_TRY:
936 return v4l2_subdev_get_try_format(&ov5645->sd, cfg, pad);
937 case V4L2_SUBDEV_FORMAT_ACTIVE:
938 return &ov5645->fmt;
939 default:
940 return NULL;
941 }
942 }
943
ov5645_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)944 static int ov5645_get_format(struct v4l2_subdev *sd,
945 struct v4l2_subdev_pad_config *cfg,
946 struct v4l2_subdev_format *format)
947 {
948 struct ov5645 *ov5645 = to_ov5645(sd);
949
950 format->format = *__ov5645_get_pad_format(ov5645, cfg, format->pad,
951 format->which);
952 return 0;
953 }
954
955 static struct v4l2_rect *
__ov5645_get_pad_crop(struct ov5645 * ov5645,struct v4l2_subdev_pad_config * cfg,unsigned int pad,enum v4l2_subdev_format_whence which)956 __ov5645_get_pad_crop(struct ov5645 *ov5645, struct v4l2_subdev_pad_config *cfg,
957 unsigned int pad, enum v4l2_subdev_format_whence which)
958 {
959 switch (which) {
960 case V4L2_SUBDEV_FORMAT_TRY:
961 return v4l2_subdev_get_try_crop(&ov5645->sd, cfg, pad);
962 case V4L2_SUBDEV_FORMAT_ACTIVE:
963 return &ov5645->crop;
964 default:
965 return NULL;
966 }
967 }
968
ov5645_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)969 static int ov5645_set_format(struct v4l2_subdev *sd,
970 struct v4l2_subdev_pad_config *cfg,
971 struct v4l2_subdev_format *format)
972 {
973 struct ov5645 *ov5645 = to_ov5645(sd);
974 struct v4l2_mbus_framefmt *__format;
975 struct v4l2_rect *__crop;
976 const struct ov5645_mode_info *new_mode;
977 int ret;
978
979 __crop = __ov5645_get_pad_crop(ov5645, cfg, format->pad,
980 format->which);
981
982 new_mode = v4l2_find_nearest_size(ov5645_mode_info_data,
983 ARRAY_SIZE(ov5645_mode_info_data),
984 width, height,
985 format->format.width, format->format.height);
986
987 __crop->width = new_mode->width;
988 __crop->height = new_mode->height;
989
990 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
991 ret = v4l2_ctrl_s_ctrl_int64(ov5645->pixel_clock,
992 new_mode->pixel_clock);
993 if (ret < 0)
994 return ret;
995
996 ret = v4l2_ctrl_s_ctrl(ov5645->link_freq,
997 new_mode->link_freq);
998 if (ret < 0)
999 return ret;
1000
1001 ov5645->current_mode = new_mode;
1002 }
1003
1004 __format = __ov5645_get_pad_format(ov5645, cfg, format->pad,
1005 format->which);
1006 __format->width = __crop->width;
1007 __format->height = __crop->height;
1008 __format->code = MEDIA_BUS_FMT_UYVY8_2X8;
1009 __format->field = V4L2_FIELD_NONE;
1010 __format->colorspace = V4L2_COLORSPACE_SRGB;
1011
1012 format->format = *__format;
1013
1014 return 0;
1015 }
1016
ov5645_entity_init_cfg(struct v4l2_subdev * subdev,struct v4l2_subdev_pad_config * cfg)1017 static int ov5645_entity_init_cfg(struct v4l2_subdev *subdev,
1018 struct v4l2_subdev_pad_config *cfg)
1019 {
1020 struct v4l2_subdev_format fmt = { 0 };
1021
1022 fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1023 fmt.format.width = 1920;
1024 fmt.format.height = 1080;
1025
1026 ov5645_set_format(subdev, cfg, &fmt);
1027
1028 return 0;
1029 }
1030
ov5645_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1031 static int ov5645_get_selection(struct v4l2_subdev *sd,
1032 struct v4l2_subdev_pad_config *cfg,
1033 struct v4l2_subdev_selection *sel)
1034 {
1035 struct ov5645 *ov5645 = to_ov5645(sd);
1036
1037 if (sel->target != V4L2_SEL_TGT_CROP)
1038 return -EINVAL;
1039
1040 sel->r = *__ov5645_get_pad_crop(ov5645, cfg, sel->pad,
1041 sel->which);
1042 return 0;
1043 }
1044
1045 #define OV5645_LANES 2
ov5645_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)1046 static int ov5645_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
1047 struct v4l2_mbus_config *config)
1048 {
1049 u32 val = 0;
1050
1051 val = 1 << (OV5645_LANES - 1) |
1052 V4L2_MBUS_CSI2_CHANNEL_0 |
1053 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
1054 config->type = V4L2_MBUS_CSI2_DPHY;
1055 config->flags = val;
1056
1057 return 0;
1058 }
1059
ov5645_s_stream(struct v4l2_subdev * subdev,int enable)1060 static int ov5645_s_stream(struct v4l2_subdev *subdev, int enable)
1061 {
1062 struct ov5645 *ov5645 = to_ov5645(subdev);
1063 int ret;
1064
1065 if (enable) {
1066 ret = ov5645_set_register_array(ov5645,
1067 ov5645->current_mode->data,
1068 ov5645->current_mode->data_size);
1069 if (ret < 0) {
1070 dev_err(ov5645->dev, "could not set mode %dx%d\n",
1071 ov5645->current_mode->width,
1072 ov5645->current_mode->height);
1073 return ret;
1074 }
1075 ret = v4l2_ctrl_handler_setup(&ov5645->ctrls);
1076 if (ret < 0) {
1077 dev_err(ov5645->dev, "could not sync v4l2 controls\n");
1078 return ret;
1079 }
1080
1081 ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x45);
1082 if (ret < 0)
1083 return ret;
1084
1085 ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1086 OV5645_SYSTEM_CTRL0_START);
1087 if (ret < 0)
1088 return ret;
1089 } else {
1090 ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x40);
1091 if (ret < 0)
1092 return ret;
1093
1094 ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1095 OV5645_SYSTEM_CTRL0_STOP);
1096 if (ret < 0)
1097 return ret;
1098 }
1099
1100 return 0;
1101 }
1102
ov5645_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)1103 static int ov5645_g_frame_interval(struct v4l2_subdev *sd,
1104 struct v4l2_subdev_frame_interval *fi)
1105 {
1106 struct ov5645 *ov5645 = to_ov5645(sd);
1107 const struct ov5645_mode_info *mode = ov5645->current_mode;
1108
1109 fi->interval = mode->max_fps;
1110
1111 return 0;
1112 }
1113
ov5645_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)1114 static long ov5645_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
1115 {
1116 struct rkmodule_inf *inf = (struct rkmodule_inf *)arg;
1117 struct rkmodule_channel_info *ch_info;
1118 struct ov5645 *ov5645 = to_ov5645(sd);
1119 u32 stream;
1120 switch (cmd) {
1121 case RKMODULE_GET_MODULE_INFO:
1122 memset(inf, 0, sizeof(*inf));
1123 strlcpy(inf->base.sensor, "ov5645", sizeof(inf->base.sensor));
1124 strlcpy(inf->base.module, ov5645->module_name,
1125 sizeof(inf->base.module));
1126 strlcpy(inf->base.lens, ov5645->len_name, sizeof(inf->base.lens));
1127
1128 break;
1129 case RKMODULE_GET_CHANNEL_INFO:
1130 ch_info = (struct rkmodule_channel_info *)arg;
1131 ch_info->vc = V4L2_MBUS_CSI2_CHANNEL_0;
1132 ch_info->width = ov5645->current_mode->width;
1133 ch_info->height = ov5645->current_mode->height;
1134 ch_info->bus_fmt = MEDIA_BUS_FMT_UYVY8_2X8;
1135 break;
1136
1137 case RKMODULE_SET_QUICK_STREAM:
1138 stream = *((u32 *)arg);
1139 if (stream) {
1140 ov5645_set_register_array(ov5645,
1141 ov5645->current_mode->data,
1142 ov5645->current_mode->data_size);
1143 //usleep_range(10000, 15000);
1144 //ov5645_set_register_array(ov5645, ov5645_check_aec, ARRAY_SIZE(ov5645_check_aec));
1145 usleep_range(10000, 15000);
1146
1147 ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x45);
1148 ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1149 OV5645_SYSTEM_CTRL0_START);
1150 } else {
1151 ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x40);
1152 ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1153 OV5645_SYSTEM_CTRL0_STOP);
1154 }
1155
1156 break;
1157 default:
1158 return -ENOIOCTLCMD;
1159 break;
1160 }
1161 return 0;
1162 }
1163
1164
1165 #ifdef CONFIG_COMPAT
ov5645_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1166 static long ov5645_compat_ioctl32(struct v4l2_subdev *sd,
1167 unsigned int cmd, unsigned long arg)
1168 {
1169 void __user *up = compat_ptr(arg);
1170 struct rkmodule_inf *inf;
1171 struct rkmodule_channel_info *ch_info;
1172 u32 stream;
1173 long ret = -ENOIOCTLCMD;
1174
1175 switch (cmd) {
1176 case RKMODULE_GET_MODULE_INFO:
1177 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1178 if (!inf) {
1179 ret = -ENOMEM;
1180 return ret;
1181 }
1182
1183 ret = ov5645_ioctl(sd, cmd, inf);
1184 if (!ret)
1185 ret = copy_to_user(up, inf, sizeof(*inf));
1186 if (ret)
1187 ret = -EFAULT;
1188 kfree(inf);
1189 return 0;
1190 break;
1191 case RKMODULE_GET_CHANNEL_INFO:
1192 ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
1193 if (!ch_info) {
1194 ret = -ENOMEM;
1195 return ret;
1196 }
1197 ret = ov5645_ioctl(sd, cmd, ch_info);
1198 if (!ret) {
1199 ret = copy_to_user(up, ch_info, sizeof(*ch_info));
1200 if (ret)
1201 ret = -EFAULT;
1202 }
1203 kfree(ch_info);
1204 break;
1205 case RKMODULE_SET_QUICK_STREAM:
1206 ret = copy_from_user(&stream, up, sizeof(u32));
1207 if (!ret)
1208 ret = ov5645_ioctl(sd, cmd, &stream);
1209 break;
1210 default:
1211 ret = -ENOIOCTLCMD;
1212 break;
1213 }
1214 return ret;
1215
1216 }
1217 #endif
1218
1219 static const struct v4l2_subdev_core_ops ov5645_core_ops = {
1220 .s_power = ov5645_s_power,
1221 .ioctl = ov5645_ioctl,
1222 #ifdef CONFIG_COMPAT
1223 .compat_ioctl32 = ov5645_compat_ioctl32,
1224 #endif
1225
1226 };
1227
1228 static const struct v4l2_subdev_video_ops ov5645_video_ops = {
1229 .s_stream = ov5645_s_stream,
1230 .g_frame_interval = ov5645_g_frame_interval,
1231 };
1232
1233 static const struct v4l2_subdev_pad_ops ov5645_subdev_pad_ops = {
1234 .init_cfg = ov5645_entity_init_cfg,
1235 .enum_mbus_code = ov5645_enum_mbus_code,
1236 .enum_frame_size = ov5645_enum_frame_size,
1237 .enum_frame_interval = ov5645_enum_frame_interval,
1238 .get_fmt = ov5645_get_format,
1239 .set_fmt = ov5645_set_format,
1240 .get_selection = ov5645_get_selection,
1241 .get_mbus_config = ov5645_g_mbus_config,
1242 };
1243
1244 static const struct v4l2_subdev_ops ov5645_subdev_ops = {
1245 .core = &ov5645_core_ops,
1246 .video = &ov5645_video_ops,
1247 .pad = &ov5645_subdev_pad_ops,
1248 };
1249
ov5645_probe(struct i2c_client * client)1250 static int ov5645_probe(struct i2c_client *client)
1251 {
1252 struct device *dev = &client->dev;
1253 struct device_node *node = dev->of_node;
1254 struct device_node *endpoint;
1255 struct ov5645 *ov5645;
1256 u8 chip_id_high, chip_id_low;
1257 u32 xclk_freq;
1258 int ret;
1259 char facing[2];
1260
1261 ov5645 = devm_kzalloc(dev, sizeof(struct ov5645), GFP_KERNEL);
1262 if (!ov5645)
1263 return -ENOMEM;
1264
1265 ov5645->i2c_client = client;
1266 ov5645->dev = dev;
1267
1268 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1269 &ov5645->module_index);
1270 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1271 &ov5645->module_facing);
1272 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1273 &ov5645->module_name);
1274 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1275 &ov5645->len_name);
1276 if (ret) {
1277 dev_err(dev, "could not get module information!\n");
1278 return -EINVAL;
1279 }
1280
1281 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1282 if (!endpoint) {
1283 dev_err(dev, "endpoint node not found\n");
1284 return -EINVAL;
1285 }
1286
1287 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1288 &ov5645->ep);
1289
1290 of_node_put(endpoint);
1291
1292 if (ret < 0) {
1293 dev_err(dev, "parsing endpoint node failed\n");
1294 return ret;
1295 }
1296
1297 if (ov5645->ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1298 dev_err(dev, "invalid bus type, must be CSI2\n");
1299 return -EINVAL;
1300 }
1301
1302 /* get system clock (xclk) */
1303 ov5645->xclk = devm_clk_get(dev, "xclk");
1304 if (IS_ERR(ov5645->xclk)) {
1305 dev_err(dev, "could not get xclk");
1306 return PTR_ERR(ov5645->xclk);
1307 }
1308
1309 ret = of_property_read_u32(dev->of_node, "clock-frequency", &xclk_freq);
1310 if (ret) {
1311 dev_err(dev, "could not get xclk frequency\n");
1312 return ret;
1313 }
1314
1315 /* external clock must be 24MHz, allow 1% tolerance */
1316 if (xclk_freq < 23760000 || xclk_freq > 24240000) {
1317 dev_err(dev, "external clock frequency %u is not supported\n",
1318 xclk_freq);
1319 return -EINVAL;
1320 }
1321
1322 ret = clk_set_rate(ov5645->xclk, xclk_freq);
1323 if (ret) {
1324 dev_err(dev, "could not set xclk frequency\n");
1325 return ret;
1326 }
1327
1328 /*
1329 for (i = 0; i < OV5645_NUM_SUPPLIES; i++)
1330 ov5645->supplies[i].supply = ov5645_supply_name[i];
1331
1332 ret = devm_regulator_bulk_get(dev, OV5645_NUM_SUPPLIES,
1333 ov5645->supplies);
1334 if (ret < 0)
1335 return ret;
1336 */
1337
1338 ov5645->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
1339 if (IS_ERR(ov5645->enable_gpio)) {
1340 dev_err(dev, "cannot get enable gpio\n");
1341 return PTR_ERR(ov5645->enable_gpio);
1342 }
1343
1344 ov5645->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
1345 if (IS_ERR(ov5645->rst_gpio)) {
1346 dev_err(dev, "cannot get reset gpio\n");
1347 return PTR_ERR(ov5645->rst_gpio);
1348 }
1349
1350 mutex_init(&ov5645->power_lock);
1351
1352 v4l2_ctrl_handler_init(&ov5645->ctrls, 9);
1353 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1354 V4L2_CID_SATURATION, -4, 4, 1, 0);
1355 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1356 V4L2_CID_HFLIP, 0, 1, 1, 0);
1357 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1358 V4L2_CID_VFLIP, 0, 1, 1, 0);
1359 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1360 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1361 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1362 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1363 v4l2_ctrl_new_std_menu(&ov5645->ctrls, &ov5645_ctrl_ops,
1364 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL,
1365 0, V4L2_EXPOSURE_AUTO);
1366 v4l2_ctrl_new_std_menu_items(&ov5645->ctrls, &ov5645_ctrl_ops,
1367 V4L2_CID_TEST_PATTERN,
1368 ARRAY_SIZE(ov5645_test_pattern_menu) - 1,
1369 0, 0, ov5645_test_pattern_menu);
1370 ov5645->pixel_clock = v4l2_ctrl_new_std(&ov5645->ctrls,
1371 &ov5645_ctrl_ops,
1372 V4L2_CID_PIXEL_RATE,
1373 1, INT_MAX, 1, 1);
1374 ov5645->link_freq = v4l2_ctrl_new_int_menu(&ov5645->ctrls,
1375 &ov5645_ctrl_ops,
1376 V4L2_CID_LINK_FREQ,
1377 ARRAY_SIZE(link_freq) - 1,
1378 0, link_freq);
1379 if (ov5645->link_freq)
1380 ov5645->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1381
1382 ov5645->sd.ctrl_handler = &ov5645->ctrls;
1383
1384 if (ov5645->ctrls.error) {
1385 dev_err(dev, "%s: control initialization error %d\n",
1386 __func__, ov5645->ctrls.error);
1387 ret = ov5645->ctrls.error;
1388 goto free_ctrl;
1389 }
1390
1391 v4l2_i2c_subdev_init(&ov5645->sd, client, &ov5645_subdev_ops);
1392 ov5645->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1393 ov5645->pad.flags = MEDIA_PAD_FL_SOURCE;
1394 ov5645->sd.dev = &client->dev;
1395 ov5645->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1396
1397 ret = media_entity_pads_init(&ov5645->sd.entity, 1, &ov5645->pad);
1398 if (ret < 0) {
1399 dev_err(dev, "could not register media entity\n");
1400 goto free_ctrl;
1401 }
1402
1403 ret = ov5645_s_power(&ov5645->sd, true);
1404 if (ret < 0) {
1405 dev_err(dev, "could not power up OV5645\n");
1406 goto free_entity;
1407 }
1408
1409 ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_HIGH, &chip_id_high);
1410 if (ret < 0 || chip_id_high != OV5645_CHIP_ID_HIGH_BYTE) {
1411 dev_err(dev, "could not read ID high\n");
1412 ret = -ENODEV;
1413 goto power_down;
1414 }
1415 ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_LOW, &chip_id_low);
1416 if (ret < 0 || chip_id_low != OV5645_CHIP_ID_LOW_BYTE) {
1417 dev_err(dev, "could not read ID low\n");
1418 ret = -ENODEV;
1419 goto power_down;
1420 }
1421
1422 dev_info(dev, "OV5645 detected at address 0x%02x\n", client->addr);
1423
1424 ret = ov5645_read_reg(ov5645, OV5645_AEC_PK_MANUAL,
1425 &ov5645->aec_pk_manual);
1426 if (ret < 0) {
1427 dev_err(dev, "could not read AEC/AGC mode\n");
1428 ret = -ENODEV;
1429 goto power_down;
1430 }
1431
1432 ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG20,
1433 &ov5645->timing_tc_reg20);
1434 if (ret < 0) {
1435 dev_err(dev, "could not read vflip value\n");
1436 ret = -ENODEV;
1437 goto power_down;
1438 }
1439
1440 ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG21,
1441 &ov5645->timing_tc_reg21);
1442 if (ret < 0) {
1443 dev_err(dev, "could not read hflip value\n");
1444 ret = -ENODEV;
1445 goto power_down;
1446 }
1447
1448 ov5645_s_power(&ov5645->sd, false);
1449
1450
1451 memset(facing, 0, sizeof(facing));
1452 if (strcmp(ov5645->module_facing, "back") == 0)
1453 facing[0] = 'b';
1454 else
1455 facing[0] = 'f';
1456
1457 snprintf(ov5645->sd.name, sizeof(ov5645->sd.name), "m%02d_%s_%s %s",
1458 ov5645->module_index, facing,
1459 "ov5645", dev_name(ov5645->sd.dev));
1460
1461 ret = v4l2_async_register_subdev_sensor_common(&ov5645->sd);
1462 if (ret) {
1463 dev_err(dev, "v4l2 async register subdev failed\n");
1464 }
1465
1466 ov5645_entity_init_cfg(&ov5645->sd, NULL);
1467
1468 return 0;
1469
1470 power_down:
1471 ov5645_s_power(&ov5645->sd, false);
1472 free_entity:
1473 media_entity_cleanup(&ov5645->sd.entity);
1474 free_ctrl:
1475 v4l2_ctrl_handler_free(&ov5645->ctrls);
1476 mutex_destroy(&ov5645->power_lock);
1477
1478 return ret;
1479 }
1480
ov5645_remove(struct i2c_client * client)1481 static int ov5645_remove(struct i2c_client *client)
1482 {
1483 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1484 struct ov5645 *ov5645 = to_ov5645(sd);
1485
1486 v4l2_async_unregister_subdev(&ov5645->sd);
1487 media_entity_cleanup(&ov5645->sd.entity);
1488 v4l2_ctrl_handler_free(&ov5645->ctrls);
1489 mutex_destroy(&ov5645->power_lock);
1490
1491 return 0;
1492 }
1493
1494 static const struct i2c_device_id ov5645_id[] = {
1495 { "ov5645", 0 },
1496 {}
1497 };
1498 MODULE_DEVICE_TABLE(i2c, ov5645_id);
1499
1500 static const struct of_device_id ov5645_of_match[] = {
1501 { .compatible = "ovti,ov5645" },
1502 { /* sentinel */ }
1503 };
1504 MODULE_DEVICE_TABLE(of, ov5645_of_match);
1505
1506 static struct i2c_driver ov5645_i2c_driver = {
1507 .driver = {
1508 .of_match_table = of_match_ptr(ov5645_of_match),
1509 .name = "ov5645",
1510 },
1511 .probe_new = ov5645_probe,
1512 .remove = ov5645_remove,
1513 .id_table = ov5645_id,
1514 };
1515
1516 module_i2c_driver(ov5645_i2c_driver);
1517
1518 MODULE_DESCRIPTION("Omnivision OV5645 Camera Driver");
1519 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1520 MODULE_LICENSE("GPL v2");
1521