xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/ov5640.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4*4882a593Smuzhiyun  * Copyright (C) 2014-2017 Mentor Graphics Inc.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/clk.h>
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/clkdev.h>
10*4882a593Smuzhiyun #include <linux/ctype.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun #include <linux/types.h>
21*4882a593Smuzhiyun #include <media/v4l2-async.h>
22*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
23*4882a593Smuzhiyun #include <media/v4l2-device.h>
24*4882a593Smuzhiyun #include <media/v4l2-event.h>
25*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
26*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* min/typical/max system clock (xclk) frequencies */
29*4882a593Smuzhiyun #define OV5640_XCLK_MIN  6000000
30*4882a593Smuzhiyun #define OV5640_XCLK_MAX 54000000
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define OV5640_DEFAULT_SLAVE_ID 0x3c
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define OV5640_REG_SYS_RESET02		0x3002
35*4882a593Smuzhiyun #define OV5640_REG_SYS_CLOCK_ENABLE02	0x3006
36*4882a593Smuzhiyun #define OV5640_REG_SYS_CTRL0		0x3008
37*4882a593Smuzhiyun #define OV5640_REG_SYS_CTRL0_SW_PWDN	0x42
38*4882a593Smuzhiyun #define OV5640_REG_SYS_CTRL0_SW_PWUP	0x02
39*4882a593Smuzhiyun #define OV5640_REG_CHIP_ID		0x300a
40*4882a593Smuzhiyun #define OV5640_REG_IO_MIPI_CTRL00	0x300e
41*4882a593Smuzhiyun #define OV5640_REG_PAD_OUTPUT_ENABLE01	0x3017
42*4882a593Smuzhiyun #define OV5640_REG_PAD_OUTPUT_ENABLE02	0x3018
43*4882a593Smuzhiyun #define OV5640_REG_PAD_OUTPUT00		0x3019
44*4882a593Smuzhiyun #define OV5640_REG_SYSTEM_CONTROL1	0x302e
45*4882a593Smuzhiyun #define OV5640_REG_SC_PLL_CTRL0		0x3034
46*4882a593Smuzhiyun #define OV5640_REG_SC_PLL_CTRL1		0x3035
47*4882a593Smuzhiyun #define OV5640_REG_SC_PLL_CTRL2		0x3036
48*4882a593Smuzhiyun #define OV5640_REG_SC_PLL_CTRL3		0x3037
49*4882a593Smuzhiyun #define OV5640_REG_SLAVE_ID		0x3100
50*4882a593Smuzhiyun #define OV5640_REG_SCCB_SYS_CTRL1	0x3103
51*4882a593Smuzhiyun #define OV5640_REG_SYS_ROOT_DIVIDER	0x3108
52*4882a593Smuzhiyun #define OV5640_REG_AWB_R_GAIN		0x3400
53*4882a593Smuzhiyun #define OV5640_REG_AWB_G_GAIN		0x3402
54*4882a593Smuzhiyun #define OV5640_REG_AWB_B_GAIN		0x3404
55*4882a593Smuzhiyun #define OV5640_REG_AWB_MANUAL_CTRL	0x3406
56*4882a593Smuzhiyun #define OV5640_REG_AEC_PK_EXPOSURE_HI	0x3500
57*4882a593Smuzhiyun #define OV5640_REG_AEC_PK_EXPOSURE_MED	0x3501
58*4882a593Smuzhiyun #define OV5640_REG_AEC_PK_EXPOSURE_LO	0x3502
59*4882a593Smuzhiyun #define OV5640_REG_AEC_PK_MANUAL	0x3503
60*4882a593Smuzhiyun #define OV5640_REG_AEC_PK_REAL_GAIN	0x350a
61*4882a593Smuzhiyun #define OV5640_REG_AEC_PK_VTS		0x350c
62*4882a593Smuzhiyun #define OV5640_REG_TIMING_DVPHO		0x3808
63*4882a593Smuzhiyun #define OV5640_REG_TIMING_DVPVO		0x380a
64*4882a593Smuzhiyun #define OV5640_REG_TIMING_HTS		0x380c
65*4882a593Smuzhiyun #define OV5640_REG_TIMING_VTS		0x380e
66*4882a593Smuzhiyun #define OV5640_REG_TIMING_TC_REG20	0x3820
67*4882a593Smuzhiyun #define OV5640_REG_TIMING_TC_REG21	0x3821
68*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL00		0x3a00
69*4882a593Smuzhiyun #define OV5640_REG_AEC_B50_STEP		0x3a08
70*4882a593Smuzhiyun #define OV5640_REG_AEC_B60_STEP		0x3a0a
71*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL0D		0x3a0d
72*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL0E		0x3a0e
73*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL0F		0x3a0f
74*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL10		0x3a10
75*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL11		0x3a11
76*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL1B		0x3a1b
77*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL1E		0x3a1e
78*4882a593Smuzhiyun #define OV5640_REG_AEC_CTRL1F		0x3a1f
79*4882a593Smuzhiyun #define OV5640_REG_HZ5060_CTRL00	0x3c00
80*4882a593Smuzhiyun #define OV5640_REG_HZ5060_CTRL01	0x3c01
81*4882a593Smuzhiyun #define OV5640_REG_SIGMADELTA_CTRL0C	0x3c0c
82*4882a593Smuzhiyun #define OV5640_REG_FRAME_CTRL01		0x4202
83*4882a593Smuzhiyun #define OV5640_REG_FORMAT_CONTROL00	0x4300
84*4882a593Smuzhiyun #define OV5640_REG_VFIFO_HSIZE		0x4602
85*4882a593Smuzhiyun #define OV5640_REG_VFIFO_VSIZE		0x4604
86*4882a593Smuzhiyun #define OV5640_REG_JPG_MODE_SELECT	0x4713
87*4882a593Smuzhiyun #define OV5640_REG_CCIR656_CTRL00	0x4730
88*4882a593Smuzhiyun #define OV5640_REG_POLARITY_CTRL00	0x4740
89*4882a593Smuzhiyun #define OV5640_REG_MIPI_CTRL00		0x4800
90*4882a593Smuzhiyun #define OV5640_REG_DEBUG_MODE		0x4814
91*4882a593Smuzhiyun #define OV5640_REG_ISP_FORMAT_MUX_CTRL	0x501f
92*4882a593Smuzhiyun #define OV5640_REG_PRE_ISP_TEST_SET1	0x503d
93*4882a593Smuzhiyun #define OV5640_REG_SDE_CTRL0		0x5580
94*4882a593Smuzhiyun #define OV5640_REG_SDE_CTRL1		0x5581
95*4882a593Smuzhiyun #define OV5640_REG_SDE_CTRL3		0x5583
96*4882a593Smuzhiyun #define OV5640_REG_SDE_CTRL4		0x5584
97*4882a593Smuzhiyun #define OV5640_REG_SDE_CTRL5		0x5585
98*4882a593Smuzhiyun #define OV5640_REG_AVG_READOUT		0x56a1
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun enum ov5640_mode_id {
101*4882a593Smuzhiyun 	OV5640_MODE_QCIF_176_144 = 0,
102*4882a593Smuzhiyun 	OV5640_MODE_QVGA_320_240,
103*4882a593Smuzhiyun 	OV5640_MODE_VGA_640_480,
104*4882a593Smuzhiyun 	OV5640_MODE_NTSC_720_480,
105*4882a593Smuzhiyun 	OV5640_MODE_PAL_720_576,
106*4882a593Smuzhiyun 	OV5640_MODE_XGA_1024_768,
107*4882a593Smuzhiyun 	OV5640_MODE_720P_1280_720,
108*4882a593Smuzhiyun 	OV5640_MODE_1080P_1920_1080,
109*4882a593Smuzhiyun 	OV5640_MODE_QSXGA_2592_1944,
110*4882a593Smuzhiyun 	OV5640_NUM_MODES,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun enum ov5640_frame_rate {
114*4882a593Smuzhiyun 	OV5640_15_FPS = 0,
115*4882a593Smuzhiyun 	OV5640_30_FPS,
116*4882a593Smuzhiyun 	OV5640_60_FPS,
117*4882a593Smuzhiyun 	OV5640_NUM_FRAMERATES,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun enum ov5640_format_mux {
121*4882a593Smuzhiyun 	OV5640_FMT_MUX_YUV422 = 0,
122*4882a593Smuzhiyun 	OV5640_FMT_MUX_RGB,
123*4882a593Smuzhiyun 	OV5640_FMT_MUX_DITHER,
124*4882a593Smuzhiyun 	OV5640_FMT_MUX_RAW_DPC,
125*4882a593Smuzhiyun 	OV5640_FMT_MUX_SNR_RAW,
126*4882a593Smuzhiyun 	OV5640_FMT_MUX_RAW_CIP,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun struct ov5640_pixfmt {
130*4882a593Smuzhiyun 	u32 code;
131*4882a593Smuzhiyun 	u32 colorspace;
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun static const struct ov5640_pixfmt ov5640_formats[] = {
135*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_JPEG_1X8, V4L2_COLORSPACE_JPEG, },
136*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB, },
137*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB, },
138*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB, },
139*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB, },
140*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB, },
141*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_SGBRG8_1X8, V4L2_COLORSPACE_SRGB, },
142*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_SGRBG8_1X8, V4L2_COLORSPACE_SRGB, },
143*4882a593Smuzhiyun 	{ MEDIA_BUS_FMT_SRGGB8_1X8, V4L2_COLORSPACE_SRGB, },
144*4882a593Smuzhiyun };
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun  * FIXME: remove this when a subdev API becomes available
148*4882a593Smuzhiyun  * to set the MIPI CSI-2 virtual channel.
149*4882a593Smuzhiyun  */
150*4882a593Smuzhiyun static unsigned int virtual_channel;
151*4882a593Smuzhiyun module_param(virtual_channel, uint, 0444);
152*4882a593Smuzhiyun MODULE_PARM_DESC(virtual_channel,
153*4882a593Smuzhiyun 		 "MIPI CSI-2 virtual channel (0..3), default 0");
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun static const int ov5640_framerates[] = {
156*4882a593Smuzhiyun 	[OV5640_15_FPS] = 15,
157*4882a593Smuzhiyun 	[OV5640_30_FPS] = 30,
158*4882a593Smuzhiyun 	[OV5640_60_FPS] = 60,
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /* regulator supplies */
162*4882a593Smuzhiyun static const char * const ov5640_supply_name[] = {
163*4882a593Smuzhiyun 	"DOVDD", /* Digital I/O (1.8V) supply */
164*4882a593Smuzhiyun 	"AVDD",  /* Analog (2.8V) supply */
165*4882a593Smuzhiyun 	"DVDD",  /* Digital Core (1.5V) supply */
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun #define OV5640_NUM_SUPPLIES ARRAY_SIZE(ov5640_supply_name)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /*
171*4882a593Smuzhiyun  * Image size under 1280 * 960 are SUBSAMPLING
172*4882a593Smuzhiyun  * Image size upper 1280 * 960 are SCALING
173*4882a593Smuzhiyun  */
174*4882a593Smuzhiyun enum ov5640_downsize_mode {
175*4882a593Smuzhiyun 	SUBSAMPLING,
176*4882a593Smuzhiyun 	SCALING,
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun struct reg_value {
180*4882a593Smuzhiyun 	u16 reg_addr;
181*4882a593Smuzhiyun 	u8 val;
182*4882a593Smuzhiyun 	u8 mask;
183*4882a593Smuzhiyun 	u32 delay_ms;
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun struct ov5640_mode_info {
187*4882a593Smuzhiyun 	enum ov5640_mode_id id;
188*4882a593Smuzhiyun 	enum ov5640_downsize_mode dn_mode;
189*4882a593Smuzhiyun 	u32 hact;
190*4882a593Smuzhiyun 	u32 htot;
191*4882a593Smuzhiyun 	u32 vact;
192*4882a593Smuzhiyun 	u32 vtot;
193*4882a593Smuzhiyun 	const struct reg_value *reg_data;
194*4882a593Smuzhiyun 	u32 reg_data_size;
195*4882a593Smuzhiyun 	u32 max_fps;
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun struct ov5640_ctrls {
199*4882a593Smuzhiyun 	struct v4l2_ctrl_handler handler;
200*4882a593Smuzhiyun 	struct v4l2_ctrl *pixel_rate;
201*4882a593Smuzhiyun 	struct {
202*4882a593Smuzhiyun 		struct v4l2_ctrl *auto_exp;
203*4882a593Smuzhiyun 		struct v4l2_ctrl *exposure;
204*4882a593Smuzhiyun 	};
205*4882a593Smuzhiyun 	struct {
206*4882a593Smuzhiyun 		struct v4l2_ctrl *auto_wb;
207*4882a593Smuzhiyun 		struct v4l2_ctrl *blue_balance;
208*4882a593Smuzhiyun 		struct v4l2_ctrl *red_balance;
209*4882a593Smuzhiyun 	};
210*4882a593Smuzhiyun 	struct {
211*4882a593Smuzhiyun 		struct v4l2_ctrl *auto_gain;
212*4882a593Smuzhiyun 		struct v4l2_ctrl *gain;
213*4882a593Smuzhiyun 	};
214*4882a593Smuzhiyun 	struct v4l2_ctrl *brightness;
215*4882a593Smuzhiyun 	struct v4l2_ctrl *light_freq;
216*4882a593Smuzhiyun 	struct v4l2_ctrl *saturation;
217*4882a593Smuzhiyun 	struct v4l2_ctrl *contrast;
218*4882a593Smuzhiyun 	struct v4l2_ctrl *hue;
219*4882a593Smuzhiyun 	struct v4l2_ctrl *test_pattern;
220*4882a593Smuzhiyun 	struct v4l2_ctrl *hflip;
221*4882a593Smuzhiyun 	struct v4l2_ctrl *vflip;
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun struct ov5640_dev {
225*4882a593Smuzhiyun 	struct i2c_client *i2c_client;
226*4882a593Smuzhiyun 	struct v4l2_subdev sd;
227*4882a593Smuzhiyun 	struct media_pad pad;
228*4882a593Smuzhiyun 	struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
229*4882a593Smuzhiyun 	struct clk *xclk; /* system clock to OV5640 */
230*4882a593Smuzhiyun 	u32 xclk_freq;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[OV5640_NUM_SUPPLIES];
233*4882a593Smuzhiyun 	struct gpio_desc *reset_gpio;
234*4882a593Smuzhiyun 	struct gpio_desc *pwdn_gpio;
235*4882a593Smuzhiyun 	bool   upside_down;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	/* lock to protect all members below */
238*4882a593Smuzhiyun 	struct mutex lock;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	int power_count;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt fmt;
243*4882a593Smuzhiyun 	bool pending_fmt_change;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	const struct ov5640_mode_info *current_mode;
246*4882a593Smuzhiyun 	const struct ov5640_mode_info *last_mode;
247*4882a593Smuzhiyun 	enum ov5640_frame_rate current_fr;
248*4882a593Smuzhiyun 	struct v4l2_fract frame_interval;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	struct ov5640_ctrls ctrls;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	u32 prev_sysclk, prev_hts;
253*4882a593Smuzhiyun 	u32 ae_low, ae_high, ae_target;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	bool pending_mode_change;
256*4882a593Smuzhiyun 	bool streaming;
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun 
to_ov5640_dev(struct v4l2_subdev * sd)259*4882a593Smuzhiyun static inline struct ov5640_dev *to_ov5640_dev(struct v4l2_subdev *sd)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun 	return container_of(sd, struct ov5640_dev, sd);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
ctrl_to_sd(struct v4l2_ctrl * ctrl)264*4882a593Smuzhiyun static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun 	return &container_of(ctrl->handler, struct ov5640_dev,
267*4882a593Smuzhiyun 			     ctrls.handler)->sd;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun /*
271*4882a593Smuzhiyun  * FIXME: all of these register tables are likely filled with
272*4882a593Smuzhiyun  * entries that set the register to their power-on default values,
273*4882a593Smuzhiyun  * and which are otherwise not touched by this driver. Those entries
274*4882a593Smuzhiyun  * should be identified and removed to speed register load time
275*4882a593Smuzhiyun  * over i2c.
276*4882a593Smuzhiyun  */
277*4882a593Smuzhiyun /* YUV422 UYVY VGA@30fps */
278*4882a593Smuzhiyun static const struct reg_value ov5640_init_setting_30fps_VGA[] = {
279*4882a593Smuzhiyun 	{0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0},
280*4882a593Smuzhiyun 	{0x3103, 0x03, 0, 0}, {0x3630, 0x36, 0, 0},
281*4882a593Smuzhiyun 	{0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
282*4882a593Smuzhiyun 	{0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
283*4882a593Smuzhiyun 	{0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
284*4882a593Smuzhiyun 	{0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
285*4882a593Smuzhiyun 	{0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
286*4882a593Smuzhiyun 	{0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
287*4882a593Smuzhiyun 	{0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
288*4882a593Smuzhiyun 	{0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
289*4882a593Smuzhiyun 	{0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
290*4882a593Smuzhiyun 	{0x3c01, 0xa4, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
291*4882a593Smuzhiyun 	{0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
292*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
293*4882a593Smuzhiyun 	{0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
294*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
295*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
296*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
297*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
298*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
299*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
300*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
301*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
302*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
303*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
304*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
305*4882a593Smuzhiyun 	{0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
306*4882a593Smuzhiyun 	{0x302e, 0x08, 0, 0}, {0x4300, 0x3f, 0, 0},
307*4882a593Smuzhiyun 	{0x501f, 0x00, 0, 0}, {0x4407, 0x04, 0, 0},
308*4882a593Smuzhiyun 	{0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
309*4882a593Smuzhiyun 	{0x4837, 0x0a, 0, 0}, {0x3824, 0x02, 0, 0},
310*4882a593Smuzhiyun 	{0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0},
311*4882a593Smuzhiyun 	{0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0},
312*4882a593Smuzhiyun 	{0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0},
313*4882a593Smuzhiyun 	{0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0},
314*4882a593Smuzhiyun 	{0x518a, 0x54, 0, 0}, {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0},
315*4882a593Smuzhiyun 	{0x518d, 0x50, 0, 0}, {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0},
316*4882a593Smuzhiyun 	{0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0},
317*4882a593Smuzhiyun 	{0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0},
318*4882a593Smuzhiyun 	{0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0},
319*4882a593Smuzhiyun 	{0x5199, 0x6c, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0},
320*4882a593Smuzhiyun 	{0x519c, 0x09, 0, 0}, {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0},
321*4882a593Smuzhiyun 	{0x5381, 0x1e, 0, 0}, {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0},
322*4882a593Smuzhiyun 	{0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0},
323*4882a593Smuzhiyun 	{0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0},
324*4882a593Smuzhiyun 	{0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0},
325*4882a593Smuzhiyun 	{0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0},
326*4882a593Smuzhiyun 	{0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0},
327*4882a593Smuzhiyun 	{0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0},
328*4882a593Smuzhiyun 	{0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0},
329*4882a593Smuzhiyun 	{0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0},
330*4882a593Smuzhiyun 	{0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0},
331*4882a593Smuzhiyun 	{0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0},
332*4882a593Smuzhiyun 	{0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0},
333*4882a593Smuzhiyun 	{0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0},
334*4882a593Smuzhiyun 	{0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0},
335*4882a593Smuzhiyun 	{0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0},
336*4882a593Smuzhiyun 	{0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0},
337*4882a593Smuzhiyun 	{0x5802, 0x0f, 0, 0}, {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0},
338*4882a593Smuzhiyun 	{0x5805, 0x26, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0},
339*4882a593Smuzhiyun 	{0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0},
340*4882a593Smuzhiyun 	{0x580b, 0x0d, 0, 0}, {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0},
341*4882a593Smuzhiyun 	{0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0},
342*4882a593Smuzhiyun 	{0x5811, 0x09, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0},
343*4882a593Smuzhiyun 	{0x5814, 0x00, 0, 0}, {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0},
344*4882a593Smuzhiyun 	{0x5817, 0x08, 0, 0}, {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0},
345*4882a593Smuzhiyun 	{0x581a, 0x05, 0, 0}, {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0},
346*4882a593Smuzhiyun 	{0x581d, 0x0e, 0, 0}, {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0},
347*4882a593Smuzhiyun 	{0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0},
348*4882a593Smuzhiyun 	{0x5823, 0x28, 0, 0}, {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0},
349*4882a593Smuzhiyun 	{0x5826, 0x08, 0, 0}, {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0},
350*4882a593Smuzhiyun 	{0x5829, 0x26, 0, 0}, {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0},
351*4882a593Smuzhiyun 	{0x582c, 0x24, 0, 0}, {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0},
352*4882a593Smuzhiyun 	{0x582f, 0x22, 0, 0}, {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0},
353*4882a593Smuzhiyun 	{0x5832, 0x24, 0, 0}, {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0},
354*4882a593Smuzhiyun 	{0x5835, 0x22, 0, 0}, {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0},
355*4882a593Smuzhiyun 	{0x5838, 0x44, 0, 0}, {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0},
356*4882a593Smuzhiyun 	{0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0},
357*4882a593Smuzhiyun 	{0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0},
358*4882a593Smuzhiyun 	{0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0},
359*4882a593Smuzhiyun 	{0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300},
360*4882a593Smuzhiyun };
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun static const struct reg_value ov5640_setting_VGA_640_480[] = {
363*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
364*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
365*4882a593Smuzhiyun 	{0x3814, 0x31, 0, 0},
366*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
367*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
368*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
369*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
370*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
371*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
372*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
373*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
374*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
375*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
376*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
377*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
378*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun static const struct reg_value ov5640_setting_XGA_1024_768[] = {
382*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
383*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
384*4882a593Smuzhiyun 	{0x3814, 0x31, 0, 0},
385*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
386*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
387*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
388*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
389*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
390*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
391*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
392*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
393*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
394*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
395*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
396*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
397*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun static const struct reg_value ov5640_setting_QVGA_320_240[] = {
401*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
402*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
403*4882a593Smuzhiyun 	{0x3814, 0x31, 0, 0},
404*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
405*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
406*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
407*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
408*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
409*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
410*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
411*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
412*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
413*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
414*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
415*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
416*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
417*4882a593Smuzhiyun };
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun static const struct reg_value ov5640_setting_QCIF_176_144[] = {
420*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
421*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
422*4882a593Smuzhiyun 	{0x3814, 0x31, 0, 0},
423*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
424*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
425*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
426*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
427*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
428*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
429*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
430*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
431*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
432*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
433*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
434*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
435*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
436*4882a593Smuzhiyun };
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun static const struct reg_value ov5640_setting_NTSC_720_480[] = {
439*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
440*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
441*4882a593Smuzhiyun 	{0x3814, 0x31, 0, 0},
442*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
443*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
444*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
445*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
446*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
447*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
448*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
449*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
450*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
451*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
452*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
453*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
454*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
455*4882a593Smuzhiyun };
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun static const struct reg_value ov5640_setting_PAL_720_576[] = {
458*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
459*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
460*4882a593Smuzhiyun 	{0x3814, 0x31, 0, 0},
461*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
462*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
463*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
464*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
465*4882a593Smuzhiyun 	{0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
466*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
467*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
468*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
469*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
470*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
471*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
472*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
473*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
474*4882a593Smuzhiyun };
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun static const struct reg_value ov5640_setting_720P_1280_720[] = {
477*4882a593Smuzhiyun 	{0x3c07, 0x07, 0, 0},
478*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
479*4882a593Smuzhiyun 	{0x3814, 0x31, 0, 0},
480*4882a593Smuzhiyun 	{0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
481*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
482*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
483*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
484*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
485*4882a593Smuzhiyun 	{0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
486*4882a593Smuzhiyun 	{0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
487*4882a593Smuzhiyun 	{0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
488*4882a593Smuzhiyun 	{0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
489*4882a593Smuzhiyun 	{0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
490*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
491*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
492*4882a593Smuzhiyun 	{0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun static const struct reg_value ov5640_setting_1080P_1920_1080[] = {
496*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
497*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
498*4882a593Smuzhiyun 	{0x3814, 0x11, 0, 0},
499*4882a593Smuzhiyun 	{0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
500*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
501*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
502*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
503*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
504*4882a593Smuzhiyun 	{0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
505*4882a593Smuzhiyun 	{0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
506*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
507*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
508*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
509*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0},
510*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
511*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0},
512*4882a593Smuzhiyun 	{0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
513*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
514*4882a593Smuzhiyun 	{0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
515*4882a593Smuzhiyun 	{0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
516*4882a593Smuzhiyun 	{0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0},
517*4882a593Smuzhiyun 	{0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
518*4882a593Smuzhiyun 	{0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
519*4882a593Smuzhiyun 	{0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
520*4882a593Smuzhiyun 	{0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
521*4882a593Smuzhiyun 	{0x3a15, 0x60, 0, 0}, {0x4407, 0x04, 0, 0},
522*4882a593Smuzhiyun 	{0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
523*4882a593Smuzhiyun 	{0x4005, 0x1a, 0, 0},
524*4882a593Smuzhiyun };
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = {
527*4882a593Smuzhiyun 	{0x3c07, 0x08, 0, 0},
528*4882a593Smuzhiyun 	{0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
529*4882a593Smuzhiyun 	{0x3814, 0x11, 0, 0},
530*4882a593Smuzhiyun 	{0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
531*4882a593Smuzhiyun 	{0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
532*4882a593Smuzhiyun 	{0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
533*4882a593Smuzhiyun 	{0x3810, 0x00, 0, 0},
534*4882a593Smuzhiyun 	{0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
535*4882a593Smuzhiyun 	{0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
536*4882a593Smuzhiyun 	{0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
537*4882a593Smuzhiyun 	{0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
538*4882a593Smuzhiyun 	{0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
539*4882a593Smuzhiyun 	{0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
540*4882a593Smuzhiyun 	{0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0},
541*4882a593Smuzhiyun 	{0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
542*4882a593Smuzhiyun 	{0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70},
543*4882a593Smuzhiyun };
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun /* power-on sensor init reg table */
546*4882a593Smuzhiyun static const struct ov5640_mode_info ov5640_mode_init_data = {
547*4882a593Smuzhiyun 	0, SUBSAMPLING, 640, 1896, 480, 984,
548*4882a593Smuzhiyun 	ov5640_init_setting_30fps_VGA,
549*4882a593Smuzhiyun 	ARRAY_SIZE(ov5640_init_setting_30fps_VGA),
550*4882a593Smuzhiyun 	OV5640_30_FPS,
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun static const struct ov5640_mode_info
554*4882a593Smuzhiyun ov5640_mode_data[OV5640_NUM_MODES] = {
555*4882a593Smuzhiyun 	{OV5640_MODE_QCIF_176_144, SUBSAMPLING,
556*4882a593Smuzhiyun 	 176, 1896, 144, 984,
557*4882a593Smuzhiyun 	 ov5640_setting_QCIF_176_144,
558*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_QCIF_176_144),
559*4882a593Smuzhiyun 	 OV5640_30_FPS},
560*4882a593Smuzhiyun 	{OV5640_MODE_QVGA_320_240, SUBSAMPLING,
561*4882a593Smuzhiyun 	 320, 1896, 240, 984,
562*4882a593Smuzhiyun 	 ov5640_setting_QVGA_320_240,
563*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_QVGA_320_240),
564*4882a593Smuzhiyun 	 OV5640_30_FPS},
565*4882a593Smuzhiyun 	{OV5640_MODE_VGA_640_480, SUBSAMPLING,
566*4882a593Smuzhiyun 	 640, 1896, 480, 1080,
567*4882a593Smuzhiyun 	 ov5640_setting_VGA_640_480,
568*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_VGA_640_480),
569*4882a593Smuzhiyun 	 OV5640_60_FPS},
570*4882a593Smuzhiyun 	{OV5640_MODE_NTSC_720_480, SUBSAMPLING,
571*4882a593Smuzhiyun 	 720, 1896, 480, 984,
572*4882a593Smuzhiyun 	 ov5640_setting_NTSC_720_480,
573*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_NTSC_720_480),
574*4882a593Smuzhiyun 	OV5640_30_FPS},
575*4882a593Smuzhiyun 	{OV5640_MODE_PAL_720_576, SUBSAMPLING,
576*4882a593Smuzhiyun 	 720, 1896, 576, 984,
577*4882a593Smuzhiyun 	 ov5640_setting_PAL_720_576,
578*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_PAL_720_576),
579*4882a593Smuzhiyun 	 OV5640_30_FPS},
580*4882a593Smuzhiyun 	{OV5640_MODE_XGA_1024_768, SUBSAMPLING,
581*4882a593Smuzhiyun 	 1024, 1896, 768, 1080,
582*4882a593Smuzhiyun 	 ov5640_setting_XGA_1024_768,
583*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_XGA_1024_768),
584*4882a593Smuzhiyun 	 OV5640_30_FPS},
585*4882a593Smuzhiyun 	{OV5640_MODE_720P_1280_720, SUBSAMPLING,
586*4882a593Smuzhiyun 	 1280, 1892, 720, 740,
587*4882a593Smuzhiyun 	 ov5640_setting_720P_1280_720,
588*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_720P_1280_720),
589*4882a593Smuzhiyun 	 OV5640_30_FPS},
590*4882a593Smuzhiyun 	{OV5640_MODE_1080P_1920_1080, SCALING,
591*4882a593Smuzhiyun 	 1920, 2500, 1080, 1120,
592*4882a593Smuzhiyun 	 ov5640_setting_1080P_1920_1080,
593*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_1080P_1920_1080),
594*4882a593Smuzhiyun 	 OV5640_30_FPS},
595*4882a593Smuzhiyun 	{OV5640_MODE_QSXGA_2592_1944, SCALING,
596*4882a593Smuzhiyun 	 2592, 2844, 1944, 1968,
597*4882a593Smuzhiyun 	 ov5640_setting_QSXGA_2592_1944,
598*4882a593Smuzhiyun 	 ARRAY_SIZE(ov5640_setting_QSXGA_2592_1944),
599*4882a593Smuzhiyun 	 OV5640_15_FPS},
600*4882a593Smuzhiyun };
601*4882a593Smuzhiyun 
ov5640_init_slave_id(struct ov5640_dev * sensor)602*4882a593Smuzhiyun static int ov5640_init_slave_id(struct ov5640_dev *sensor)
603*4882a593Smuzhiyun {
604*4882a593Smuzhiyun 	struct i2c_client *client = sensor->i2c_client;
605*4882a593Smuzhiyun 	struct i2c_msg msg;
606*4882a593Smuzhiyun 	u8 buf[3];
607*4882a593Smuzhiyun 	int ret;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	if (client->addr == OV5640_DEFAULT_SLAVE_ID)
610*4882a593Smuzhiyun 		return 0;
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	buf[0] = OV5640_REG_SLAVE_ID >> 8;
613*4882a593Smuzhiyun 	buf[1] = OV5640_REG_SLAVE_ID & 0xff;
614*4882a593Smuzhiyun 	buf[2] = client->addr << 1;
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun 	msg.addr = OV5640_DEFAULT_SLAVE_ID;
617*4882a593Smuzhiyun 	msg.flags = 0;
618*4882a593Smuzhiyun 	msg.buf = buf;
619*4882a593Smuzhiyun 	msg.len = sizeof(buf);
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, &msg, 1);
622*4882a593Smuzhiyun 	if (ret < 0) {
623*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: failed with %d\n", __func__, ret);
624*4882a593Smuzhiyun 		return ret;
625*4882a593Smuzhiyun 	}
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	return 0;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun 
ov5640_write_reg(struct ov5640_dev * sensor,u16 reg,u8 val)630*4882a593Smuzhiyun static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun 	struct i2c_client *client = sensor->i2c_client;
633*4882a593Smuzhiyun 	struct i2c_msg msg;
634*4882a593Smuzhiyun 	u8 buf[3];
635*4882a593Smuzhiyun 	int ret;
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	buf[0] = reg >> 8;
638*4882a593Smuzhiyun 	buf[1] = reg & 0xff;
639*4882a593Smuzhiyun 	buf[2] = val;
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	msg.addr = client->addr;
642*4882a593Smuzhiyun 	msg.flags = client->flags;
643*4882a593Smuzhiyun 	msg.buf = buf;
644*4882a593Smuzhiyun 	msg.len = sizeof(buf);
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, &msg, 1);
647*4882a593Smuzhiyun 	if (ret < 0) {
648*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: error: reg=%x, val=%x\n",
649*4882a593Smuzhiyun 			__func__, reg, val);
650*4882a593Smuzhiyun 		return ret;
651*4882a593Smuzhiyun 	}
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun 	return 0;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun 
ov5640_read_reg(struct ov5640_dev * sensor,u16 reg,u8 * val)656*4882a593Smuzhiyun static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun 	struct i2c_client *client = sensor->i2c_client;
659*4882a593Smuzhiyun 	struct i2c_msg msg[2];
660*4882a593Smuzhiyun 	u8 buf[2];
661*4882a593Smuzhiyun 	int ret;
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun 	buf[0] = reg >> 8;
664*4882a593Smuzhiyun 	buf[1] = reg & 0xff;
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	msg[0].addr = client->addr;
667*4882a593Smuzhiyun 	msg[0].flags = client->flags;
668*4882a593Smuzhiyun 	msg[0].buf = buf;
669*4882a593Smuzhiyun 	msg[0].len = sizeof(buf);
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	msg[1].addr = client->addr;
672*4882a593Smuzhiyun 	msg[1].flags = client->flags | I2C_M_RD;
673*4882a593Smuzhiyun 	msg[1].buf = buf;
674*4882a593Smuzhiyun 	msg[1].len = 1;
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	ret = i2c_transfer(client->adapter, msg, 2);
677*4882a593Smuzhiyun 	if (ret < 0) {
678*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: error: reg=%x\n",
679*4882a593Smuzhiyun 			__func__, reg);
680*4882a593Smuzhiyun 		return ret;
681*4882a593Smuzhiyun 	}
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	*val = buf[0];
684*4882a593Smuzhiyun 	return 0;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun 
ov5640_read_reg16(struct ov5640_dev * sensor,u16 reg,u16 * val)687*4882a593Smuzhiyun static int ov5640_read_reg16(struct ov5640_dev *sensor, u16 reg, u16 *val)
688*4882a593Smuzhiyun {
689*4882a593Smuzhiyun 	u8 hi, lo;
690*4882a593Smuzhiyun 	int ret;
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, reg, &hi);
693*4882a593Smuzhiyun 	if (ret)
694*4882a593Smuzhiyun 		return ret;
695*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, reg + 1, &lo);
696*4882a593Smuzhiyun 	if (ret)
697*4882a593Smuzhiyun 		return ret;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	*val = ((u16)hi << 8) | (u16)lo;
700*4882a593Smuzhiyun 	return 0;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun 
ov5640_write_reg16(struct ov5640_dev * sensor,u16 reg,u16 val)703*4882a593Smuzhiyun static int ov5640_write_reg16(struct ov5640_dev *sensor, u16 reg, u16 val)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun 	int ret;
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, reg, val >> 8);
708*4882a593Smuzhiyun 	if (ret)
709*4882a593Smuzhiyun 		return ret;
710*4882a593Smuzhiyun 
711*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, reg + 1, val & 0xff);
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun 
ov5640_mod_reg(struct ov5640_dev * sensor,u16 reg,u8 mask,u8 val)714*4882a593Smuzhiyun static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg,
715*4882a593Smuzhiyun 			  u8 mask, u8 val)
716*4882a593Smuzhiyun {
717*4882a593Smuzhiyun 	u8 readval;
718*4882a593Smuzhiyun 	int ret;
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, reg, &readval);
721*4882a593Smuzhiyun 	if (ret)
722*4882a593Smuzhiyun 		return ret;
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	readval &= ~mask;
725*4882a593Smuzhiyun 	val &= mask;
726*4882a593Smuzhiyun 	val |= readval;
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, reg, val);
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun /*
732*4882a593Smuzhiyun  * After trying the various combinations, reading various
733*4882a593Smuzhiyun  * documentations spread around the net, and from the various
734*4882a593Smuzhiyun  * feedback, the clock tree is probably as follows:
735*4882a593Smuzhiyun  *
736*4882a593Smuzhiyun  *   +--------------+
737*4882a593Smuzhiyun  *   |  Ext. Clock  |
738*4882a593Smuzhiyun  *   +-+------------+
739*4882a593Smuzhiyun  *     |  +----------+
740*4882a593Smuzhiyun  *     +->|   PLL1   | - reg 0x3036, for the multiplier
741*4882a593Smuzhiyun  *        +-+--------+ - reg 0x3037, bits 0-3 for the pre-divider
742*4882a593Smuzhiyun  *          |  +--------------+
743*4882a593Smuzhiyun  *          +->| System Clock |  - reg 0x3035, bits 4-7
744*4882a593Smuzhiyun  *             +-+------------+
745*4882a593Smuzhiyun  *               |  +--------------+
746*4882a593Smuzhiyun  *               +->| MIPI Divider | - reg 0x3035, bits 0-3
747*4882a593Smuzhiyun  *               |  +-+------------+
748*4882a593Smuzhiyun  *               |    +----------------> MIPI SCLK
749*4882a593Smuzhiyun  *               |    +  +-----+
750*4882a593Smuzhiyun  *               |    +->| / 2 |-------> MIPI BIT CLK
751*4882a593Smuzhiyun  *               |       +-----+
752*4882a593Smuzhiyun  *               |  +--------------+
753*4882a593Smuzhiyun  *               +->| PLL Root Div | - reg 0x3037, bit 4
754*4882a593Smuzhiyun  *                  +-+------------+
755*4882a593Smuzhiyun  *                    |  +---------+
756*4882a593Smuzhiyun  *                    +->| Bit Div | - reg 0x3034, bits 0-3
757*4882a593Smuzhiyun  *                       +-+-------+
758*4882a593Smuzhiyun  *                         |  +-------------+
759*4882a593Smuzhiyun  *                         +->| SCLK Div    | - reg 0x3108, bits 0-1
760*4882a593Smuzhiyun  *                         |  +-+-----------+
761*4882a593Smuzhiyun  *                         |    +---------------> SCLK
762*4882a593Smuzhiyun  *                         |  +-------------+
763*4882a593Smuzhiyun  *                         +->| SCLK 2X Div | - reg 0x3108, bits 2-3
764*4882a593Smuzhiyun  *                         |  +-+-----------+
765*4882a593Smuzhiyun  *                         |    +---------------> SCLK 2X
766*4882a593Smuzhiyun  *                         |  +-------------+
767*4882a593Smuzhiyun  *                         +->| PCLK Div    | - reg 0x3108, bits 4-5
768*4882a593Smuzhiyun  *                            ++------------+
769*4882a593Smuzhiyun  *                             +  +-----------+
770*4882a593Smuzhiyun  *                             +->|   P_DIV   | - reg 0x3035, bits 0-3
771*4882a593Smuzhiyun  *                                +-----+-----+
772*4882a593Smuzhiyun  *                                       +------------> PCLK
773*4882a593Smuzhiyun  *
774*4882a593Smuzhiyun  * This is deviating from the datasheet at least for the register
775*4882a593Smuzhiyun  * 0x3108, since it's said here that the PCLK would be clocked from
776*4882a593Smuzhiyun  * the PLL.
777*4882a593Smuzhiyun  *
778*4882a593Smuzhiyun  * There seems to be also (unverified) constraints:
779*4882a593Smuzhiyun  *  - the PLL pre-divider output rate should be in the 4-27MHz range
780*4882a593Smuzhiyun  *  - the PLL multiplier output rate should be in the 500-1000MHz range
781*4882a593Smuzhiyun  *  - PCLK >= SCLK * 2 in YUV, >= SCLK in Raw or JPEG
782*4882a593Smuzhiyun  *
783*4882a593Smuzhiyun  * In the two latter cases, these constraints are met since our
784*4882a593Smuzhiyun  * factors are hardcoded. If we were to change that, we would need to
785*4882a593Smuzhiyun  * take this into account. The only varying parts are the PLL
786*4882a593Smuzhiyun  * multiplier and the system clock divider, which are shared between
787*4882a593Smuzhiyun  * all these clocks so won't cause any issue.
788*4882a593Smuzhiyun  */
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun /*
791*4882a593Smuzhiyun  * This is supposed to be ranging from 1 to 8, but the value is always
792*4882a593Smuzhiyun  * set to 3 in the vendor kernels.
793*4882a593Smuzhiyun  */
794*4882a593Smuzhiyun #define OV5640_PLL_PREDIV	3
795*4882a593Smuzhiyun 
796*4882a593Smuzhiyun #define OV5640_PLL_MULT_MIN	4
797*4882a593Smuzhiyun #define OV5640_PLL_MULT_MAX	252
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun /*
800*4882a593Smuzhiyun  * This is supposed to be ranging from 1 to 16, but the value is
801*4882a593Smuzhiyun  * always set to either 1 or 2 in the vendor kernels.
802*4882a593Smuzhiyun  */
803*4882a593Smuzhiyun #define OV5640_SYSDIV_MIN	1
804*4882a593Smuzhiyun #define OV5640_SYSDIV_MAX	16
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun /*
807*4882a593Smuzhiyun  * Hardcode these values for scaler and non-scaler modes.
808*4882a593Smuzhiyun  * FIXME: to be re-calcualted for 1 data lanes setups
809*4882a593Smuzhiyun  */
810*4882a593Smuzhiyun #define OV5640_MIPI_DIV_PCLK	2
811*4882a593Smuzhiyun #define OV5640_MIPI_DIV_SCLK	1
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun /*
814*4882a593Smuzhiyun  * This is supposed to be ranging from 1 to 2, but the value is always
815*4882a593Smuzhiyun  * set to 2 in the vendor kernels.
816*4882a593Smuzhiyun  */
817*4882a593Smuzhiyun #define OV5640_PLL_ROOT_DIV			2
818*4882a593Smuzhiyun #define OV5640_PLL_CTRL3_PLL_ROOT_DIV_2		BIT(4)
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun /*
821*4882a593Smuzhiyun  * We only supports 8-bit formats at the moment
822*4882a593Smuzhiyun  */
823*4882a593Smuzhiyun #define OV5640_BIT_DIV				2
824*4882a593Smuzhiyun #define OV5640_PLL_CTRL0_MIPI_MODE_8BIT		0x08
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun /*
827*4882a593Smuzhiyun  * This is supposed to be ranging from 1 to 8, but the value is always
828*4882a593Smuzhiyun  * set to 2 in the vendor kernels.
829*4882a593Smuzhiyun  */
830*4882a593Smuzhiyun #define OV5640_SCLK_ROOT_DIV	2
831*4882a593Smuzhiyun 
832*4882a593Smuzhiyun /*
833*4882a593Smuzhiyun  * This is hardcoded so that the consistency is maintained between SCLK and
834*4882a593Smuzhiyun  * SCLK 2x.
835*4882a593Smuzhiyun  */
836*4882a593Smuzhiyun #define OV5640_SCLK2X_ROOT_DIV (OV5640_SCLK_ROOT_DIV / 2)
837*4882a593Smuzhiyun 
838*4882a593Smuzhiyun /*
839*4882a593Smuzhiyun  * This is supposed to be ranging from 1 to 8, but the value is always
840*4882a593Smuzhiyun  * set to 1 in the vendor kernels.
841*4882a593Smuzhiyun  */
842*4882a593Smuzhiyun #define OV5640_PCLK_ROOT_DIV			1
843*4882a593Smuzhiyun #define OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS	0x00
844*4882a593Smuzhiyun 
ov5640_compute_sys_clk(struct ov5640_dev * sensor,u8 pll_prediv,u8 pll_mult,u8 sysdiv)845*4882a593Smuzhiyun static unsigned long ov5640_compute_sys_clk(struct ov5640_dev *sensor,
846*4882a593Smuzhiyun 					    u8 pll_prediv, u8 pll_mult,
847*4882a593Smuzhiyun 					    u8 sysdiv)
848*4882a593Smuzhiyun {
849*4882a593Smuzhiyun 	unsigned long sysclk = sensor->xclk_freq / pll_prediv * pll_mult;
850*4882a593Smuzhiyun 
851*4882a593Smuzhiyun 	/* PLL1 output cannot exceed 1GHz. */
852*4882a593Smuzhiyun 	if (sysclk / 1000000 > 1000)
853*4882a593Smuzhiyun 		return 0;
854*4882a593Smuzhiyun 
855*4882a593Smuzhiyun 	return sysclk / sysdiv;
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun 
ov5640_calc_sys_clk(struct ov5640_dev * sensor,unsigned long rate,u8 * pll_prediv,u8 * pll_mult,u8 * sysdiv)858*4882a593Smuzhiyun static unsigned long ov5640_calc_sys_clk(struct ov5640_dev *sensor,
859*4882a593Smuzhiyun 					 unsigned long rate,
860*4882a593Smuzhiyun 					 u8 *pll_prediv, u8 *pll_mult,
861*4882a593Smuzhiyun 					 u8 *sysdiv)
862*4882a593Smuzhiyun {
863*4882a593Smuzhiyun 	unsigned long best = ~0;
864*4882a593Smuzhiyun 	u8 best_sysdiv = 1, best_mult = 1;
865*4882a593Smuzhiyun 	u8 _sysdiv, _pll_mult;
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	for (_sysdiv = OV5640_SYSDIV_MIN;
868*4882a593Smuzhiyun 	     _sysdiv <= OV5640_SYSDIV_MAX;
869*4882a593Smuzhiyun 	     _sysdiv++) {
870*4882a593Smuzhiyun 		for (_pll_mult = OV5640_PLL_MULT_MIN;
871*4882a593Smuzhiyun 		     _pll_mult <= OV5640_PLL_MULT_MAX;
872*4882a593Smuzhiyun 		     _pll_mult++) {
873*4882a593Smuzhiyun 			unsigned long _rate;
874*4882a593Smuzhiyun 
875*4882a593Smuzhiyun 			/*
876*4882a593Smuzhiyun 			 * The PLL multiplier cannot be odd if above
877*4882a593Smuzhiyun 			 * 127.
878*4882a593Smuzhiyun 			 */
879*4882a593Smuzhiyun 			if (_pll_mult > 127 && (_pll_mult % 2))
880*4882a593Smuzhiyun 				continue;
881*4882a593Smuzhiyun 
882*4882a593Smuzhiyun 			_rate = ov5640_compute_sys_clk(sensor,
883*4882a593Smuzhiyun 						       OV5640_PLL_PREDIV,
884*4882a593Smuzhiyun 						       _pll_mult, _sysdiv);
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun 			/*
887*4882a593Smuzhiyun 			 * We have reached the maximum allowed PLL1 output,
888*4882a593Smuzhiyun 			 * increase sysdiv.
889*4882a593Smuzhiyun 			 */
890*4882a593Smuzhiyun 			if (!_rate)
891*4882a593Smuzhiyun 				break;
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 			/*
894*4882a593Smuzhiyun 			 * Prefer rates above the expected clock rate than
895*4882a593Smuzhiyun 			 * below, even if that means being less precise.
896*4882a593Smuzhiyun 			 */
897*4882a593Smuzhiyun 			if (_rate < rate)
898*4882a593Smuzhiyun 				continue;
899*4882a593Smuzhiyun 
900*4882a593Smuzhiyun 			if (abs(rate - _rate) < abs(rate - best)) {
901*4882a593Smuzhiyun 				best = _rate;
902*4882a593Smuzhiyun 				best_sysdiv = _sysdiv;
903*4882a593Smuzhiyun 				best_mult = _pll_mult;
904*4882a593Smuzhiyun 			}
905*4882a593Smuzhiyun 
906*4882a593Smuzhiyun 			if (_rate == rate)
907*4882a593Smuzhiyun 				goto out;
908*4882a593Smuzhiyun 		}
909*4882a593Smuzhiyun 	}
910*4882a593Smuzhiyun 
911*4882a593Smuzhiyun out:
912*4882a593Smuzhiyun 	*sysdiv = best_sysdiv;
913*4882a593Smuzhiyun 	*pll_prediv = OV5640_PLL_PREDIV;
914*4882a593Smuzhiyun 	*pll_mult = best_mult;
915*4882a593Smuzhiyun 
916*4882a593Smuzhiyun 	return best;
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun 
919*4882a593Smuzhiyun /*
920*4882a593Smuzhiyun  * ov5640_set_mipi_pclk() - Calculate the clock tree configuration values
921*4882a593Smuzhiyun  *			    for the MIPI CSI-2 output.
922*4882a593Smuzhiyun  *
923*4882a593Smuzhiyun  * @rate: The requested bandwidth per lane in bytes per second.
924*4882a593Smuzhiyun  *	  'Bandwidth Per Lane' is calculated as:
925*4882a593Smuzhiyun  *	  bpl = HTOT * VTOT * FPS * bpp / num_lanes;
926*4882a593Smuzhiyun  *
927*4882a593Smuzhiyun  * This function use the requested bandwidth to calculate:
928*4882a593Smuzhiyun  * - sample_rate = bpl / (bpp / num_lanes);
929*4882a593Smuzhiyun  *	         = bpl / (PLL_RDIV * BIT_DIV * PCLK_DIV * MIPI_DIV / num_lanes);
930*4882a593Smuzhiyun  *
931*4882a593Smuzhiyun  * - mipi_sclk   = bpl / MIPI_DIV / 2; ( / 2 is for CSI-2 DDR)
932*4882a593Smuzhiyun  *
933*4882a593Smuzhiyun  * with these fixed parameters:
934*4882a593Smuzhiyun  *	PLL_RDIV	= 2;
935*4882a593Smuzhiyun  *	BIT_DIVIDER	= 2; (MIPI_BIT_MODE == 8 ? 2 : 2,5);
936*4882a593Smuzhiyun  *	PCLK_DIV	= 1;
937*4882a593Smuzhiyun  *
938*4882a593Smuzhiyun  * The MIPI clock generation differs for modes that use the scaler and modes
939*4882a593Smuzhiyun  * that do not. In case the scaler is in use, the MIPI_SCLK generates the MIPI
940*4882a593Smuzhiyun  * BIT CLk, and thus:
941*4882a593Smuzhiyun  *
942*4882a593Smuzhiyun  * - mipi_sclk = bpl / MIPI_DIV / 2;
943*4882a593Smuzhiyun  *   MIPI_DIV = 1;
944*4882a593Smuzhiyun  *
945*4882a593Smuzhiyun  * For modes that do not go through the scaler, the MIPI BIT CLOCK is generated
946*4882a593Smuzhiyun  * from the pixel clock, and thus:
947*4882a593Smuzhiyun  *
948*4882a593Smuzhiyun  * - sample_rate = bpl / (bpp / num_lanes);
949*4882a593Smuzhiyun  *	         = bpl / (2 * 2 * 1 * MIPI_DIV / num_lanes);
950*4882a593Smuzhiyun  *		 = bpl / (4 * MIPI_DIV / num_lanes);
951*4882a593Smuzhiyun  * - MIPI_DIV	 = bpp / (4 * num_lanes);
952*4882a593Smuzhiyun  *
953*4882a593Smuzhiyun  * FIXME: this have been tested with 16bpp and 2 lanes setup only.
954*4882a593Smuzhiyun  * MIPI_DIV is fixed to value 2, but it -might- be changed according to the
955*4882a593Smuzhiyun  * above formula for setups with 1 lane or image formats with different bpp.
956*4882a593Smuzhiyun  *
957*4882a593Smuzhiyun  * FIXME: this deviates from the sensor manual documentation which is quite
958*4882a593Smuzhiyun  * thin on the MIPI clock tree generation part.
959*4882a593Smuzhiyun  */
ov5640_set_mipi_pclk(struct ov5640_dev * sensor,unsigned long rate)960*4882a593Smuzhiyun static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor,
961*4882a593Smuzhiyun 				unsigned long rate)
962*4882a593Smuzhiyun {
963*4882a593Smuzhiyun 	const struct ov5640_mode_info *mode = sensor->current_mode;
964*4882a593Smuzhiyun 	u8 prediv, mult, sysdiv;
965*4882a593Smuzhiyun 	u8 mipi_div;
966*4882a593Smuzhiyun 	int ret;
967*4882a593Smuzhiyun 
968*4882a593Smuzhiyun 	/*
969*4882a593Smuzhiyun 	 * 1280x720 is reported to use 'SUBSAMPLING' only,
970*4882a593Smuzhiyun 	 * but according to the sensor manual it goes through the
971*4882a593Smuzhiyun 	 * scaler before subsampling.
972*4882a593Smuzhiyun 	 */
973*4882a593Smuzhiyun 	if (mode->dn_mode == SCALING ||
974*4882a593Smuzhiyun 	   (mode->id == OV5640_MODE_720P_1280_720))
975*4882a593Smuzhiyun 		mipi_div = OV5640_MIPI_DIV_SCLK;
976*4882a593Smuzhiyun 	else
977*4882a593Smuzhiyun 		mipi_div = OV5640_MIPI_DIV_PCLK;
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun 	ov5640_calc_sys_clk(sensor, rate, &prediv, &mult, &sysdiv);
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
982*4882a593Smuzhiyun 			     0x0f, OV5640_PLL_CTRL0_MIPI_MODE_8BIT);
983*4882a593Smuzhiyun 
984*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
985*4882a593Smuzhiyun 			     0xff, sysdiv << 4 | mipi_div);
986*4882a593Smuzhiyun 	if (ret)
987*4882a593Smuzhiyun 		return ret;
988*4882a593Smuzhiyun 
989*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2, 0xff, mult);
990*4882a593Smuzhiyun 	if (ret)
991*4882a593Smuzhiyun 		return ret;
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
994*4882a593Smuzhiyun 			     0x1f, OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 | prediv);
995*4882a593Smuzhiyun 	if (ret)
996*4882a593Smuzhiyun 		return ret;
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER,
999*4882a593Smuzhiyun 			      0x30, OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS);
1000*4882a593Smuzhiyun }
1001*4882a593Smuzhiyun 
ov5640_calc_pclk(struct ov5640_dev * sensor,unsigned long rate,u8 * pll_prediv,u8 * pll_mult,u8 * sysdiv,u8 * pll_rdiv,u8 * bit_div,u8 * pclk_div)1002*4882a593Smuzhiyun static unsigned long ov5640_calc_pclk(struct ov5640_dev *sensor,
1003*4882a593Smuzhiyun 				      unsigned long rate,
1004*4882a593Smuzhiyun 				      u8 *pll_prediv, u8 *pll_mult, u8 *sysdiv,
1005*4882a593Smuzhiyun 				      u8 *pll_rdiv, u8 *bit_div, u8 *pclk_div)
1006*4882a593Smuzhiyun {
1007*4882a593Smuzhiyun 	unsigned long _rate = rate * OV5640_PLL_ROOT_DIV * OV5640_BIT_DIV *
1008*4882a593Smuzhiyun 				OV5640_PCLK_ROOT_DIV;
1009*4882a593Smuzhiyun 
1010*4882a593Smuzhiyun 	_rate = ov5640_calc_sys_clk(sensor, _rate, pll_prediv, pll_mult,
1011*4882a593Smuzhiyun 				    sysdiv);
1012*4882a593Smuzhiyun 	*pll_rdiv = OV5640_PLL_ROOT_DIV;
1013*4882a593Smuzhiyun 	*bit_div = OV5640_BIT_DIV;
1014*4882a593Smuzhiyun 	*pclk_div = OV5640_PCLK_ROOT_DIV;
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	return _rate / *pll_rdiv / *bit_div / *pclk_div;
1017*4882a593Smuzhiyun }
1018*4882a593Smuzhiyun 
ov5640_set_dvp_pclk(struct ov5640_dev * sensor,unsigned long rate)1019*4882a593Smuzhiyun static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, unsigned long rate)
1020*4882a593Smuzhiyun {
1021*4882a593Smuzhiyun 	u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div;
1022*4882a593Smuzhiyun 	int ret;
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv,
1025*4882a593Smuzhiyun 			 &bit_div, &pclk_div);
1026*4882a593Smuzhiyun 
1027*4882a593Smuzhiyun 	if (bit_div == 2)
1028*4882a593Smuzhiyun 		bit_div = 8;
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
1031*4882a593Smuzhiyun 			     0x0f, bit_div);
1032*4882a593Smuzhiyun 	if (ret)
1033*4882a593Smuzhiyun 		return ret;
1034*4882a593Smuzhiyun 
1035*4882a593Smuzhiyun 	/*
1036*4882a593Smuzhiyun 	 * We need to set sysdiv according to the clock, and to clear
1037*4882a593Smuzhiyun 	 * the MIPI divider.
1038*4882a593Smuzhiyun 	 */
1039*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
1040*4882a593Smuzhiyun 			     0xff, sysdiv << 4);
1041*4882a593Smuzhiyun 	if (ret)
1042*4882a593Smuzhiyun 		return ret;
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2,
1045*4882a593Smuzhiyun 			     0xff, mult);
1046*4882a593Smuzhiyun 	if (ret)
1047*4882a593Smuzhiyun 		return ret;
1048*4882a593Smuzhiyun 
1049*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
1050*4882a593Smuzhiyun 			     0x1f, prediv | ((pll_rdiv - 1) << 4));
1051*4882a593Smuzhiyun 	if (ret)
1052*4882a593Smuzhiyun 		return ret;
1053*4882a593Smuzhiyun 
1054*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x30,
1055*4882a593Smuzhiyun 			      (ilog2(pclk_div) << 4));
1056*4882a593Smuzhiyun }
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun /* set JPEG framing sizes */
ov5640_set_jpeg_timings(struct ov5640_dev * sensor,const struct ov5640_mode_info * mode)1059*4882a593Smuzhiyun static int ov5640_set_jpeg_timings(struct ov5640_dev *sensor,
1060*4882a593Smuzhiyun 				   const struct ov5640_mode_info *mode)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun 	int ret;
1063*4882a593Smuzhiyun 
1064*4882a593Smuzhiyun 	/*
1065*4882a593Smuzhiyun 	 * compression mode 3 timing
1066*4882a593Smuzhiyun 	 *
1067*4882a593Smuzhiyun 	 * Data is transmitted with programmable width (VFIFO_HSIZE).
1068*4882a593Smuzhiyun 	 * No padding done. Last line may have less data. Varying
1069*4882a593Smuzhiyun 	 * number of lines per frame, depending on amount of data.
1070*4882a593Smuzhiyun 	 */
1071*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_JPG_MODE_SELECT, 0x7, 0x3);
1072*4882a593Smuzhiyun 	if (ret < 0)
1073*4882a593Smuzhiyun 		return ret;
1074*4882a593Smuzhiyun 
1075*4882a593Smuzhiyun 	ret = ov5640_write_reg16(sensor, OV5640_REG_VFIFO_HSIZE, mode->hact);
1076*4882a593Smuzhiyun 	if (ret < 0)
1077*4882a593Smuzhiyun 		return ret;
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	return ov5640_write_reg16(sensor, OV5640_REG_VFIFO_VSIZE, mode->vact);
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun 
1082*4882a593Smuzhiyun /* download ov5640 settings to sensor through i2c */
ov5640_set_timings(struct ov5640_dev * sensor,const struct ov5640_mode_info * mode)1083*4882a593Smuzhiyun static int ov5640_set_timings(struct ov5640_dev *sensor,
1084*4882a593Smuzhiyun 			      const struct ov5640_mode_info *mode)
1085*4882a593Smuzhiyun {
1086*4882a593Smuzhiyun 	int ret;
1087*4882a593Smuzhiyun 
1088*4882a593Smuzhiyun 	if (sensor->fmt.code == MEDIA_BUS_FMT_JPEG_1X8) {
1089*4882a593Smuzhiyun 		ret = ov5640_set_jpeg_timings(sensor, mode);
1090*4882a593Smuzhiyun 		if (ret < 0)
1091*4882a593Smuzhiyun 			return ret;
1092*4882a593Smuzhiyun 	}
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun 	ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_DVPHO, mode->hact);
1095*4882a593Smuzhiyun 	if (ret < 0)
1096*4882a593Smuzhiyun 		return ret;
1097*4882a593Smuzhiyun 
1098*4882a593Smuzhiyun 	ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_DVPVO, mode->vact);
1099*4882a593Smuzhiyun 	if (ret < 0)
1100*4882a593Smuzhiyun 		return ret;
1101*4882a593Smuzhiyun 
1102*4882a593Smuzhiyun 	ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_HTS, mode->htot);
1103*4882a593Smuzhiyun 	if (ret < 0)
1104*4882a593Smuzhiyun 		return ret;
1105*4882a593Smuzhiyun 
1106*4882a593Smuzhiyun 	return ov5640_write_reg16(sensor, OV5640_REG_TIMING_VTS, mode->vtot);
1107*4882a593Smuzhiyun }
1108*4882a593Smuzhiyun 
ov5640_load_regs(struct ov5640_dev * sensor,const struct ov5640_mode_info * mode)1109*4882a593Smuzhiyun static int ov5640_load_regs(struct ov5640_dev *sensor,
1110*4882a593Smuzhiyun 			    const struct ov5640_mode_info *mode)
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun 	const struct reg_value *regs = mode->reg_data;
1113*4882a593Smuzhiyun 	unsigned int i;
1114*4882a593Smuzhiyun 	u32 delay_ms;
1115*4882a593Smuzhiyun 	u16 reg_addr;
1116*4882a593Smuzhiyun 	u8 mask, val;
1117*4882a593Smuzhiyun 	int ret = 0;
1118*4882a593Smuzhiyun 
1119*4882a593Smuzhiyun 	for (i = 0; i < mode->reg_data_size; ++i, ++regs) {
1120*4882a593Smuzhiyun 		delay_ms = regs->delay_ms;
1121*4882a593Smuzhiyun 		reg_addr = regs->reg_addr;
1122*4882a593Smuzhiyun 		val = regs->val;
1123*4882a593Smuzhiyun 		mask = regs->mask;
1124*4882a593Smuzhiyun 
1125*4882a593Smuzhiyun 		/* remain in power down mode for DVP */
1126*4882a593Smuzhiyun 		if (regs->reg_addr == OV5640_REG_SYS_CTRL0 &&
1127*4882a593Smuzhiyun 		    val == OV5640_REG_SYS_CTRL0_SW_PWUP &&
1128*4882a593Smuzhiyun 		    sensor->ep.bus_type != V4L2_MBUS_CSI2_DPHY)
1129*4882a593Smuzhiyun 			continue;
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun 		if (mask)
1132*4882a593Smuzhiyun 			ret = ov5640_mod_reg(sensor, reg_addr, mask, val);
1133*4882a593Smuzhiyun 		else
1134*4882a593Smuzhiyun 			ret = ov5640_write_reg(sensor, reg_addr, val);
1135*4882a593Smuzhiyun 		if (ret)
1136*4882a593Smuzhiyun 			break;
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 		if (delay_ms)
1139*4882a593Smuzhiyun 			usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
1140*4882a593Smuzhiyun 	}
1141*4882a593Smuzhiyun 
1142*4882a593Smuzhiyun 	return ov5640_set_timings(sensor, mode);
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun 
ov5640_set_autoexposure(struct ov5640_dev * sensor,bool on)1145*4882a593Smuzhiyun static int ov5640_set_autoexposure(struct ov5640_dev *sensor, bool on)
1146*4882a593Smuzhiyun {
1147*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_AEC_PK_MANUAL,
1148*4882a593Smuzhiyun 			      BIT(0), on ? 0 : BIT(0));
1149*4882a593Smuzhiyun }
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun /* read exposure, in number of line periods */
ov5640_get_exposure(struct ov5640_dev * sensor)1152*4882a593Smuzhiyun static int ov5640_get_exposure(struct ov5640_dev *sensor)
1153*4882a593Smuzhiyun {
1154*4882a593Smuzhiyun 	int exp, ret;
1155*4882a593Smuzhiyun 	u8 temp;
1156*4882a593Smuzhiyun 
1157*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_HI, &temp);
1158*4882a593Smuzhiyun 	if (ret)
1159*4882a593Smuzhiyun 		return ret;
1160*4882a593Smuzhiyun 	exp = ((int)temp & 0x0f) << 16;
1161*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_MED, &temp);
1162*4882a593Smuzhiyun 	if (ret)
1163*4882a593Smuzhiyun 		return ret;
1164*4882a593Smuzhiyun 	exp |= ((int)temp << 8);
1165*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_LO, &temp);
1166*4882a593Smuzhiyun 	if (ret)
1167*4882a593Smuzhiyun 		return ret;
1168*4882a593Smuzhiyun 	exp |= (int)temp;
1169*4882a593Smuzhiyun 
1170*4882a593Smuzhiyun 	return exp >> 4;
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun 
1173*4882a593Smuzhiyun /* write exposure, given number of line periods */
ov5640_set_exposure(struct ov5640_dev * sensor,u32 exposure)1174*4882a593Smuzhiyun static int ov5640_set_exposure(struct ov5640_dev *sensor, u32 exposure)
1175*4882a593Smuzhiyun {
1176*4882a593Smuzhiyun 	int ret;
1177*4882a593Smuzhiyun 
1178*4882a593Smuzhiyun 	exposure <<= 4;
1179*4882a593Smuzhiyun 
1180*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor,
1181*4882a593Smuzhiyun 			       OV5640_REG_AEC_PK_EXPOSURE_LO,
1182*4882a593Smuzhiyun 			       exposure & 0xff);
1183*4882a593Smuzhiyun 	if (ret)
1184*4882a593Smuzhiyun 		return ret;
1185*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor,
1186*4882a593Smuzhiyun 			       OV5640_REG_AEC_PK_EXPOSURE_MED,
1187*4882a593Smuzhiyun 			       (exposure >> 8) & 0xff);
1188*4882a593Smuzhiyun 	if (ret)
1189*4882a593Smuzhiyun 		return ret;
1190*4882a593Smuzhiyun 	return ov5640_write_reg(sensor,
1191*4882a593Smuzhiyun 				OV5640_REG_AEC_PK_EXPOSURE_HI,
1192*4882a593Smuzhiyun 				(exposure >> 16) & 0x0f);
1193*4882a593Smuzhiyun }
1194*4882a593Smuzhiyun 
ov5640_get_gain(struct ov5640_dev * sensor)1195*4882a593Smuzhiyun static int ov5640_get_gain(struct ov5640_dev *sensor)
1196*4882a593Smuzhiyun {
1197*4882a593Smuzhiyun 	u16 gain;
1198*4882a593Smuzhiyun 	int ret;
1199*4882a593Smuzhiyun 
1200*4882a593Smuzhiyun 	ret = ov5640_read_reg16(sensor, OV5640_REG_AEC_PK_REAL_GAIN, &gain);
1201*4882a593Smuzhiyun 	if (ret)
1202*4882a593Smuzhiyun 		return ret;
1203*4882a593Smuzhiyun 
1204*4882a593Smuzhiyun 	return gain & 0x3ff;
1205*4882a593Smuzhiyun }
1206*4882a593Smuzhiyun 
ov5640_set_gain(struct ov5640_dev * sensor,int gain)1207*4882a593Smuzhiyun static int ov5640_set_gain(struct ov5640_dev *sensor, int gain)
1208*4882a593Smuzhiyun {
1209*4882a593Smuzhiyun 	return ov5640_write_reg16(sensor, OV5640_REG_AEC_PK_REAL_GAIN,
1210*4882a593Smuzhiyun 				  (u16)gain & 0x3ff);
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun 
ov5640_set_autogain(struct ov5640_dev * sensor,bool on)1213*4882a593Smuzhiyun static int ov5640_set_autogain(struct ov5640_dev *sensor, bool on)
1214*4882a593Smuzhiyun {
1215*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_AEC_PK_MANUAL,
1216*4882a593Smuzhiyun 			      BIT(1), on ? 0 : BIT(1));
1217*4882a593Smuzhiyun }
1218*4882a593Smuzhiyun 
ov5640_set_stream_dvp(struct ov5640_dev * sensor,bool on)1219*4882a593Smuzhiyun static int ov5640_set_stream_dvp(struct ov5640_dev *sensor, bool on)
1220*4882a593Smuzhiyun {
1221*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_SYS_CTRL0, on ?
1222*4882a593Smuzhiyun 				OV5640_REG_SYS_CTRL0_SW_PWUP :
1223*4882a593Smuzhiyun 				OV5640_REG_SYS_CTRL0_SW_PWDN);
1224*4882a593Smuzhiyun }
1225*4882a593Smuzhiyun 
ov5640_set_stream_mipi(struct ov5640_dev * sensor,bool on)1226*4882a593Smuzhiyun static int ov5640_set_stream_mipi(struct ov5640_dev *sensor, bool on)
1227*4882a593Smuzhiyun {
1228*4882a593Smuzhiyun 	int ret;
1229*4882a593Smuzhiyun 
1230*4882a593Smuzhiyun 	/*
1231*4882a593Smuzhiyun 	 * Enable/disable the MIPI interface
1232*4882a593Smuzhiyun 	 *
1233*4882a593Smuzhiyun 	 * 0x300e = on ? 0x45 : 0x40
1234*4882a593Smuzhiyun 	 *
1235*4882a593Smuzhiyun 	 * FIXME: the sensor manual (version 2.03) reports
1236*4882a593Smuzhiyun 	 * [7:5] = 000  : 1 data lane mode
1237*4882a593Smuzhiyun 	 * [7:5] = 001  : 2 data lanes mode
1238*4882a593Smuzhiyun 	 * But this settings do not work, while the following ones
1239*4882a593Smuzhiyun 	 * have been validated for 2 data lanes mode.
1240*4882a593Smuzhiyun 	 *
1241*4882a593Smuzhiyun 	 * [7:5] = 010	: 2 data lanes mode
1242*4882a593Smuzhiyun 	 * [4] = 0	: Power up MIPI HS Tx
1243*4882a593Smuzhiyun 	 * [3] = 0	: Power up MIPI LS Rx
1244*4882a593Smuzhiyun 	 * [2] = 1/0	: MIPI interface enable/disable
1245*4882a593Smuzhiyun 	 * [1:0] = 01/00: FIXME: 'debug'
1246*4882a593Smuzhiyun 	 */
1247*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00,
1248*4882a593Smuzhiyun 			       on ? 0x45 : 0x40);
1249*4882a593Smuzhiyun 	if (ret)
1250*4882a593Smuzhiyun 		return ret;
1251*4882a593Smuzhiyun 
1252*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_FRAME_CTRL01,
1253*4882a593Smuzhiyun 				on ? 0x00 : 0x0f);
1254*4882a593Smuzhiyun }
1255*4882a593Smuzhiyun 
ov5640_get_sysclk(struct ov5640_dev * sensor)1256*4882a593Smuzhiyun static int ov5640_get_sysclk(struct ov5640_dev *sensor)
1257*4882a593Smuzhiyun {
1258*4882a593Smuzhiyun 	 /* calculate sysclk */
1259*4882a593Smuzhiyun 	u32 xvclk = sensor->xclk_freq / 10000;
1260*4882a593Smuzhiyun 	u32 multiplier, prediv, VCO, sysdiv, pll_rdiv;
1261*4882a593Smuzhiyun 	u32 sclk_rdiv_map[] = {1, 2, 4, 8};
1262*4882a593Smuzhiyun 	u32 bit_div2x = 1, sclk_rdiv, sysclk;
1263*4882a593Smuzhiyun 	u8 temp1, temp2;
1264*4882a593Smuzhiyun 	int ret;
1265*4882a593Smuzhiyun 
1266*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL0, &temp1);
1267*4882a593Smuzhiyun 	if (ret)
1268*4882a593Smuzhiyun 		return ret;
1269*4882a593Smuzhiyun 	temp2 = temp1 & 0x0f;
1270*4882a593Smuzhiyun 	if (temp2 == 8 || temp2 == 10)
1271*4882a593Smuzhiyun 		bit_div2x = temp2 / 2;
1272*4882a593Smuzhiyun 
1273*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL1, &temp1);
1274*4882a593Smuzhiyun 	if (ret)
1275*4882a593Smuzhiyun 		return ret;
1276*4882a593Smuzhiyun 	sysdiv = temp1 >> 4;
1277*4882a593Smuzhiyun 	if (sysdiv == 0)
1278*4882a593Smuzhiyun 		sysdiv = 16;
1279*4882a593Smuzhiyun 
1280*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL2, &temp1);
1281*4882a593Smuzhiyun 	if (ret)
1282*4882a593Smuzhiyun 		return ret;
1283*4882a593Smuzhiyun 	multiplier = temp1;
1284*4882a593Smuzhiyun 
1285*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL3, &temp1);
1286*4882a593Smuzhiyun 	if (ret)
1287*4882a593Smuzhiyun 		return ret;
1288*4882a593Smuzhiyun 	prediv = temp1 & 0x0f;
1289*4882a593Smuzhiyun 	pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
1290*4882a593Smuzhiyun 
1291*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, &temp1);
1292*4882a593Smuzhiyun 	if (ret)
1293*4882a593Smuzhiyun 		return ret;
1294*4882a593Smuzhiyun 	temp2 = temp1 & 0x03;
1295*4882a593Smuzhiyun 	sclk_rdiv = sclk_rdiv_map[temp2];
1296*4882a593Smuzhiyun 
1297*4882a593Smuzhiyun 	if (!prediv || !sysdiv || !pll_rdiv || !bit_div2x)
1298*4882a593Smuzhiyun 		return -EINVAL;
1299*4882a593Smuzhiyun 
1300*4882a593Smuzhiyun 	VCO = xvclk * multiplier / prediv;
1301*4882a593Smuzhiyun 
1302*4882a593Smuzhiyun 	sysclk = VCO / sysdiv / pll_rdiv * 2 / bit_div2x / sclk_rdiv;
1303*4882a593Smuzhiyun 
1304*4882a593Smuzhiyun 	return sysclk;
1305*4882a593Smuzhiyun }
1306*4882a593Smuzhiyun 
ov5640_set_night_mode(struct ov5640_dev * sensor)1307*4882a593Smuzhiyun static int ov5640_set_night_mode(struct ov5640_dev *sensor)
1308*4882a593Smuzhiyun {
1309*4882a593Smuzhiyun 	 /* read HTS from register settings */
1310*4882a593Smuzhiyun 	u8 mode;
1311*4882a593Smuzhiyun 	int ret;
1312*4882a593Smuzhiyun 
1313*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_AEC_CTRL00, &mode);
1314*4882a593Smuzhiyun 	if (ret)
1315*4882a593Smuzhiyun 		return ret;
1316*4882a593Smuzhiyun 	mode &= 0xfb;
1317*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL00, mode);
1318*4882a593Smuzhiyun }
1319*4882a593Smuzhiyun 
ov5640_get_hts(struct ov5640_dev * sensor)1320*4882a593Smuzhiyun static int ov5640_get_hts(struct ov5640_dev *sensor)
1321*4882a593Smuzhiyun {
1322*4882a593Smuzhiyun 	/* read HTS from register settings */
1323*4882a593Smuzhiyun 	u16 hts;
1324*4882a593Smuzhiyun 	int ret;
1325*4882a593Smuzhiyun 
1326*4882a593Smuzhiyun 	ret = ov5640_read_reg16(sensor, OV5640_REG_TIMING_HTS, &hts);
1327*4882a593Smuzhiyun 	if (ret)
1328*4882a593Smuzhiyun 		return ret;
1329*4882a593Smuzhiyun 	return hts;
1330*4882a593Smuzhiyun }
1331*4882a593Smuzhiyun 
ov5640_get_vts(struct ov5640_dev * sensor)1332*4882a593Smuzhiyun static int ov5640_get_vts(struct ov5640_dev *sensor)
1333*4882a593Smuzhiyun {
1334*4882a593Smuzhiyun 	u16 vts;
1335*4882a593Smuzhiyun 	int ret;
1336*4882a593Smuzhiyun 
1337*4882a593Smuzhiyun 	ret = ov5640_read_reg16(sensor, OV5640_REG_TIMING_VTS, &vts);
1338*4882a593Smuzhiyun 	if (ret)
1339*4882a593Smuzhiyun 		return ret;
1340*4882a593Smuzhiyun 	return vts;
1341*4882a593Smuzhiyun }
1342*4882a593Smuzhiyun 
ov5640_set_vts(struct ov5640_dev * sensor,int vts)1343*4882a593Smuzhiyun static int ov5640_set_vts(struct ov5640_dev *sensor, int vts)
1344*4882a593Smuzhiyun {
1345*4882a593Smuzhiyun 	return ov5640_write_reg16(sensor, OV5640_REG_TIMING_VTS, vts);
1346*4882a593Smuzhiyun }
1347*4882a593Smuzhiyun 
ov5640_get_light_freq(struct ov5640_dev * sensor)1348*4882a593Smuzhiyun static int ov5640_get_light_freq(struct ov5640_dev *sensor)
1349*4882a593Smuzhiyun {
1350*4882a593Smuzhiyun 	/* get banding filter value */
1351*4882a593Smuzhiyun 	int ret, light_freq = 0;
1352*4882a593Smuzhiyun 	u8 temp, temp1;
1353*4882a593Smuzhiyun 
1354*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_HZ5060_CTRL01, &temp);
1355*4882a593Smuzhiyun 	if (ret)
1356*4882a593Smuzhiyun 		return ret;
1357*4882a593Smuzhiyun 
1358*4882a593Smuzhiyun 	if (temp & 0x80) {
1359*4882a593Smuzhiyun 		/* manual */
1360*4882a593Smuzhiyun 		ret = ov5640_read_reg(sensor, OV5640_REG_HZ5060_CTRL00,
1361*4882a593Smuzhiyun 				      &temp1);
1362*4882a593Smuzhiyun 		if (ret)
1363*4882a593Smuzhiyun 			return ret;
1364*4882a593Smuzhiyun 		if (temp1 & 0x04) {
1365*4882a593Smuzhiyun 			/* 50Hz */
1366*4882a593Smuzhiyun 			light_freq = 50;
1367*4882a593Smuzhiyun 		} else {
1368*4882a593Smuzhiyun 			/* 60Hz */
1369*4882a593Smuzhiyun 			light_freq = 60;
1370*4882a593Smuzhiyun 		}
1371*4882a593Smuzhiyun 	} else {
1372*4882a593Smuzhiyun 		/* auto */
1373*4882a593Smuzhiyun 		ret = ov5640_read_reg(sensor, OV5640_REG_SIGMADELTA_CTRL0C,
1374*4882a593Smuzhiyun 				      &temp1);
1375*4882a593Smuzhiyun 		if (ret)
1376*4882a593Smuzhiyun 			return ret;
1377*4882a593Smuzhiyun 
1378*4882a593Smuzhiyun 		if (temp1 & 0x01) {
1379*4882a593Smuzhiyun 			/* 50Hz */
1380*4882a593Smuzhiyun 			light_freq = 50;
1381*4882a593Smuzhiyun 		} else {
1382*4882a593Smuzhiyun 			/* 60Hz */
1383*4882a593Smuzhiyun 		}
1384*4882a593Smuzhiyun 	}
1385*4882a593Smuzhiyun 
1386*4882a593Smuzhiyun 	return light_freq;
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun 
ov5640_set_bandingfilter(struct ov5640_dev * sensor)1389*4882a593Smuzhiyun static int ov5640_set_bandingfilter(struct ov5640_dev *sensor)
1390*4882a593Smuzhiyun {
1391*4882a593Smuzhiyun 	u32 band_step60, max_band60, band_step50, max_band50, prev_vts;
1392*4882a593Smuzhiyun 	int ret;
1393*4882a593Smuzhiyun 
1394*4882a593Smuzhiyun 	/* read preview PCLK */
1395*4882a593Smuzhiyun 	ret = ov5640_get_sysclk(sensor);
1396*4882a593Smuzhiyun 	if (ret < 0)
1397*4882a593Smuzhiyun 		return ret;
1398*4882a593Smuzhiyun 	if (ret == 0)
1399*4882a593Smuzhiyun 		return -EINVAL;
1400*4882a593Smuzhiyun 	sensor->prev_sysclk = ret;
1401*4882a593Smuzhiyun 	/* read preview HTS */
1402*4882a593Smuzhiyun 	ret = ov5640_get_hts(sensor);
1403*4882a593Smuzhiyun 	if (ret < 0)
1404*4882a593Smuzhiyun 		return ret;
1405*4882a593Smuzhiyun 	if (ret == 0)
1406*4882a593Smuzhiyun 		return -EINVAL;
1407*4882a593Smuzhiyun 	sensor->prev_hts = ret;
1408*4882a593Smuzhiyun 
1409*4882a593Smuzhiyun 	/* read preview VTS */
1410*4882a593Smuzhiyun 	ret = ov5640_get_vts(sensor);
1411*4882a593Smuzhiyun 	if (ret < 0)
1412*4882a593Smuzhiyun 		return ret;
1413*4882a593Smuzhiyun 	prev_vts = ret;
1414*4882a593Smuzhiyun 
1415*4882a593Smuzhiyun 	/* calculate banding filter */
1416*4882a593Smuzhiyun 	/* 60Hz */
1417*4882a593Smuzhiyun 	band_step60 = sensor->prev_sysclk * 100 / sensor->prev_hts * 100 / 120;
1418*4882a593Smuzhiyun 	ret = ov5640_write_reg16(sensor, OV5640_REG_AEC_B60_STEP, band_step60);
1419*4882a593Smuzhiyun 	if (ret)
1420*4882a593Smuzhiyun 		return ret;
1421*4882a593Smuzhiyun 	if (!band_step60)
1422*4882a593Smuzhiyun 		return -EINVAL;
1423*4882a593Smuzhiyun 	max_band60 = (int)((prev_vts - 4) / band_step60);
1424*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0D, max_band60);
1425*4882a593Smuzhiyun 	if (ret)
1426*4882a593Smuzhiyun 		return ret;
1427*4882a593Smuzhiyun 
1428*4882a593Smuzhiyun 	/* 50Hz */
1429*4882a593Smuzhiyun 	band_step50 = sensor->prev_sysclk * 100 / sensor->prev_hts;
1430*4882a593Smuzhiyun 	ret = ov5640_write_reg16(sensor, OV5640_REG_AEC_B50_STEP, band_step50);
1431*4882a593Smuzhiyun 	if (ret)
1432*4882a593Smuzhiyun 		return ret;
1433*4882a593Smuzhiyun 	if (!band_step50)
1434*4882a593Smuzhiyun 		return -EINVAL;
1435*4882a593Smuzhiyun 	max_band50 = (int)((prev_vts - 4) / band_step50);
1436*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0E, max_band50);
1437*4882a593Smuzhiyun }
1438*4882a593Smuzhiyun 
ov5640_set_ae_target(struct ov5640_dev * sensor,int target)1439*4882a593Smuzhiyun static int ov5640_set_ae_target(struct ov5640_dev *sensor, int target)
1440*4882a593Smuzhiyun {
1441*4882a593Smuzhiyun 	/* stable in high */
1442*4882a593Smuzhiyun 	u32 fast_high, fast_low;
1443*4882a593Smuzhiyun 	int ret;
1444*4882a593Smuzhiyun 
1445*4882a593Smuzhiyun 	sensor->ae_low = target * 23 / 25;	/* 0.92 */
1446*4882a593Smuzhiyun 	sensor->ae_high = target * 27 / 25;	/* 1.08 */
1447*4882a593Smuzhiyun 
1448*4882a593Smuzhiyun 	fast_high = sensor->ae_high << 1;
1449*4882a593Smuzhiyun 	if (fast_high > 255)
1450*4882a593Smuzhiyun 		fast_high = 255;
1451*4882a593Smuzhiyun 
1452*4882a593Smuzhiyun 	fast_low = sensor->ae_low >> 1;
1453*4882a593Smuzhiyun 
1454*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0F, sensor->ae_high);
1455*4882a593Smuzhiyun 	if (ret)
1456*4882a593Smuzhiyun 		return ret;
1457*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL10, sensor->ae_low);
1458*4882a593Smuzhiyun 	if (ret)
1459*4882a593Smuzhiyun 		return ret;
1460*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1B, sensor->ae_high);
1461*4882a593Smuzhiyun 	if (ret)
1462*4882a593Smuzhiyun 		return ret;
1463*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1E, sensor->ae_low);
1464*4882a593Smuzhiyun 	if (ret)
1465*4882a593Smuzhiyun 		return ret;
1466*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL11, fast_high);
1467*4882a593Smuzhiyun 	if (ret)
1468*4882a593Smuzhiyun 		return ret;
1469*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1F, fast_low);
1470*4882a593Smuzhiyun }
1471*4882a593Smuzhiyun 
ov5640_get_binning(struct ov5640_dev * sensor)1472*4882a593Smuzhiyun static int ov5640_get_binning(struct ov5640_dev *sensor)
1473*4882a593Smuzhiyun {
1474*4882a593Smuzhiyun 	u8 temp;
1475*4882a593Smuzhiyun 	int ret;
1476*4882a593Smuzhiyun 
1477*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_TIMING_TC_REG21, &temp);
1478*4882a593Smuzhiyun 	if (ret)
1479*4882a593Smuzhiyun 		return ret;
1480*4882a593Smuzhiyun 
1481*4882a593Smuzhiyun 	return temp & BIT(0);
1482*4882a593Smuzhiyun }
1483*4882a593Smuzhiyun 
ov5640_set_binning(struct ov5640_dev * sensor,bool enable)1484*4882a593Smuzhiyun static int ov5640_set_binning(struct ov5640_dev *sensor, bool enable)
1485*4882a593Smuzhiyun {
1486*4882a593Smuzhiyun 	int ret;
1487*4882a593Smuzhiyun 
1488*4882a593Smuzhiyun 	/*
1489*4882a593Smuzhiyun 	 * TIMING TC REG21:
1490*4882a593Smuzhiyun 	 * - [0]:	Horizontal binning enable
1491*4882a593Smuzhiyun 	 */
1492*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
1493*4882a593Smuzhiyun 			     BIT(0), enable ? BIT(0) : 0);
1494*4882a593Smuzhiyun 	if (ret)
1495*4882a593Smuzhiyun 		return ret;
1496*4882a593Smuzhiyun 	/*
1497*4882a593Smuzhiyun 	 * TIMING TC REG20:
1498*4882a593Smuzhiyun 	 * - [0]:	Undocumented, but hardcoded init sequences
1499*4882a593Smuzhiyun 	 *		are always setting REG21/REG20 bit 0 to same value...
1500*4882a593Smuzhiyun 	 */
1501*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG20,
1502*4882a593Smuzhiyun 			      BIT(0), enable ? BIT(0) : 0);
1503*4882a593Smuzhiyun }
1504*4882a593Smuzhiyun 
ov5640_set_virtual_channel(struct ov5640_dev * sensor)1505*4882a593Smuzhiyun static int ov5640_set_virtual_channel(struct ov5640_dev *sensor)
1506*4882a593Smuzhiyun {
1507*4882a593Smuzhiyun 	struct i2c_client *client = sensor->i2c_client;
1508*4882a593Smuzhiyun 	u8 temp, channel = virtual_channel;
1509*4882a593Smuzhiyun 	int ret;
1510*4882a593Smuzhiyun 
1511*4882a593Smuzhiyun 	if (channel > 3) {
1512*4882a593Smuzhiyun 		dev_err(&client->dev,
1513*4882a593Smuzhiyun 			"%s: wrong virtual_channel parameter, expected (0..3), got %d\n",
1514*4882a593Smuzhiyun 			__func__, channel);
1515*4882a593Smuzhiyun 		return -EINVAL;
1516*4882a593Smuzhiyun 	}
1517*4882a593Smuzhiyun 
1518*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_DEBUG_MODE, &temp);
1519*4882a593Smuzhiyun 	if (ret)
1520*4882a593Smuzhiyun 		return ret;
1521*4882a593Smuzhiyun 	temp &= ~(3 << 6);
1522*4882a593Smuzhiyun 	temp |= (channel << 6);
1523*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_DEBUG_MODE, temp);
1524*4882a593Smuzhiyun }
1525*4882a593Smuzhiyun 
1526*4882a593Smuzhiyun static const struct ov5640_mode_info *
ov5640_find_mode(struct ov5640_dev * sensor,enum ov5640_frame_rate fr,int width,int height,bool nearest)1527*4882a593Smuzhiyun ov5640_find_mode(struct ov5640_dev *sensor, enum ov5640_frame_rate fr,
1528*4882a593Smuzhiyun 		 int width, int height, bool nearest)
1529*4882a593Smuzhiyun {
1530*4882a593Smuzhiyun 	const struct ov5640_mode_info *mode;
1531*4882a593Smuzhiyun 
1532*4882a593Smuzhiyun 	mode = v4l2_find_nearest_size(ov5640_mode_data,
1533*4882a593Smuzhiyun 				      ARRAY_SIZE(ov5640_mode_data),
1534*4882a593Smuzhiyun 				      hact, vact,
1535*4882a593Smuzhiyun 				      width, height);
1536*4882a593Smuzhiyun 
1537*4882a593Smuzhiyun 	if (!mode ||
1538*4882a593Smuzhiyun 	    (!nearest && (mode->hact != width || mode->vact != height)))
1539*4882a593Smuzhiyun 		return NULL;
1540*4882a593Smuzhiyun 
1541*4882a593Smuzhiyun 	/* Check to see if the current mode exceeds the max frame rate */
1542*4882a593Smuzhiyun 	if (ov5640_framerates[fr] > ov5640_framerates[mode->max_fps])
1543*4882a593Smuzhiyun 		return NULL;
1544*4882a593Smuzhiyun 
1545*4882a593Smuzhiyun 	return mode;
1546*4882a593Smuzhiyun }
1547*4882a593Smuzhiyun 
ov5640_calc_pixel_rate(struct ov5640_dev * sensor)1548*4882a593Smuzhiyun static u64 ov5640_calc_pixel_rate(struct ov5640_dev *sensor)
1549*4882a593Smuzhiyun {
1550*4882a593Smuzhiyun 	u64 rate;
1551*4882a593Smuzhiyun 
1552*4882a593Smuzhiyun 	rate = sensor->current_mode->vtot * sensor->current_mode->htot;
1553*4882a593Smuzhiyun 	rate *= ov5640_framerates[sensor->current_fr];
1554*4882a593Smuzhiyun 
1555*4882a593Smuzhiyun 	return rate;
1556*4882a593Smuzhiyun }
1557*4882a593Smuzhiyun 
1558*4882a593Smuzhiyun /*
1559*4882a593Smuzhiyun  * sensor changes between scaling and subsampling, go through
1560*4882a593Smuzhiyun  * exposure calculation
1561*4882a593Smuzhiyun  */
ov5640_set_mode_exposure_calc(struct ov5640_dev * sensor,const struct ov5640_mode_info * mode)1562*4882a593Smuzhiyun static int ov5640_set_mode_exposure_calc(struct ov5640_dev *sensor,
1563*4882a593Smuzhiyun 					 const struct ov5640_mode_info *mode)
1564*4882a593Smuzhiyun {
1565*4882a593Smuzhiyun 	u32 prev_shutter, prev_gain16;
1566*4882a593Smuzhiyun 	u32 cap_shutter, cap_gain16;
1567*4882a593Smuzhiyun 	u32 cap_sysclk, cap_hts, cap_vts;
1568*4882a593Smuzhiyun 	u32 light_freq, cap_bandfilt, cap_maxband;
1569*4882a593Smuzhiyun 	u32 cap_gain16_shutter;
1570*4882a593Smuzhiyun 	u8 average;
1571*4882a593Smuzhiyun 	int ret;
1572*4882a593Smuzhiyun 
1573*4882a593Smuzhiyun 	if (!mode->reg_data)
1574*4882a593Smuzhiyun 		return -EINVAL;
1575*4882a593Smuzhiyun 
1576*4882a593Smuzhiyun 	/* read preview shutter */
1577*4882a593Smuzhiyun 	ret = ov5640_get_exposure(sensor);
1578*4882a593Smuzhiyun 	if (ret < 0)
1579*4882a593Smuzhiyun 		return ret;
1580*4882a593Smuzhiyun 	prev_shutter = ret;
1581*4882a593Smuzhiyun 	ret = ov5640_get_binning(sensor);
1582*4882a593Smuzhiyun 	if (ret < 0)
1583*4882a593Smuzhiyun 		return ret;
1584*4882a593Smuzhiyun 	if (ret && mode->id != OV5640_MODE_720P_1280_720 &&
1585*4882a593Smuzhiyun 	    mode->id != OV5640_MODE_1080P_1920_1080)
1586*4882a593Smuzhiyun 		prev_shutter *= 2;
1587*4882a593Smuzhiyun 
1588*4882a593Smuzhiyun 	/* read preview gain */
1589*4882a593Smuzhiyun 	ret = ov5640_get_gain(sensor);
1590*4882a593Smuzhiyun 	if (ret < 0)
1591*4882a593Smuzhiyun 		return ret;
1592*4882a593Smuzhiyun 	prev_gain16 = ret;
1593*4882a593Smuzhiyun 
1594*4882a593Smuzhiyun 	/* get average */
1595*4882a593Smuzhiyun 	ret = ov5640_read_reg(sensor, OV5640_REG_AVG_READOUT, &average);
1596*4882a593Smuzhiyun 	if (ret)
1597*4882a593Smuzhiyun 		return ret;
1598*4882a593Smuzhiyun 
1599*4882a593Smuzhiyun 	/* turn off night mode for capture */
1600*4882a593Smuzhiyun 	ret = ov5640_set_night_mode(sensor);
1601*4882a593Smuzhiyun 	if (ret < 0)
1602*4882a593Smuzhiyun 		return ret;
1603*4882a593Smuzhiyun 
1604*4882a593Smuzhiyun 	/* Write capture setting */
1605*4882a593Smuzhiyun 	ret = ov5640_load_regs(sensor, mode);
1606*4882a593Smuzhiyun 	if (ret < 0)
1607*4882a593Smuzhiyun 		return ret;
1608*4882a593Smuzhiyun 
1609*4882a593Smuzhiyun 	/* read capture VTS */
1610*4882a593Smuzhiyun 	ret = ov5640_get_vts(sensor);
1611*4882a593Smuzhiyun 	if (ret < 0)
1612*4882a593Smuzhiyun 		return ret;
1613*4882a593Smuzhiyun 	cap_vts = ret;
1614*4882a593Smuzhiyun 	ret = ov5640_get_hts(sensor);
1615*4882a593Smuzhiyun 	if (ret < 0)
1616*4882a593Smuzhiyun 		return ret;
1617*4882a593Smuzhiyun 	if (ret == 0)
1618*4882a593Smuzhiyun 		return -EINVAL;
1619*4882a593Smuzhiyun 	cap_hts = ret;
1620*4882a593Smuzhiyun 
1621*4882a593Smuzhiyun 	ret = ov5640_get_sysclk(sensor);
1622*4882a593Smuzhiyun 	if (ret < 0)
1623*4882a593Smuzhiyun 		return ret;
1624*4882a593Smuzhiyun 	if (ret == 0)
1625*4882a593Smuzhiyun 		return -EINVAL;
1626*4882a593Smuzhiyun 	cap_sysclk = ret;
1627*4882a593Smuzhiyun 
1628*4882a593Smuzhiyun 	/* calculate capture banding filter */
1629*4882a593Smuzhiyun 	ret = ov5640_get_light_freq(sensor);
1630*4882a593Smuzhiyun 	if (ret < 0)
1631*4882a593Smuzhiyun 		return ret;
1632*4882a593Smuzhiyun 	light_freq = ret;
1633*4882a593Smuzhiyun 
1634*4882a593Smuzhiyun 	if (light_freq == 60) {
1635*4882a593Smuzhiyun 		/* 60Hz */
1636*4882a593Smuzhiyun 		cap_bandfilt = cap_sysclk * 100 / cap_hts * 100 / 120;
1637*4882a593Smuzhiyun 	} else {
1638*4882a593Smuzhiyun 		/* 50Hz */
1639*4882a593Smuzhiyun 		cap_bandfilt = cap_sysclk * 100 / cap_hts;
1640*4882a593Smuzhiyun 	}
1641*4882a593Smuzhiyun 
1642*4882a593Smuzhiyun 	if (!sensor->prev_sysclk) {
1643*4882a593Smuzhiyun 		ret = ov5640_get_sysclk(sensor);
1644*4882a593Smuzhiyun 		if (ret < 0)
1645*4882a593Smuzhiyun 			return ret;
1646*4882a593Smuzhiyun 		if (ret == 0)
1647*4882a593Smuzhiyun 			return -EINVAL;
1648*4882a593Smuzhiyun 		sensor->prev_sysclk = ret;
1649*4882a593Smuzhiyun 	}
1650*4882a593Smuzhiyun 
1651*4882a593Smuzhiyun 	if (!cap_bandfilt)
1652*4882a593Smuzhiyun 		return -EINVAL;
1653*4882a593Smuzhiyun 
1654*4882a593Smuzhiyun 	cap_maxband = (int)((cap_vts - 4) / cap_bandfilt);
1655*4882a593Smuzhiyun 
1656*4882a593Smuzhiyun 	/* calculate capture shutter/gain16 */
1657*4882a593Smuzhiyun 	if (average > sensor->ae_low && average < sensor->ae_high) {
1658*4882a593Smuzhiyun 		/* in stable range */
1659*4882a593Smuzhiyun 		cap_gain16_shutter =
1660*4882a593Smuzhiyun 			prev_gain16 * prev_shutter *
1661*4882a593Smuzhiyun 			cap_sysclk / sensor->prev_sysclk *
1662*4882a593Smuzhiyun 			sensor->prev_hts / cap_hts *
1663*4882a593Smuzhiyun 			sensor->ae_target / average;
1664*4882a593Smuzhiyun 	} else {
1665*4882a593Smuzhiyun 		cap_gain16_shutter =
1666*4882a593Smuzhiyun 			prev_gain16 * prev_shutter *
1667*4882a593Smuzhiyun 			cap_sysclk / sensor->prev_sysclk *
1668*4882a593Smuzhiyun 			sensor->prev_hts / cap_hts;
1669*4882a593Smuzhiyun 	}
1670*4882a593Smuzhiyun 
1671*4882a593Smuzhiyun 	/* gain to shutter */
1672*4882a593Smuzhiyun 	if (cap_gain16_shutter < (cap_bandfilt * 16)) {
1673*4882a593Smuzhiyun 		/* shutter < 1/100 */
1674*4882a593Smuzhiyun 		cap_shutter = cap_gain16_shutter / 16;
1675*4882a593Smuzhiyun 		if (cap_shutter < 1)
1676*4882a593Smuzhiyun 			cap_shutter = 1;
1677*4882a593Smuzhiyun 
1678*4882a593Smuzhiyun 		cap_gain16 = cap_gain16_shutter / cap_shutter;
1679*4882a593Smuzhiyun 		if (cap_gain16 < 16)
1680*4882a593Smuzhiyun 			cap_gain16 = 16;
1681*4882a593Smuzhiyun 	} else {
1682*4882a593Smuzhiyun 		if (cap_gain16_shutter > (cap_bandfilt * cap_maxband * 16)) {
1683*4882a593Smuzhiyun 			/* exposure reach max */
1684*4882a593Smuzhiyun 			cap_shutter = cap_bandfilt * cap_maxband;
1685*4882a593Smuzhiyun 			if (!cap_shutter)
1686*4882a593Smuzhiyun 				return -EINVAL;
1687*4882a593Smuzhiyun 
1688*4882a593Smuzhiyun 			cap_gain16 = cap_gain16_shutter / cap_shutter;
1689*4882a593Smuzhiyun 		} else {
1690*4882a593Smuzhiyun 			/* 1/100 < (cap_shutter = n/100) =< max */
1691*4882a593Smuzhiyun 			cap_shutter =
1692*4882a593Smuzhiyun 				((int)(cap_gain16_shutter / 16 / cap_bandfilt))
1693*4882a593Smuzhiyun 				* cap_bandfilt;
1694*4882a593Smuzhiyun 			if (!cap_shutter)
1695*4882a593Smuzhiyun 				return -EINVAL;
1696*4882a593Smuzhiyun 
1697*4882a593Smuzhiyun 			cap_gain16 = cap_gain16_shutter / cap_shutter;
1698*4882a593Smuzhiyun 		}
1699*4882a593Smuzhiyun 	}
1700*4882a593Smuzhiyun 
1701*4882a593Smuzhiyun 	/* set capture gain */
1702*4882a593Smuzhiyun 	ret = ov5640_set_gain(sensor, cap_gain16);
1703*4882a593Smuzhiyun 	if (ret)
1704*4882a593Smuzhiyun 		return ret;
1705*4882a593Smuzhiyun 
1706*4882a593Smuzhiyun 	/* write capture shutter */
1707*4882a593Smuzhiyun 	if (cap_shutter > (cap_vts - 4)) {
1708*4882a593Smuzhiyun 		cap_vts = cap_shutter + 4;
1709*4882a593Smuzhiyun 		ret = ov5640_set_vts(sensor, cap_vts);
1710*4882a593Smuzhiyun 		if (ret < 0)
1711*4882a593Smuzhiyun 			return ret;
1712*4882a593Smuzhiyun 	}
1713*4882a593Smuzhiyun 
1714*4882a593Smuzhiyun 	/* set exposure */
1715*4882a593Smuzhiyun 	return ov5640_set_exposure(sensor, cap_shutter);
1716*4882a593Smuzhiyun }
1717*4882a593Smuzhiyun 
1718*4882a593Smuzhiyun /*
1719*4882a593Smuzhiyun  * if sensor changes inside scaling or subsampling
1720*4882a593Smuzhiyun  * change mode directly
1721*4882a593Smuzhiyun  */
ov5640_set_mode_direct(struct ov5640_dev * sensor,const struct ov5640_mode_info * mode)1722*4882a593Smuzhiyun static int ov5640_set_mode_direct(struct ov5640_dev *sensor,
1723*4882a593Smuzhiyun 				  const struct ov5640_mode_info *mode)
1724*4882a593Smuzhiyun {
1725*4882a593Smuzhiyun 	if (!mode->reg_data)
1726*4882a593Smuzhiyun 		return -EINVAL;
1727*4882a593Smuzhiyun 
1728*4882a593Smuzhiyun 	/* Write capture setting */
1729*4882a593Smuzhiyun 	return ov5640_load_regs(sensor, mode);
1730*4882a593Smuzhiyun }
1731*4882a593Smuzhiyun 
ov5640_set_mode(struct ov5640_dev * sensor)1732*4882a593Smuzhiyun static int ov5640_set_mode(struct ov5640_dev *sensor)
1733*4882a593Smuzhiyun {
1734*4882a593Smuzhiyun 	const struct ov5640_mode_info *mode = sensor->current_mode;
1735*4882a593Smuzhiyun 	const struct ov5640_mode_info *orig_mode = sensor->last_mode;
1736*4882a593Smuzhiyun 	enum ov5640_downsize_mode dn_mode, orig_dn_mode;
1737*4882a593Smuzhiyun 	bool auto_gain = sensor->ctrls.auto_gain->val == 1;
1738*4882a593Smuzhiyun 	bool auto_exp =  sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
1739*4882a593Smuzhiyun 	unsigned long rate;
1740*4882a593Smuzhiyun 	int ret;
1741*4882a593Smuzhiyun 
1742*4882a593Smuzhiyun 	dn_mode = mode->dn_mode;
1743*4882a593Smuzhiyun 	orig_dn_mode = orig_mode->dn_mode;
1744*4882a593Smuzhiyun 
1745*4882a593Smuzhiyun 	/* auto gain and exposure must be turned off when changing modes */
1746*4882a593Smuzhiyun 	if (auto_gain) {
1747*4882a593Smuzhiyun 		ret = ov5640_set_autogain(sensor, false);
1748*4882a593Smuzhiyun 		if (ret)
1749*4882a593Smuzhiyun 			return ret;
1750*4882a593Smuzhiyun 	}
1751*4882a593Smuzhiyun 
1752*4882a593Smuzhiyun 	if (auto_exp) {
1753*4882a593Smuzhiyun 		ret = ov5640_set_autoexposure(sensor, false);
1754*4882a593Smuzhiyun 		if (ret)
1755*4882a593Smuzhiyun 			goto restore_auto_gain;
1756*4882a593Smuzhiyun 	}
1757*4882a593Smuzhiyun 
1758*4882a593Smuzhiyun 	/*
1759*4882a593Smuzhiyun 	 * All the formats we support have 16 bits per pixel, seems to require
1760*4882a593Smuzhiyun 	 * the same rate than YUV, so we can just use 16 bpp all the time.
1761*4882a593Smuzhiyun 	 */
1762*4882a593Smuzhiyun 	rate = ov5640_calc_pixel_rate(sensor) * 16;
1763*4882a593Smuzhiyun 	if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) {
1764*4882a593Smuzhiyun 		rate = rate / sensor->ep.bus.mipi_csi2.num_data_lanes;
1765*4882a593Smuzhiyun 		ret = ov5640_set_mipi_pclk(sensor, rate);
1766*4882a593Smuzhiyun 	} else {
1767*4882a593Smuzhiyun 		rate = rate / sensor->ep.bus.parallel.bus_width;
1768*4882a593Smuzhiyun 		ret = ov5640_set_dvp_pclk(sensor, rate);
1769*4882a593Smuzhiyun 	}
1770*4882a593Smuzhiyun 
1771*4882a593Smuzhiyun 	if (ret < 0)
1772*4882a593Smuzhiyun 		return 0;
1773*4882a593Smuzhiyun 
1774*4882a593Smuzhiyun 	if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) ||
1775*4882a593Smuzhiyun 	    (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) {
1776*4882a593Smuzhiyun 		/*
1777*4882a593Smuzhiyun 		 * change between subsampling and scaling
1778*4882a593Smuzhiyun 		 * go through exposure calculation
1779*4882a593Smuzhiyun 		 */
1780*4882a593Smuzhiyun 		ret = ov5640_set_mode_exposure_calc(sensor, mode);
1781*4882a593Smuzhiyun 	} else {
1782*4882a593Smuzhiyun 		/*
1783*4882a593Smuzhiyun 		 * change inside subsampling or scaling
1784*4882a593Smuzhiyun 		 * download firmware directly
1785*4882a593Smuzhiyun 		 */
1786*4882a593Smuzhiyun 		ret = ov5640_set_mode_direct(sensor, mode);
1787*4882a593Smuzhiyun 	}
1788*4882a593Smuzhiyun 	if (ret < 0)
1789*4882a593Smuzhiyun 		goto restore_auto_exp_gain;
1790*4882a593Smuzhiyun 
1791*4882a593Smuzhiyun 	/* restore auto gain and exposure */
1792*4882a593Smuzhiyun 	if (auto_gain)
1793*4882a593Smuzhiyun 		ov5640_set_autogain(sensor, true);
1794*4882a593Smuzhiyun 	if (auto_exp)
1795*4882a593Smuzhiyun 		ov5640_set_autoexposure(sensor, true);
1796*4882a593Smuzhiyun 
1797*4882a593Smuzhiyun 	ret = ov5640_set_binning(sensor, dn_mode != SCALING);
1798*4882a593Smuzhiyun 	if (ret < 0)
1799*4882a593Smuzhiyun 		return ret;
1800*4882a593Smuzhiyun 	ret = ov5640_set_ae_target(sensor, sensor->ae_target);
1801*4882a593Smuzhiyun 	if (ret < 0)
1802*4882a593Smuzhiyun 		return ret;
1803*4882a593Smuzhiyun 	ret = ov5640_get_light_freq(sensor);
1804*4882a593Smuzhiyun 	if (ret < 0)
1805*4882a593Smuzhiyun 		return ret;
1806*4882a593Smuzhiyun 	ret = ov5640_set_bandingfilter(sensor);
1807*4882a593Smuzhiyun 	if (ret < 0)
1808*4882a593Smuzhiyun 		return ret;
1809*4882a593Smuzhiyun 	ret = ov5640_set_virtual_channel(sensor);
1810*4882a593Smuzhiyun 	if (ret < 0)
1811*4882a593Smuzhiyun 		return ret;
1812*4882a593Smuzhiyun 
1813*4882a593Smuzhiyun 	sensor->pending_mode_change = false;
1814*4882a593Smuzhiyun 	sensor->last_mode = mode;
1815*4882a593Smuzhiyun 
1816*4882a593Smuzhiyun 	return 0;
1817*4882a593Smuzhiyun 
1818*4882a593Smuzhiyun restore_auto_exp_gain:
1819*4882a593Smuzhiyun 	if (auto_exp)
1820*4882a593Smuzhiyun 		ov5640_set_autoexposure(sensor, true);
1821*4882a593Smuzhiyun restore_auto_gain:
1822*4882a593Smuzhiyun 	if (auto_gain)
1823*4882a593Smuzhiyun 		ov5640_set_autogain(sensor, true);
1824*4882a593Smuzhiyun 
1825*4882a593Smuzhiyun 	return ret;
1826*4882a593Smuzhiyun }
1827*4882a593Smuzhiyun 
1828*4882a593Smuzhiyun static int ov5640_set_framefmt(struct ov5640_dev *sensor,
1829*4882a593Smuzhiyun 			       struct v4l2_mbus_framefmt *format);
1830*4882a593Smuzhiyun 
1831*4882a593Smuzhiyun /* restore the last set video mode after chip power-on */
ov5640_restore_mode(struct ov5640_dev * sensor)1832*4882a593Smuzhiyun static int ov5640_restore_mode(struct ov5640_dev *sensor)
1833*4882a593Smuzhiyun {
1834*4882a593Smuzhiyun 	int ret;
1835*4882a593Smuzhiyun 
1836*4882a593Smuzhiyun 	/* first load the initial register values */
1837*4882a593Smuzhiyun 	ret = ov5640_load_regs(sensor, &ov5640_mode_init_data);
1838*4882a593Smuzhiyun 	if (ret < 0)
1839*4882a593Smuzhiyun 		return ret;
1840*4882a593Smuzhiyun 	sensor->last_mode = &ov5640_mode_init_data;
1841*4882a593Smuzhiyun 
1842*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x3f,
1843*4882a593Smuzhiyun 			     (ilog2(OV5640_SCLK2X_ROOT_DIV) << 2) |
1844*4882a593Smuzhiyun 			     ilog2(OV5640_SCLK_ROOT_DIV));
1845*4882a593Smuzhiyun 	if (ret)
1846*4882a593Smuzhiyun 		return ret;
1847*4882a593Smuzhiyun 
1848*4882a593Smuzhiyun 	/* now restore the last capture mode */
1849*4882a593Smuzhiyun 	ret = ov5640_set_mode(sensor);
1850*4882a593Smuzhiyun 	if (ret < 0)
1851*4882a593Smuzhiyun 		return ret;
1852*4882a593Smuzhiyun 
1853*4882a593Smuzhiyun 	return ov5640_set_framefmt(sensor, &sensor->fmt);
1854*4882a593Smuzhiyun }
1855*4882a593Smuzhiyun 
ov5640_power(struct ov5640_dev * sensor,bool enable)1856*4882a593Smuzhiyun static void ov5640_power(struct ov5640_dev *sensor, bool enable)
1857*4882a593Smuzhiyun {
1858*4882a593Smuzhiyun 	gpiod_set_value_cansleep(sensor->pwdn_gpio, enable ? 0 : 1);
1859*4882a593Smuzhiyun }
1860*4882a593Smuzhiyun 
ov5640_reset(struct ov5640_dev * sensor)1861*4882a593Smuzhiyun static void ov5640_reset(struct ov5640_dev *sensor)
1862*4882a593Smuzhiyun {
1863*4882a593Smuzhiyun 	if (!sensor->reset_gpio)
1864*4882a593Smuzhiyun 		return;
1865*4882a593Smuzhiyun 
1866*4882a593Smuzhiyun 	gpiod_set_value_cansleep(sensor->reset_gpio, 0);
1867*4882a593Smuzhiyun 
1868*4882a593Smuzhiyun 	/* camera power cycle */
1869*4882a593Smuzhiyun 	ov5640_power(sensor, false);
1870*4882a593Smuzhiyun 	usleep_range(5000, 10000);
1871*4882a593Smuzhiyun 	ov5640_power(sensor, true);
1872*4882a593Smuzhiyun 	usleep_range(5000, 10000);
1873*4882a593Smuzhiyun 
1874*4882a593Smuzhiyun 	gpiod_set_value_cansleep(sensor->reset_gpio, 1);
1875*4882a593Smuzhiyun 	usleep_range(1000, 2000);
1876*4882a593Smuzhiyun 
1877*4882a593Smuzhiyun 	gpiod_set_value_cansleep(sensor->reset_gpio, 0);
1878*4882a593Smuzhiyun 	usleep_range(20000, 25000);
1879*4882a593Smuzhiyun }
1880*4882a593Smuzhiyun 
ov5640_set_power_on(struct ov5640_dev * sensor)1881*4882a593Smuzhiyun static int ov5640_set_power_on(struct ov5640_dev *sensor)
1882*4882a593Smuzhiyun {
1883*4882a593Smuzhiyun 	struct i2c_client *client = sensor->i2c_client;
1884*4882a593Smuzhiyun 	int ret;
1885*4882a593Smuzhiyun 
1886*4882a593Smuzhiyun 	ret = clk_prepare_enable(sensor->xclk);
1887*4882a593Smuzhiyun 	if (ret) {
1888*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: failed to enable clock\n",
1889*4882a593Smuzhiyun 			__func__);
1890*4882a593Smuzhiyun 		return ret;
1891*4882a593Smuzhiyun 	}
1892*4882a593Smuzhiyun 
1893*4882a593Smuzhiyun 	ret = regulator_bulk_enable(OV5640_NUM_SUPPLIES,
1894*4882a593Smuzhiyun 				    sensor->supplies);
1895*4882a593Smuzhiyun 	if (ret) {
1896*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: failed to enable regulators\n",
1897*4882a593Smuzhiyun 			__func__);
1898*4882a593Smuzhiyun 		goto xclk_off;
1899*4882a593Smuzhiyun 	}
1900*4882a593Smuzhiyun 
1901*4882a593Smuzhiyun 	ov5640_reset(sensor);
1902*4882a593Smuzhiyun 	ov5640_power(sensor, true);
1903*4882a593Smuzhiyun 
1904*4882a593Smuzhiyun 	ret = ov5640_init_slave_id(sensor);
1905*4882a593Smuzhiyun 	if (ret)
1906*4882a593Smuzhiyun 		goto power_off;
1907*4882a593Smuzhiyun 
1908*4882a593Smuzhiyun 	return 0;
1909*4882a593Smuzhiyun 
1910*4882a593Smuzhiyun power_off:
1911*4882a593Smuzhiyun 	ov5640_power(sensor, false);
1912*4882a593Smuzhiyun 	regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
1913*4882a593Smuzhiyun xclk_off:
1914*4882a593Smuzhiyun 	clk_disable_unprepare(sensor->xclk);
1915*4882a593Smuzhiyun 	return ret;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun 
ov5640_set_power_off(struct ov5640_dev * sensor)1918*4882a593Smuzhiyun static void ov5640_set_power_off(struct ov5640_dev *sensor)
1919*4882a593Smuzhiyun {
1920*4882a593Smuzhiyun 	ov5640_power(sensor, false);
1921*4882a593Smuzhiyun 	regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
1922*4882a593Smuzhiyun 	clk_disable_unprepare(sensor->xclk);
1923*4882a593Smuzhiyun }
1924*4882a593Smuzhiyun 
ov5640_set_power_mipi(struct ov5640_dev * sensor,bool on)1925*4882a593Smuzhiyun static int ov5640_set_power_mipi(struct ov5640_dev *sensor, bool on)
1926*4882a593Smuzhiyun {
1927*4882a593Smuzhiyun 	int ret;
1928*4882a593Smuzhiyun 
1929*4882a593Smuzhiyun 	if (!on) {
1930*4882a593Smuzhiyun 		/* Reset MIPI bus settings to their default values. */
1931*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x58);
1932*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_MIPI_CTRL00, 0x04);
1933*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT00, 0x00);
1934*4882a593Smuzhiyun 		return 0;
1935*4882a593Smuzhiyun 	}
1936*4882a593Smuzhiyun 
1937*4882a593Smuzhiyun 	/*
1938*4882a593Smuzhiyun 	 * Power up MIPI HS Tx and LS Rx; 2 data lanes mode
1939*4882a593Smuzhiyun 	 *
1940*4882a593Smuzhiyun 	 * 0x300e = 0x40
1941*4882a593Smuzhiyun 	 * [7:5] = 010	: 2 data lanes mode (see FIXME note in
1942*4882a593Smuzhiyun 	 *		  "ov5640_set_stream_mipi()")
1943*4882a593Smuzhiyun 	 * [4] = 0	: Power up MIPI HS Tx
1944*4882a593Smuzhiyun 	 * [3] = 0	: Power up MIPI LS Rx
1945*4882a593Smuzhiyun 	 * [2] = 0	: MIPI interface disabled
1946*4882a593Smuzhiyun 	 */
1947*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x40);
1948*4882a593Smuzhiyun 	if (ret)
1949*4882a593Smuzhiyun 		return ret;
1950*4882a593Smuzhiyun 
1951*4882a593Smuzhiyun 	/*
1952*4882a593Smuzhiyun 	 * Gate clock and set LP11 in 'no packets mode' (idle)
1953*4882a593Smuzhiyun 	 *
1954*4882a593Smuzhiyun 	 * 0x4800 = 0x24
1955*4882a593Smuzhiyun 	 * [5] = 1	: Gate clock when 'no packets'
1956*4882a593Smuzhiyun 	 * [2] = 1	: MIPI bus in LP11 when 'no packets'
1957*4882a593Smuzhiyun 	 */
1958*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_MIPI_CTRL00, 0x24);
1959*4882a593Smuzhiyun 	if (ret)
1960*4882a593Smuzhiyun 		return ret;
1961*4882a593Smuzhiyun 
1962*4882a593Smuzhiyun 	/*
1963*4882a593Smuzhiyun 	 * Set data lanes and clock in LP11 when 'sleeping'
1964*4882a593Smuzhiyun 	 *
1965*4882a593Smuzhiyun 	 * 0x3019 = 0x70
1966*4882a593Smuzhiyun 	 * [6] = 1	: MIPI data lane 2 in LP11 when 'sleeping'
1967*4882a593Smuzhiyun 	 * [5] = 1	: MIPI data lane 1 in LP11 when 'sleeping'
1968*4882a593Smuzhiyun 	 * [4] = 1	: MIPI clock lane in LP11 when 'sleeping'
1969*4882a593Smuzhiyun 	 */
1970*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT00, 0x70);
1971*4882a593Smuzhiyun 	if (ret)
1972*4882a593Smuzhiyun 		return ret;
1973*4882a593Smuzhiyun 
1974*4882a593Smuzhiyun 	/* Give lanes some time to coax into LP11 state. */
1975*4882a593Smuzhiyun 	usleep_range(500, 1000);
1976*4882a593Smuzhiyun 
1977*4882a593Smuzhiyun 	return 0;
1978*4882a593Smuzhiyun }
1979*4882a593Smuzhiyun 
ov5640_set_power_dvp(struct ov5640_dev * sensor,bool on)1980*4882a593Smuzhiyun static int ov5640_set_power_dvp(struct ov5640_dev *sensor, bool on)
1981*4882a593Smuzhiyun {
1982*4882a593Smuzhiyun 	unsigned int flags = sensor->ep.bus.parallel.flags;
1983*4882a593Smuzhiyun 	bool bt656 = sensor->ep.bus_type == V4L2_MBUS_BT656;
1984*4882a593Smuzhiyun 	u8 polarities = 0;
1985*4882a593Smuzhiyun 	int ret;
1986*4882a593Smuzhiyun 
1987*4882a593Smuzhiyun 	if (!on) {
1988*4882a593Smuzhiyun 		/* Reset settings to their default values. */
1989*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00, 0x00);
1990*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x58);
1991*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, 0x20);
1992*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01, 0x00);
1993*4882a593Smuzhiyun 		ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE02, 0x00);
1994*4882a593Smuzhiyun 		return 0;
1995*4882a593Smuzhiyun 	}
1996*4882a593Smuzhiyun 
1997*4882a593Smuzhiyun 	/*
1998*4882a593Smuzhiyun 	 * Note about parallel port configuration.
1999*4882a593Smuzhiyun 	 *
2000*4882a593Smuzhiyun 	 * When configured in parallel mode, the OV5640 will
2001*4882a593Smuzhiyun 	 * output 10 bits data on DVP data lines [9:0].
2002*4882a593Smuzhiyun 	 * If only 8 bits data are wanted, the 8 bits data lines
2003*4882a593Smuzhiyun 	 * of the camera interface must be physically connected
2004*4882a593Smuzhiyun 	 * on the DVP data lines [9:2].
2005*4882a593Smuzhiyun 	 *
2006*4882a593Smuzhiyun 	 * Control lines polarity can be configured through
2007*4882a593Smuzhiyun 	 * devicetree endpoint control lines properties.
2008*4882a593Smuzhiyun 	 * If no endpoint control lines properties are set,
2009*4882a593Smuzhiyun 	 * polarity will be as below:
2010*4882a593Smuzhiyun 	 * - VSYNC:	active high
2011*4882a593Smuzhiyun 	 * - HREF:	active low
2012*4882a593Smuzhiyun 	 * - PCLK:	active low
2013*4882a593Smuzhiyun 	 *
2014*4882a593Smuzhiyun 	 * VSYNC & HREF are not configured if BT656 bus mode is selected
2015*4882a593Smuzhiyun 	 */
2016*4882a593Smuzhiyun 
2017*4882a593Smuzhiyun 	/*
2018*4882a593Smuzhiyun 	 * BT656 embedded synchronization configuration
2019*4882a593Smuzhiyun 	 *
2020*4882a593Smuzhiyun 	 * CCIR656 CTRL00
2021*4882a593Smuzhiyun 	 * - [7]:	SYNC code selection (0: auto generate sync code,
2022*4882a593Smuzhiyun 	 *		1: sync code from regs 0x4732-0x4735)
2023*4882a593Smuzhiyun 	 * - [6]:	f value in CCIR656 SYNC code when fixed f value
2024*4882a593Smuzhiyun 	 * - [5]:	Fixed f value
2025*4882a593Smuzhiyun 	 * - [4:3]:	Blank toggle data options (00: data=1'h040/1'h200,
2026*4882a593Smuzhiyun 	 *		01: data from regs 0x4736-0x4738, 10: always keep 0)
2027*4882a593Smuzhiyun 	 * - [1]:	Clip data disable
2028*4882a593Smuzhiyun 	 * - [0]:	CCIR656 mode enable
2029*4882a593Smuzhiyun 	 *
2030*4882a593Smuzhiyun 	 * Default CCIR656 SAV/EAV mode with default codes
2031*4882a593Smuzhiyun 	 * SAV=0xff000080 & EAV=0xff00009d is enabled here with settings:
2032*4882a593Smuzhiyun 	 * - CCIR656 mode enable
2033*4882a593Smuzhiyun 	 * - auto generation of sync codes
2034*4882a593Smuzhiyun 	 * - blank toggle data 1'h040/1'h200
2035*4882a593Smuzhiyun 	 * - clip reserved data (0x00 & 0xff changed to 0x01 & 0xfe)
2036*4882a593Smuzhiyun 	 */
2037*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00,
2038*4882a593Smuzhiyun 			       bt656 ? 0x01 : 0x00);
2039*4882a593Smuzhiyun 	if (ret)
2040*4882a593Smuzhiyun 		return ret;
2041*4882a593Smuzhiyun 
2042*4882a593Smuzhiyun 	/*
2043*4882a593Smuzhiyun 	 * configure parallel port control lines polarity
2044*4882a593Smuzhiyun 	 *
2045*4882a593Smuzhiyun 	 * POLARITY CTRL0
2046*4882a593Smuzhiyun 	 * - [5]:	PCLK polarity (0: active low, 1: active high)
2047*4882a593Smuzhiyun 	 * - [1]:	HREF polarity (0: active low, 1: active high)
2048*4882a593Smuzhiyun 	 * - [0]:	VSYNC polarity (mismatch here between
2049*4882a593Smuzhiyun 	 *		datasheet and hardware, 0 is active high
2050*4882a593Smuzhiyun 	 *		and 1 is active low...)
2051*4882a593Smuzhiyun 	 */
2052*4882a593Smuzhiyun 	if (!bt656) {
2053*4882a593Smuzhiyun 		if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2054*4882a593Smuzhiyun 			polarities |= BIT(1);
2055*4882a593Smuzhiyun 		if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
2056*4882a593Smuzhiyun 			polarities |= BIT(0);
2057*4882a593Smuzhiyun 	}
2058*4882a593Smuzhiyun 	if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2059*4882a593Smuzhiyun 		polarities |= BIT(5);
2060*4882a593Smuzhiyun 
2061*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, polarities);
2062*4882a593Smuzhiyun 	if (ret)
2063*4882a593Smuzhiyun 		return ret;
2064*4882a593Smuzhiyun 
2065*4882a593Smuzhiyun 	/*
2066*4882a593Smuzhiyun 	 * powerdown MIPI TX/RX PHY & enable DVP
2067*4882a593Smuzhiyun 	 *
2068*4882a593Smuzhiyun 	 * MIPI CONTROL 00
2069*4882a593Smuzhiyun 	 * [4] = 1	: Power down MIPI HS Tx
2070*4882a593Smuzhiyun 	 * [3] = 1	: Power down MIPI LS Rx
2071*4882a593Smuzhiyun 	 * [2] = 0	: DVP enable (MIPI disable)
2072*4882a593Smuzhiyun 	 */
2073*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x18);
2074*4882a593Smuzhiyun 	if (ret)
2075*4882a593Smuzhiyun 		return ret;
2076*4882a593Smuzhiyun 
2077*4882a593Smuzhiyun 	/*
2078*4882a593Smuzhiyun 	 * enable VSYNC/HREF/PCLK DVP control lines
2079*4882a593Smuzhiyun 	 * & D[9:6] DVP data lines
2080*4882a593Smuzhiyun 	 *
2081*4882a593Smuzhiyun 	 * PAD OUTPUT ENABLE 01
2082*4882a593Smuzhiyun 	 * - 6:		VSYNC output enable
2083*4882a593Smuzhiyun 	 * - 5:		HREF output enable
2084*4882a593Smuzhiyun 	 * - 4:		PCLK output enable
2085*4882a593Smuzhiyun 	 * - [3:0]:	D[9:6] output enable
2086*4882a593Smuzhiyun 	 */
2087*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01,
2088*4882a593Smuzhiyun 			       bt656 ? 0x1f : 0x7f);
2089*4882a593Smuzhiyun 	if (ret)
2090*4882a593Smuzhiyun 		return ret;
2091*4882a593Smuzhiyun 
2092*4882a593Smuzhiyun 	/*
2093*4882a593Smuzhiyun 	 * enable D[5:0] DVP data lines
2094*4882a593Smuzhiyun 	 *
2095*4882a593Smuzhiyun 	 * PAD OUTPUT ENABLE 02
2096*4882a593Smuzhiyun 	 * - [7:2]:	D[5:0] output enable
2097*4882a593Smuzhiyun 	 */
2098*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE02, 0xfc);
2099*4882a593Smuzhiyun }
2100*4882a593Smuzhiyun 
ov5640_set_power(struct ov5640_dev * sensor,bool on)2101*4882a593Smuzhiyun static int ov5640_set_power(struct ov5640_dev *sensor, bool on)
2102*4882a593Smuzhiyun {
2103*4882a593Smuzhiyun 	int ret = 0;
2104*4882a593Smuzhiyun 
2105*4882a593Smuzhiyun 	if (on) {
2106*4882a593Smuzhiyun 		ret = ov5640_set_power_on(sensor);
2107*4882a593Smuzhiyun 		if (ret)
2108*4882a593Smuzhiyun 			return ret;
2109*4882a593Smuzhiyun 
2110*4882a593Smuzhiyun 		ret = ov5640_restore_mode(sensor);
2111*4882a593Smuzhiyun 		if (ret)
2112*4882a593Smuzhiyun 			goto power_off;
2113*4882a593Smuzhiyun 	}
2114*4882a593Smuzhiyun 
2115*4882a593Smuzhiyun 	if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY)
2116*4882a593Smuzhiyun 		ret = ov5640_set_power_mipi(sensor, on);
2117*4882a593Smuzhiyun 	else
2118*4882a593Smuzhiyun 		ret = ov5640_set_power_dvp(sensor, on);
2119*4882a593Smuzhiyun 	if (ret)
2120*4882a593Smuzhiyun 		goto power_off;
2121*4882a593Smuzhiyun 
2122*4882a593Smuzhiyun 	if (!on)
2123*4882a593Smuzhiyun 		ov5640_set_power_off(sensor);
2124*4882a593Smuzhiyun 
2125*4882a593Smuzhiyun 	return 0;
2126*4882a593Smuzhiyun 
2127*4882a593Smuzhiyun power_off:
2128*4882a593Smuzhiyun 	ov5640_set_power_off(sensor);
2129*4882a593Smuzhiyun 	return ret;
2130*4882a593Smuzhiyun }
2131*4882a593Smuzhiyun 
2132*4882a593Smuzhiyun /* --------------- Subdev Operations --------------- */
2133*4882a593Smuzhiyun 
ov5640_s_power(struct v4l2_subdev * sd,int on)2134*4882a593Smuzhiyun static int ov5640_s_power(struct v4l2_subdev *sd, int on)
2135*4882a593Smuzhiyun {
2136*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2137*4882a593Smuzhiyun 	int ret = 0;
2138*4882a593Smuzhiyun 
2139*4882a593Smuzhiyun 	mutex_lock(&sensor->lock);
2140*4882a593Smuzhiyun 
2141*4882a593Smuzhiyun 	/*
2142*4882a593Smuzhiyun 	 * If the power count is modified from 0 to != 0 or from != 0 to 0,
2143*4882a593Smuzhiyun 	 * update the power state.
2144*4882a593Smuzhiyun 	 */
2145*4882a593Smuzhiyun 	if (sensor->power_count == !on) {
2146*4882a593Smuzhiyun 		ret = ov5640_set_power(sensor, !!on);
2147*4882a593Smuzhiyun 		if (ret)
2148*4882a593Smuzhiyun 			goto out;
2149*4882a593Smuzhiyun 	}
2150*4882a593Smuzhiyun 
2151*4882a593Smuzhiyun 	/* Update the power count. */
2152*4882a593Smuzhiyun 	sensor->power_count += on ? 1 : -1;
2153*4882a593Smuzhiyun 	WARN_ON(sensor->power_count < 0);
2154*4882a593Smuzhiyun out:
2155*4882a593Smuzhiyun 	mutex_unlock(&sensor->lock);
2156*4882a593Smuzhiyun 
2157*4882a593Smuzhiyun 	if (on && !ret && sensor->power_count == 1) {
2158*4882a593Smuzhiyun 		/* restore controls */
2159*4882a593Smuzhiyun 		ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
2160*4882a593Smuzhiyun 	}
2161*4882a593Smuzhiyun 
2162*4882a593Smuzhiyun 	return ret;
2163*4882a593Smuzhiyun }
2164*4882a593Smuzhiyun 
ov5640_try_frame_interval(struct ov5640_dev * sensor,struct v4l2_fract * fi,u32 width,u32 height)2165*4882a593Smuzhiyun static int ov5640_try_frame_interval(struct ov5640_dev *sensor,
2166*4882a593Smuzhiyun 				     struct v4l2_fract *fi,
2167*4882a593Smuzhiyun 				     u32 width, u32 height)
2168*4882a593Smuzhiyun {
2169*4882a593Smuzhiyun 	const struct ov5640_mode_info *mode;
2170*4882a593Smuzhiyun 	enum ov5640_frame_rate rate = OV5640_15_FPS;
2171*4882a593Smuzhiyun 	int minfps, maxfps, best_fps, fps;
2172*4882a593Smuzhiyun 	int i;
2173*4882a593Smuzhiyun 
2174*4882a593Smuzhiyun 	minfps = ov5640_framerates[OV5640_15_FPS];
2175*4882a593Smuzhiyun 	maxfps = ov5640_framerates[OV5640_60_FPS];
2176*4882a593Smuzhiyun 
2177*4882a593Smuzhiyun 	if (fi->numerator == 0) {
2178*4882a593Smuzhiyun 		fi->denominator = maxfps;
2179*4882a593Smuzhiyun 		fi->numerator = 1;
2180*4882a593Smuzhiyun 		rate = OV5640_60_FPS;
2181*4882a593Smuzhiyun 		goto find_mode;
2182*4882a593Smuzhiyun 	}
2183*4882a593Smuzhiyun 
2184*4882a593Smuzhiyun 	fps = clamp_val(DIV_ROUND_CLOSEST(fi->denominator, fi->numerator),
2185*4882a593Smuzhiyun 			minfps, maxfps);
2186*4882a593Smuzhiyun 
2187*4882a593Smuzhiyun 	best_fps = minfps;
2188*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(ov5640_framerates); i++) {
2189*4882a593Smuzhiyun 		int curr_fps = ov5640_framerates[i];
2190*4882a593Smuzhiyun 
2191*4882a593Smuzhiyun 		if (abs(curr_fps - fps) < abs(best_fps - fps)) {
2192*4882a593Smuzhiyun 			best_fps = curr_fps;
2193*4882a593Smuzhiyun 			rate = i;
2194*4882a593Smuzhiyun 		}
2195*4882a593Smuzhiyun 	}
2196*4882a593Smuzhiyun 
2197*4882a593Smuzhiyun 	fi->numerator = 1;
2198*4882a593Smuzhiyun 	fi->denominator = best_fps;
2199*4882a593Smuzhiyun 
2200*4882a593Smuzhiyun find_mode:
2201*4882a593Smuzhiyun 	mode = ov5640_find_mode(sensor, rate, width, height, false);
2202*4882a593Smuzhiyun 	return mode ? rate : -EINVAL;
2203*4882a593Smuzhiyun }
2204*4882a593Smuzhiyun 
ov5640_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)2205*4882a593Smuzhiyun static int ov5640_get_fmt(struct v4l2_subdev *sd,
2206*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
2207*4882a593Smuzhiyun 			  struct v4l2_subdev_format *format)
2208*4882a593Smuzhiyun {
2209*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2210*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *fmt;
2211*4882a593Smuzhiyun 
2212*4882a593Smuzhiyun 	if (format->pad != 0)
2213*4882a593Smuzhiyun 		return -EINVAL;
2214*4882a593Smuzhiyun 
2215*4882a593Smuzhiyun 	mutex_lock(&sensor->lock);
2216*4882a593Smuzhiyun 
2217*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
2218*4882a593Smuzhiyun 		fmt = v4l2_subdev_get_try_format(&sensor->sd, cfg,
2219*4882a593Smuzhiyun 						 format->pad);
2220*4882a593Smuzhiyun 	else
2221*4882a593Smuzhiyun 		fmt = &sensor->fmt;
2222*4882a593Smuzhiyun 
2223*4882a593Smuzhiyun 	format->format = *fmt;
2224*4882a593Smuzhiyun 
2225*4882a593Smuzhiyun 	mutex_unlock(&sensor->lock);
2226*4882a593Smuzhiyun 
2227*4882a593Smuzhiyun 	return 0;
2228*4882a593Smuzhiyun }
2229*4882a593Smuzhiyun 
ov5640_try_fmt_internal(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * fmt,enum ov5640_frame_rate fr,const struct ov5640_mode_info ** new_mode)2230*4882a593Smuzhiyun static int ov5640_try_fmt_internal(struct v4l2_subdev *sd,
2231*4882a593Smuzhiyun 				   struct v4l2_mbus_framefmt *fmt,
2232*4882a593Smuzhiyun 				   enum ov5640_frame_rate fr,
2233*4882a593Smuzhiyun 				   const struct ov5640_mode_info **new_mode)
2234*4882a593Smuzhiyun {
2235*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2236*4882a593Smuzhiyun 	const struct ov5640_mode_info *mode;
2237*4882a593Smuzhiyun 	int i;
2238*4882a593Smuzhiyun 
2239*4882a593Smuzhiyun 	mode = ov5640_find_mode(sensor, fr, fmt->width, fmt->height, true);
2240*4882a593Smuzhiyun 	if (!mode)
2241*4882a593Smuzhiyun 		return -EINVAL;
2242*4882a593Smuzhiyun 	fmt->width = mode->hact;
2243*4882a593Smuzhiyun 	fmt->height = mode->vact;
2244*4882a593Smuzhiyun 
2245*4882a593Smuzhiyun 	if (new_mode)
2246*4882a593Smuzhiyun 		*new_mode = mode;
2247*4882a593Smuzhiyun 
2248*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(ov5640_formats); i++)
2249*4882a593Smuzhiyun 		if (ov5640_formats[i].code == fmt->code)
2250*4882a593Smuzhiyun 			break;
2251*4882a593Smuzhiyun 	if (i >= ARRAY_SIZE(ov5640_formats))
2252*4882a593Smuzhiyun 		i = 0;
2253*4882a593Smuzhiyun 
2254*4882a593Smuzhiyun 	fmt->code = ov5640_formats[i].code;
2255*4882a593Smuzhiyun 	fmt->colorspace = ov5640_formats[i].colorspace;
2256*4882a593Smuzhiyun 	fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
2257*4882a593Smuzhiyun 	fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
2258*4882a593Smuzhiyun 	fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
2259*4882a593Smuzhiyun 
2260*4882a593Smuzhiyun 	return 0;
2261*4882a593Smuzhiyun }
2262*4882a593Smuzhiyun 
ov5640_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * format)2263*4882a593Smuzhiyun static int ov5640_set_fmt(struct v4l2_subdev *sd,
2264*4882a593Smuzhiyun 			  struct v4l2_subdev_pad_config *cfg,
2265*4882a593Smuzhiyun 			  struct v4l2_subdev_format *format)
2266*4882a593Smuzhiyun {
2267*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2268*4882a593Smuzhiyun 	const struct ov5640_mode_info *new_mode;
2269*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
2270*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *fmt;
2271*4882a593Smuzhiyun 	int ret;
2272*4882a593Smuzhiyun 
2273*4882a593Smuzhiyun 	if (format->pad != 0)
2274*4882a593Smuzhiyun 		return -EINVAL;
2275*4882a593Smuzhiyun 
2276*4882a593Smuzhiyun 	mutex_lock(&sensor->lock);
2277*4882a593Smuzhiyun 
2278*4882a593Smuzhiyun 	if (sensor->streaming) {
2279*4882a593Smuzhiyun 		ret = -EBUSY;
2280*4882a593Smuzhiyun 		goto out;
2281*4882a593Smuzhiyun 	}
2282*4882a593Smuzhiyun 
2283*4882a593Smuzhiyun 	ret = ov5640_try_fmt_internal(sd, mbus_fmt,
2284*4882a593Smuzhiyun 				      sensor->current_fr, &new_mode);
2285*4882a593Smuzhiyun 	if (ret)
2286*4882a593Smuzhiyun 		goto out;
2287*4882a593Smuzhiyun 
2288*4882a593Smuzhiyun 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
2289*4882a593Smuzhiyun 		fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
2290*4882a593Smuzhiyun 	else
2291*4882a593Smuzhiyun 		fmt = &sensor->fmt;
2292*4882a593Smuzhiyun 
2293*4882a593Smuzhiyun 	*fmt = *mbus_fmt;
2294*4882a593Smuzhiyun 
2295*4882a593Smuzhiyun 	if (new_mode != sensor->current_mode) {
2296*4882a593Smuzhiyun 		sensor->current_mode = new_mode;
2297*4882a593Smuzhiyun 		sensor->pending_mode_change = true;
2298*4882a593Smuzhiyun 	}
2299*4882a593Smuzhiyun 	if (mbus_fmt->code != sensor->fmt.code)
2300*4882a593Smuzhiyun 		sensor->pending_fmt_change = true;
2301*4882a593Smuzhiyun 
2302*4882a593Smuzhiyun 	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
2303*4882a593Smuzhiyun 				 ov5640_calc_pixel_rate(sensor));
2304*4882a593Smuzhiyun out:
2305*4882a593Smuzhiyun 	mutex_unlock(&sensor->lock);
2306*4882a593Smuzhiyun 	return ret;
2307*4882a593Smuzhiyun }
2308*4882a593Smuzhiyun 
ov5640_set_framefmt(struct ov5640_dev * sensor,struct v4l2_mbus_framefmt * format)2309*4882a593Smuzhiyun static int ov5640_set_framefmt(struct ov5640_dev *sensor,
2310*4882a593Smuzhiyun 			       struct v4l2_mbus_framefmt *format)
2311*4882a593Smuzhiyun {
2312*4882a593Smuzhiyun 	int ret = 0;
2313*4882a593Smuzhiyun 	bool is_jpeg = false;
2314*4882a593Smuzhiyun 	u8 fmt, mux;
2315*4882a593Smuzhiyun 
2316*4882a593Smuzhiyun 	switch (format->code) {
2317*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_UYVY8_2X8:
2318*4882a593Smuzhiyun 		/* YUV422, UYVY */
2319*4882a593Smuzhiyun 		fmt = 0x3f;
2320*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_YUV422;
2321*4882a593Smuzhiyun 		break;
2322*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_YUYV8_2X8:
2323*4882a593Smuzhiyun 		/* YUV422, YUYV */
2324*4882a593Smuzhiyun 		fmt = 0x30;
2325*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_YUV422;
2326*4882a593Smuzhiyun 		break;
2327*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB565_2X8_LE:
2328*4882a593Smuzhiyun 		/* RGB565 {g[2:0],b[4:0]},{r[4:0],g[5:3]} */
2329*4882a593Smuzhiyun 		fmt = 0x6F;
2330*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_RGB;
2331*4882a593Smuzhiyun 		break;
2332*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_RGB565_2X8_BE:
2333*4882a593Smuzhiyun 		/* RGB565 {r[4:0],g[5:3]},{g[2:0],b[4:0]} */
2334*4882a593Smuzhiyun 		fmt = 0x61;
2335*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_RGB;
2336*4882a593Smuzhiyun 		break;
2337*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_JPEG_1X8:
2338*4882a593Smuzhiyun 		/* YUV422, YUYV */
2339*4882a593Smuzhiyun 		fmt = 0x30;
2340*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_YUV422;
2341*4882a593Smuzhiyun 		is_jpeg = true;
2342*4882a593Smuzhiyun 		break;
2343*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SBGGR8_1X8:
2344*4882a593Smuzhiyun 		/* Raw, BGBG... / GRGR... */
2345*4882a593Smuzhiyun 		fmt = 0x00;
2346*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_RAW_DPC;
2347*4882a593Smuzhiyun 		break;
2348*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SGBRG8_1X8:
2349*4882a593Smuzhiyun 		/* Raw bayer, GBGB... / RGRG... */
2350*4882a593Smuzhiyun 		fmt = 0x01;
2351*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_RAW_DPC;
2352*4882a593Smuzhiyun 		break;
2353*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SGRBG8_1X8:
2354*4882a593Smuzhiyun 		/* Raw bayer, GRGR... / BGBG... */
2355*4882a593Smuzhiyun 		fmt = 0x02;
2356*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_RAW_DPC;
2357*4882a593Smuzhiyun 		break;
2358*4882a593Smuzhiyun 	case MEDIA_BUS_FMT_SRGGB8_1X8:
2359*4882a593Smuzhiyun 		/* Raw bayer, RGRG... / GBGB... */
2360*4882a593Smuzhiyun 		fmt = 0x03;
2361*4882a593Smuzhiyun 		mux = OV5640_FMT_MUX_RAW_DPC;
2362*4882a593Smuzhiyun 		break;
2363*4882a593Smuzhiyun 	default:
2364*4882a593Smuzhiyun 		return -EINVAL;
2365*4882a593Smuzhiyun 	}
2366*4882a593Smuzhiyun 
2367*4882a593Smuzhiyun 	/* FORMAT CONTROL00: YUV and RGB formatting */
2368*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_FORMAT_CONTROL00, fmt);
2369*4882a593Smuzhiyun 	if (ret)
2370*4882a593Smuzhiyun 		return ret;
2371*4882a593Smuzhiyun 
2372*4882a593Smuzhiyun 	/* FORMAT MUX CONTROL: ISP YUV or RGB */
2373*4882a593Smuzhiyun 	ret = ov5640_write_reg(sensor, OV5640_REG_ISP_FORMAT_MUX_CTRL, mux);
2374*4882a593Smuzhiyun 	if (ret)
2375*4882a593Smuzhiyun 		return ret;
2376*4882a593Smuzhiyun 
2377*4882a593Smuzhiyun 	/*
2378*4882a593Smuzhiyun 	 * TIMING TC REG21:
2379*4882a593Smuzhiyun 	 * - [5]:	JPEG enable
2380*4882a593Smuzhiyun 	 */
2381*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
2382*4882a593Smuzhiyun 			     BIT(5), is_jpeg ? BIT(5) : 0);
2383*4882a593Smuzhiyun 	if (ret)
2384*4882a593Smuzhiyun 		return ret;
2385*4882a593Smuzhiyun 
2386*4882a593Smuzhiyun 	/*
2387*4882a593Smuzhiyun 	 * SYSTEM RESET02:
2388*4882a593Smuzhiyun 	 * - [4]:	Reset JFIFO
2389*4882a593Smuzhiyun 	 * - [3]:	Reset SFIFO
2390*4882a593Smuzhiyun 	 * - [2]:	Reset JPEG
2391*4882a593Smuzhiyun 	 */
2392*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_RESET02,
2393*4882a593Smuzhiyun 			     BIT(4) | BIT(3) | BIT(2),
2394*4882a593Smuzhiyun 			     is_jpeg ? 0 : (BIT(4) | BIT(3) | BIT(2)));
2395*4882a593Smuzhiyun 	if (ret)
2396*4882a593Smuzhiyun 		return ret;
2397*4882a593Smuzhiyun 
2398*4882a593Smuzhiyun 	/*
2399*4882a593Smuzhiyun 	 * CLOCK ENABLE02:
2400*4882a593Smuzhiyun 	 * - [5]:	Enable JPEG 2x clock
2401*4882a593Smuzhiyun 	 * - [3]:	Enable JPEG clock
2402*4882a593Smuzhiyun 	 */
2403*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE02,
2404*4882a593Smuzhiyun 			      BIT(5) | BIT(3),
2405*4882a593Smuzhiyun 			      is_jpeg ? (BIT(5) | BIT(3)) : 0);
2406*4882a593Smuzhiyun }
2407*4882a593Smuzhiyun 
2408*4882a593Smuzhiyun /*
2409*4882a593Smuzhiyun  * Sensor Controls.
2410*4882a593Smuzhiyun  */
2411*4882a593Smuzhiyun 
ov5640_set_ctrl_hue(struct ov5640_dev * sensor,int value)2412*4882a593Smuzhiyun static int ov5640_set_ctrl_hue(struct ov5640_dev *sensor, int value)
2413*4882a593Smuzhiyun {
2414*4882a593Smuzhiyun 	int ret;
2415*4882a593Smuzhiyun 
2416*4882a593Smuzhiyun 	if (value) {
2417*4882a593Smuzhiyun 		ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
2418*4882a593Smuzhiyun 				     BIT(0), BIT(0));
2419*4882a593Smuzhiyun 		if (ret)
2420*4882a593Smuzhiyun 			return ret;
2421*4882a593Smuzhiyun 		ret = ov5640_write_reg16(sensor, OV5640_REG_SDE_CTRL1, value);
2422*4882a593Smuzhiyun 	} else {
2423*4882a593Smuzhiyun 		ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(0), 0);
2424*4882a593Smuzhiyun 	}
2425*4882a593Smuzhiyun 
2426*4882a593Smuzhiyun 	return ret;
2427*4882a593Smuzhiyun }
2428*4882a593Smuzhiyun 
ov5640_set_ctrl_contrast(struct ov5640_dev * sensor,int value)2429*4882a593Smuzhiyun static int ov5640_set_ctrl_contrast(struct ov5640_dev *sensor, int value)
2430*4882a593Smuzhiyun {
2431*4882a593Smuzhiyun 	int ret;
2432*4882a593Smuzhiyun 
2433*4882a593Smuzhiyun 	if (value) {
2434*4882a593Smuzhiyun 		ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
2435*4882a593Smuzhiyun 				     BIT(2), BIT(2));
2436*4882a593Smuzhiyun 		if (ret)
2437*4882a593Smuzhiyun 			return ret;
2438*4882a593Smuzhiyun 		ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL5,
2439*4882a593Smuzhiyun 				       value & 0xff);
2440*4882a593Smuzhiyun 	} else {
2441*4882a593Smuzhiyun 		ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(2), 0);
2442*4882a593Smuzhiyun 	}
2443*4882a593Smuzhiyun 
2444*4882a593Smuzhiyun 	return ret;
2445*4882a593Smuzhiyun }
2446*4882a593Smuzhiyun 
ov5640_set_ctrl_saturation(struct ov5640_dev * sensor,int value)2447*4882a593Smuzhiyun static int ov5640_set_ctrl_saturation(struct ov5640_dev *sensor, int value)
2448*4882a593Smuzhiyun {
2449*4882a593Smuzhiyun 	int ret;
2450*4882a593Smuzhiyun 
2451*4882a593Smuzhiyun 	if (value) {
2452*4882a593Smuzhiyun 		ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
2453*4882a593Smuzhiyun 				     BIT(1), BIT(1));
2454*4882a593Smuzhiyun 		if (ret)
2455*4882a593Smuzhiyun 			return ret;
2456*4882a593Smuzhiyun 		ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL3,
2457*4882a593Smuzhiyun 				       value & 0xff);
2458*4882a593Smuzhiyun 		if (ret)
2459*4882a593Smuzhiyun 			return ret;
2460*4882a593Smuzhiyun 		ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL4,
2461*4882a593Smuzhiyun 				       value & 0xff);
2462*4882a593Smuzhiyun 	} else {
2463*4882a593Smuzhiyun 		ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(1), 0);
2464*4882a593Smuzhiyun 	}
2465*4882a593Smuzhiyun 
2466*4882a593Smuzhiyun 	return ret;
2467*4882a593Smuzhiyun }
2468*4882a593Smuzhiyun 
ov5640_set_ctrl_white_balance(struct ov5640_dev * sensor,int awb)2469*4882a593Smuzhiyun static int ov5640_set_ctrl_white_balance(struct ov5640_dev *sensor, int awb)
2470*4882a593Smuzhiyun {
2471*4882a593Smuzhiyun 	int ret;
2472*4882a593Smuzhiyun 
2473*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_AWB_MANUAL_CTRL,
2474*4882a593Smuzhiyun 			     BIT(0), awb ? 0 : 1);
2475*4882a593Smuzhiyun 	if (ret)
2476*4882a593Smuzhiyun 		return ret;
2477*4882a593Smuzhiyun 
2478*4882a593Smuzhiyun 	if (!awb) {
2479*4882a593Smuzhiyun 		u16 red = (u16)sensor->ctrls.red_balance->val;
2480*4882a593Smuzhiyun 		u16 blue = (u16)sensor->ctrls.blue_balance->val;
2481*4882a593Smuzhiyun 
2482*4882a593Smuzhiyun 		ret = ov5640_write_reg16(sensor, OV5640_REG_AWB_R_GAIN, red);
2483*4882a593Smuzhiyun 		if (ret)
2484*4882a593Smuzhiyun 			return ret;
2485*4882a593Smuzhiyun 		ret = ov5640_write_reg16(sensor, OV5640_REG_AWB_B_GAIN, blue);
2486*4882a593Smuzhiyun 	}
2487*4882a593Smuzhiyun 
2488*4882a593Smuzhiyun 	return ret;
2489*4882a593Smuzhiyun }
2490*4882a593Smuzhiyun 
ov5640_set_ctrl_exposure(struct ov5640_dev * sensor,enum v4l2_exposure_auto_type auto_exposure)2491*4882a593Smuzhiyun static int ov5640_set_ctrl_exposure(struct ov5640_dev *sensor,
2492*4882a593Smuzhiyun 				    enum v4l2_exposure_auto_type auto_exposure)
2493*4882a593Smuzhiyun {
2494*4882a593Smuzhiyun 	struct ov5640_ctrls *ctrls = &sensor->ctrls;
2495*4882a593Smuzhiyun 	bool auto_exp = (auto_exposure == V4L2_EXPOSURE_AUTO);
2496*4882a593Smuzhiyun 	int ret = 0;
2497*4882a593Smuzhiyun 
2498*4882a593Smuzhiyun 	if (ctrls->auto_exp->is_new) {
2499*4882a593Smuzhiyun 		ret = ov5640_set_autoexposure(sensor, auto_exp);
2500*4882a593Smuzhiyun 		if (ret)
2501*4882a593Smuzhiyun 			return ret;
2502*4882a593Smuzhiyun 	}
2503*4882a593Smuzhiyun 
2504*4882a593Smuzhiyun 	if (!auto_exp && ctrls->exposure->is_new) {
2505*4882a593Smuzhiyun 		u16 max_exp;
2506*4882a593Smuzhiyun 
2507*4882a593Smuzhiyun 		ret = ov5640_read_reg16(sensor, OV5640_REG_AEC_PK_VTS,
2508*4882a593Smuzhiyun 					&max_exp);
2509*4882a593Smuzhiyun 		if (ret)
2510*4882a593Smuzhiyun 			return ret;
2511*4882a593Smuzhiyun 		ret = ov5640_get_vts(sensor);
2512*4882a593Smuzhiyun 		if (ret < 0)
2513*4882a593Smuzhiyun 			return ret;
2514*4882a593Smuzhiyun 		max_exp += ret;
2515*4882a593Smuzhiyun 		ret = 0;
2516*4882a593Smuzhiyun 
2517*4882a593Smuzhiyun 		if (ctrls->exposure->val < max_exp)
2518*4882a593Smuzhiyun 			ret = ov5640_set_exposure(sensor, ctrls->exposure->val);
2519*4882a593Smuzhiyun 	}
2520*4882a593Smuzhiyun 
2521*4882a593Smuzhiyun 	return ret;
2522*4882a593Smuzhiyun }
2523*4882a593Smuzhiyun 
ov5640_set_ctrl_gain(struct ov5640_dev * sensor,bool auto_gain)2524*4882a593Smuzhiyun static int ov5640_set_ctrl_gain(struct ov5640_dev *sensor, bool auto_gain)
2525*4882a593Smuzhiyun {
2526*4882a593Smuzhiyun 	struct ov5640_ctrls *ctrls = &sensor->ctrls;
2527*4882a593Smuzhiyun 	int ret = 0;
2528*4882a593Smuzhiyun 
2529*4882a593Smuzhiyun 	if (ctrls->auto_gain->is_new) {
2530*4882a593Smuzhiyun 		ret = ov5640_set_autogain(sensor, auto_gain);
2531*4882a593Smuzhiyun 		if (ret)
2532*4882a593Smuzhiyun 			return ret;
2533*4882a593Smuzhiyun 	}
2534*4882a593Smuzhiyun 
2535*4882a593Smuzhiyun 	if (!auto_gain && ctrls->gain->is_new)
2536*4882a593Smuzhiyun 		ret = ov5640_set_gain(sensor, ctrls->gain->val);
2537*4882a593Smuzhiyun 
2538*4882a593Smuzhiyun 	return ret;
2539*4882a593Smuzhiyun }
2540*4882a593Smuzhiyun 
2541*4882a593Smuzhiyun static const char * const test_pattern_menu[] = {
2542*4882a593Smuzhiyun 	"Disabled",
2543*4882a593Smuzhiyun 	"Color bars",
2544*4882a593Smuzhiyun 	"Color bars w/ rolling bar",
2545*4882a593Smuzhiyun 	"Color squares",
2546*4882a593Smuzhiyun 	"Color squares w/ rolling bar",
2547*4882a593Smuzhiyun };
2548*4882a593Smuzhiyun 
2549*4882a593Smuzhiyun #define OV5640_TEST_ENABLE		BIT(7)
2550*4882a593Smuzhiyun #define OV5640_TEST_ROLLING		BIT(6)	/* rolling horizontal bar */
2551*4882a593Smuzhiyun #define OV5640_TEST_TRANSPARENT		BIT(5)
2552*4882a593Smuzhiyun #define OV5640_TEST_SQUARE_BW		BIT(4)	/* black & white squares */
2553*4882a593Smuzhiyun #define OV5640_TEST_BAR_STANDARD	(0 << 2)
2554*4882a593Smuzhiyun #define OV5640_TEST_BAR_VERT_CHANGE_1	(1 << 2)
2555*4882a593Smuzhiyun #define OV5640_TEST_BAR_HOR_CHANGE	(2 << 2)
2556*4882a593Smuzhiyun #define OV5640_TEST_BAR_VERT_CHANGE_2	(3 << 2)
2557*4882a593Smuzhiyun #define OV5640_TEST_BAR			(0 << 0)
2558*4882a593Smuzhiyun #define OV5640_TEST_RANDOM		(1 << 0)
2559*4882a593Smuzhiyun #define OV5640_TEST_SQUARE		(2 << 0)
2560*4882a593Smuzhiyun #define OV5640_TEST_BLACK		(3 << 0)
2561*4882a593Smuzhiyun 
2562*4882a593Smuzhiyun static const u8 test_pattern_val[] = {
2563*4882a593Smuzhiyun 	0,
2564*4882a593Smuzhiyun 	OV5640_TEST_ENABLE | OV5640_TEST_BAR_VERT_CHANGE_1 |
2565*4882a593Smuzhiyun 		OV5640_TEST_BAR,
2566*4882a593Smuzhiyun 	OV5640_TEST_ENABLE | OV5640_TEST_ROLLING |
2567*4882a593Smuzhiyun 		OV5640_TEST_BAR_VERT_CHANGE_1 | OV5640_TEST_BAR,
2568*4882a593Smuzhiyun 	OV5640_TEST_ENABLE | OV5640_TEST_SQUARE,
2569*4882a593Smuzhiyun 	OV5640_TEST_ENABLE | OV5640_TEST_ROLLING | OV5640_TEST_SQUARE,
2570*4882a593Smuzhiyun };
2571*4882a593Smuzhiyun 
ov5640_set_ctrl_test_pattern(struct ov5640_dev * sensor,int value)2572*4882a593Smuzhiyun static int ov5640_set_ctrl_test_pattern(struct ov5640_dev *sensor, int value)
2573*4882a593Smuzhiyun {
2574*4882a593Smuzhiyun 	return ov5640_write_reg(sensor, OV5640_REG_PRE_ISP_TEST_SET1,
2575*4882a593Smuzhiyun 				test_pattern_val[value]);
2576*4882a593Smuzhiyun }
2577*4882a593Smuzhiyun 
ov5640_set_ctrl_light_freq(struct ov5640_dev * sensor,int value)2578*4882a593Smuzhiyun static int ov5640_set_ctrl_light_freq(struct ov5640_dev *sensor, int value)
2579*4882a593Smuzhiyun {
2580*4882a593Smuzhiyun 	int ret;
2581*4882a593Smuzhiyun 
2582*4882a593Smuzhiyun 	ret = ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL01, BIT(7),
2583*4882a593Smuzhiyun 			     (value == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) ?
2584*4882a593Smuzhiyun 			     0 : BIT(7));
2585*4882a593Smuzhiyun 	if (ret)
2586*4882a593Smuzhiyun 		return ret;
2587*4882a593Smuzhiyun 
2588*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL00, BIT(2),
2589*4882a593Smuzhiyun 			      (value == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
2590*4882a593Smuzhiyun 			      BIT(2) : 0);
2591*4882a593Smuzhiyun }
2592*4882a593Smuzhiyun 
ov5640_set_ctrl_hflip(struct ov5640_dev * sensor,int value)2593*4882a593Smuzhiyun static int ov5640_set_ctrl_hflip(struct ov5640_dev *sensor, int value)
2594*4882a593Smuzhiyun {
2595*4882a593Smuzhiyun 	/*
2596*4882a593Smuzhiyun 	 * If sensor is mounted upside down, mirror logic is inversed.
2597*4882a593Smuzhiyun 	 *
2598*4882a593Smuzhiyun 	 * Sensor is a BSI (Back Side Illuminated) one,
2599*4882a593Smuzhiyun 	 * so image captured is physically mirrored.
2600*4882a593Smuzhiyun 	 * This is why mirror logic is inversed in
2601*4882a593Smuzhiyun 	 * order to cancel this mirror effect.
2602*4882a593Smuzhiyun 	 */
2603*4882a593Smuzhiyun 
2604*4882a593Smuzhiyun 	/*
2605*4882a593Smuzhiyun 	 * TIMING TC REG21:
2606*4882a593Smuzhiyun 	 * - [2]:	ISP mirror
2607*4882a593Smuzhiyun 	 * - [1]:	Sensor mirror
2608*4882a593Smuzhiyun 	 */
2609*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
2610*4882a593Smuzhiyun 			      BIT(2) | BIT(1),
2611*4882a593Smuzhiyun 			      (!(value ^ sensor->upside_down)) ?
2612*4882a593Smuzhiyun 			      (BIT(2) | BIT(1)) : 0);
2613*4882a593Smuzhiyun }
2614*4882a593Smuzhiyun 
ov5640_set_ctrl_vflip(struct ov5640_dev * sensor,int value)2615*4882a593Smuzhiyun static int ov5640_set_ctrl_vflip(struct ov5640_dev *sensor, int value)
2616*4882a593Smuzhiyun {
2617*4882a593Smuzhiyun 	/* If sensor is mounted upside down, flip logic is inversed */
2618*4882a593Smuzhiyun 
2619*4882a593Smuzhiyun 	/*
2620*4882a593Smuzhiyun 	 * TIMING TC REG20:
2621*4882a593Smuzhiyun 	 * - [2]:	ISP vflip
2622*4882a593Smuzhiyun 	 * - [1]:	Sensor vflip
2623*4882a593Smuzhiyun 	 */
2624*4882a593Smuzhiyun 	return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG20,
2625*4882a593Smuzhiyun 			      BIT(2) | BIT(1),
2626*4882a593Smuzhiyun 			      (value ^ sensor->upside_down) ?
2627*4882a593Smuzhiyun 			      (BIT(2) | BIT(1)) : 0);
2628*4882a593Smuzhiyun }
2629*4882a593Smuzhiyun 
ov5640_g_volatile_ctrl(struct v4l2_ctrl * ctrl)2630*4882a593Smuzhiyun static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
2631*4882a593Smuzhiyun {
2632*4882a593Smuzhiyun 	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
2633*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2634*4882a593Smuzhiyun 	int val;
2635*4882a593Smuzhiyun 
2636*4882a593Smuzhiyun 	/* v4l2_ctrl_lock() locks our own mutex */
2637*4882a593Smuzhiyun 
2638*4882a593Smuzhiyun 	switch (ctrl->id) {
2639*4882a593Smuzhiyun 	case V4L2_CID_AUTOGAIN:
2640*4882a593Smuzhiyun 		val = ov5640_get_gain(sensor);
2641*4882a593Smuzhiyun 		if (val < 0)
2642*4882a593Smuzhiyun 			return val;
2643*4882a593Smuzhiyun 		sensor->ctrls.gain->val = val;
2644*4882a593Smuzhiyun 		break;
2645*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE_AUTO:
2646*4882a593Smuzhiyun 		val = ov5640_get_exposure(sensor);
2647*4882a593Smuzhiyun 		if (val < 0)
2648*4882a593Smuzhiyun 			return val;
2649*4882a593Smuzhiyun 		sensor->ctrls.exposure->val = val;
2650*4882a593Smuzhiyun 		break;
2651*4882a593Smuzhiyun 	}
2652*4882a593Smuzhiyun 
2653*4882a593Smuzhiyun 	return 0;
2654*4882a593Smuzhiyun }
2655*4882a593Smuzhiyun 
ov5640_s_ctrl(struct v4l2_ctrl * ctrl)2656*4882a593Smuzhiyun static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
2657*4882a593Smuzhiyun {
2658*4882a593Smuzhiyun 	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
2659*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2660*4882a593Smuzhiyun 	int ret;
2661*4882a593Smuzhiyun 
2662*4882a593Smuzhiyun 	/* v4l2_ctrl_lock() locks our own mutex */
2663*4882a593Smuzhiyun 
2664*4882a593Smuzhiyun 	/*
2665*4882a593Smuzhiyun 	 * If the device is not powered up by the host driver do
2666*4882a593Smuzhiyun 	 * not apply any controls to H/W at this time. Instead
2667*4882a593Smuzhiyun 	 * the controls will be restored right after power-up.
2668*4882a593Smuzhiyun 	 */
2669*4882a593Smuzhiyun 	if (sensor->power_count == 0)
2670*4882a593Smuzhiyun 		return 0;
2671*4882a593Smuzhiyun 
2672*4882a593Smuzhiyun 	switch (ctrl->id) {
2673*4882a593Smuzhiyun 	case V4L2_CID_AUTOGAIN:
2674*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_gain(sensor, ctrl->val);
2675*4882a593Smuzhiyun 		break;
2676*4882a593Smuzhiyun 	case V4L2_CID_EXPOSURE_AUTO:
2677*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_exposure(sensor, ctrl->val);
2678*4882a593Smuzhiyun 		break;
2679*4882a593Smuzhiyun 	case V4L2_CID_AUTO_WHITE_BALANCE:
2680*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_white_balance(sensor, ctrl->val);
2681*4882a593Smuzhiyun 		break;
2682*4882a593Smuzhiyun 	case V4L2_CID_HUE:
2683*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_hue(sensor, ctrl->val);
2684*4882a593Smuzhiyun 		break;
2685*4882a593Smuzhiyun 	case V4L2_CID_CONTRAST:
2686*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_contrast(sensor, ctrl->val);
2687*4882a593Smuzhiyun 		break;
2688*4882a593Smuzhiyun 	case V4L2_CID_SATURATION:
2689*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_saturation(sensor, ctrl->val);
2690*4882a593Smuzhiyun 		break;
2691*4882a593Smuzhiyun 	case V4L2_CID_TEST_PATTERN:
2692*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_test_pattern(sensor, ctrl->val);
2693*4882a593Smuzhiyun 		break;
2694*4882a593Smuzhiyun 	case V4L2_CID_POWER_LINE_FREQUENCY:
2695*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_light_freq(sensor, ctrl->val);
2696*4882a593Smuzhiyun 		break;
2697*4882a593Smuzhiyun 	case V4L2_CID_HFLIP:
2698*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_hflip(sensor, ctrl->val);
2699*4882a593Smuzhiyun 		break;
2700*4882a593Smuzhiyun 	case V4L2_CID_VFLIP:
2701*4882a593Smuzhiyun 		ret = ov5640_set_ctrl_vflip(sensor, ctrl->val);
2702*4882a593Smuzhiyun 		break;
2703*4882a593Smuzhiyun 	default:
2704*4882a593Smuzhiyun 		ret = -EINVAL;
2705*4882a593Smuzhiyun 		break;
2706*4882a593Smuzhiyun 	}
2707*4882a593Smuzhiyun 
2708*4882a593Smuzhiyun 	return ret;
2709*4882a593Smuzhiyun }
2710*4882a593Smuzhiyun 
2711*4882a593Smuzhiyun static const struct v4l2_ctrl_ops ov5640_ctrl_ops = {
2712*4882a593Smuzhiyun 	.g_volatile_ctrl = ov5640_g_volatile_ctrl,
2713*4882a593Smuzhiyun 	.s_ctrl = ov5640_s_ctrl,
2714*4882a593Smuzhiyun };
2715*4882a593Smuzhiyun 
ov5640_init_controls(struct ov5640_dev * sensor)2716*4882a593Smuzhiyun static int ov5640_init_controls(struct ov5640_dev *sensor)
2717*4882a593Smuzhiyun {
2718*4882a593Smuzhiyun 	const struct v4l2_ctrl_ops *ops = &ov5640_ctrl_ops;
2719*4882a593Smuzhiyun 	struct ov5640_ctrls *ctrls = &sensor->ctrls;
2720*4882a593Smuzhiyun 	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
2721*4882a593Smuzhiyun 	int ret;
2722*4882a593Smuzhiyun 
2723*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(hdl, 32);
2724*4882a593Smuzhiyun 
2725*4882a593Smuzhiyun 	/* we can use our own mutex for the ctrl lock */
2726*4882a593Smuzhiyun 	hdl->lock = &sensor->lock;
2727*4882a593Smuzhiyun 
2728*4882a593Smuzhiyun 	/* Clock related controls */
2729*4882a593Smuzhiyun 	ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
2730*4882a593Smuzhiyun 					      0, INT_MAX, 1,
2731*4882a593Smuzhiyun 					      ov5640_calc_pixel_rate(sensor));
2732*4882a593Smuzhiyun 
2733*4882a593Smuzhiyun 	/* Auto/manual white balance */
2734*4882a593Smuzhiyun 	ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
2735*4882a593Smuzhiyun 					   V4L2_CID_AUTO_WHITE_BALANCE,
2736*4882a593Smuzhiyun 					   0, 1, 1, 1);
2737*4882a593Smuzhiyun 	ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
2738*4882a593Smuzhiyun 						0, 4095, 1, 0);
2739*4882a593Smuzhiyun 	ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
2740*4882a593Smuzhiyun 					       0, 4095, 1, 0);
2741*4882a593Smuzhiyun 	/* Auto/manual exposure */
2742*4882a593Smuzhiyun 	ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
2743*4882a593Smuzhiyun 						 V4L2_CID_EXPOSURE_AUTO,
2744*4882a593Smuzhiyun 						 V4L2_EXPOSURE_MANUAL, 0,
2745*4882a593Smuzhiyun 						 V4L2_EXPOSURE_AUTO);
2746*4882a593Smuzhiyun 	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
2747*4882a593Smuzhiyun 					    0, 65535, 1, 0);
2748*4882a593Smuzhiyun 	/* Auto/manual gain */
2749*4882a593Smuzhiyun 	ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN,
2750*4882a593Smuzhiyun 					     0, 1, 1, 1);
2751*4882a593Smuzhiyun 	ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
2752*4882a593Smuzhiyun 					0, 1023, 1, 0);
2753*4882a593Smuzhiyun 
2754*4882a593Smuzhiyun 	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
2755*4882a593Smuzhiyun 					      0, 255, 1, 64);
2756*4882a593Smuzhiyun 	ctrls->hue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE,
2757*4882a593Smuzhiyun 				       0, 359, 1, 0);
2758*4882a593Smuzhiyun 	ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
2759*4882a593Smuzhiyun 					    0, 255, 1, 0);
2760*4882a593Smuzhiyun 	ctrls->test_pattern =
2761*4882a593Smuzhiyun 		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
2762*4882a593Smuzhiyun 					     ARRAY_SIZE(test_pattern_menu) - 1,
2763*4882a593Smuzhiyun 					     0, 0, test_pattern_menu);
2764*4882a593Smuzhiyun 	ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP,
2765*4882a593Smuzhiyun 					 0, 1, 1, 0);
2766*4882a593Smuzhiyun 	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP,
2767*4882a593Smuzhiyun 					 0, 1, 1, 0);
2768*4882a593Smuzhiyun 
2769*4882a593Smuzhiyun 	ctrls->light_freq =
2770*4882a593Smuzhiyun 		v4l2_ctrl_new_std_menu(hdl, ops,
2771*4882a593Smuzhiyun 				       V4L2_CID_POWER_LINE_FREQUENCY,
2772*4882a593Smuzhiyun 				       V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
2773*4882a593Smuzhiyun 				       V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
2774*4882a593Smuzhiyun 
2775*4882a593Smuzhiyun 	if (hdl->error) {
2776*4882a593Smuzhiyun 		ret = hdl->error;
2777*4882a593Smuzhiyun 		goto free_ctrls;
2778*4882a593Smuzhiyun 	}
2779*4882a593Smuzhiyun 
2780*4882a593Smuzhiyun 	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
2781*4882a593Smuzhiyun 	ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
2782*4882a593Smuzhiyun 	ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
2783*4882a593Smuzhiyun 
2784*4882a593Smuzhiyun 	v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
2785*4882a593Smuzhiyun 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
2786*4882a593Smuzhiyun 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
2787*4882a593Smuzhiyun 
2788*4882a593Smuzhiyun 	sensor->sd.ctrl_handler = hdl;
2789*4882a593Smuzhiyun 	return 0;
2790*4882a593Smuzhiyun 
2791*4882a593Smuzhiyun free_ctrls:
2792*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(hdl);
2793*4882a593Smuzhiyun 	return ret;
2794*4882a593Smuzhiyun }
2795*4882a593Smuzhiyun 
ov5640_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)2796*4882a593Smuzhiyun static int ov5640_enum_frame_size(struct v4l2_subdev *sd,
2797*4882a593Smuzhiyun 				  struct v4l2_subdev_pad_config *cfg,
2798*4882a593Smuzhiyun 				  struct v4l2_subdev_frame_size_enum *fse)
2799*4882a593Smuzhiyun {
2800*4882a593Smuzhiyun 	if (fse->pad != 0)
2801*4882a593Smuzhiyun 		return -EINVAL;
2802*4882a593Smuzhiyun 	if (fse->index >= OV5640_NUM_MODES)
2803*4882a593Smuzhiyun 		return -EINVAL;
2804*4882a593Smuzhiyun 
2805*4882a593Smuzhiyun 	fse->min_width =
2806*4882a593Smuzhiyun 		ov5640_mode_data[fse->index].hact;
2807*4882a593Smuzhiyun 	fse->max_width = fse->min_width;
2808*4882a593Smuzhiyun 	fse->min_height =
2809*4882a593Smuzhiyun 		ov5640_mode_data[fse->index].vact;
2810*4882a593Smuzhiyun 	fse->max_height = fse->min_height;
2811*4882a593Smuzhiyun 
2812*4882a593Smuzhiyun 	return 0;
2813*4882a593Smuzhiyun }
2814*4882a593Smuzhiyun 
ov5640_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)2815*4882a593Smuzhiyun static int ov5640_enum_frame_interval(
2816*4882a593Smuzhiyun 	struct v4l2_subdev *sd,
2817*4882a593Smuzhiyun 	struct v4l2_subdev_pad_config *cfg,
2818*4882a593Smuzhiyun 	struct v4l2_subdev_frame_interval_enum *fie)
2819*4882a593Smuzhiyun {
2820*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2821*4882a593Smuzhiyun 	struct v4l2_fract tpf;
2822*4882a593Smuzhiyun 	int ret;
2823*4882a593Smuzhiyun 
2824*4882a593Smuzhiyun 	if (fie->pad != 0)
2825*4882a593Smuzhiyun 		return -EINVAL;
2826*4882a593Smuzhiyun 	if (fie->index >= OV5640_NUM_FRAMERATES)
2827*4882a593Smuzhiyun 		return -EINVAL;
2828*4882a593Smuzhiyun 
2829*4882a593Smuzhiyun 	tpf.numerator = 1;
2830*4882a593Smuzhiyun 	tpf.denominator = ov5640_framerates[fie->index];
2831*4882a593Smuzhiyun 
2832*4882a593Smuzhiyun 	ret = ov5640_try_frame_interval(sensor, &tpf,
2833*4882a593Smuzhiyun 					fie->width, fie->height);
2834*4882a593Smuzhiyun 	if (ret < 0)
2835*4882a593Smuzhiyun 		return -EINVAL;
2836*4882a593Smuzhiyun 
2837*4882a593Smuzhiyun 	fie->interval = tpf;
2838*4882a593Smuzhiyun 	return 0;
2839*4882a593Smuzhiyun }
2840*4882a593Smuzhiyun 
ov5640_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)2841*4882a593Smuzhiyun static int ov5640_g_frame_interval(struct v4l2_subdev *sd,
2842*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_interval *fi)
2843*4882a593Smuzhiyun {
2844*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2845*4882a593Smuzhiyun 
2846*4882a593Smuzhiyun 	mutex_lock(&sensor->lock);
2847*4882a593Smuzhiyun 	fi->interval = sensor->frame_interval;
2848*4882a593Smuzhiyun 	mutex_unlock(&sensor->lock);
2849*4882a593Smuzhiyun 
2850*4882a593Smuzhiyun 	return 0;
2851*4882a593Smuzhiyun }
2852*4882a593Smuzhiyun 
ov5640_s_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)2853*4882a593Smuzhiyun static int ov5640_s_frame_interval(struct v4l2_subdev *sd,
2854*4882a593Smuzhiyun 				   struct v4l2_subdev_frame_interval *fi)
2855*4882a593Smuzhiyun {
2856*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2857*4882a593Smuzhiyun 	const struct ov5640_mode_info *mode;
2858*4882a593Smuzhiyun 	int frame_rate, ret = 0;
2859*4882a593Smuzhiyun 
2860*4882a593Smuzhiyun 	if (fi->pad != 0)
2861*4882a593Smuzhiyun 		return -EINVAL;
2862*4882a593Smuzhiyun 
2863*4882a593Smuzhiyun 	mutex_lock(&sensor->lock);
2864*4882a593Smuzhiyun 
2865*4882a593Smuzhiyun 	if (sensor->streaming) {
2866*4882a593Smuzhiyun 		ret = -EBUSY;
2867*4882a593Smuzhiyun 		goto out;
2868*4882a593Smuzhiyun 	}
2869*4882a593Smuzhiyun 
2870*4882a593Smuzhiyun 	mode = sensor->current_mode;
2871*4882a593Smuzhiyun 
2872*4882a593Smuzhiyun 	frame_rate = ov5640_try_frame_interval(sensor, &fi->interval,
2873*4882a593Smuzhiyun 					       mode->hact, mode->vact);
2874*4882a593Smuzhiyun 	if (frame_rate < 0) {
2875*4882a593Smuzhiyun 		/* Always return a valid frame interval value */
2876*4882a593Smuzhiyun 		fi->interval = sensor->frame_interval;
2877*4882a593Smuzhiyun 		goto out;
2878*4882a593Smuzhiyun 	}
2879*4882a593Smuzhiyun 
2880*4882a593Smuzhiyun 	mode = ov5640_find_mode(sensor, frame_rate, mode->hact,
2881*4882a593Smuzhiyun 				mode->vact, true);
2882*4882a593Smuzhiyun 	if (!mode) {
2883*4882a593Smuzhiyun 		ret = -EINVAL;
2884*4882a593Smuzhiyun 		goto out;
2885*4882a593Smuzhiyun 	}
2886*4882a593Smuzhiyun 
2887*4882a593Smuzhiyun 	if (mode != sensor->current_mode ||
2888*4882a593Smuzhiyun 	    frame_rate != sensor->current_fr) {
2889*4882a593Smuzhiyun 		sensor->current_fr = frame_rate;
2890*4882a593Smuzhiyun 		sensor->frame_interval = fi->interval;
2891*4882a593Smuzhiyun 		sensor->current_mode = mode;
2892*4882a593Smuzhiyun 		sensor->pending_mode_change = true;
2893*4882a593Smuzhiyun 
2894*4882a593Smuzhiyun 		__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
2895*4882a593Smuzhiyun 					 ov5640_calc_pixel_rate(sensor));
2896*4882a593Smuzhiyun 	}
2897*4882a593Smuzhiyun out:
2898*4882a593Smuzhiyun 	mutex_unlock(&sensor->lock);
2899*4882a593Smuzhiyun 	return ret;
2900*4882a593Smuzhiyun }
2901*4882a593Smuzhiyun 
ov5640_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)2902*4882a593Smuzhiyun static int ov5640_enum_mbus_code(struct v4l2_subdev *sd,
2903*4882a593Smuzhiyun 				 struct v4l2_subdev_pad_config *cfg,
2904*4882a593Smuzhiyun 				 struct v4l2_subdev_mbus_code_enum *code)
2905*4882a593Smuzhiyun {
2906*4882a593Smuzhiyun 	if (code->pad != 0)
2907*4882a593Smuzhiyun 		return -EINVAL;
2908*4882a593Smuzhiyun 	if (code->index >= ARRAY_SIZE(ov5640_formats))
2909*4882a593Smuzhiyun 		return -EINVAL;
2910*4882a593Smuzhiyun 
2911*4882a593Smuzhiyun 	code->code = ov5640_formats[code->index].code;
2912*4882a593Smuzhiyun 	return 0;
2913*4882a593Smuzhiyun }
2914*4882a593Smuzhiyun 
ov5640_s_stream(struct v4l2_subdev * sd,int enable)2915*4882a593Smuzhiyun static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
2916*4882a593Smuzhiyun {
2917*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
2918*4882a593Smuzhiyun 	int ret = 0;
2919*4882a593Smuzhiyun 
2920*4882a593Smuzhiyun 	mutex_lock(&sensor->lock);
2921*4882a593Smuzhiyun 
2922*4882a593Smuzhiyun 	if (sensor->streaming == !enable) {
2923*4882a593Smuzhiyun 		if (enable && sensor->pending_mode_change) {
2924*4882a593Smuzhiyun 			ret = ov5640_set_mode(sensor);
2925*4882a593Smuzhiyun 			if (ret)
2926*4882a593Smuzhiyun 				goto out;
2927*4882a593Smuzhiyun 		}
2928*4882a593Smuzhiyun 
2929*4882a593Smuzhiyun 		if (enable && sensor->pending_fmt_change) {
2930*4882a593Smuzhiyun 			ret = ov5640_set_framefmt(sensor, &sensor->fmt);
2931*4882a593Smuzhiyun 			if (ret)
2932*4882a593Smuzhiyun 				goto out;
2933*4882a593Smuzhiyun 			sensor->pending_fmt_change = false;
2934*4882a593Smuzhiyun 		}
2935*4882a593Smuzhiyun 
2936*4882a593Smuzhiyun 		if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY)
2937*4882a593Smuzhiyun 			ret = ov5640_set_stream_mipi(sensor, enable);
2938*4882a593Smuzhiyun 		else
2939*4882a593Smuzhiyun 			ret = ov5640_set_stream_dvp(sensor, enable);
2940*4882a593Smuzhiyun 
2941*4882a593Smuzhiyun 		if (!ret)
2942*4882a593Smuzhiyun 			sensor->streaming = enable;
2943*4882a593Smuzhiyun 	}
2944*4882a593Smuzhiyun out:
2945*4882a593Smuzhiyun 	mutex_unlock(&sensor->lock);
2946*4882a593Smuzhiyun 	return ret;
2947*4882a593Smuzhiyun }
2948*4882a593Smuzhiyun 
2949*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops ov5640_core_ops = {
2950*4882a593Smuzhiyun 	.s_power = ov5640_s_power,
2951*4882a593Smuzhiyun 	.log_status = v4l2_ctrl_subdev_log_status,
2952*4882a593Smuzhiyun 	.subscribe_event = v4l2_ctrl_subdev_subscribe_event,
2953*4882a593Smuzhiyun 	.unsubscribe_event = v4l2_event_subdev_unsubscribe,
2954*4882a593Smuzhiyun };
2955*4882a593Smuzhiyun 
2956*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops ov5640_video_ops = {
2957*4882a593Smuzhiyun 	.g_frame_interval = ov5640_g_frame_interval,
2958*4882a593Smuzhiyun 	.s_frame_interval = ov5640_s_frame_interval,
2959*4882a593Smuzhiyun 	.s_stream = ov5640_s_stream,
2960*4882a593Smuzhiyun };
2961*4882a593Smuzhiyun 
2962*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops ov5640_pad_ops = {
2963*4882a593Smuzhiyun 	.enum_mbus_code = ov5640_enum_mbus_code,
2964*4882a593Smuzhiyun 	.get_fmt = ov5640_get_fmt,
2965*4882a593Smuzhiyun 	.set_fmt = ov5640_set_fmt,
2966*4882a593Smuzhiyun 	.enum_frame_size = ov5640_enum_frame_size,
2967*4882a593Smuzhiyun 	.enum_frame_interval = ov5640_enum_frame_interval,
2968*4882a593Smuzhiyun };
2969*4882a593Smuzhiyun 
2970*4882a593Smuzhiyun static const struct v4l2_subdev_ops ov5640_subdev_ops = {
2971*4882a593Smuzhiyun 	.core = &ov5640_core_ops,
2972*4882a593Smuzhiyun 	.video = &ov5640_video_ops,
2973*4882a593Smuzhiyun 	.pad = &ov5640_pad_ops,
2974*4882a593Smuzhiyun };
2975*4882a593Smuzhiyun 
ov5640_get_regulators(struct ov5640_dev * sensor)2976*4882a593Smuzhiyun static int ov5640_get_regulators(struct ov5640_dev *sensor)
2977*4882a593Smuzhiyun {
2978*4882a593Smuzhiyun 	int i;
2979*4882a593Smuzhiyun 
2980*4882a593Smuzhiyun 	for (i = 0; i < OV5640_NUM_SUPPLIES; i++)
2981*4882a593Smuzhiyun 		sensor->supplies[i].supply = ov5640_supply_name[i];
2982*4882a593Smuzhiyun 
2983*4882a593Smuzhiyun 	return devm_regulator_bulk_get(&sensor->i2c_client->dev,
2984*4882a593Smuzhiyun 				       OV5640_NUM_SUPPLIES,
2985*4882a593Smuzhiyun 				       sensor->supplies);
2986*4882a593Smuzhiyun }
2987*4882a593Smuzhiyun 
ov5640_check_chip_id(struct ov5640_dev * sensor)2988*4882a593Smuzhiyun static int ov5640_check_chip_id(struct ov5640_dev *sensor)
2989*4882a593Smuzhiyun {
2990*4882a593Smuzhiyun 	struct i2c_client *client = sensor->i2c_client;
2991*4882a593Smuzhiyun 	int ret = 0;
2992*4882a593Smuzhiyun 	u16 chip_id;
2993*4882a593Smuzhiyun 
2994*4882a593Smuzhiyun 	ret = ov5640_set_power_on(sensor);
2995*4882a593Smuzhiyun 	if (ret)
2996*4882a593Smuzhiyun 		return ret;
2997*4882a593Smuzhiyun 
2998*4882a593Smuzhiyun 	ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
2999*4882a593Smuzhiyun 	if (ret) {
3000*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: failed to read chip identifier\n",
3001*4882a593Smuzhiyun 			__func__);
3002*4882a593Smuzhiyun 		goto power_off;
3003*4882a593Smuzhiyun 	}
3004*4882a593Smuzhiyun 
3005*4882a593Smuzhiyun 	if (chip_id != 0x5640) {
3006*4882a593Smuzhiyun 		dev_err(&client->dev, "%s: wrong chip identifier, expected 0x5640, got 0x%x\n",
3007*4882a593Smuzhiyun 			__func__, chip_id);
3008*4882a593Smuzhiyun 		ret = -ENXIO;
3009*4882a593Smuzhiyun 	}
3010*4882a593Smuzhiyun 
3011*4882a593Smuzhiyun power_off:
3012*4882a593Smuzhiyun 	ov5640_set_power_off(sensor);
3013*4882a593Smuzhiyun 	return ret;
3014*4882a593Smuzhiyun }
3015*4882a593Smuzhiyun 
ov5640_probe(struct i2c_client * client)3016*4882a593Smuzhiyun static int ov5640_probe(struct i2c_client *client)
3017*4882a593Smuzhiyun {
3018*4882a593Smuzhiyun 	struct device *dev = &client->dev;
3019*4882a593Smuzhiyun 	struct fwnode_handle *endpoint;
3020*4882a593Smuzhiyun 	struct ov5640_dev *sensor;
3021*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *fmt;
3022*4882a593Smuzhiyun 	u32 rotation;
3023*4882a593Smuzhiyun 	int ret;
3024*4882a593Smuzhiyun 
3025*4882a593Smuzhiyun 	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
3026*4882a593Smuzhiyun 	if (!sensor)
3027*4882a593Smuzhiyun 		return -ENOMEM;
3028*4882a593Smuzhiyun 
3029*4882a593Smuzhiyun 	sensor->i2c_client = client;
3030*4882a593Smuzhiyun 
3031*4882a593Smuzhiyun 	/*
3032*4882a593Smuzhiyun 	 * default init sequence initialize sensor to
3033*4882a593Smuzhiyun 	 * YUV422 UYVY VGA@30fps
3034*4882a593Smuzhiyun 	 */
3035*4882a593Smuzhiyun 	fmt = &sensor->fmt;
3036*4882a593Smuzhiyun 	fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
3037*4882a593Smuzhiyun 	fmt->colorspace = V4L2_COLORSPACE_SRGB;
3038*4882a593Smuzhiyun 	fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
3039*4882a593Smuzhiyun 	fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
3040*4882a593Smuzhiyun 	fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
3041*4882a593Smuzhiyun 	fmt->width = 640;
3042*4882a593Smuzhiyun 	fmt->height = 480;
3043*4882a593Smuzhiyun 	fmt->field = V4L2_FIELD_NONE;
3044*4882a593Smuzhiyun 	sensor->frame_interval.numerator = 1;
3045*4882a593Smuzhiyun 	sensor->frame_interval.denominator = ov5640_framerates[OV5640_30_FPS];
3046*4882a593Smuzhiyun 	sensor->current_fr = OV5640_30_FPS;
3047*4882a593Smuzhiyun 	sensor->current_mode =
3048*4882a593Smuzhiyun 		&ov5640_mode_data[OV5640_MODE_VGA_640_480];
3049*4882a593Smuzhiyun 	sensor->last_mode = sensor->current_mode;
3050*4882a593Smuzhiyun 
3051*4882a593Smuzhiyun 	sensor->ae_target = 52;
3052*4882a593Smuzhiyun 
3053*4882a593Smuzhiyun 	/* optional indication of physical rotation of sensor */
3054*4882a593Smuzhiyun 	ret = fwnode_property_read_u32(dev_fwnode(&client->dev), "rotation",
3055*4882a593Smuzhiyun 				       &rotation);
3056*4882a593Smuzhiyun 	if (!ret) {
3057*4882a593Smuzhiyun 		switch (rotation) {
3058*4882a593Smuzhiyun 		case 180:
3059*4882a593Smuzhiyun 			sensor->upside_down = true;
3060*4882a593Smuzhiyun 			fallthrough;
3061*4882a593Smuzhiyun 		case 0:
3062*4882a593Smuzhiyun 			break;
3063*4882a593Smuzhiyun 		default:
3064*4882a593Smuzhiyun 			dev_warn(dev, "%u degrees rotation is not supported, ignoring...\n",
3065*4882a593Smuzhiyun 				 rotation);
3066*4882a593Smuzhiyun 		}
3067*4882a593Smuzhiyun 	}
3068*4882a593Smuzhiyun 
3069*4882a593Smuzhiyun 	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev),
3070*4882a593Smuzhiyun 						  NULL);
3071*4882a593Smuzhiyun 	if (!endpoint) {
3072*4882a593Smuzhiyun 		dev_err(dev, "endpoint node not found\n");
3073*4882a593Smuzhiyun 		return -EINVAL;
3074*4882a593Smuzhiyun 	}
3075*4882a593Smuzhiyun 
3076*4882a593Smuzhiyun 	ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
3077*4882a593Smuzhiyun 	fwnode_handle_put(endpoint);
3078*4882a593Smuzhiyun 	if (ret) {
3079*4882a593Smuzhiyun 		dev_err(dev, "Could not parse endpoint\n");
3080*4882a593Smuzhiyun 		return ret;
3081*4882a593Smuzhiyun 	}
3082*4882a593Smuzhiyun 
3083*4882a593Smuzhiyun 	if (sensor->ep.bus_type != V4L2_MBUS_PARALLEL &&
3084*4882a593Smuzhiyun 	    sensor->ep.bus_type != V4L2_MBUS_CSI2_DPHY &&
3085*4882a593Smuzhiyun 	    sensor->ep.bus_type != V4L2_MBUS_BT656) {
3086*4882a593Smuzhiyun 		dev_err(dev, "Unsupported bus type %d\n", sensor->ep.bus_type);
3087*4882a593Smuzhiyun 		return -EINVAL;
3088*4882a593Smuzhiyun 	}
3089*4882a593Smuzhiyun 
3090*4882a593Smuzhiyun 	/* get system clock (xclk) */
3091*4882a593Smuzhiyun 	sensor->xclk = devm_clk_get(dev, "xclk");
3092*4882a593Smuzhiyun 	if (IS_ERR(sensor->xclk)) {
3093*4882a593Smuzhiyun 		dev_err(dev, "failed to get xclk\n");
3094*4882a593Smuzhiyun 		return PTR_ERR(sensor->xclk);
3095*4882a593Smuzhiyun 	}
3096*4882a593Smuzhiyun 
3097*4882a593Smuzhiyun 	sensor->xclk_freq = clk_get_rate(sensor->xclk);
3098*4882a593Smuzhiyun 	if (sensor->xclk_freq < OV5640_XCLK_MIN ||
3099*4882a593Smuzhiyun 	    sensor->xclk_freq > OV5640_XCLK_MAX) {
3100*4882a593Smuzhiyun 		dev_err(dev, "xclk frequency out of range: %d Hz\n",
3101*4882a593Smuzhiyun 			sensor->xclk_freq);
3102*4882a593Smuzhiyun 		return -EINVAL;
3103*4882a593Smuzhiyun 	}
3104*4882a593Smuzhiyun 
3105*4882a593Smuzhiyun 	/* request optional power down pin */
3106*4882a593Smuzhiyun 	sensor->pwdn_gpio = devm_gpiod_get_optional(dev, "powerdown",
3107*4882a593Smuzhiyun 						    GPIOD_OUT_HIGH);
3108*4882a593Smuzhiyun 	if (IS_ERR(sensor->pwdn_gpio))
3109*4882a593Smuzhiyun 		return PTR_ERR(sensor->pwdn_gpio);
3110*4882a593Smuzhiyun 
3111*4882a593Smuzhiyun 	/* request optional reset pin */
3112*4882a593Smuzhiyun 	sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
3113*4882a593Smuzhiyun 						     GPIOD_OUT_HIGH);
3114*4882a593Smuzhiyun 	if (IS_ERR(sensor->reset_gpio))
3115*4882a593Smuzhiyun 		return PTR_ERR(sensor->reset_gpio);
3116*4882a593Smuzhiyun 
3117*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(&sensor->sd, client, &ov5640_subdev_ops);
3118*4882a593Smuzhiyun 
3119*4882a593Smuzhiyun 	sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
3120*4882a593Smuzhiyun 			    V4L2_SUBDEV_FL_HAS_EVENTS;
3121*4882a593Smuzhiyun 	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
3122*4882a593Smuzhiyun 	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
3123*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
3124*4882a593Smuzhiyun 	if (ret)
3125*4882a593Smuzhiyun 		return ret;
3126*4882a593Smuzhiyun 
3127*4882a593Smuzhiyun 	ret = ov5640_get_regulators(sensor);
3128*4882a593Smuzhiyun 	if (ret)
3129*4882a593Smuzhiyun 		return ret;
3130*4882a593Smuzhiyun 
3131*4882a593Smuzhiyun 	mutex_init(&sensor->lock);
3132*4882a593Smuzhiyun 
3133*4882a593Smuzhiyun 	ret = ov5640_check_chip_id(sensor);
3134*4882a593Smuzhiyun 	if (ret)
3135*4882a593Smuzhiyun 		goto entity_cleanup;
3136*4882a593Smuzhiyun 
3137*4882a593Smuzhiyun 	ret = ov5640_init_controls(sensor);
3138*4882a593Smuzhiyun 	if (ret)
3139*4882a593Smuzhiyun 		goto entity_cleanup;
3140*4882a593Smuzhiyun 
3141*4882a593Smuzhiyun 	ret = v4l2_async_register_subdev_sensor_common(&sensor->sd);
3142*4882a593Smuzhiyun 	if (ret)
3143*4882a593Smuzhiyun 		goto free_ctrls;
3144*4882a593Smuzhiyun 
3145*4882a593Smuzhiyun 	return 0;
3146*4882a593Smuzhiyun 
3147*4882a593Smuzhiyun free_ctrls:
3148*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
3149*4882a593Smuzhiyun entity_cleanup:
3150*4882a593Smuzhiyun 	media_entity_cleanup(&sensor->sd.entity);
3151*4882a593Smuzhiyun 	mutex_destroy(&sensor->lock);
3152*4882a593Smuzhiyun 	return ret;
3153*4882a593Smuzhiyun }
3154*4882a593Smuzhiyun 
ov5640_remove(struct i2c_client * client)3155*4882a593Smuzhiyun static int ov5640_remove(struct i2c_client *client)
3156*4882a593Smuzhiyun {
3157*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
3158*4882a593Smuzhiyun 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
3159*4882a593Smuzhiyun 
3160*4882a593Smuzhiyun 	v4l2_async_unregister_subdev(&sensor->sd);
3161*4882a593Smuzhiyun 	media_entity_cleanup(&sensor->sd.entity);
3162*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
3163*4882a593Smuzhiyun 	mutex_destroy(&sensor->lock);
3164*4882a593Smuzhiyun 
3165*4882a593Smuzhiyun 	return 0;
3166*4882a593Smuzhiyun }
3167*4882a593Smuzhiyun 
3168*4882a593Smuzhiyun static const struct i2c_device_id ov5640_id[] = {
3169*4882a593Smuzhiyun 	{"ov5640", 0},
3170*4882a593Smuzhiyun 	{},
3171*4882a593Smuzhiyun };
3172*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ov5640_id);
3173*4882a593Smuzhiyun 
3174*4882a593Smuzhiyun static const struct of_device_id ov5640_dt_ids[] = {
3175*4882a593Smuzhiyun 	{ .compatible = "ovti,ov5640" },
3176*4882a593Smuzhiyun 	{ /* sentinel */ }
3177*4882a593Smuzhiyun };
3178*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ov5640_dt_ids);
3179*4882a593Smuzhiyun 
3180*4882a593Smuzhiyun static struct i2c_driver ov5640_i2c_driver = {
3181*4882a593Smuzhiyun 	.driver = {
3182*4882a593Smuzhiyun 		.name  = "ov5640",
3183*4882a593Smuzhiyun 		.of_match_table	= ov5640_dt_ids,
3184*4882a593Smuzhiyun 	},
3185*4882a593Smuzhiyun 	.id_table = ov5640_id,
3186*4882a593Smuzhiyun 	.probe_new = ov5640_probe,
3187*4882a593Smuzhiyun 	.remove   = ov5640_remove,
3188*4882a593Smuzhiyun };
3189*4882a593Smuzhiyun 
3190*4882a593Smuzhiyun module_i2c_driver(ov5640_i2c_driver);
3191*4882a593Smuzhiyun 
3192*4882a593Smuzhiyun MODULE_DESCRIPTION("OV5640 MIPI Camera Subdev Driver");
3193*4882a593Smuzhiyun MODULE_LICENSE("GPL");
3194