1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * OV4686 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version.
8 */
9
10 #include <linux/clk.h>
11 #include <linux/device.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/i2c.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/sysfs.h>
19 #include <linux/slab.h>
20 #include <linux/version.h>
21 #include <linux/rk-camera-module.h>
22 #include <linux/rk-preisp.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-subdev.h>
27 #include <linux/pinctrl/consumer.h>
28
29 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
30
31 #ifndef V4L2_CID_DIGITAL_GAIN
32 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
33 #endif
34
35 #define OV4686_LANES 4
36 #define OV4686_BITS_PER_SAMPLE 10
37 #define OV4686_LINK_FREQ_500MHZ 500000000LL
38 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
39 #define OV4686_PIXEL_RATE (OV4686_LINK_FREQ_500MHZ * 2 * \
40 OV4686_LANES / OV4686_BITS_PER_SAMPLE)
41 #define OV4686_XVCLK_FREQ 24000000
42
43 #define CHIP_ID 0x004688
44 #define OV4686_REG_CHIP_ID 0x300a
45
46 #define OV4686_REG_CTRL_MODE 0x0100
47 #define OV4686_MODE_SW_STANDBY 0x0
48 #define OV4686_MODE_STREAMING BIT(0)
49
50 #define OV4686_REG_EXPOSURE 0x3500
51 #define OV4686_EXPOSURE_MIN 4
52 #define OV4686_EXPOSURE_STEP 1
53 #define OV4686_VTS_MAX 0x7fff
54
55 #define OV4686_REG_GAIN_H 0x3508
56 #define OV4686_REG_GAIN_L 0x3509//low 7bit fraction
57 #define OV4686_GAIN_H_MASK 0x07
58 #define OV4686_GAIN_H_SHIFT 8
59 #define OV4686_GAIN_L_MASK 0xff
60 #define OV4686_GAIN_MIN 0x80
61 #define OV4686_GAIN_MAX 0x7f8
62 #define OV4686_GAIN_STEP 1
63 #define OV4686_GAIN_DEFAULT 0x80
64
65 #define OV4686_REG_L_GAIN 0x3508
66 #define OV4686_REG_M_GAIN 0x350e
67 #define OV4686_REG_S_GAIN 0x3514
68 #define OV4686_REG_L_EXP 0x3500
69 #define OV4686_REG_M_EXP 0x350a
70 #define OV4686_REG_S_EXP 0x3510
71
72 #define OV4686_GROUP_UPDATE_ADDRESS 0x3208
73 #define OV4686_GROUP_UPDATE_START_DATA 0x00
74 #define OV4686_GROUP_UPDATE_END_DATA 0x10
75 #define OV4686_GROUP_UPDATE_LAUNCH 0xA0
76
77 #define OV4686_REG_TEST_PATTERN 0x5040
78 #define OV4686_TEST_PATTERN_ENABLE 0x80
79 #define OV4686_TEST_PATTERN_DISABLE 0x0
80
81 #define OV4686_REG_VTS 0x380e
82
83 #define OV4686_VFLIP_REG 0x3820
84 #define OV4686_HFLIP_REG 0x3821
85 #define MIRROR_BIT_MASK (BIT(1) | BIT(2))
86 #define FLIP_BIT_MASK (BIT(1) | BIT(2))
87
88 #define REG_NULL 0xFFFF
89
90 #define OV4686_REG_VALUE_08BIT 1
91 #define OV4686_REG_VALUE_16BIT 2
92 #define OV4686_REG_VALUE_24BIT 3
93
94 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
95 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
96 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
97 #define OV4686_NAME "ov4686"
98
99 static const char * const OV4686_supply_names[] = {
100 "avdd", /* Analog power */
101 "dovdd", /* Digital I/O power */
102 "dvdd", /* Digital core power */
103 };
104
105 #define OV4686_NUM_SUPPLIES ARRAY_SIZE(OV4686_supply_names)
106
107 struct regval {
108 u16 addr;
109 u8 val;
110 };
111
112 struct OV4686_mode {
113 u32 width;
114 u32 height;
115 struct v4l2_fract max_fps;
116 u32 hts_def;
117 u32 vts_def;
118 u32 exp_def;
119 const struct regval *reg_list;
120 u32 hdr_mode;
121 u32 vc[PAD_MAX];
122 };
123
124 struct OV4686 {
125 struct i2c_client *client;
126 struct clk *xvclk;
127 struct gpio_desc *reset_gpio;
128 struct gpio_desc *pwdn_gpio;
129 struct regulator_bulk_data supplies[OV4686_NUM_SUPPLIES];
130
131 struct pinctrl *pinctrl;
132 struct pinctrl_state *pins_default;
133 struct pinctrl_state *pins_sleep;
134
135 struct v4l2_subdev subdev;
136 struct media_pad pad;
137 struct v4l2_ctrl_handler ctrl_handler;
138 struct v4l2_ctrl *exposure;
139 struct v4l2_ctrl *anal_gain;
140 struct v4l2_ctrl *digi_gain;
141 struct v4l2_ctrl *hblank;
142 struct v4l2_ctrl *vblank;
143 struct v4l2_ctrl *test_pattern;
144 struct mutex mutex;
145 bool streaming;
146 bool power_on;
147 const struct OV4686_mode *cur_mode;
148 u32 module_index;
149 const char *module_facing;
150 const char *module_name;
151 const char *len_name;
152 bool has_init_exp;
153 struct preisp_hdrae_exp_s init_hdrae_exp;
154 };
155
156 #define to_OV4686(sd) container_of(sd, struct OV4686, subdev)
157
158 /*
159 * Xclk 24Mhz
160 */
161 static const struct regval OV4686_global_regs[] = {
162 {REG_NULL, 0x00},
163 };
164
165 /*
166 * Xclk 24Mhz
167 * max_framerate 90fps
168 * mipi_datarate per lane 1008Mbps, 4lane
169 */
170 static const struct regval OV4686_2688x1520_regs[] = {
171 {0x0103, 0x01},
172 {0x3638, 0x00},
173 {0x0300, 0x00},
174 {0x0302, 0x2a},
175 {0x0303, 0x00},
176 {0x0304, 0x03},
177 {0x030b, 0x00},
178 {0x030d, 0x1e},
179 {0x030e, 0x04},
180 {0x030f, 0x01},
181 {0x0312, 0x01},
182 {0x031e, 0x00},
183 {0x3000, 0x20},
184 {0x3002, 0x00},
185 {0x3018, 0x72},
186 {0x3020, 0x93},
187 {0x3021, 0x03},
188 {0x3022, 0x01},
189 {0x3031, 0x0a},
190 {0x303f, 0x0c},
191 {0x3305, 0xf1},
192 {0x3307, 0x04},
193 {0x3309, 0x29},
194 {0x3500, 0x00},
195 {0x3501, 0x5f},
196 {0x3502, 0x00},
197 {0x3503, 0x04},
198 {0x3504, 0x00},
199 {0x3505, 0x00},
200 {0x3506, 0x00},
201 {0x3507, 0x00},
202 {0x3508, 0x00},
203 {0x3509, 0x80},
204 {0x350a, 0x00},
205 {0x350b, 0x00},
206 {0x350c, 0x00},
207 {0x350d, 0x00},
208 {0x350e, 0x00},
209 {0x350f, 0x80},
210 {0x3510, 0x00},
211 {0x3511, 0x00},
212 {0x3512, 0x00},
213 {0x3513, 0x00},
214 {0x3514, 0x00},
215 {0x3515, 0x80},
216 {0x3516, 0x00},
217 {0x3517, 0x00},
218 {0x3518, 0x00},
219 {0x3519, 0x00},
220 {0x351a, 0x00},
221 {0x351b, 0x80},
222 {0x351c, 0x00},
223 {0x351d, 0x00},
224 {0x351e, 0x00},
225 {0x351f, 0x00},
226 {0x3520, 0x00},
227 {0x3521, 0x80},
228 {0x3522, 0x08},
229 {0x3524, 0x08},
230 {0x3526, 0x08},
231 {0x3528, 0x08},
232 {0x352a, 0x08},
233 {0x3602, 0x00},
234 {0x3603, 0x40},
235 {0x3604, 0x02},
236 {0x3605, 0x00},
237 {0x3606, 0x00},
238 {0x3607, 0x00},
239 {0x3609, 0x12},
240 {0x360a, 0x40},
241 {0x360c, 0x08},
242 {0x360f, 0xe0},
243 {0x3608, 0x8f},
244 {0x3611, 0x00},
245 {0x3613, 0xf7},
246 {0x3616, 0x58},
247 {0x3619, 0x99},
248 {0x361b, 0x60},
249 {0x361c, 0x7a},
250 {0x361e, 0x79},
251 {0x361f, 0x02},
252 {0x3632, 0x00},
253 {0x3633, 0x10},
254 {0x3634, 0x10},
255 {0x3635, 0x10},
256 {0x3636, 0x10},
257 {0x3646, 0x86},
258 {0x364a, 0x0b},
259 {0x3700, 0x17},
260 {0x3701, 0x22},
261 {0x3703, 0x10},
262 {0x370a, 0x37},
263 {0x3705, 0x00},
264 {0x3706, 0x63},
265 {0x3709, 0x3c},
266 {0x370b, 0x01},
267 {0x370c, 0x30},
268 {0x3710, 0x24},
269 {0x3711, 0x0c},
270 {0x3716, 0x00},
271 {0x3720, 0x28},
272 {0x3729, 0x7b},
273 {0x372a, 0x84},
274 {0x372b, 0xbd},
275 {0x372c, 0xbc},
276 {0x372e, 0x52},
277 {0x373c, 0x0e},
278 {0x373e, 0x33},
279 {0x3743, 0x10},
280 {0x3744, 0x88},
281 {0x3745, 0xc0},
282 {0x374a, 0x43},
283 {0x374c, 0x00},
284 {0x374e, 0x23},
285 {0x3751, 0x7b},
286 {0x3752, 0x84},
287 {0x3753, 0xbd},
288 {0x3754, 0xbc},
289 {0x3756, 0x52},
290 {0x375c, 0x00},
291 {0x3760, 0x00},
292 {0x3761, 0x00},
293 {0x3762, 0x00},
294 {0x3763, 0x00},
295 {0x3764, 0x00},
296 {0x3767, 0x04},
297 {0x3768, 0x04},
298 {0x3769, 0x08},
299 {0x376a, 0x08},
300 {0x376b, 0x20},
301 {0x376c, 0x00},
302 {0x376d, 0x00},
303 {0x376e, 0x00},
304 {0x3773, 0x00},
305 {0x3774, 0x51},
306 {0x3776, 0xbd},
307 {0x3777, 0xbd},
308 {0x3781, 0x18},
309 {0x3783, 0x25},
310 {0x3798, 0x1b},
311 {0x3800, 0x00},
312 {0x3801, 0x08},
313 {0x3802, 0x00},
314 {0x3803, 0x04},
315 {0x3804, 0x0a},
316 {0x3805, 0x97},
317 {0x3806, 0x05},
318 {0x3807, 0xfb},
319 {0x3808, 0x0a},
320 {0x3809, 0x80},
321 {0x380a, 0x05},
322 {0x380b, 0xf0},
323 {0x380c, 0x0a},
324 {0x380d, 0x14},
325 {0x380e, 0x06},
326 {0x380f, 0x12},
327 {0x3810, 0x00},
328 {0x3811, 0x08},
329 {0x3812, 0x00},
330 {0x3813, 0x04},
331 {0x3814, 0x01},
332 {0x3815, 0x01},
333 {0x3819, 0x01},
334 {0x3820, 0x00},
335 {0x3821, 0x06},
336 {0x3829, 0x00},
337 {0x382a, 0x01},
338 {0x382b, 0x01},
339 {0x382d, 0x7f},
340 {0x3830, 0x04},
341 {0x3836, 0x01},
342 {0x3837, 0x00},
343 {0x3841, 0x02},
344 {0x3846, 0x08},
345 {0x3847, 0x07},
346 {0x3d85, 0x36},
347 {0x3d8c, 0x71},
348 {0x3d8d, 0xcb},
349 {0x3f0a, 0x00},
350 {0x4000, 0xf1},
351 {0x4001, 0x40},
352 {0x4002, 0x04},
353 {0x4003, 0x14},
354 {0x400e, 0x00},
355 {0x4011, 0x00},
356 {0x401a, 0x00},
357 {0x401b, 0x00},
358 {0x401c, 0x00},
359 {0x401d, 0x00},
360 {0x401f, 0x00},
361 {0x4020, 0x00},
362 {0x4021, 0x10},
363 {0x4022, 0x07},
364 {0x4023, 0xcf},
365 {0x4024, 0x09},
366 {0x4025, 0x60},
367 {0x4026, 0x09},
368 {0x4027, 0x6f},
369 {0x4028, 0x00},
370 {0x4029, 0x02},
371 {0x402a, 0x06},
372 {0x402b, 0x04},
373 {0x402c, 0x02},
374 {0x402d, 0x02},
375 {0x402e, 0x0e},
376 {0x402f, 0x04},
377 {0x4302, 0xff},
378 {0x4303, 0xff},
379 {0x4304, 0x00},
380 {0x4305, 0x00},
381 {0x4306, 0x00},
382 {0x4308, 0x02},
383 {0x4500, 0x6c},
384 {0x4501, 0xc4},
385 {0x4502, 0x40},
386 {0x4503, 0x01},
387 {0x4601, 0x04},
388 {0x4800, 0x04},
389 {0x4813, 0x08},
390 {0x481f, 0x40},
391 {0x4829, 0x78},
392 {0x4837, 0x10},
393 {0x4b00, 0x2a},
394 {0x4b0d, 0x00},
395 {0x4d00, 0x04},
396 {0x4d01, 0x42},
397 {0x4d02, 0xd1},
398 {0x4d03, 0x93},
399 {0x4d04, 0xf5},
400 {0x4d05, 0xc1},
401 {0x5000, 0xd3},
402 {0x5001, 0x11},
403 {0x5004, 0x00},
404 {0x500a, 0x00},
405 {0x500b, 0x00},
406 {0x5032, 0x00},
407 {0x5040, 0x00},
408 {0x5050, 0x0c},
409 {0x5500, 0x00},
410 {0x5501, 0x10},
411 {0x5502, 0x01},
412 {0x5503, 0x0f},
413 {0x8000, 0x00},
414 {0x8001, 0x00},
415 {0x8002, 0x00},
416 {0x8003, 0x00},
417 {0x8004, 0x00},
418 {0x8005, 0x00},
419 {0x8006, 0x00},
420 {0x8007, 0x00},
421 {0x8008, 0x00},
422 {0x3638, 0x00},
423 {REG_NULL, 0x00},
424 };
425
426 static const struct regval OV4686_linear_regs[] = {
427 {0x380c, 0x0a},
428 {0x380d, 0x14},
429 {0x3841, 0x02},
430 {0x4800, 0x04},
431 {0x376e, 0x00},
432 {REG_NULL, 0x00},
433 };
434
435 static const struct regval OV4686_hdr_x2_regs[] = {
436 {0x380c, 0x05},
437 {0x380d, 0x10},
438
439 {0x3841, 0x03},
440 {0x3846, 0x08},
441 {0x3847, 0x04},//04
442 {0x4800, 0x0c},
443 {0x376e, 0x01},
444 {0x3501, 0x10},
445 {0x350b, 0x08},
446 {0x3511, 0x01},
447 {0x3517, 0x00},
448 {0x351d, 0x00},
449
450 {0x3841, 0x03},//HDR_2
451 {0x3847, 0x06},//HDR_2_ALL
452 {REG_NULL, 0x00},
453 };
454
455 static const struct OV4686_mode supported_modes[] = {
456 {
457 .width = 2688,
458 .height = 1520,
459 .max_fps = {
460 .numerator = 10000,
461 .denominator = 300000,
462 },
463 .exp_def = 0x0600,
464 .hts_def = 0x0a18,
465 .vts_def = 0x0612,
466 .reg_list = OV4686_linear_regs,
467 .hdr_mode = NO_HDR,
468 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
469 }, {
470 .width = 2688,
471 .height = 1520,
472 .max_fps = {
473 .numerator = 10000,
474 .denominator = 300000,
475 },
476 .exp_def = 0x0600,
477 .hts_def = 0x0a20,
478 .vts_def = 0x0612,
479 .reg_list = OV4686_hdr_x2_regs,
480 .hdr_mode = HDR_X2,
481 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
482 .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
483 .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
484 .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
485 },
486 };
487
488 static const s64 link_freq_menu_items[] = {
489 OV4686_LINK_FREQ_500MHZ
490 };
491
492 static const char * const OV4686_test_pattern_menu[] = {
493 "Disabled",
494 "Vertical Color Bar Type 1",
495 "Vertical Color Bar Type 2",
496 "Vertical Color Bar Type 3",
497 "Vertical Color Bar Type 4"
498 };
499
500 /* Write registers up to 4 at a time */
OV4686_write_reg(struct i2c_client * client,u16 reg,u32 len,u32 val)501 static int OV4686_write_reg(struct i2c_client *client, u16 reg,
502 u32 len, u32 val)
503 {
504 u32 buf_i, val_i;
505 u8 buf[6];
506 u8 *val_p;
507 __be32 val_be;
508
509 if (len > 4)
510 return -EINVAL;
511
512 buf[0] = reg >> 8;
513 buf[1] = reg & 0xff;
514
515 val_be = cpu_to_be32(val);
516 val_p = (u8 *)&val_be;
517 buf_i = 2;
518 val_i = 4 - len;
519
520 while (val_i < 4)
521 buf[buf_i++] = val_p[val_i++];
522
523 if (i2c_master_send(client, buf, len + 2) != len + 2)
524 return -EIO;
525
526 return 0;
527 }
528
OV4686_write_array(struct i2c_client * client,const struct regval * regs)529 static int OV4686_write_array(struct i2c_client *client,
530 const struct regval *regs)
531 {
532 u32 i;
533 int ret = 0;
534
535 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
536 ret = OV4686_write_reg(client, regs[i].addr,
537 OV4686_REG_VALUE_08BIT, regs[i].val);
538
539 return ret;
540 }
541
542 /* Read registers up to 4 at a time */
OV4686_read_reg(struct i2c_client * client,u16 reg,unsigned int len,u32 * val)543 static int OV4686_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
544 u32 *val)
545 {
546 struct i2c_msg msgs[2];
547 u8 *data_be_p;
548 __be32 data_be = 0;
549 __be16 reg_addr_be = cpu_to_be16(reg);
550 int ret;
551
552 if (len > 4 || !len)
553 return -EINVAL;
554
555 data_be_p = (u8 *)&data_be;
556 /* Write register address */
557 msgs[0].addr = client->addr;
558 msgs[0].flags = 0;
559 msgs[0].len = 2;
560 msgs[0].buf = (u8 *)®_addr_be;
561
562 /* Read data from register */
563 msgs[1].addr = client->addr;
564 msgs[1].flags = I2C_M_RD;
565 msgs[1].len = len;
566 msgs[1].buf = &data_be_p[4 - len];
567
568 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
569 if (ret != ARRAY_SIZE(msgs))
570 return -EIO;
571
572 *val = be32_to_cpu(data_be);
573
574 return 0;
575 }
576
OV4686_get_reso_dist(const struct OV4686_mode * mode,struct v4l2_mbus_framefmt * framefmt)577 static int OV4686_get_reso_dist(const struct OV4686_mode *mode,
578 struct v4l2_mbus_framefmt *framefmt)
579 {
580 return abs(mode->width - framefmt->width) +
581 abs(mode->height - framefmt->height);
582 }
583
584 static const struct OV4686_mode *
OV4686_find_best_fit(struct v4l2_subdev_format * fmt)585 OV4686_find_best_fit(struct v4l2_subdev_format *fmt)
586 {
587 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
588 int dist;
589 int cur_best_fit = 0;
590 int cur_best_fit_dist = -1;
591 unsigned int i;
592
593 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
594 dist = OV4686_get_reso_dist(&supported_modes[i], framefmt);
595 if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
596 cur_best_fit_dist = dist;
597 cur_best_fit = i;
598 }
599 }
600
601 return &supported_modes[cur_best_fit];
602 }
603
OV4686_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)604 static int OV4686_set_fmt(struct v4l2_subdev *sd,
605 struct v4l2_subdev_pad_config *cfg,
606 struct v4l2_subdev_format *fmt)
607 {
608 struct OV4686 *OV4686 = to_OV4686(sd);
609 const struct OV4686_mode *mode;
610 s64 h_blank, vblank_def;
611
612 mutex_lock(&OV4686->mutex);
613
614 mode = OV4686_find_best_fit(fmt);
615 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
616 fmt->format.width = mode->width;
617 fmt->format.height = mode->height;
618 fmt->format.field = V4L2_FIELD_NONE;
619 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
620 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
621 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
622 #else
623 mutex_unlock(&OV4686->mutex);
624 return -ENOTTY;
625 #endif
626 } else {
627 OV4686->cur_mode = mode;
628 h_blank = mode->hts_def - mode->width;
629 __v4l2_ctrl_modify_range(OV4686->hblank, h_blank,
630 h_blank, 1, h_blank);
631 vblank_def = mode->vts_def - mode->height;
632 __v4l2_ctrl_modify_range(OV4686->vblank, vblank_def,
633 OV4686_VTS_MAX - mode->height,
634 1, vblank_def);
635 }
636
637 mutex_unlock(&OV4686->mutex);
638
639 return 0;
640 }
641
OV4686_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)642 static int OV4686_get_fmt(struct v4l2_subdev *sd,
643 struct v4l2_subdev_pad_config *cfg,
644 struct v4l2_subdev_format *fmt)
645 {
646 struct OV4686 *OV4686 = to_OV4686(sd);
647 const struct OV4686_mode *mode = OV4686->cur_mode;
648
649 mutex_lock(&OV4686->mutex);
650 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
651 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
652 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
653 #else
654 mutex_unlock(&OV4686->mutex);
655 return -ENOTTY;
656 #endif
657 } else {
658 fmt->format.width = mode->width;
659 fmt->format.height = mode->height;
660 fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
661 fmt->format.field = V4L2_FIELD_NONE;
662 /* format info: width/height/data type/virctual channel */
663 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
664 fmt->reserved[0] = mode->vc[fmt->pad];
665 else
666 fmt->reserved[0] = mode->vc[PAD0];
667 }
668 mutex_unlock(&OV4686->mutex);
669
670 return 0;
671 }
672
OV4686_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)673 static int OV4686_enum_mbus_code(struct v4l2_subdev *sd,
674 struct v4l2_subdev_pad_config *cfg,
675 struct v4l2_subdev_mbus_code_enum *code)
676 {
677 if (code->index != 0)
678 return -EINVAL;
679 code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
680
681 return 0;
682 }
683
OV4686_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)684 static int OV4686_enum_frame_sizes(struct v4l2_subdev *sd,
685 struct v4l2_subdev_pad_config *cfg,
686 struct v4l2_subdev_frame_size_enum *fse)
687 {
688 if (fse->index >= ARRAY_SIZE(supported_modes))
689 return -EINVAL;
690
691 if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
692 return -EINVAL;
693
694 fse->min_width = supported_modes[fse->index].width;
695 fse->max_width = supported_modes[fse->index].width;
696 fse->max_height = supported_modes[fse->index].height;
697 fse->min_height = supported_modes[fse->index].height;
698
699 return 0;
700 }
701
OV4686_enable_test_pattern(struct OV4686 * OV4686,u32 pattern)702 static int OV4686_enable_test_pattern(struct OV4686 *OV4686, u32 pattern)
703 {
704 u32 val;
705
706 if (pattern)
707 val = (pattern - 1) | OV4686_TEST_PATTERN_ENABLE;
708 else
709 val = OV4686_TEST_PATTERN_DISABLE;
710
711 return OV4686_write_reg(OV4686->client, OV4686_REG_TEST_PATTERN,
712 OV4686_REG_VALUE_08BIT, val);
713 }
714
OV4686_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)715 static int OV4686_g_frame_interval(struct v4l2_subdev *sd,
716 struct v4l2_subdev_frame_interval *fi)
717 {
718 struct OV4686 *OV4686 = to_OV4686(sd);
719 const struct OV4686_mode *mode = OV4686->cur_mode;
720
721 fi->interval = mode->max_fps;
722
723 return 0;
724 }
725
OV4686_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)726 static int OV4686_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
727 struct v4l2_mbus_config *config)
728 {
729 struct OV4686 *OV4686 = to_OV4686(sd);
730 const struct OV4686_mode *mode = OV4686->cur_mode;
731 u32 val = 1 << (OV4686_LANES - 1) |
732 V4L2_MBUS_CSI2_CHANNEL_0 |
733 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
734
735 if (mode->hdr_mode != NO_HDR)
736 val |= V4L2_MBUS_CSI2_CHANNEL_1;
737 if (mode->hdr_mode == HDR_X3)
738 val |= V4L2_MBUS_CSI2_CHANNEL_2;
739
740 config->type = V4L2_MBUS_CSI2_DPHY;
741 config->flags = val;
742
743 return 0;
744 }
745
OV4686_get_module_inf(struct OV4686 * OV4686,struct rkmodule_inf * inf)746 static void OV4686_get_module_inf(struct OV4686 *OV4686,
747 struct rkmodule_inf *inf)
748 {
749 memset(inf, 0, sizeof(*inf));
750 strlcpy(inf->base.sensor, OV4686_NAME, sizeof(inf->base.sensor));
751 strlcpy(inf->base.module, OV4686->module_name,
752 sizeof(inf->base.module));
753 strlcpy(inf->base.lens, OV4686->len_name, sizeof(inf->base.lens));
754 }
755
OV4686_set_hdrae(struct OV4686 * OV4686,struct preisp_hdrae_exp_s * ae)756 static int OV4686_set_hdrae(struct OV4686 *OV4686,
757 struct preisp_hdrae_exp_s *ae)
758 {
759 int ret = 0;
760 u32 l_exp = ae->long_exp_reg;
761 u32 m_exp = ae->middle_exp_reg;
762 u32 s_exp = ae->short_exp_reg;
763 u32 l_gain = ae->long_gain_reg;
764 u32 m_gain = ae->middle_gain_reg;
765 u32 s_gain = ae->short_gain_reg;
766
767 if (!OV4686->has_init_exp && !OV4686->streaming) {
768 OV4686->init_hdrae_exp = *ae;
769 OV4686->has_init_exp = true;
770 dev_dbg(&OV4686->client->dev, "OV4686 don't stream, record exp for hdr!\n");
771 return ret;
772 }
773
774 dev_dbg(&OV4686->client->dev,
775 "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
776 l_exp, l_gain, m_exp, m_gain, s_exp, s_gain);
777
778 if (l_exp < 3)
779 l_exp = 3;
780 if (m_exp < 3)
781 m_exp = 3;
782 if (s_exp < 3)
783 s_exp = 3;
784
785 if (OV4686->cur_mode->hdr_mode == HDR_X2) {
786 l_gain = m_gain;
787 l_exp = m_exp;
788 m_gain = s_gain;
789 m_exp = s_exp;
790 }
791
792 ret = OV4686_write_reg(OV4686->client, OV4686_GROUP_UPDATE_ADDRESS,
793 OV4686_REG_VALUE_08BIT, OV4686_GROUP_UPDATE_START_DATA);
794
795 ret |= OV4686_write_reg(OV4686->client, OV4686_REG_L_GAIN,
796 OV4686_REG_VALUE_16BIT, l_gain);
797 ret |= OV4686_write_reg(OV4686->client, OV4686_REG_L_EXP,
798 OV4686_REG_VALUE_24BIT, l_exp << 4);
799 ret |= OV4686_write_reg(OV4686->client, OV4686_REG_M_GAIN,
800 OV4686_REG_VALUE_16BIT, m_gain);
801 ret |= OV4686_write_reg(OV4686->client, OV4686_REG_M_EXP,
802 OV4686_REG_VALUE_24BIT, m_exp << 4);
803 if (OV4686->cur_mode->hdr_mode == HDR_X3) {
804 ret |= OV4686_write_reg(OV4686->client, OV4686_REG_S_GAIN,
805 OV4686_REG_VALUE_16BIT, s_gain);
806 ret |= OV4686_write_reg(OV4686->client, OV4686_REG_S_EXP,
807 OV4686_REG_VALUE_24BIT, s_exp << 4);
808 }
809 ret |= OV4686_write_reg(OV4686->client, OV4686_GROUP_UPDATE_ADDRESS,
810 OV4686_REG_VALUE_08BIT, OV4686_GROUP_UPDATE_END_DATA);
811 ret |= OV4686_write_reg(OV4686->client, OV4686_GROUP_UPDATE_ADDRESS,
812 OV4686_REG_VALUE_08BIT, OV4686_GROUP_UPDATE_LAUNCH);
813 return ret;
814 }
815
OV4686_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)816 static long OV4686_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
817 {
818 struct OV4686 *OV4686 = to_OV4686(sd);
819 struct rkmodule_hdr_cfg *hdr;
820 u32 i, h, w;
821 long ret = 0;
822 u32 stream = 0;
823
824 switch (cmd) {
825 case RKMODULE_GET_MODULE_INFO:
826 OV4686_get_module_inf(OV4686, (struct rkmodule_inf *)arg);
827 break;
828 case RKMODULE_GET_HDR_CFG:
829 hdr = (struct rkmodule_hdr_cfg *)arg;
830 hdr->esp.mode = HDR_NORMAL_VC;
831 hdr->hdr_mode = OV4686->cur_mode->hdr_mode;
832 break;
833 case RKMODULE_SET_HDR_CFG:
834 hdr = (struct rkmodule_hdr_cfg *)arg;
835 w = OV4686->cur_mode->width;
836 h = OV4686->cur_mode->height;
837 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
838 if (w == supported_modes[i].width &&
839 h == supported_modes[i].height &&
840 supported_modes[i].hdr_mode == hdr->hdr_mode) {
841 OV4686->cur_mode = &supported_modes[i];
842 break;
843 }
844 }
845 if (i == ARRAY_SIZE(supported_modes)) {
846 dev_err(&OV4686->client->dev,
847 "not find hdr mode:%d %dx%d config\n",
848 hdr->hdr_mode, w, h);
849 ret = -EINVAL;
850 } else {
851 w = OV4686->cur_mode->hts_def - OV4686->cur_mode->width;
852 h = OV4686->cur_mode->vts_def - OV4686->cur_mode->height;
853 __v4l2_ctrl_modify_range(OV4686->hblank, w, w, 1, w);
854 __v4l2_ctrl_modify_range(OV4686->vblank, h,
855 OV4686_VTS_MAX - OV4686->cur_mode->height, 1, h);
856 }
857 break;
858 case PREISP_CMD_SET_HDRAE_EXP:
859 return OV4686_set_hdrae(OV4686, arg);
860 case RKMODULE_SET_QUICK_STREAM:
861
862 stream = *((u32 *)arg);
863
864 if (stream)
865 ret = OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
866 OV4686_REG_VALUE_08BIT, OV4686_MODE_STREAMING);
867 else
868 ret = OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
869 OV4686_REG_VALUE_08BIT, OV4686_MODE_SW_STANDBY);
870 break;
871 default:
872 ret = -ENOIOCTLCMD;
873 break;
874 }
875
876 return ret;
877 }
878
879 #ifdef CONFIG_COMPAT
OV4686_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)880 static long OV4686_compat_ioctl32(struct v4l2_subdev *sd,
881 unsigned int cmd, unsigned long arg)
882 {
883 void __user *up = compat_ptr(arg);
884 struct rkmodule_inf *inf;
885 struct rkmodule_awb_cfg *cfg;
886 struct rkmodule_hdr_cfg *hdr;
887 struct preisp_hdrae_exp_s *hdrae;
888 long ret;
889 u32 stream = 0;
890
891 switch (cmd) {
892 case RKMODULE_GET_MODULE_INFO:
893 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
894 if (!inf) {
895 ret = -ENOMEM;
896 return ret;
897 }
898
899 ret = OV4686_ioctl(sd, cmd, inf);
900 if (!ret)
901 ret = copy_to_user(up, inf, sizeof(*inf));
902 kfree(inf);
903 break;
904 case RKMODULE_AWB_CFG:
905 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
906 if (!cfg) {
907 ret = -ENOMEM;
908 return ret;
909 }
910
911 ret = copy_from_user(cfg, up, sizeof(*cfg));
912 if (!ret)
913 ret = OV4686_ioctl(sd, cmd, cfg);
914 kfree(cfg);
915 break;
916 case RKMODULE_GET_HDR_CFG:
917 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
918 if (!hdr) {
919 ret = -ENOMEM;
920 return ret;
921 }
922
923 ret = OV4686_ioctl(sd, cmd, hdr);
924 if (!ret)
925 ret = copy_to_user(up, hdr, sizeof(*hdr));
926 kfree(hdr);
927 break;
928 case RKMODULE_SET_HDR_CFG:
929 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
930 if (!hdr) {
931 ret = -ENOMEM;
932 return ret;
933 }
934
935 ret = copy_from_user(hdr, up, sizeof(*hdr));
936 if (!ret)
937 ret = OV4686_ioctl(sd, cmd, hdr);
938 kfree(hdr);
939 break;
940 case PREISP_CMD_SET_HDRAE_EXP:
941 hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
942 if (!hdrae) {
943 ret = -ENOMEM;
944 return ret;
945 }
946
947 ret = copy_from_user(hdrae, up, sizeof(*hdrae));
948 if (!ret)
949 ret = OV4686_ioctl(sd, cmd, hdrae);
950 kfree(hdrae);
951 break;
952 case RKMODULE_SET_QUICK_STREAM:
953 ret = copy_from_user(&stream, up, sizeof(u32));
954 if (!ret)
955 ret = OV4686_ioctl(sd, cmd, &stream);
956 break;
957 default:
958 ret = -ENOIOCTLCMD;
959 break;
960 }
961
962 return ret;
963 }
964 #endif
965
__OV4686_start_stream(struct OV4686 * OV4686)966 static int __OV4686_start_stream(struct OV4686 *OV4686)
967 {
968 int ret;
969
970 ret = OV4686_write_array(OV4686->client, OV4686_2688x1520_regs);
971 ret |= OV4686_write_array(OV4686->client, OV4686->cur_mode->reg_list);
972 if (ret)
973 return ret;
974
975 /* In case these controls are set before streaming */
976 ret = __v4l2_ctrl_handler_setup(&OV4686->ctrl_handler);
977 if (ret)
978 return ret;
979 if (OV4686->has_init_exp && OV4686->cur_mode->hdr_mode != NO_HDR) {
980 ret = OV4686_ioctl(&OV4686->subdev,
981 PREISP_CMD_SET_HDRAE_EXP,
982 &OV4686->init_hdrae_exp);
983 if (ret) {
984 dev_err(&OV4686->client->dev,
985 "init exp fail in hdr mode\n");
986 return ret;
987 }
988 }
989
990 return OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
991 OV4686_REG_VALUE_08BIT, OV4686_MODE_STREAMING);
992 }
993
__OV4686_stop_stream(struct OV4686 * OV4686)994 static int __OV4686_stop_stream(struct OV4686 *OV4686)
995 {
996 OV4686->has_init_exp = false;
997 return OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
998 OV4686_REG_VALUE_08BIT, OV4686_MODE_SW_STANDBY);
999 }
1000
OV4686_s_stream(struct v4l2_subdev * sd,int on)1001 static int OV4686_s_stream(struct v4l2_subdev *sd, int on)
1002 {
1003 struct OV4686 *OV4686 = to_OV4686(sd);
1004 struct i2c_client *client = OV4686->client;
1005 int ret = 0;
1006
1007 mutex_lock(&OV4686->mutex);
1008 on = !!on;
1009 if (on == OV4686->streaming)
1010 goto unlock_and_return;
1011
1012 if (on) {
1013 ret = pm_runtime_get_sync(&client->dev);
1014 if (ret < 0) {
1015 pm_runtime_put_noidle(&client->dev);
1016 goto unlock_and_return;
1017 }
1018
1019 ret = __OV4686_start_stream(OV4686);
1020 if (ret) {
1021 v4l2_err(sd, "start stream failed while write regs\n");
1022 pm_runtime_put(&client->dev);
1023 goto unlock_and_return;
1024 }
1025 } else {
1026 __OV4686_stop_stream(OV4686);
1027 pm_runtime_put(&client->dev);
1028 }
1029
1030 OV4686->streaming = on;
1031
1032 unlock_and_return:
1033 mutex_unlock(&OV4686->mutex);
1034
1035 return ret;
1036 }
1037
OV4686_s_power(struct v4l2_subdev * sd,int on)1038 static int OV4686_s_power(struct v4l2_subdev *sd, int on)
1039 {
1040 struct OV4686 *OV4686 = to_OV4686(sd);
1041 struct i2c_client *client = OV4686->client;
1042 int ret = 0;
1043
1044 mutex_lock(&OV4686->mutex);
1045
1046 /* If the power state is not modified - no work to do. */
1047 if (OV4686->power_on == !!on)
1048 goto unlock_and_return;
1049
1050 if (on) {
1051 ret = pm_runtime_get_sync(&client->dev);
1052 if (ret < 0) {
1053 pm_runtime_put_noidle(&client->dev);
1054 goto unlock_and_return;
1055 }
1056
1057 ret = OV4686_write_array(OV4686->client, OV4686_global_regs);
1058 if (ret) {
1059 v4l2_err(sd, "could not set init registers\n");
1060 pm_runtime_put_noidle(&client->dev);
1061 goto unlock_and_return;
1062 }
1063
1064 OV4686->power_on = true;
1065 } else {
1066 pm_runtime_put(&client->dev);
1067 OV4686->power_on = false;
1068 }
1069
1070 unlock_and_return:
1071 mutex_unlock(&OV4686->mutex);
1072
1073 return ret;
1074 }
1075
1076 /* Calculate the delay in us by clock rate and clock cycles */
OV4686_cal_delay(u32 cycles)1077 static inline u32 OV4686_cal_delay(u32 cycles)
1078 {
1079 return DIV_ROUND_UP(cycles, OV4686_XVCLK_FREQ / 1000 / 1000);
1080 }
1081
__OV4686_power_on(struct OV4686 * OV4686)1082 static int __OV4686_power_on(struct OV4686 *OV4686)
1083 {
1084 int ret;
1085 u32 delay_us;
1086 struct device *dev = &OV4686->client->dev;
1087
1088 if (!IS_ERR_OR_NULL(OV4686->pins_default)) {
1089 ret = pinctrl_select_state(OV4686->pinctrl,
1090 OV4686->pins_default);
1091 if (ret < 0)
1092 dev_err(dev, "could not set pins\n");
1093 }
1094 ret = clk_set_rate(OV4686->xvclk, OV4686_XVCLK_FREQ);
1095 if (ret < 0)
1096 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
1097 if (clk_get_rate(OV4686->xvclk) != OV4686_XVCLK_FREQ)
1098 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1099 ret = clk_prepare_enable(OV4686->xvclk);
1100 if (ret < 0) {
1101 dev_err(dev, "Failed to enable xvclk\n");
1102 return ret;
1103 }
1104 if (!IS_ERR(OV4686->reset_gpio))
1105 gpiod_set_value_cansleep(OV4686->reset_gpio, 0);
1106
1107 ret = regulator_bulk_enable(OV4686_NUM_SUPPLIES, OV4686->supplies);
1108 if (ret < 0) {
1109 dev_err(dev, "Failed to enable regulators\n");
1110 goto disable_clk;
1111 }
1112
1113 if (!IS_ERR(OV4686->reset_gpio))
1114 gpiod_set_value_cansleep(OV4686->reset_gpio, 1);
1115
1116 usleep_range(500, 1000);
1117 if (!IS_ERR(OV4686->pwdn_gpio))
1118 gpiod_set_value_cansleep(OV4686->pwdn_gpio, 1);
1119
1120 /* 8192 cycles prior to first SCCB transaction */
1121 delay_us = OV4686_cal_delay(8192);
1122 usleep_range(delay_us, delay_us * 2);
1123
1124 return 0;
1125
1126 disable_clk:
1127 clk_disable_unprepare(OV4686->xvclk);
1128
1129 return ret;
1130 }
1131
__OV4686_power_off(struct OV4686 * OV4686)1132 static void __OV4686_power_off(struct OV4686 *OV4686)
1133 {
1134 int ret;
1135 struct device *dev = &OV4686->client->dev;
1136
1137 if (!IS_ERR(OV4686->pwdn_gpio))
1138 gpiod_set_value_cansleep(OV4686->pwdn_gpio, 0);
1139 clk_disable_unprepare(OV4686->xvclk);
1140 if (!IS_ERR(OV4686->reset_gpio))
1141 gpiod_set_value_cansleep(OV4686->reset_gpio, 0);
1142 if (!IS_ERR_OR_NULL(OV4686->pins_sleep)) {
1143 ret = pinctrl_select_state(OV4686->pinctrl,
1144 OV4686->pins_sleep);
1145 if (ret < 0)
1146 dev_dbg(dev, "could not set pins\n");
1147 }
1148 regulator_bulk_disable(OV4686_NUM_SUPPLIES, OV4686->supplies);
1149 }
1150
OV4686_runtime_resume(struct device * dev)1151 static int OV4686_runtime_resume(struct device *dev)
1152 {
1153 struct i2c_client *client = to_i2c_client(dev);
1154 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1155 struct OV4686 *OV4686 = to_OV4686(sd);
1156
1157 return __OV4686_power_on(OV4686);
1158 }
1159
OV4686_runtime_suspend(struct device * dev)1160 static int OV4686_runtime_suspend(struct device *dev)
1161 {
1162 struct i2c_client *client = to_i2c_client(dev);
1163 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1164 struct OV4686 *OV4686 = to_OV4686(sd);
1165
1166 __OV4686_power_off(OV4686);
1167
1168 return 0;
1169 }
1170
1171 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
OV4686_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1172 static int OV4686_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1173 {
1174 struct OV4686 *OV4686 = to_OV4686(sd);
1175 struct v4l2_mbus_framefmt *try_fmt =
1176 v4l2_subdev_get_try_format(sd, fh->pad, 0);
1177 const struct OV4686_mode *def_mode = &supported_modes[0];
1178
1179 mutex_lock(&OV4686->mutex);
1180 /* Initialize try_fmt */
1181 try_fmt->width = def_mode->width;
1182 try_fmt->height = def_mode->height;
1183 try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;//grbg
1184 try_fmt->field = V4L2_FIELD_NONE;
1185
1186 mutex_unlock(&OV4686->mutex);
1187 /* No crop or compose */
1188
1189 return 0;
1190 }
1191 #endif
1192
OV4686_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)1193 static int OV4686_enum_frame_interval(struct v4l2_subdev *sd,
1194 struct v4l2_subdev_pad_config *cfg,
1195 struct v4l2_subdev_frame_interval_enum *fie)
1196 {
1197 if (fie->index >= ARRAY_SIZE(supported_modes))
1198 return -EINVAL;
1199
1200 fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
1201 fie->width = supported_modes[fie->index].width;
1202 fie->height = supported_modes[fie->index].height;
1203 fie->interval = supported_modes[fie->index].max_fps;
1204 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
1205 return 0;
1206 }
1207
1208 static const struct dev_pm_ops OV4686_pm_ops = {
1209 SET_RUNTIME_PM_OPS(OV4686_runtime_suspend,
1210 OV4686_runtime_resume, NULL)
1211 };
1212
1213 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1214 static const struct v4l2_subdev_internal_ops OV4686_internal_ops = {
1215 .open = OV4686_open,
1216 };
1217 #endif
1218
1219 static const struct v4l2_subdev_core_ops OV4686_core_ops = {
1220 .s_power = OV4686_s_power,
1221 .ioctl = OV4686_ioctl,
1222 #ifdef CONFIG_COMPAT
1223 .compat_ioctl32 = OV4686_compat_ioctl32,
1224 #endif
1225 };
1226
1227 static const struct v4l2_subdev_video_ops OV4686_video_ops = {
1228 .s_stream = OV4686_s_stream,
1229 .g_frame_interval = OV4686_g_frame_interval,
1230 };
1231
1232 static const struct v4l2_subdev_pad_ops OV4686_pad_ops = {
1233 .enum_mbus_code = OV4686_enum_mbus_code,
1234 .enum_frame_size = OV4686_enum_frame_sizes,
1235 .enum_frame_interval = OV4686_enum_frame_interval,
1236 .get_fmt = OV4686_get_fmt,
1237 .set_fmt = OV4686_set_fmt,
1238 .get_mbus_config = OV4686_g_mbus_config,
1239 };
1240
1241 static const struct v4l2_subdev_ops OV4686_subdev_ops = {
1242 .core = &OV4686_core_ops,
1243 .video = &OV4686_video_ops,
1244 .pad = &OV4686_pad_ops,
1245 };
1246
OV4686_set_ctrl(struct v4l2_ctrl * ctrl)1247 static int OV4686_set_ctrl(struct v4l2_ctrl *ctrl)
1248 {
1249 struct OV4686 *OV4686 = container_of(ctrl->handler,
1250 struct OV4686, ctrl_handler);
1251 struct i2c_client *client = OV4686->client;
1252 s64 max;
1253 int ret = 0;
1254 u32 val = 0;
1255
1256 /* Propagate change of current control to all related controls */
1257 switch (ctrl->id) {
1258 case V4L2_CID_VBLANK:
1259 /* Update max exposure while meeting expected vblanking */
1260 max = OV4686->cur_mode->height + ctrl->val - 4;
1261 __v4l2_ctrl_modify_range(OV4686->exposure,
1262 OV4686->exposure->minimum, max,
1263 OV4686->exposure->step,
1264 OV4686->exposure->default_value);
1265 break;
1266 }
1267
1268 if (!pm_runtime_get_if_in_use(&client->dev))
1269 return 0;
1270
1271 switch (ctrl->id) {
1272 case V4L2_CID_EXPOSURE:
1273 /* 4 least significant bits of expsoure are fractional part */
1274 ret = OV4686_write_reg(OV4686->client, OV4686_REG_EXPOSURE,
1275 OV4686_REG_VALUE_24BIT, ctrl->val << 4);
1276 break;
1277 case V4L2_CID_ANALOGUE_GAIN:
1278 ret = OV4686_write_reg(OV4686->client, OV4686_REG_GAIN_H,
1279 OV4686_REG_VALUE_08BIT,
1280 (ctrl->val >> OV4686_GAIN_H_SHIFT) & OV4686_GAIN_H_MASK);
1281 ret |= OV4686_write_reg(OV4686->client, OV4686_REG_GAIN_L,
1282 OV4686_REG_VALUE_08BIT,
1283 ctrl->val & OV4686_GAIN_L_MASK);
1284 break;
1285 case V4L2_CID_VBLANK:
1286 ret = OV4686_write_reg(OV4686->client, OV4686_REG_VTS,
1287 OV4686_REG_VALUE_16BIT,
1288 ctrl->val + OV4686->cur_mode->height);
1289 break;
1290 case V4L2_CID_TEST_PATTERN:
1291 ret = OV4686_enable_test_pattern(OV4686, ctrl->val);
1292 break;
1293 case V4L2_CID_HFLIP:
1294 ret = OV4686_read_reg(OV4686->client, OV4686_HFLIP_REG,
1295 OV4686_REG_VALUE_08BIT,
1296 &val);
1297 if (ctrl->val)
1298 val |= MIRROR_BIT_MASK;
1299 else
1300 val &= ~MIRROR_BIT_MASK;
1301 ret = OV4686_write_reg(OV4686->client, OV4686_HFLIP_REG,
1302 OV4686_REG_VALUE_08BIT,
1303 val);
1304 break;
1305 case V4L2_CID_VFLIP:
1306 ret = OV4686_read_reg(OV4686->client, OV4686_VFLIP_REG,
1307 OV4686_REG_VALUE_08BIT,
1308 &val);
1309 if (ctrl->val)
1310 val |= FLIP_BIT_MASK;
1311 else
1312 val &= ~FLIP_BIT_MASK;
1313 ret = OV4686_write_reg(OV4686->client, OV4686_VFLIP_REG,
1314 OV4686_REG_VALUE_08BIT,
1315 val);
1316 break;
1317 default:
1318 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1319 __func__, ctrl->id, ctrl->val);
1320 break;
1321 }
1322
1323 pm_runtime_put(&client->dev);
1324
1325 return ret;
1326 }
1327
1328 static const struct v4l2_ctrl_ops OV4686_ctrl_ops = {
1329 .s_ctrl = OV4686_set_ctrl,
1330 };
1331
OV4686_initialize_controls(struct OV4686 * OV4686)1332 static int OV4686_initialize_controls(struct OV4686 *OV4686)
1333 {
1334 const struct OV4686_mode *mode;
1335 struct v4l2_ctrl_handler *handler;
1336 struct v4l2_ctrl *ctrl;
1337 s64 exposure_max, vblank_def;
1338 u32 h_blank;
1339 int ret;
1340
1341 handler = &OV4686->ctrl_handler;
1342 mode = OV4686->cur_mode;
1343 ret = v4l2_ctrl_handler_init(handler, 9);
1344 if (ret)
1345 return ret;
1346 handler->lock = &OV4686->mutex;
1347
1348 ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
1349 0, 0, link_freq_menu_items);
1350 if (ctrl)
1351 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1352
1353 v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
1354 0, OV4686_PIXEL_RATE, 1, OV4686_PIXEL_RATE);
1355
1356 h_blank = mode->hts_def - mode->width;
1357 OV4686->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1358 h_blank, h_blank, 1, h_blank);
1359 if (OV4686->hblank)
1360 OV4686->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1361
1362 vblank_def = mode->vts_def - mode->height;
1363 OV4686->vblank = v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
1364 V4L2_CID_VBLANK, vblank_def,
1365 OV4686_VTS_MAX - mode->height,
1366 1, vblank_def);
1367
1368 exposure_max = mode->vts_def - 4;
1369 OV4686->exposure = v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
1370 V4L2_CID_EXPOSURE, OV4686_EXPOSURE_MIN,
1371 exposure_max, OV4686_EXPOSURE_STEP,
1372 mode->exp_def);
1373
1374 OV4686->anal_gain = v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
1375 V4L2_CID_ANALOGUE_GAIN, OV4686_GAIN_MIN,
1376 OV4686_GAIN_MAX, OV4686_GAIN_STEP,
1377 OV4686_GAIN_DEFAULT);
1378
1379 OV4686->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
1380 &OV4686_ctrl_ops, V4L2_CID_TEST_PATTERN,
1381 ARRAY_SIZE(OV4686_test_pattern_menu) - 1,
1382 0, 0, OV4686_test_pattern_menu);
1383 v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
1384 V4L2_CID_HFLIP, 0, 1, 1, 0);
1385
1386 v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
1387 V4L2_CID_VFLIP, 0, 1, 1, 0);
1388
1389 if (handler->error) {
1390 ret = handler->error;
1391 dev_err(&OV4686->client->dev,
1392 "Failed to init controls(%d)\n", ret);
1393 goto err_free_handler;
1394 }
1395
1396 OV4686->subdev.ctrl_handler = handler;
1397 OV4686->has_init_exp = false;
1398
1399 return 0;
1400
1401 err_free_handler:
1402 v4l2_ctrl_handler_free(handler);
1403
1404 return ret;
1405 }
1406
OV4686_check_sensor_id(struct OV4686 * OV4686,struct i2c_client * client)1407 static int OV4686_check_sensor_id(struct OV4686 *OV4686,
1408 struct i2c_client *client)
1409 {
1410 struct device *dev = &OV4686->client->dev;
1411 u32 id = 0;
1412 int ret;
1413
1414 ret = OV4686_read_reg(client, OV4686_REG_CHIP_ID,
1415 OV4686_REG_VALUE_16BIT, &id);
1416 if (id != CHIP_ID) {
1417 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1418 return -ENODEV;
1419 }
1420
1421 dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
1422
1423 return 0;
1424 }
1425
OV4686_configure_regulators(struct OV4686 * OV4686)1426 static int OV4686_configure_regulators(struct OV4686 *OV4686)
1427 {
1428 unsigned int i;
1429
1430 for (i = 0; i < OV4686_NUM_SUPPLIES; i++)
1431 OV4686->supplies[i].supply = OV4686_supply_names[i];
1432
1433 return devm_regulator_bulk_get(&OV4686->client->dev,
1434 OV4686_NUM_SUPPLIES,
1435 OV4686->supplies);
1436 }
1437
OV4686_probe(struct i2c_client * client,const struct i2c_device_id * id)1438 static int OV4686_probe(struct i2c_client *client,
1439 const struct i2c_device_id *id)
1440 {
1441 struct device *dev = &client->dev;
1442 struct device_node *node = dev->of_node;
1443 struct OV4686 *OV4686;
1444 struct v4l2_subdev *sd;
1445 char facing[2];
1446 int ret;
1447 u32 i, hdr_mode = 0;
1448
1449 dev_info(dev, "driver version: %02x.%02x.%02x",
1450 DRIVER_VERSION >> 16,
1451 (DRIVER_VERSION & 0xff00) >> 8,
1452 DRIVER_VERSION & 0x00ff);
1453
1454 OV4686 = devm_kzalloc(dev, sizeof(*OV4686), GFP_KERNEL);
1455 if (!OV4686)
1456 return -ENOMEM;
1457
1458 of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1459 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1460 &OV4686->module_index);
1461 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1462 &OV4686->module_facing);
1463 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1464 &OV4686->module_name);
1465 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1466 &OV4686->len_name);
1467 if (ret) {
1468 dev_err(dev, "could not get module information!\n");
1469 return -EINVAL;
1470 }
1471
1472 OV4686->client = client;
1473 for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
1474 if (hdr_mode == supported_modes[i].hdr_mode) {
1475 OV4686->cur_mode = &supported_modes[i];
1476 break;
1477 }
1478 }
1479 if (i == ARRAY_SIZE(supported_modes))
1480 OV4686->cur_mode = &supported_modes[0];
1481
1482 OV4686->xvclk = devm_clk_get(dev, "xvclk");
1483 if (IS_ERR(OV4686->xvclk)) {
1484 dev_err(dev, "Failed to get xvclk\n");
1485 return -EINVAL;
1486 }
1487
1488 OV4686->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
1489 if (IS_ERR(OV4686->reset_gpio))
1490 dev_warn(dev, "Failed to get reset-gpios\n");
1491
1492 OV4686->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1493 if (IS_ERR(OV4686->pwdn_gpio))
1494 dev_warn(dev, "Failed to get pwdn-gpios\n");
1495
1496 OV4686->pinctrl = devm_pinctrl_get(dev);
1497 if (!IS_ERR(OV4686->pinctrl)) {
1498 OV4686->pins_default =
1499 pinctrl_lookup_state(OV4686->pinctrl,
1500 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1501 if (IS_ERR(OV4686->pins_default))
1502 dev_err(dev, "could not get default pinstate\n");
1503
1504 OV4686->pins_sleep =
1505 pinctrl_lookup_state(OV4686->pinctrl,
1506 OF_CAMERA_PINCTRL_STATE_SLEEP);
1507 if (IS_ERR(OV4686->pins_sleep))
1508 dev_err(dev, "could not get sleep pinstate\n");
1509 } else {
1510 dev_err(dev, "no pinctrl\n");
1511 }
1512
1513 ret = OV4686_configure_regulators(OV4686);
1514 if (ret) {
1515 dev_err(dev, "Failed to get power regulators\n");
1516 return ret;
1517 }
1518
1519 mutex_init(&OV4686->mutex);
1520
1521 sd = &OV4686->subdev;
1522 v4l2_i2c_subdev_init(sd, client, &OV4686_subdev_ops);
1523 ret = OV4686_initialize_controls(OV4686);
1524 if (ret)
1525 goto err_destroy_mutex;
1526
1527 ret = __OV4686_power_on(OV4686);
1528 if (ret)
1529 goto err_free_handler;
1530
1531 ret = OV4686_check_sensor_id(OV4686, client);
1532 if (ret)
1533 goto err_power_off;
1534
1535 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1536 sd->internal_ops = &OV4686_internal_ops;
1537 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1538 V4L2_SUBDEV_FL_HAS_EVENTS;
1539 #endif
1540 #if defined(CONFIG_MEDIA_CONTROLLER)
1541 OV4686->pad.flags = MEDIA_PAD_FL_SOURCE;
1542 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1543 ret = media_entity_pads_init(&sd->entity, 1, &OV4686->pad);
1544 if (ret < 0)
1545 goto err_power_off;
1546 #endif
1547
1548 memset(facing, 0, sizeof(facing));
1549 if (strcmp(OV4686->module_facing, "back") == 0)
1550 facing[0] = 'b';
1551 else
1552 facing[0] = 'f';
1553
1554 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1555 OV4686->module_index, facing,
1556 OV4686_NAME, dev_name(sd->dev));
1557 ret = v4l2_async_register_subdev_sensor_common(sd);
1558 if (ret) {
1559 dev_err(dev, "v4l2 async register subdev failed\n");
1560 goto err_clean_entity;
1561 }
1562
1563 pm_runtime_set_active(dev);
1564 pm_runtime_enable(dev);
1565 pm_runtime_idle(dev);
1566
1567 return 0;
1568
1569 err_clean_entity:
1570 #if defined(CONFIG_MEDIA_CONTROLLER)
1571 media_entity_cleanup(&sd->entity);
1572 #endif
1573 err_power_off:
1574 __OV4686_power_off(OV4686);
1575 err_free_handler:
1576 v4l2_ctrl_handler_free(&OV4686->ctrl_handler);
1577 err_destroy_mutex:
1578 mutex_destroy(&OV4686->mutex);
1579
1580 return ret;
1581 }
1582
OV4686_remove(struct i2c_client * client)1583 static int OV4686_remove(struct i2c_client *client)
1584 {
1585 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1586 struct OV4686 *OV4686 = to_OV4686(sd);
1587
1588 v4l2_async_unregister_subdev(sd);
1589 #if defined(CONFIG_MEDIA_CONTROLLER)
1590 media_entity_cleanup(&sd->entity);
1591 #endif
1592 v4l2_ctrl_handler_free(&OV4686->ctrl_handler);
1593 mutex_destroy(&OV4686->mutex);
1594
1595 pm_runtime_disable(&client->dev);
1596 if (!pm_runtime_status_suspended(&client->dev))
1597 __OV4686_power_off(OV4686);
1598 pm_runtime_set_suspended(&client->dev);
1599
1600 return 0;
1601 }
1602
1603 #if IS_ENABLED(CONFIG_OF)
1604 static const struct of_device_id OV4686_of_match[] = {
1605 { .compatible = "ovti,OV4686" },
1606 {},
1607 };
1608 MODULE_DEVICE_TABLE(of, OV4686_of_match);
1609 #endif
1610
1611 static const struct i2c_device_id OV4686_match_id[] = {
1612 { "ovti,OV4686", 0 },
1613 { },
1614 };
1615
1616 static struct i2c_driver OV4686_i2c_driver = {
1617 .driver = {
1618 .name = OV4686_NAME,
1619 .pm = &OV4686_pm_ops,
1620 .of_match_table = of_match_ptr(OV4686_of_match),
1621 },
1622 .probe = &OV4686_probe,
1623 .remove = &OV4686_remove,
1624 .id_table = OV4686_match_id,
1625 };
1626
sensor_mod_init(void)1627 static int __init sensor_mod_init(void)
1628 {
1629 return i2c_add_driver(&OV4686_i2c_driver);
1630 }
1631
sensor_mod_exit(void)1632 static void __exit sensor_mod_exit(void)
1633 {
1634 i2c_del_driver(&OV4686_i2c_driver);
1635 }
1636
1637 device_initcall_sync(sensor_mod_init);
1638 module_exit(sensor_mod_exit);
1639
1640 MODULE_DESCRIPTION("OmniVision OV4686 sensor driver");
1641 MODULE_LICENSE("GPL v2");
1642