1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* Copyright (c) 2020 Rockchip Electronics Co., Ltd. */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #ifndef OTP_EEPROM_HEAD_H 5*4882a593Smuzhiyun #define OTP_EEPROM_HEAD_H 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #define SLAVE_ADDRESS 0x50 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define INFO_FLAG_REG 0X0000 10*4882a593Smuzhiyun #define INFO_ID_REG 0X0001 11*4882a593Smuzhiyun #define SMARTISAN_PN_REG 0X000A 12*4882a593Smuzhiyun #define SMARTISAN_PN_SIZE 0x000C //12 13*4882a593Smuzhiyun #define MOUDLE_ID_REG 0X0016 14*4882a593Smuzhiyun #define MOUDLE_ID_SIZE 0X0010 //16 15*4882a593Smuzhiyun #define MIRROR_FLIP_REG 0X0026 16*4882a593Smuzhiyun #define FULL_SIZE_WIGHT_REG 0X0027 17*4882a593Smuzhiyun #define FULL_SIZE_HEIGHT_REG 0X0029 18*4882a593Smuzhiyun #define INFO_CHECKSUM_REG 0X0033 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AWB_FLAG_REG 0x0034 21*4882a593Smuzhiyun #define AWB_VERSION_REG 0x0035 22*4882a593Smuzhiyun #define CUR_R_REG 0x0036 23*4882a593Smuzhiyun #define CUR_B_REG 0x0038 24*4882a593Smuzhiyun #define CUR_G_REG 0x003A 25*4882a593Smuzhiyun #define GOLDEN_R_REG 0x003C 26*4882a593Smuzhiyun #define GOLDEN_B_REG 0x003E 27*4882a593Smuzhiyun #define GOLDEN_G_REG 0x0040 28*4882a593Smuzhiyun #define AWB_CHECKSUM_REG 0x0062 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define LSC_FLAG_REG 0X0063 31*4882a593Smuzhiyun #define LSC_VERSION_REG 0x0064 32*4882a593Smuzhiyun #define LSC_TABLE_SIZE_REG 0x0065 33*4882a593Smuzhiyun #define LSC_DATA_START_REG 0x0067 34*4882a593Smuzhiyun #define LSC_DATA_SIZE 0x0908 //2312 35*4882a593Smuzhiyun #define LSC_CHECKSUM_REG 0x097B 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define SFR_FLAG_REG 0X097C 38*4882a593Smuzhiyun #define SFR_EQUIQ_NUM_REG 0X097D 39*4882a593Smuzhiyun #define SFR_C_HOR_REG 0X097E 40*4882a593Smuzhiyun #define SFR_C_VER_REG 0X0980 41*4882a593Smuzhiyun #define SFR_TOP_L_HOR_REG 0X0982 42*4882a593Smuzhiyun #define SFR_TOP_L_VER_REG 0X0984 43*4882a593Smuzhiyun #define SFR_TOP_R_HOR_REG 0X0986 44*4882a593Smuzhiyun #define SFR_TOP_R_VER_REG 0X0988 45*4882a593Smuzhiyun #define SFR_BOTTOM_L_HOR_REG 0X098A 46*4882a593Smuzhiyun #define SFR_BOTTOM_L_VER_REG 0X098C 47*4882a593Smuzhiyun #define SFR_BOTTOM_R_HOR_REG 0X098E 48*4882a593Smuzhiyun #define SFR_BOTTOM_R_VER_REG 0X0990 49*4882a593Smuzhiyun #define SFR_CHECKSUM_REG 0x09BE 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define TOTAL_CHECKSUM_REG 0x09BF 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define RKMOUDLE_ID_SIZE 0X0004 //16 54*4882a593Smuzhiyun #define RK_INFO_RESERVED_SIZE 0x000f// v1 23, v2 0x000f 55*4882a593Smuzhiyun #define RK_AWB_RESERVED_SIZE 0x001c 56*4882a593Smuzhiyun #define RK_LSC_RESERVED_SIZE 0x0020 57*4882a593Smuzhiyun #define RK_GAINMAP_SIZE 0x0800 58*4882a593Smuzhiyun #define RK_DCCMAP_SIZE 0x0200 59*4882a593Smuzhiyun #define RK_PDAF_RESERVED_SIZE 0x0020 60*4882a593Smuzhiyun #define RK_AF_RESERVED_SIZE 0x0014 61*4882a593Smuzhiyun #define RKOTP_MAX_MODULE 0x0008 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define RKOTP_REG_START 0x0008//v1 0, v2 0x0008 64*4882a593Smuzhiyun #define RKOTP_INFO_ID 0 65*4882a593Smuzhiyun #define RKOTP_AWB_ID 1 66*4882a593Smuzhiyun #define RKOTP_LSC_ID 2 67*4882a593Smuzhiyun #define RKOTP_PDAF_ID 3 68*4882a593Smuzhiyun #define RKOTP_AF_ID 4 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct id_defination { 71*4882a593Smuzhiyun u32 supplier_id; 72*4882a593Smuzhiyun u32 year; 73*4882a593Smuzhiyun u32 month; 74*4882a593Smuzhiyun u32 day; 75*4882a593Smuzhiyun u32 sensor_id; 76*4882a593Smuzhiyun u32 lens_id; 77*4882a593Smuzhiyun u32 vcm_id; 78*4882a593Smuzhiyun u32 driver_ic_id; 79*4882a593Smuzhiyun u32 color_temperature_id; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct full_size { 83*4882a593Smuzhiyun u16 width; 84*4882a593Smuzhiyun u16 height; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct basic_info { 88*4882a593Smuzhiyun u32 flag; 89*4882a593Smuzhiyun struct id_defination id; 90*4882a593Smuzhiyun u32 smartisan_pn[SMARTISAN_PN_SIZE]; 91*4882a593Smuzhiyun u32 modul_id[MOUDLE_ID_SIZE]; 92*4882a593Smuzhiyun u32 mirror_flip; 93*4882a593Smuzhiyun struct full_size size; 94*4882a593Smuzhiyun u32 checksum; 95*4882a593Smuzhiyun u32 version; 96*4882a593Smuzhiyun u32 module_size; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct awb_otp_info { 100*4882a593Smuzhiyun u32 flag; 101*4882a593Smuzhiyun u32 version; 102*4882a593Smuzhiyun u32 r_ratio; 103*4882a593Smuzhiyun u32 b_ratio; 104*4882a593Smuzhiyun u32 g_ratio; 105*4882a593Smuzhiyun u32 r_golden; 106*4882a593Smuzhiyun u32 b_golden; 107*4882a593Smuzhiyun u32 g_golden; 108*4882a593Smuzhiyun u32 checksum; 109*4882a593Smuzhiyun u32 size; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct lsc_otp_info { 113*4882a593Smuzhiyun u32 flag; 114*4882a593Smuzhiyun u32 version; 115*4882a593Smuzhiyun u16 table_size; 116*4882a593Smuzhiyun u8 data[LSC_DATA_SIZE]; 117*4882a593Smuzhiyun u32 checksum; 118*4882a593Smuzhiyun u32 size; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun struct sfr_data { 122*4882a593Smuzhiyun u32 top_l_horizontal; 123*4882a593Smuzhiyun u32 top_l_vertical; 124*4882a593Smuzhiyun u32 top_r_horizontal; 125*4882a593Smuzhiyun u32 top_r_vertical; 126*4882a593Smuzhiyun u32 bottom_l_horizontal; 127*4882a593Smuzhiyun u32 bottom_l_vertical; 128*4882a593Smuzhiyun u32 bottom_r_horizontal; 129*4882a593Smuzhiyun u32 bottom_r_vertical; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun struct sfr_otp_info { 133*4882a593Smuzhiyun u32 flag; 134*4882a593Smuzhiyun u32 equip_num; 135*4882a593Smuzhiyun u32 center_horizontal; 136*4882a593Smuzhiyun u32 center_vertical; 137*4882a593Smuzhiyun struct sfr_data data[3]; 138*4882a593Smuzhiyun u32 checksum; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun struct pdaf_otp_info { 142*4882a593Smuzhiyun u32 flag; 143*4882a593Smuzhiyun u32 version; 144*4882a593Smuzhiyun u32 gainmap_width; 145*4882a593Smuzhiyun u32 gainmap_height; 146*4882a593Smuzhiyun u32 gainmap[RK_GAINMAP_SIZE]; 147*4882a593Smuzhiyun u32 gainmap_checksum; 148*4882a593Smuzhiyun u32 dcc_mode; 149*4882a593Smuzhiyun u32 dcc_dir; 150*4882a593Smuzhiyun u32 dccmap_width; 151*4882a593Smuzhiyun u32 dccmap_height; 152*4882a593Smuzhiyun u32 dccmap[RK_DCCMAP_SIZE]; 153*4882a593Smuzhiyun u32 dccmap_checksum; 154*4882a593Smuzhiyun u32 checksum; 155*4882a593Smuzhiyun u32 size; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun struct af_otp_info { 159*4882a593Smuzhiyun u32 flag; 160*4882a593Smuzhiyun u32 version; 161*4882a593Smuzhiyun u32 af_inf; 162*4882a593Smuzhiyun u32 af_macro; 163*4882a593Smuzhiyun u32 checksum; 164*4882a593Smuzhiyun u32 size; 165*4882a593Smuzhiyun }; 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun struct otp_info { 168*4882a593Smuzhiyun u32 flag; 169*4882a593Smuzhiyun u32 total_checksum; 170*4882a593Smuzhiyun struct basic_info basic_data; 171*4882a593Smuzhiyun struct awb_otp_info awb_data; 172*4882a593Smuzhiyun struct lsc_otp_info lsc_data; 173*4882a593Smuzhiyun struct sfr_otp_info sfr_otp_data; 174*4882a593Smuzhiyun struct pdaf_otp_info pdaf_data; 175*4882a593Smuzhiyun struct af_otp_info af_data; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* eeprom device structure */ 179*4882a593Smuzhiyun struct eeprom_device { 180*4882a593Smuzhiyun struct v4l2_subdev sd; 181*4882a593Smuzhiyun struct i2c_client *client; 182*4882a593Smuzhiyun struct otp_info *otp; 183*4882a593Smuzhiyun struct proc_dir_entry *procfs; 184*4882a593Smuzhiyun char name[128]; 185*4882a593Smuzhiyun struct mutex mutex; 186*4882a593Smuzhiyun }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun #endif /* OTP_EEPROM_HEAD_H */ 189*4882a593Smuzhiyun 190