1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * os03b10 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X01 first version.
8 */
9
10 //define DEBUG
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/delay.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/sysfs.h>
20 #include <linux/slab.h>
21 #include <linux/version.h>
22 #include <linux/rk-camera-module.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-async.h>
25 #include <media/v4l2-ctrls.h>
26 #include <media/v4l2-subdev.h>
27 #include <linux/pinctrl/consumer.h>
28 #include <linux/rk-preisp.h>
29 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
30
31 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
32
33 #ifndef V4L2_CID_DIGITAL_GAIN
34 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
35 #endif
36
37 #define OS03B10_CHIP_ID 0x5303
38 #define OS03B10_REG_CHIP_ID_H 0x02
39 #define OS03B10_REG_CHIP_ID_L 0x03
40
41 #define OS03B10_XVCLK_FREQ 24000000
42 #define BITS_PER_SAMPLE 10
43 #define MIPI_FREQ_270M 270000000
44 #define OS03B10_LANES 2
45 #define PIXEL_RATE_WITH_270M (MIPI_FREQ_270M * OS03B10_LANES * 2 / BITS_PER_SAMPLE)
46
47 #define OS03B10_REG_PAGE_SELECT 0xfd
48
49 #define OS03B10_REG_EXP_H 0x03
50 #define OS03B10_REG_EXP_L 0x04
51 #define OS03B10_EXPOSURE_MIN 4
52 #define OS03B10_EXPOSURE_STEP 1
53
54 #define OS03B10_REG_AGAIN 0x24
55 #define OS03B10_REG_DGAIN_H 0x37
56 #define OS03B10_REG_DGAIN_L 0x39
57 #define OS03B10_GAIN_MIN 0x10
58 #define OS03B10_GAIN_MAX 0x2000
59 #define OS03B10_GAIN_STEP 1
60 #define OS03B10_GAIN_DEFAULT 0x10
61
62 #define OS03B10_REG_HTS_H 0x41
63 #define OS03B10_REG_HTS_L 0x42
64 #define OS03B10_REG_VTS_H 0x4e
65 #define OS03B10_REG_VTS_L 0x4f
66
67 #define OS03B10_REG_VBLANK_H 0x05
68 #define OS03B10_REG_VBLANK_L 0x06
69
70 #define OS03B10_VTS_MAX 0xffff
71 #define OS03B10_REG_RESTART 0x01
72
73 #define OS03B10_REG_CTRL_MODE 0xb1
74 #define OS03B10_MODE_SW_STANDBY 0x0
75 #define OS03B10_MODE_STREAMING 0x03
76
77 #define OS03B10_REG_SOFTWARE_RESET 0x20
78 #define OS03B10_SOFTWARE_RESET_VAL 0x1
79
80 #define OS03B10_FLIP_REG 0x3f
81 #define MIRROR_BIT_MASK BIT(0)
82 #define FLIP_BIT_MASK BIT(1)
83 #define OS03B10_REG_BAYER_ORDER 0x5e
84
85 #define OS03B10_FETCH_EXP_H(VAL) (((VAL) >> 8) & 0xFF)
86 #define OS03B10_FETCH_EXP_L(VAL) ((VAL) & 0xFF)
87
88 #define OS03B10_FETCH_AGAIN(VAL) ((VAL) & 0xFF)
89 #define OS03B10_FETCH_DGAIN_H(VAL) (((VAL) >> 8) & 0xFF)
90 #define OS03B10_FETCH_DGAIN_L(VAL) ((VAL) & 0xFF)
91
92 #define OS03B10_NAME "os03b10"
93
94 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
95 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
96 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
97
98 #define REG_DELAY 0xEE
99 #define REG_NULL 0xEF
100
101 #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
102
103 static const char * const OS03B10_supply_names[] = {
104 "avdd", /* Analog power */
105 "dovdd", /* Digital I/O power */
106 "dvdd", /* Digital core power */
107 };
108
109 #define OS03B10_NUM_SUPPLIES ARRAY_SIZE(OS03B10_supply_names)
110
111 struct regval {
112 u8 addr;
113 u8 val;
114 };
115
116 struct os03b10_mode {
117 u32 bus_fmt;
118 u32 width;
119 u32 height;
120 struct v4l2_fract max_fps;
121 u32 hts_def;
122 u32 vts_def;
123 u32 exp_def;
124 const struct regval *reg_list;
125 u32 hdr_mode;
126 u32 vc[PAD_MAX];
127 };
128
129 struct os03b10 {
130 struct i2c_client *client;
131 struct clk *xvclk;
132 struct gpio_desc *reset_gpio;
133 struct gpio_desc *pwdn_gpio;
134 struct regulator_bulk_data supplies[OS03B10_NUM_SUPPLIES];
135 struct pinctrl *pinctrl;
136 struct pinctrl_state *pins_default;
137 struct pinctrl_state *pins_sleep;
138 struct v4l2_subdev subdev;
139 struct media_pad pad;
140 struct v4l2_ctrl_handler ctrl_handler;
141 struct v4l2_ctrl *exposure;
142 struct v4l2_ctrl *anal_gain;
143 struct v4l2_ctrl *digi_gain;
144 struct v4l2_ctrl *hblank;
145 struct v4l2_ctrl *vblank;
146 struct v4l2_ctrl *pixel_rate;
147 struct v4l2_ctrl *link_freq;
148 struct mutex mutex;
149 bool streaming;
150 bool power_on;
151 const struct os03b10_mode *cur_mode;
152 u32 cfg_num;
153 u32 module_index;
154 const char *module_facing;
155 const char *module_name;
156 const char *len_name;
157 bool has_init_exp;
158 struct preisp_hdrae_exp_s init_hdrae_exp;
159 u8 flip;
160 };
161
162 #define to_os03b10(sd) container_of(sd, struct os03b10, subdev)
163
164 static const struct regval os03b10_linear10bit_2304x1296_regs[] = {
165 {0xfd, 0x00},
166 {0x20, 0x00},
167 {0xfd, 0x00},
168 {0x36, 0x01},
169 {0xfd, 0x00},
170 {0x2e, 0x2d},
171 {0x2f, 0x01},
172 {0x41, 0x12},
173 {0x36, 0x00},
174 {0xfd, 0x00},
175 {0xfd, 0x00},
176 {0xfd, 0x00},
177 {0xfd, 0x00},
178 {REG_DELAY, 0x05},
179 {0xfd, 0x00},
180 {0xfd, 0x00},
181 {0x44, 0x40},
182 {0x38, 0x21},
183 {0x45, 0x04},
184 {0xfd, 0x01},
185 {0x03, 0x00},
186 {0x04, 0x04},
187 {0x06, 0x00},
188 {0x24, 0xff},
189 {0x01, 0x01},
190 {0x18, 0x2f},
191 {0x1a, 0x06},
192 {0x19, 0x58},
193 {0x1b, 0x3c},
194 {0x2e, 0x03},
195 {0x2f, 0x02},
196 {0x30, 0x52},
197 {0x3c, 0xca},
198 {0xfd, 0x03},
199 {0x01, 0x0e},
200 {0xfd, 0x01},
201 {0x51, 0x0e},
202 {0x52, 0x0b},
203 {0x57, 0x0b},
204 {0x5a, 0xe0},
205 {0x66, 0xd0},
206 {0x6e, 0x26},
207 {0x71, 0x80},
208 {0x73, 0x2b},
209 {0xb8, 0x1c},
210 {0xd0, 0x20},
211 {0xd2, 0x8e},
212 {0xd3, 0x1a},
213 {0xfd, 0x01},
214 {0xbd, 0x00},
215 {0xd7, 0xbe},
216 {0xd8, 0xef},
217 {0xe8, 0x09},
218 {0xe9, 0x05},
219 {0xea, 0x08},
220 {0xeb, 0x06},
221 {0xfd, 0x03},
222 {0x00, 0x5c},
223 {0x03, 0xcd},
224 {0x06, 0x07},
225 {0x07, 0x78},
226 {0x08, 0x36},
227 {0x09, 0x28},
228 {0x0a, 0x0c},
229 {0x0b, 0x06},
230 {0x0f, 0x13},
231 {0xfd, 0x01},
232 {0x1d, 0x08},
233 {0x1e, 0x18},
234 {0x1f, 0x30},
235 {0x20, 0x5c},
236 {0xbc, 0x00},
237 {0xfd, 0x03},
238 {0x02, 0x00},
239 {0x05, 0x18},
240 {0xfd, 0x02},
241 {0x5e, 0x22},
242 {0x34, 0x80},
243 {0xfd, 0x01},
244 {0xf0, 0x40},
245 {0xf1, 0x40},
246 {0xf2, 0x40},
247 {0xf3, 0x40},
248 {0xfa, 0x5c},
249 {0xfb, 0x6b},
250 {0xf6, 0x00},
251 {0xf7, 0xc0},
252 {0xfc, 0x00},
253 {0xfe, 0xc0},
254 {0xff, 0x88},
255 {0xc4, 0x70},
256 {0xc5, 0x70},
257 {0xc6, 0x70},
258 {0xc7, 0x70},
259 {0xfd, 0x01},
260 {0xce, 0x7c},
261 {0x8f, 0x00},
262 {0x91, 0x10},
263 {0x92, 0x19},
264 {0x94, 0x44},
265 {0x95, 0x44},
266 {0x98, 0x55},
267 {0x9d, 0x03},
268 {0x9e, 0x5f},
269 {0xa4, 0x13},
270 {0xa5, 0xff},
271 {0xa6, 0xff},
272 {0x01, 0x02},
273 {0x14, 0x03},
274 {REG_NULL, 0x00},
275 };
276
277 /*
278 * The width and height must be configured to be
279 * the same as the current output resolution of the sensor.
280 * The input width of the isp needs to be 16 aligned.
281 * The input height of the isp needs to be 8 aligned.
282 * If the width or height does not meet the alignment rules,
283 * you can configure the cropping parameters with the following function to
284 * crop out the appropriate resolution.
285 * struct v4l2_subdev_pad_ops {
286 * .get_selection
287 * }
288 */
289 static const struct os03b10_mode supported_modes[] = {
290 {
291 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
292 .width = 2304,
293 .height = 1296,
294 .max_fps = {
295 .numerator = 10000,
296 .denominator = 300000,
297 },
298 .exp_def = 0x044c,
299 .hts_def = 0x054e * 2,
300 .vts_def = 0x052d,
301 .reg_list = os03b10_linear10bit_2304x1296_regs,
302 .hdr_mode = NO_HDR,
303 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
304 },
305 };
306
307 static const s64 link_freq_menu_items[] = {
308 MIPI_FREQ_270M,
309 };
310
311 /* sensor register write */
os03b10_write_reg(struct i2c_client * client,u8 reg,u8 val)312 static int os03b10_write_reg(struct i2c_client *client, u8 reg, u8 val)
313 {
314 struct i2c_msg msg;
315 u8 buf[2];
316 int ret;
317
318 buf[0] = reg & 0xFF;
319 buf[1] = val;
320
321 msg.addr = client->addr;
322 msg.flags = client->flags;
323 msg.buf = buf;
324 msg.len = sizeof(buf);
325
326 ret = i2c_transfer(client->adapter, &msg, 1);
327
328 if (ret >= 0)
329 return 0;
330
331 dev_err(&client->dev,
332 "write reg(0x%x val:0x%x) failed !\n", reg, val);
333
334 return ret;
335 }
336
os03b10_write_array(struct i2c_client * client,const struct regval * regs)337 static int os03b10_write_array(struct i2c_client *client,
338 const struct regval *regs)
339 {
340 int i, ret = 0;
341
342 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
343
344 ret = os03b10_write_reg(client, regs[i].addr, regs[i].val);
345 if (regs[i].addr == REG_DELAY)
346 usleep_range(5 * 1000, 6 * 1000);
347
348 if (ret) {
349 dev_err(&client->dev, "%s failed !\n", __func__);
350 break;
351 }
352 }
353
354 return ret;
355 }
356
357 /* sensor register read */
os03b10_read_reg(struct i2c_client * client,u8 reg,u8 * val)358 static int os03b10_read_reg(struct i2c_client *client, u8 reg, u8 *val)
359 {
360 struct i2c_msg msg[2];
361 u8 buf[1];
362 int ret;
363
364 buf[0] = reg & 0xFF;
365
366 msg[0].addr = client->addr;
367 msg[0].flags = client->flags;
368 msg[0].buf = buf;
369 msg[0].len = sizeof(buf);
370
371 msg[1].addr = client->addr;
372 msg[1].flags = client->flags | I2C_M_RD;
373 msg[1].buf = buf;
374 msg[1].len = 1;
375
376 ret = i2c_transfer(client->adapter, msg, 2);
377 if (ret >= 0) {
378 *val = buf[0];
379 return 0;
380 }
381
382 dev_err(&client->dev,
383 "os03b10 read reg(0x%x val:0x%x) failed !\n", reg, *val);
384
385 return ret;
386 }
387
os03b10_get_reso_dist(const struct os03b10_mode * mode,struct v4l2_mbus_framefmt * framefmt)388 static int os03b10_get_reso_dist(const struct os03b10_mode *mode,
389 struct v4l2_mbus_framefmt *framefmt)
390 {
391 return abs(mode->width - framefmt->width) +
392 abs(mode->height - framefmt->height);
393 }
394
395 static const struct os03b10_mode *
os03b10_find_best_fit(struct os03b10 * os03b10,struct v4l2_subdev_format * fmt)396 os03b10_find_best_fit(struct os03b10 *os03b10, struct v4l2_subdev_format *fmt)
397 {
398 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
399 int dist;
400 int cur_best_fit = 0;
401 int cur_best_fit_dist = -1;
402 unsigned int i;
403
404 for (i = 0; i < os03b10->cfg_num; i++) {
405 dist = os03b10_get_reso_dist(&supported_modes[i], framefmt);
406 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
407 (supported_modes[i].bus_fmt == framefmt->code)) {
408 cur_best_fit_dist = dist;
409 cur_best_fit = i;
410 }
411 }
412
413 return &supported_modes[cur_best_fit];
414 }
415
os03b10_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)416 static int os03b10_set_fmt(struct v4l2_subdev *sd,
417 struct v4l2_subdev_pad_config *cfg,
418 struct v4l2_subdev_format *fmt)
419 {
420 struct os03b10 *os03b10 = to_os03b10(sd);
421 const struct os03b10_mode *mode;
422 s64 h_blank, vblank_def;
423 u64 dst_link_freq = 0;
424 u64 dst_pixel_rate = 0;
425
426 mutex_lock(&os03b10->mutex);
427
428 mode = os03b10_find_best_fit(os03b10, fmt);
429 fmt->format.code = mode->bus_fmt;
430 fmt->format.width = mode->width;
431 fmt->format.height = mode->height;
432 fmt->format.field = V4L2_FIELD_NONE;
433 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
434 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
435 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
436 #else
437 mutex_unlock(&os03b10->mutex);
438 return -ENOTTY;
439 #endif
440 } else {
441 os03b10->cur_mode = mode;
442 h_blank = mode->hts_def - mode->width;
443 __v4l2_ctrl_modify_range(os03b10->hblank, h_blank,
444 h_blank, 1, h_blank);
445
446 vblank_def = mode->vts_def - mode->height;
447 __v4l2_ctrl_modify_range(os03b10->vblank, vblank_def,
448 OS03B10_VTS_MAX - mode->height,
449 1, vblank_def);
450 if (mode->hdr_mode == NO_HDR) {
451 if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
452 dst_link_freq = 0;
453 dst_pixel_rate = PIXEL_RATE_WITH_270M;
454 }
455 }
456 __v4l2_ctrl_s_ctrl_int64(os03b10->pixel_rate,
457 dst_pixel_rate);
458 __v4l2_ctrl_s_ctrl(os03b10->link_freq,
459 dst_link_freq);
460 }
461
462 mutex_unlock(&os03b10->mutex);
463
464 return 0;
465 }
466
os03b10_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)467 static int os03b10_get_fmt(struct v4l2_subdev *sd,
468 struct v4l2_subdev_pad_config *cfg,
469 struct v4l2_subdev_format *fmt)
470 {
471 struct os03b10 *os03b10 = to_os03b10(sd);
472 const struct os03b10_mode *mode = os03b10->cur_mode;
473
474 mutex_lock(&os03b10->mutex);
475 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
476 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
477 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
478 #else
479 mutex_unlock(&os03b10->mutex);
480 return -ENOTTY;
481 #endif
482 } else {
483 fmt->format.width = mode->width;
484 fmt->format.height = mode->height;
485 fmt->format.code = mode->bus_fmt;
486 fmt->format.field = V4L2_FIELD_NONE;
487 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
488 fmt->reserved[0] = mode->vc[fmt->pad];
489 else
490 fmt->reserved[0] = mode->vc[PAD0];
491 }
492 mutex_unlock(&os03b10->mutex);
493
494 return 0;
495 }
496
os03b10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)497 static int os03b10_enum_mbus_code(struct v4l2_subdev *sd,
498 struct v4l2_subdev_pad_config *cfg,
499 struct v4l2_subdev_mbus_code_enum *code)
500 {
501 struct os03b10 *os03b10 = to_os03b10(sd);
502
503 if (code->index != 0)
504 return -EINVAL;
505 code->code = os03b10->cur_mode->bus_fmt;
506
507 return 0;
508 }
509
os03b10_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)510 static int os03b10_enum_frame_sizes(struct v4l2_subdev *sd,
511 struct v4l2_subdev_pad_config *cfg,
512 struct v4l2_subdev_frame_size_enum *fse)
513 {
514 struct os03b10 *os03b10 = to_os03b10(sd);
515
516 if (fse->index >= os03b10->cfg_num)
517 return -EINVAL;
518
519 if (fse->code != supported_modes[fse->index].bus_fmt)
520 return -EINVAL;
521
522 fse->min_width = supported_modes[fse->index].width;
523 fse->max_width = supported_modes[fse->index].width;
524 fse->max_height = supported_modes[fse->index].height;
525 fse->min_height = supported_modes[fse->index].height;
526
527 return 0;
528 }
529
os03b10_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)530 static int os03b10_g_frame_interval(struct v4l2_subdev *sd,
531 struct v4l2_subdev_frame_interval *fi)
532 {
533 struct os03b10 *os03b10 = to_os03b10(sd);
534 const struct os03b10_mode *mode = os03b10->cur_mode;
535
536 fi->interval = mode->max_fps;
537
538 return 0;
539 }
540
os03b10_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)541 static int os03b10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
542 struct v4l2_mbus_config *config)
543 {
544 struct os03b10 *os03b10 = to_os03b10(sd);
545 const struct os03b10_mode *mode = os03b10->cur_mode;
546 u32 val = 0;
547
548 if (mode->hdr_mode == NO_HDR)
549 val = 1 << (OS03B10_LANES - 1) |
550 V4L2_MBUS_CSI2_CHANNEL_0 |
551 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
552
553 config->type = V4L2_MBUS_CSI2_DPHY;
554 config->flags = val;
555
556 return 0;
557 }
558
os03b10_get_module_inf(struct os03b10 * os03b10,struct rkmodule_inf * inf)559 static void os03b10_get_module_inf(struct os03b10 *os03b10,
560 struct rkmodule_inf *inf)
561 {
562 memset(inf, 0, sizeof(*inf));
563 strscpy(inf->base.sensor, OS03B10_NAME, sizeof(inf->base.sensor));
564 strscpy(inf->base.module, os03b10->module_name, sizeof(inf->base.module));
565 strscpy(inf->base.lens, os03b10->len_name, sizeof(inf->base.lens));
566 }
567
os03b10_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)568 static long os03b10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
569 {
570 struct os03b10 *os03b10 = to_os03b10(sd);
571 struct rkmodule_hdr_cfg *hdr_cfg;
572 long ret = 0;
573 u32 stream = 0;
574
575 switch (cmd) {
576 case RKMODULE_GET_MODULE_INFO:
577 os03b10_get_module_inf(os03b10, (struct rkmodule_inf *)arg);
578 break;
579 case RKMODULE_SET_HDR_CFG:
580 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
581 if (hdr_cfg->hdr_mode != 0)
582 ret = -1;
583 break;
584 case RKMODULE_GET_HDR_CFG:
585 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
586 hdr_cfg->esp.mode = HDR_NORMAL_VC;
587 hdr_cfg->hdr_mode = os03b10->cur_mode->hdr_mode;
588 break;
589 case RKMODULE_SET_QUICK_STREAM:
590 stream = *((u32 *)arg);
591 if (stream)
592 ret = os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
593 OS03B10_MODE_STREAMING);
594 else
595 ret = os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
596 OS03B10_MODE_SW_STANDBY);
597 break;
598 default:
599 ret = -ENOIOCTLCMD;
600 break;
601 }
602
603 return ret;
604 }
605
606 #ifdef CONFIG_COMPAT
os03b10_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)607 static long os03b10_compat_ioctl32(struct v4l2_subdev *sd,
608 unsigned int cmd, unsigned long arg)
609 {
610 void __user *up = compat_ptr(arg);
611 struct rkmodule_inf *inf;
612 struct rkmodule_hdr_cfg *hdr;
613 long ret;
614 u32 stream = 0;
615
616 switch (cmd) {
617 case RKMODULE_GET_MODULE_INFO:
618 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
619 if (!inf) {
620 ret = -ENOMEM;
621 return ret;
622 }
623
624 ret = os03b10_ioctl(sd, cmd, inf);
625 if (!ret) {
626 ret = copy_to_user(up, inf, sizeof(*inf));
627 if (ret)
628 ret = -EFAULT;
629 }
630 kfree(inf);
631 break;
632 case RKMODULE_GET_HDR_CFG:
633 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
634 if (!hdr) {
635 ret = -ENOMEM;
636 return ret;
637 }
638
639 ret = os03b10_ioctl(sd, cmd, hdr);
640 if (!ret) {
641 ret = copy_to_user(up, hdr, sizeof(*hdr));
642 if (ret)
643 ret = -EFAULT;
644 }
645 kfree(hdr);
646 break;
647 case RKMODULE_SET_HDR_CFG:
648 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
649 if (!hdr) {
650 ret = -ENOMEM;
651 return ret;
652 }
653
654 if (copy_from_user(hdr, up, sizeof(*hdr)))
655 return -EFAULT;
656
657 ret = os03b10_ioctl(sd, cmd, hdr);
658 kfree(hdr);
659 break;
660 case RKMODULE_SET_QUICK_STREAM:
661 if (copy_from_user(&stream, up, sizeof(u32)))
662 return -EFAULT;
663
664 ret = os03b10_ioctl(sd, cmd, &stream);
665 break;
666 default:
667 ret = -ENOIOCTLCMD;
668 break;
669 }
670
671 return ret;
672 }
673 #endif
674
__os03b10_start_stream(struct os03b10 * os03b10)675 static int __os03b10_start_stream(struct os03b10 *os03b10)
676 {
677 int ret = 0;
678
679 ret |= os03b10_write_array(os03b10->client, os03b10->cur_mode->reg_list);
680 if (ret) {
681 dev_err(&os03b10->client->dev,
682 "write array failed in start stream\n");
683 return ret;
684 }
685
686 /* In case these controls are set before streaming */
687 ret = __v4l2_ctrl_handler_setup(&os03b10->ctrl_handler);
688 if (ret)
689 return ret;
690 if (os03b10->has_init_exp && os03b10->cur_mode->hdr_mode != NO_HDR) {
691 ret = os03b10_ioctl(&os03b10->subdev, PREISP_CMD_SET_HDRAE_EXP,
692 &os03b10->init_hdrae_exp);
693 if (ret) {
694 dev_err(&os03b10->client->dev,
695 "init exp fail in hdr mode\n");
696 return ret;
697 }
698 }
699
700 ret |= os03b10_write_reg(os03b10->client, OS03B10_REG_PAGE_SELECT, 0x01);
701 ret |= os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
702 OS03B10_MODE_STREAMING);
703
704 return ret;
705 }
706
__os03b10_stop_stream(struct os03b10 * os03b10)707 static int __os03b10_stop_stream(struct os03b10 *os03b10)
708 {
709 os03b10->has_init_exp = false;
710 return os03b10_write_reg(os03b10->client, OS03B10_REG_CTRL_MODE,
711 OS03B10_MODE_SW_STANDBY);
712 }
713
os03b10_s_stream(struct v4l2_subdev * sd,int on)714 static int os03b10_s_stream(struct v4l2_subdev *sd, int on)
715 {
716 struct os03b10 *os03b10 = to_os03b10(sd);
717 struct i2c_client *client = os03b10->client;
718 int ret = 0;
719
720 mutex_lock(&os03b10->mutex);
721 on = !!on;
722 if (on == os03b10->streaming)
723 goto unlock_and_return;
724
725 if (on) {
726 ret = pm_runtime_get_sync(&client->dev);
727 if (ret < 0) {
728 pm_runtime_put_noidle(&client->dev);
729 goto unlock_and_return;
730 }
731
732 ret = __os03b10_start_stream(os03b10);
733 if (ret) {
734 v4l2_err(sd, "start stream failed while write regs\n");
735 pm_runtime_put(&client->dev);
736 goto unlock_and_return;
737 }
738 } else {
739 __os03b10_stop_stream(os03b10);
740 pm_runtime_put(&client->dev);
741 }
742
743 os03b10->streaming = on;
744
745 unlock_and_return:
746 mutex_unlock(&os03b10->mutex);
747
748 return ret;
749 }
750
os03b10_s_power(struct v4l2_subdev * sd,int on)751 static int os03b10_s_power(struct v4l2_subdev *sd, int on)
752 {
753 struct os03b10 *os03b10 = to_os03b10(sd);
754 struct i2c_client *client = os03b10->client;
755 int ret = 0;
756
757 mutex_lock(&os03b10->mutex);
758
759 /* If the power state is not modified - no work to do. */
760 if (os03b10->power_on == !!on)
761 goto unlock_and_return;
762
763 if (on) {
764 ret = pm_runtime_get_sync(&client->dev);
765 if (ret < 0) {
766 pm_runtime_put_noidle(&client->dev);
767 goto unlock_and_return;
768 }
769
770 ret |= os03b10_write_reg(os03b10->client,
771 OS03B10_REG_SOFTWARE_RESET,
772 OS03B10_SOFTWARE_RESET_VAL);
773 usleep_range(100, 200);
774
775 os03b10->power_on = true;
776 } else {
777 pm_runtime_put(&client->dev);
778 os03b10->power_on = false;
779 }
780
781 unlock_and_return:
782 mutex_unlock(&os03b10->mutex);
783
784 return ret;
785 }
786
__os03b10_power_on(struct os03b10 * os03b10)787 static int __os03b10_power_on(struct os03b10 *os03b10)
788 {
789 int ret;
790 struct device *dev = &os03b10->client->dev;
791
792 if (!IS_ERR_OR_NULL(os03b10->pins_default)) {
793 ret = pinctrl_select_state(os03b10->pinctrl,
794 os03b10->pins_default);
795 if (ret < 0)
796 dev_err(dev, "could not set pins\n");
797 }
798 ret = clk_set_rate(os03b10->xvclk, OS03B10_XVCLK_FREQ);
799 if (ret < 0)
800 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
801 if (clk_get_rate(os03b10->xvclk) != OS03B10_XVCLK_FREQ)
802 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
803 ret = clk_prepare_enable(os03b10->xvclk);
804 if (ret < 0) {
805 dev_err(dev, "Failed to enable xvclk\n");
806 return ret;
807 }
808
809 if (!IS_ERR(os03b10->pwdn_gpio))
810 gpiod_direction_output(os03b10->pwdn_gpio, 0);
811
812 if (!IS_ERR(os03b10->reset_gpio))
813 gpiod_direction_output(os03b10->reset_gpio, 0);
814
815 ret = regulator_bulk_enable(OS03B10_NUM_SUPPLIES, os03b10->supplies);
816 if (ret < 0) {
817 dev_err(dev, "Failed to enable regulators\n");
818 goto disable_clk;
819 }
820
821 /* From spec: delay from power stable to pwdn off: 5ms */
822 usleep_range(5000, 6000);
823 if (!IS_ERR(os03b10->pwdn_gpio))
824 gpiod_direction_output(os03b10->pwdn_gpio, 1);
825
826 /* From spec: delay from pwdn off to reset off */
827 usleep_range(4000, 5000);
828 if (!IS_ERR(os03b10->reset_gpio))
829 gpiod_direction_output(os03b10->reset_gpio, 1);
830
831 /* From spec: 5ms for SCCB initialization */
832 usleep_range(9000, 10000);
833 return 0;
834
835 disable_clk:
836 clk_disable_unprepare(os03b10->xvclk);
837
838 return ret;
839 }
840
__os03b10_power_off(struct os03b10 * os03b10)841 static void __os03b10_power_off(struct os03b10 *os03b10)
842 {
843 int ret;
844 struct device *dev = &os03b10->client->dev;
845
846 if (!IS_ERR(os03b10->pwdn_gpio))
847 gpiod_direction_output(os03b10->pwdn_gpio, 0);
848
849 clk_disable_unprepare(os03b10->xvclk);
850
851 if (!IS_ERR(os03b10->reset_gpio))
852 gpiod_direction_output(os03b10->reset_gpio, 0);
853 if (!IS_ERR_OR_NULL(os03b10->pins_sleep)) {
854 ret = pinctrl_select_state(os03b10->pinctrl,
855 os03b10->pins_sleep);
856 if (ret < 0)
857 dev_dbg(dev, "could not set pins\n");
858 }
859 regulator_bulk_disable(OS03B10_NUM_SUPPLIES, os03b10->supplies);
860 }
861
os03b10_runtime_resume(struct device * dev)862 static int os03b10_runtime_resume(struct device *dev)
863 {
864 struct i2c_client *client = to_i2c_client(dev);
865 struct v4l2_subdev *sd = i2c_get_clientdata(client);
866 struct os03b10 *os03b10 = to_os03b10(sd);
867
868 return __os03b10_power_on(os03b10);
869 }
870
os03b10_runtime_suspend(struct device * dev)871 static int os03b10_runtime_suspend(struct device *dev)
872 {
873 struct i2c_client *client = to_i2c_client(dev);
874 struct v4l2_subdev *sd = i2c_get_clientdata(client);
875 struct os03b10 *os03b10 = to_os03b10(sd);
876
877 __os03b10_power_off(os03b10);
878
879 return 0;
880 }
881
882 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
os03b10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)883 static int os03b10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
884 {
885 struct os03b10 *os03b10 = to_os03b10(sd);
886 struct v4l2_mbus_framefmt *try_fmt =
887 v4l2_subdev_get_try_format(sd, fh->pad, 0);
888 const struct os03b10_mode *def_mode = &supported_modes[0];
889
890 mutex_lock(&os03b10->mutex);
891 /* Initialize try_fmt */
892 try_fmt->width = def_mode->width;
893 try_fmt->height = def_mode->height;
894 try_fmt->code = def_mode->bus_fmt;
895 try_fmt->field = V4L2_FIELD_NONE;
896
897 mutex_unlock(&os03b10->mutex);
898 /* No crop or compose */
899
900 return 0;
901 }
902 #endif
903
os03b10_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)904 static int os03b10_enum_frame_interval(struct v4l2_subdev *sd,
905 struct v4l2_subdev_pad_config *cfg,
906 struct v4l2_subdev_frame_interval_enum *fie)
907 {
908 struct os03b10 *os03b10 = to_os03b10(sd);
909
910 if (fie->index >= os03b10->cfg_num)
911 return -EINVAL;
912
913 fie->code = supported_modes[fie->index].bus_fmt;
914 fie->width = supported_modes[fie->index].width;
915 fie->height = supported_modes[fie->index].height;
916 fie->interval = supported_modes[fie->index].max_fps;
917 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
918 return 0;
919 }
920
921 static const struct dev_pm_ops os03b10_pm_ops = {
922 SET_RUNTIME_PM_OPS(os03b10_runtime_suspend,
923 os03b10_runtime_resume, NULL)
924 };
925
926 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
927 static const struct v4l2_subdev_internal_ops os03b10_internal_ops = {
928 .open = os03b10_open,
929 };
930 #endif
931
932 static const struct v4l2_subdev_core_ops os03b10_core_ops = {
933 .s_power = os03b10_s_power,
934 .ioctl = os03b10_ioctl,
935 #ifdef CONFIG_COMPAT
936 .compat_ioctl32 = os03b10_compat_ioctl32,
937 #endif
938 };
939
940 static const struct v4l2_subdev_video_ops os03b10_video_ops = {
941 .s_stream = os03b10_s_stream,
942 .g_frame_interval = os03b10_g_frame_interval,
943 };
944
945 static const struct v4l2_subdev_pad_ops os03b10_pad_ops = {
946 .enum_mbus_code = os03b10_enum_mbus_code,
947 .enum_frame_size = os03b10_enum_frame_sizes,
948 .enum_frame_interval = os03b10_enum_frame_interval,
949 .get_fmt = os03b10_get_fmt,
950 .set_fmt = os03b10_set_fmt,
951 .get_mbus_config = os03b10_g_mbus_config,
952 };
953
954 static const struct v4l2_subdev_ops os03b10_subdev_ops = {
955 .core = &os03b10_core_ops,
956 .video = &os03b10_video_ops,
957 .pad = &os03b10_pad_ops,
958 };
959
960
os03b10_get_gain_reg(u32 total_gain,u32 * again,u32 * dgain)961 static void os03b10_get_gain_reg(u32 total_gain, u32 *again, u32 *dgain)
962 {
963 u32 step = 0;
964
965 if (total_gain < 256) {/* 1x gain ~ 16x gain*/
966 *again = total_gain;
967 *dgain = 0x40;
968 } else if (total_gain < 512) {/* 16x gain ~ 32x gain */
969 step = (total_gain - 256) * 0x40 / 256;
970 *again = 0xff;
971 *dgain = 0x40 + step;
972 } else if (total_gain < 1024) {/* 32x gain ~ 64x gain */
973 step = (total_gain - 512) * 0x80 / 512;
974 *again = 0xff;
975 *dgain = 0x80 + step;
976 } else if (total_gain < 2048) {/* 64x gain ~ 128x gain */
977 step = (total_gain - 1024) * 0x100 / 1024;
978 *again = 0xff;
979 *dgain = 0x100 + step;
980 } else if (total_gain < 4096) {/* 128x gain ~ 256x gain */
981 step = (total_gain - 2048) * 0x200 / 2048;
982 *again = 0xff;
983 *dgain = 0x200 + step;
984 } else if (total_gain <= 8192) {/* 256x gain ~ 512x gain */
985 step = (total_gain - 4096) * 0x400 / 4096;
986 *again = 0xff;
987 *dgain = (0x400 + step) > 0x7ff ? 0x7ff : (0x400 + step);
988 }
989 }
990
os03b10_set_ctrl(struct v4l2_ctrl * ctrl)991 static int os03b10_set_ctrl(struct v4l2_ctrl *ctrl)
992 {
993 struct os03b10 *os03b10 = container_of(ctrl->handler,
994 struct os03b10, ctrl_handler);
995 struct i2c_client *client = os03b10->client;
996 s64 max;
997 int ret = 0;
998 u32 again = 0, dgain = 0;
999
1000 /* Propagate change of current control to all related controls */
1001 switch (ctrl->id) {
1002 case V4L2_CID_VBLANK:
1003 /* Update max exposure while meeting expected vblanking */
1004 max = os03b10->cur_mode->height + ctrl->val - 9;
1005 __v4l2_ctrl_modify_range(os03b10->exposure,
1006 os03b10->exposure->minimum, max,
1007 os03b10->exposure->step,
1008 os03b10->exposure->default_value);
1009 break;
1010 }
1011
1012 if (!pm_runtime_get_if_in_use(&client->dev))
1013 return 0;
1014
1015 switch (ctrl->id) {
1016 case V4L2_CID_EXPOSURE:
1017 ret = os03b10_write_reg(os03b10->client,
1018 OS03B10_REG_PAGE_SELECT, 0x1);
1019 ret |= os03b10_write_reg(os03b10->client,
1020 OS03B10_REG_EXP_H,
1021 OS03B10_FETCH_EXP_H(ctrl->val));
1022 ret |= os03b10_write_reg(os03b10->client,
1023 OS03B10_REG_EXP_L,
1024 OS03B10_FETCH_EXP_L(ctrl->val));
1025 ret |= os03b10_write_reg(os03b10->client,
1026 OS03B10_REG_RESTART, 0x01);
1027 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1028 break;
1029 case V4L2_CID_ANALOGUE_GAIN:
1030 os03b10_get_gain_reg(ctrl->val, &again, &dgain);
1031
1032 ret = os03b10_write_reg(os03b10->client,
1033 OS03B10_REG_PAGE_SELECT, 0x01);
1034 ret |= os03b10_write_reg(os03b10->client,
1035 OS03B10_REG_AGAIN,
1036 OS03B10_FETCH_AGAIN(again));
1037 ret |= os03b10_write_reg(os03b10->client,
1038 OS03B10_REG_DGAIN_H,
1039 OS03B10_FETCH_DGAIN_H(dgain));
1040 ret |= os03b10_write_reg(os03b10->client,
1041 OS03B10_REG_DGAIN_L,
1042 OS03B10_FETCH_DGAIN_L(dgain));
1043 ret |= os03b10_write_reg(os03b10->client,
1044 OS03B10_REG_RESTART, 0x01);
1045
1046 dev_dbg(&client->dev, "set gain 0x%x, again 0x%x, dgain 0x%x\n",
1047 ctrl->val, again, dgain);
1048 break;
1049 case V4L2_CID_VBLANK:
1050 ret = os03b10_write_reg(os03b10->client,
1051 OS03B10_REG_PAGE_SELECT, 0x01);
1052 ret |= os03b10_write_reg(os03b10->client,
1053 OS03B10_REG_VBLANK_H,
1054 (ctrl->val >> 8) & 0xFF);
1055 ret |= os03b10_write_reg(os03b10->client,
1056 OS03B10_REG_VBLANK_L,
1057 ctrl->val & 0xFF);
1058 ret |= os03b10_write_reg(os03b10->client,
1059 OS03B10_REG_RESTART, 0x01);
1060 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1061 break;
1062 case V4L2_CID_TEST_PATTERN:
1063 break;
1064 case V4L2_CID_HFLIP:
1065 if (ctrl->val)
1066 os03b10->flip |= MIRROR_BIT_MASK;
1067 else
1068 os03b10->flip &= ~MIRROR_BIT_MASK;
1069
1070 ret = os03b10_write_reg(os03b10->client,
1071 OS03B10_REG_PAGE_SELECT, 0x01);
1072 ret |= os03b10_write_reg(os03b10->client,
1073 OS03B10_FLIP_REG, os03b10->flip);
1074 ret |= os03b10_write_reg(os03b10->client,
1075 OS03B10_REG_PAGE_SELECT, 0x02);
1076 ret |= os03b10_write_reg(os03b10->client,
1077 OS03B10_REG_BAYER_ORDER, 0x32);
1078 ret |= os03b10_write_reg(os03b10->client,
1079 OS03B10_REG_PAGE_SELECT, 0x01);
1080 ret |= os03b10_write_reg(os03b10->client,
1081 OS03B10_REG_RESTART, 0x01);
1082 dev_dbg(&client->dev, "set hflip 0x%x\n", os03b10->flip);
1083 break;
1084 case V4L2_CID_VFLIP:
1085 if (ctrl->val)
1086 os03b10->flip |= FLIP_BIT_MASK;
1087 else
1088 os03b10->flip &= ~FLIP_BIT_MASK;
1089
1090 ret = os03b10_write_reg(os03b10->client,
1091 OS03B10_REG_PAGE_SELECT, 0x01);
1092 ret |= os03b10_write_reg(os03b10->client,
1093 OS03B10_FLIP_REG, os03b10->flip);
1094 ret |= os03b10_write_reg(os03b10->client,
1095 OS03B10_REG_PAGE_SELECT, 0x02);
1096 ret |= os03b10_write_reg(os03b10->client,
1097 OS03B10_REG_BAYER_ORDER, 0x32);
1098 ret |= os03b10_write_reg(os03b10->client,
1099 OS03B10_REG_PAGE_SELECT, 0x01);
1100 ret |= os03b10_write_reg(os03b10->client,
1101 OS03B10_REG_RESTART, 0x01);
1102 dev_dbg(&client->dev, "set vflip 0x%x\n", os03b10->flip);
1103 break;
1104 default:
1105 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1106 __func__, ctrl->id, ctrl->val);
1107 break;
1108 }
1109 pm_runtime_put(&client->dev);
1110
1111 return ret;
1112 }
1113
1114 static const struct v4l2_ctrl_ops os03b10_ctrl_ops = {
1115 .s_ctrl = os03b10_set_ctrl,
1116 };
1117
os03b10_initialize_controls(struct os03b10 * os03b10)1118 static int os03b10_initialize_controls(struct os03b10 *os03b10)
1119 {
1120 const struct os03b10_mode *mode;
1121 struct v4l2_ctrl_handler *handler;
1122 s64 exposure_max, vblank_def;
1123 u32 h_blank;
1124 int ret;
1125 u64 dst_link_freq = 0;
1126 u64 dst_pixel_rate = 0;
1127
1128 handler = &os03b10->ctrl_handler;
1129 mode = os03b10->cur_mode;
1130 ret = v4l2_ctrl_handler_init(handler, 9);
1131 if (ret)
1132 return ret;
1133 handler->lock = &os03b10->mutex;
1134
1135 os03b10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1136 V4L2_CID_LINK_FREQ,
1137 1, 0,
1138 link_freq_menu_items);
1139
1140 if (os03b10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
1141 dst_link_freq = 0;
1142 dst_pixel_rate = PIXEL_RATE_WITH_270M;
1143 }
1144 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1145 os03b10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1146 V4L2_CID_PIXEL_RATE,
1147 0, PIXEL_RATE_WITH_270M,
1148 1, dst_pixel_rate);
1149
1150 __v4l2_ctrl_s_ctrl(os03b10->link_freq, dst_link_freq);
1151
1152 h_blank = mode->hts_def - mode->width;
1153 os03b10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1154 h_blank, h_blank, 1, h_blank);
1155 if (os03b10->hblank)
1156 os03b10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1157
1158 vblank_def = 0;
1159 os03b10->vblank = v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops,
1160 V4L2_CID_VBLANK, vblank_def,
1161 OS03B10_VTS_MAX - mode->height,
1162 1, vblank_def);
1163
1164 exposure_max = mode->vts_def - 9;
1165 os03b10->exposure = v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops,
1166 V4L2_CID_EXPOSURE, OS03B10_EXPOSURE_MIN,
1167 exposure_max, OS03B10_EXPOSURE_STEP,
1168 mode->exp_def);
1169
1170 os03b10->anal_gain = v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops,
1171 V4L2_CID_ANALOGUE_GAIN, OS03B10_GAIN_MIN,
1172 OS03B10_GAIN_MAX, OS03B10_GAIN_STEP,
1173 OS03B10_GAIN_DEFAULT);
1174
1175 v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1176
1177 v4l2_ctrl_new_std(handler, &os03b10_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1178
1179 os03b10->flip = 0;
1180
1181 if (handler->error) {
1182 ret = handler->error;
1183 dev_err(&os03b10->client->dev,
1184 "Failed to init controls(%d)\n", ret);
1185 goto err_free_handler;
1186 }
1187
1188 os03b10->subdev.ctrl_handler = handler;
1189 os03b10->has_init_exp = false;
1190
1191 return 0;
1192
1193 err_free_handler:
1194 v4l2_ctrl_handler_free(handler);
1195
1196 return ret;
1197 }
1198
os03b10_check_sensor_id(struct os03b10 * os03b10,struct i2c_client * client)1199 static int os03b10_check_sensor_id(struct os03b10 *os03b10,
1200 struct i2c_client *client)
1201 {
1202 struct device *dev = &os03b10->client->dev;
1203 u8 id_h = 0, id_l = 0;
1204 u32 id = 0;
1205 int ret;
1206
1207 ret = os03b10_read_reg(client, OS03B10_REG_CHIP_ID_H, &id_h);
1208 ret |= os03b10_read_reg(client, OS03B10_REG_CHIP_ID_L, &id_l);
1209
1210 id = SENSOR_ID(id_h, id_l);
1211 if (id != OS03B10_CHIP_ID) {
1212 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1213 return -ENODEV;
1214 }
1215 dev_info(dev, "Detected OV%06x sensor\n", OS03B10_CHIP_ID);
1216 return 0;
1217 }
1218
os03b10_configure_regulators(struct os03b10 * os03b10)1219 static int os03b10_configure_regulators(struct os03b10 *os03b10)
1220 {
1221 unsigned int i;
1222
1223 for (i = 0; i < OS03B10_NUM_SUPPLIES; i++)
1224 os03b10->supplies[i].supply = OS03B10_supply_names[i];
1225
1226 return devm_regulator_bulk_get(&os03b10->client->dev,
1227 OS03B10_NUM_SUPPLIES,
1228 os03b10->supplies);
1229 }
1230
os03b10_probe(struct i2c_client * client,const struct i2c_device_id * id)1231 static int os03b10_probe(struct i2c_client *client,
1232 const struct i2c_device_id *id)
1233 {
1234 struct device *dev = &client->dev;
1235 struct device_node *node = dev->of_node;
1236 struct os03b10 *os03b10;
1237 struct v4l2_subdev *sd;
1238 char facing[2];
1239 int ret;
1240 u32 i, hdr_mode = 0;
1241
1242 dev_info(dev, "driver version: %02x.%02x.%02x",
1243 DRIVER_VERSION >> 16,
1244 (DRIVER_VERSION & 0xff00) >> 8,
1245 DRIVER_VERSION & 0x00ff);
1246
1247 os03b10 = devm_kzalloc(dev, sizeof(*os03b10), GFP_KERNEL);
1248 if (!os03b10)
1249 return -ENOMEM;
1250
1251 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1252 &os03b10->module_index);
1253 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1254 &os03b10->module_facing);
1255 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1256 &os03b10->module_name);
1257 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1258 &os03b10->len_name);
1259 if (ret) {
1260 dev_err(dev, "could not get module information!\n");
1261 return -EINVAL;
1262 }
1263
1264 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
1265 if (ret) {
1266 hdr_mode = NO_HDR;
1267 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1268 }
1269 os03b10->cfg_num = ARRAY_SIZE(supported_modes);
1270 for (i = 0; i < os03b10->cfg_num; i++) {
1271 if (hdr_mode == supported_modes[i].hdr_mode) {
1272 os03b10->cur_mode = &supported_modes[i];
1273 break;
1274 }
1275 }
1276 os03b10->client = client;
1277
1278 os03b10->xvclk = devm_clk_get(dev, "xvclk");
1279 if (IS_ERR(os03b10->xvclk)) {
1280 dev_err(dev, "Failed to get xvclk\n");
1281 return -EINVAL;
1282 }
1283
1284 os03b10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1285 if (IS_ERR(os03b10->reset_gpio))
1286 dev_warn(dev, "Failed to get reset-gpios\n");
1287
1288 os03b10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1289 if (IS_ERR(os03b10->pwdn_gpio))
1290 dev_warn(dev, "Failed to get pwdn-gpios\n");
1291
1292 os03b10->pinctrl = devm_pinctrl_get(dev);
1293 if (!IS_ERR(os03b10->pinctrl)) {
1294 os03b10->pins_default =
1295 pinctrl_lookup_state(os03b10->pinctrl,
1296 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1297 if (IS_ERR(os03b10->pins_default))
1298 dev_err(dev, "could not get default pinstate\n");
1299
1300 os03b10->pins_sleep =
1301 pinctrl_lookup_state(os03b10->pinctrl,
1302 OF_CAMERA_PINCTRL_STATE_SLEEP);
1303 if (IS_ERR(os03b10->pins_sleep))
1304 dev_err(dev, "could not get sleep pinstate\n");
1305 } else {
1306 dev_err(dev, "no pinctrl\n");
1307 }
1308
1309 ret = os03b10_configure_regulators(os03b10);
1310 if (ret) {
1311 dev_err(dev, "Failed to get power regulators\n");
1312 return ret;
1313 }
1314
1315 mutex_init(&os03b10->mutex);
1316
1317 sd = &os03b10->subdev;
1318 v4l2_i2c_subdev_init(sd, client, &os03b10_subdev_ops);
1319 ret = os03b10_initialize_controls(os03b10);
1320 if (ret)
1321 goto err_destroy_mutex;
1322
1323 ret = __os03b10_power_on(os03b10);
1324 if (ret)
1325 goto err_free_handler;
1326
1327 ret = os03b10_check_sensor_id(os03b10, client);
1328 if (ret)
1329 goto err_power_off;
1330
1331 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1332 sd->internal_ops = &os03b10_internal_ops;
1333 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1334 #endif
1335 #if defined(CONFIG_MEDIA_CONTROLLER)
1336 os03b10->pad.flags = MEDIA_PAD_FL_SOURCE;
1337 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1338 ret = media_entity_pads_init(&sd->entity, 1, &os03b10->pad);
1339 if (ret < 0)
1340 goto err_power_off;
1341 #endif
1342
1343 memset(facing, 0, sizeof(facing));
1344 if (strcmp(os03b10->module_facing, "back") == 0)
1345 facing[0] = 'b';
1346 else
1347 facing[0] = 'f';
1348
1349 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1350 os03b10->module_index, facing,
1351 OS03B10_NAME, dev_name(sd->dev));
1352 ret = v4l2_async_register_subdev_sensor_common(sd);
1353 if (ret) {
1354 dev_err(dev, "v4l2 async register subdev failed\n");
1355 goto err_clean_entity;
1356 }
1357
1358 pm_runtime_set_active(dev);
1359 pm_runtime_enable(dev);
1360 pm_runtime_idle(dev);
1361
1362 return 0;
1363
1364 err_clean_entity:
1365 #if defined(CONFIG_MEDIA_CONTROLLER)
1366 media_entity_cleanup(&sd->entity);
1367 #endif
1368 err_power_off:
1369 __os03b10_power_off(os03b10);
1370 err_free_handler:
1371 v4l2_ctrl_handler_free(&os03b10->ctrl_handler);
1372 err_destroy_mutex:
1373 mutex_destroy(&os03b10->mutex);
1374
1375 return ret;
1376 }
1377
os03b10_remove(struct i2c_client * client)1378 static int os03b10_remove(struct i2c_client *client)
1379 {
1380 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1381 struct os03b10 *os03b10 = to_os03b10(sd);
1382
1383 v4l2_async_unregister_subdev(sd);
1384 #if defined(CONFIG_MEDIA_CONTROLLER)
1385 media_entity_cleanup(&sd->entity);
1386 #endif
1387 v4l2_ctrl_handler_free(&os03b10->ctrl_handler);
1388 mutex_destroy(&os03b10->mutex);
1389
1390 pm_runtime_disable(&client->dev);
1391 if (!pm_runtime_status_suspended(&client->dev))
1392 __os03b10_power_off(os03b10);
1393 pm_runtime_set_suspended(&client->dev);
1394
1395 return 0;
1396 }
1397
1398 #if IS_ENABLED(CONFIG_OF)
1399 static const struct of_device_id os03b10_of_match[] = {
1400 { .compatible = "ovti,os03b10" },
1401 {},
1402 };
1403 MODULE_DEVICE_TABLE(of, os03b10_of_match);
1404 #endif
1405
1406 static const struct i2c_device_id os03b10_match_id[] = {
1407 { "ovti,os03b10", 0 },
1408 { },
1409 };
1410
1411 static struct i2c_driver os03b10_i2c_driver = {
1412 .driver = {
1413 .name = OS03B10_NAME,
1414 .pm = &os03b10_pm_ops,
1415 .of_match_table = of_match_ptr(os03b10_of_match),
1416 },
1417 .probe = &os03b10_probe,
1418 .remove = &os03b10_remove,
1419 .id_table = os03b10_match_id,
1420 };
1421
sensor_mod_init(void)1422 static int __init sensor_mod_init(void)
1423 {
1424 return i2c_add_driver(&os03b10_i2c_driver);
1425 }
1426
sensor_mod_exit(void)1427 static void __exit sensor_mod_exit(void)
1428 {
1429 i2c_del_driver(&os03b10_i2c_driver);
1430 }
1431
1432 device_initcall_sync(sensor_mod_init);
1433 module_exit(sensor_mod_exit);
1434
1435 MODULE_DESCRIPTION("OmniVision os03b10 sensor driver");
1436 MODULE_LICENSE("GPL");
1437