1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * nvp6158_v4l2 interface driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * V0.0X01.0X00 first version.
8*4882a593Smuzhiyun * V0.0X01.0X01
9*4882a593Smuzhiyun * 1. add workqueue to detect ahd state.
10*4882a593Smuzhiyun * 2. add more resolution support.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/clk.h>
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
21*4882a593Smuzhiyun #include <linux/sysfs.h>
22*4882a593Smuzhiyun #include <media/media-entity.h>
23*4882a593Smuzhiyun #include <media/v4l2-async.h>
24*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
25*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
26*4882a593Smuzhiyun #include <media/v4l2-fwnode.h>
27*4882a593Smuzhiyun #include <linux/pinctrl/consumer.h>
28*4882a593Smuzhiyun #include <linux/of.h>
29*4882a593Smuzhiyun #include <linux/of_device.h>
30*4882a593Smuzhiyun #include <linux/of_graph.h>
31*4882a593Smuzhiyun #include <linux/of_platform.h>
32*4882a593Smuzhiyun #include <linux/of_gpio.h>
33*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
34*4882a593Smuzhiyun #include <linux/version.h>
35*4882a593Smuzhiyun #include <linux/rk-camera-module.h>
36*4882a593Smuzhiyun #include <linux/rk-preisp.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include "nvp6158_common.h"
39*4882a593Smuzhiyun #include "nvp6158_video.h"
40*4882a593Smuzhiyun #include "nvp6158_coax_protocol.h"
41*4882a593Smuzhiyun #include "nvp6158_motion.h"
42*4882a593Smuzhiyun #include "nvp6158_video_eq.h"
43*4882a593Smuzhiyun #include "nvp6158_drv.h"
44*4882a593Smuzhiyun #include "nvp6158_audio.h"
45*4882a593Smuzhiyun #include "nvp6158_video_auto_detect.h"
46*4882a593Smuzhiyun #include "nvp6158_drv.h"
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun //#define WORK_QUEUE
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #ifdef WORK_QUEUE
51*4882a593Smuzhiyun #include <linux/workqueue.h>
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct sensor_state_check_work {
54*4882a593Smuzhiyun struct workqueue_struct *state_check_wq;
55*4882a593Smuzhiyun struct delayed_work d_work;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #endif
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x1)
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #ifndef V4L2_CID_DIGITAL_GAIN
63*4882a593Smuzhiyun #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define NVP6158_XVCLK_FREQ 24000000
67*4882a593Smuzhiyun #define NVP6158_BITS_PER_SAMPLE 8
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
70*4882a593Smuzhiyun #define NVP6158_PIXEL_RATE 297000000LL
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
73*4882a593Smuzhiyun #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define OF_CAMERA_MODULE_REGULATORS "rockchip,regulator-names"
76*4882a593Smuzhiyun #define OF_CAMERA_MODULE_REGULATOR_VOLTAGES "rockchip,regulator-voltages"
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* DVP MODE, BT1120 or BT656 */
79*4882a593Smuzhiyun #define RK_CAMERA_MODULE_DVP_MODE "rockchip,dvp_mode"
80*4882a593Smuzhiyun #define RK_CAMERA_MODULE_CHANNEL_NUMS "rockchip,channel_nums"
81*4882a593Smuzhiyun #define RK_CAMERA_MODULE_DUAL_EDGE "rockchip,dual_edge"
82*4882a593Smuzhiyun #define RK_CAMERA_MODULE_DEFAULT_RECT "rockchip,default_rect"
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define NVP6158_DEFAULT_DVP_MODE "BT1120"
85*4882a593Smuzhiyun #define NVP6158_DEFAULT_CHANNEL_NUMS 4U
86*4882a593Smuzhiyun #define NVP6158_DEFAULT_DUAL_EDGE 0U
87*4882a593Smuzhiyun #define NVP6158_NAME "nvp6158"
88*4882a593Smuzhiyun #define NVP6158_DEFAULT_WIDTH 1920
89*4882a593Smuzhiyun #define NVP6158_DEFAULT_HEIGHT 1080
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct nvp6158_gpio {
92*4882a593Smuzhiyun int pltfrm_gpio;
93*4882a593Smuzhiyun const char *label;
94*4882a593Smuzhiyun enum of_gpio_flags active_low;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun struct nvp6158_regulator {
98*4882a593Smuzhiyun struct regulator *regulator;
99*4882a593Smuzhiyun u32 min_uV;
100*4882a593Smuzhiyun u32 max_uV;
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun struct nvp6158_regulators {
104*4882a593Smuzhiyun u32 cnt;
105*4882a593Smuzhiyun struct nvp6158_regulator *regulator;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun struct nvp6158_pixfmt {
109*4882a593Smuzhiyun u32 code;
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun struct nvp6158_framesize {
113*4882a593Smuzhiyun u16 width;
114*4882a593Smuzhiyun u16 height;
115*4882a593Smuzhiyun NC_VIVO_CH_FORMATDEF fmt_idx;
116*4882a593Smuzhiyun struct v4l2_fract max_fps;
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun struct nvp6158_default_rect {
120*4882a593Smuzhiyun unsigned int width;
121*4882a593Smuzhiyun unsigned int height;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #ifdef WORK_QUEUE
125*4882a593Smuzhiyun enum nvp6158_hot_plug_state {
126*4882a593Smuzhiyun PLUG_IN = 0,
127*4882a593Smuzhiyun PLUG_OUT,
128*4882a593Smuzhiyun PLUG_STATE_MAX,
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun #endif
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun struct nvp6158 {
133*4882a593Smuzhiyun struct i2c_client *client;
134*4882a593Smuzhiyun struct clk *xvclk;
135*4882a593Smuzhiyun struct gpio_desc *pwr_gpio;
136*4882a593Smuzhiyun struct gpio_desc *pwr2_gpio;
137*4882a593Smuzhiyun struct gpio_desc *rst_gpio;
138*4882a593Smuzhiyun struct gpio_desc *rst2_gpio;
139*4882a593Smuzhiyun struct gpio_desc *pwdn_gpio;
140*4882a593Smuzhiyun struct gpio_desc *pwdn2_gpio;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun struct pinctrl *pinctrl;
143*4882a593Smuzhiyun struct pinctrl_state *pins_default;
144*4882a593Smuzhiyun struct pinctrl_state *pins_sleep;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun struct v4l2_subdev subdev;
147*4882a593Smuzhiyun struct media_pad pad[PAD_MAX];
148*4882a593Smuzhiyun struct v4l2_ctrl_handler ctrl_handler;
149*4882a593Smuzhiyun struct mutex mutex;
150*4882a593Smuzhiyun bool power_on;
151*4882a593Smuzhiyun struct nvp6158_regulators regulators;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun u32 module_index;
154*4882a593Smuzhiyun const char *module_facing;
155*4882a593Smuzhiyun const char *module_name;
156*4882a593Smuzhiyun const char *len_name;
157*4882a593Smuzhiyun const char *dvp_mode;
158*4882a593Smuzhiyun NVP6158_DVP_MODE mode;
159*4882a593Smuzhiyun u32 ch_nums;
160*4882a593Smuzhiyun u32 dual_edge;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun struct v4l2_mbus_framefmt format;
163*4882a593Smuzhiyun const struct nvp6158_framesize *frame_size;
164*4882a593Smuzhiyun int streaming;
165*4882a593Smuzhiyun struct nvp6158_default_rect defrect;
166*4882a593Smuzhiyun #ifdef WORK_QUEUE
167*4882a593Smuzhiyun struct sensor_state_check_work plug_state_check;
168*4882a593Smuzhiyun u8 cur_detect_status;
169*4882a593Smuzhiyun u8 last_detect_status;
170*4882a593Smuzhiyun #endif
171*4882a593Smuzhiyun bool hot_plug;
172*4882a593Smuzhiyun u8 is_reset;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #define to_nvp6158(sd) container_of(sd, struct nvp6158, subdev)
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun static const struct nvp6158_framesize nvp6158_framesizes[] = {
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun .width = 1280,
181*4882a593Smuzhiyun .height = 720,
182*4882a593Smuzhiyun .fmt_idx = AHD20_720P_30P,
183*4882a593Smuzhiyun .max_fps = {
184*4882a593Smuzhiyun .numerator = 10000,
185*4882a593Smuzhiyun .denominator = 250000,
186*4882a593Smuzhiyun },
187*4882a593Smuzhiyun }, {
188*4882a593Smuzhiyun .width = 1920,
189*4882a593Smuzhiyun .height = 1080,
190*4882a593Smuzhiyun .fmt_idx = AHD20_1080P_25P,
191*4882a593Smuzhiyun .max_fps = {
192*4882a593Smuzhiyun .numerator = 10000,
193*4882a593Smuzhiyun .denominator = 250000,
194*4882a593Smuzhiyun },
195*4882a593Smuzhiyun }, {
196*4882a593Smuzhiyun .width = 2048,
197*4882a593Smuzhiyun .height = 1536,
198*4882a593Smuzhiyun .fmt_idx = AHD30_3M_18P,
199*4882a593Smuzhiyun .max_fps = {
200*4882a593Smuzhiyun .numerator = 10000,
201*4882a593Smuzhiyun .denominator = 180000,
202*4882a593Smuzhiyun },
203*4882a593Smuzhiyun }, {
204*4882a593Smuzhiyun .width = 1280,
205*4882a593Smuzhiyun .height = 1440,
206*4882a593Smuzhiyun .fmt_idx = AHD30_4M_30P,
207*4882a593Smuzhiyun .max_fps = {
208*4882a593Smuzhiyun .numerator = 10000,
209*4882a593Smuzhiyun .denominator = 300000,
210*4882a593Smuzhiyun },
211*4882a593Smuzhiyun }, {
212*4882a593Smuzhiyun .width = 2560,
213*4882a593Smuzhiyun .height = 1440,
214*4882a593Smuzhiyun .fmt_idx = AHD30_4M_15P,
215*4882a593Smuzhiyun .max_fps = {
216*4882a593Smuzhiyun .numerator = 10000,
217*4882a593Smuzhiyun .denominator = 150000,
218*4882a593Smuzhiyun },
219*4882a593Smuzhiyun }, {
220*4882a593Smuzhiyun .width = 2592,
221*4882a593Smuzhiyun .height = 1944,
222*4882a593Smuzhiyun .fmt_idx = AHD30_5M_12_5P,
223*4882a593Smuzhiyun .max_fps = {
224*4882a593Smuzhiyun .numerator = 10000,
225*4882a593Smuzhiyun .denominator = 125000,
226*4882a593Smuzhiyun },
227*4882a593Smuzhiyun }, {
228*4882a593Smuzhiyun .width = 3840,
229*4882a593Smuzhiyun .height = 2160,
230*4882a593Smuzhiyun .fmt_idx = AHD30_8M_7_5P,
231*4882a593Smuzhiyun .max_fps = {
232*4882a593Smuzhiyun .numerator = 10000,
233*4882a593Smuzhiyun .denominator = 75000,
234*4882a593Smuzhiyun },
235*4882a593Smuzhiyun }, {/* test modes, Interlace mode*/
236*4882a593Smuzhiyun .width = 720,
237*4882a593Smuzhiyun .height = 480,
238*4882a593Smuzhiyun .fmt_idx = AHD20_SD_SH720_NT,
239*4882a593Smuzhiyun .max_fps = {
240*4882a593Smuzhiyun .numerator = 10000,
241*4882a593Smuzhiyun .denominator = 250000,
242*4882a593Smuzhiyun },
243*4882a593Smuzhiyun }, {
244*4882a593Smuzhiyun .width = 720,
245*4882a593Smuzhiyun .height = 576,
246*4882a593Smuzhiyun .fmt_idx = AHD20_SD_SH720_PAL,
247*4882a593Smuzhiyun .max_fps = {
248*4882a593Smuzhiyun .numerator = 10000,
249*4882a593Smuzhiyun .denominator = 250000,
250*4882a593Smuzhiyun },
251*4882a593Smuzhiyun }, {
252*4882a593Smuzhiyun .width = 960,
253*4882a593Smuzhiyun .height = 576,
254*4882a593Smuzhiyun .fmt_idx = AHD20_SD_H960_PAL,
255*4882a593Smuzhiyun .max_fps = {
256*4882a593Smuzhiyun .numerator = 10000,
257*4882a593Smuzhiyun .denominator = 250000,
258*4882a593Smuzhiyun },
259*4882a593Smuzhiyun }, {
260*4882a593Smuzhiyun .width = 1920,
261*4882a593Smuzhiyun .height = 576,
262*4882a593Smuzhiyun .fmt_idx = AHD20_SD_H960_EX_PAL,
263*4882a593Smuzhiyun .max_fps = {
264*4882a593Smuzhiyun .numerator = 10000,
265*4882a593Smuzhiyun .denominator = 250000,
266*4882a593Smuzhiyun },
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun };
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun static char *nvp6158_dvp_mode_lists[] = {
271*4882a593Smuzhiyun [BT601] = "BT601",
272*4882a593Smuzhiyun [BT656_1MUX] = "BT656_1MUX",
273*4882a593Smuzhiyun [BT656_2MUX] = "BT656_2MUX",
274*4882a593Smuzhiyun [BT656_4MUX] = "BT656_4MUX",
275*4882a593Smuzhiyun [BT1120_1MUX] = "BT1120_1MUX",
276*4882a593Smuzhiyun [BT1120_2MUX] = "BT1120_2MUX",
277*4882a593Smuzhiyun [BT1120_4MUX] = "BT1120_4MUX",
278*4882a593Smuzhiyun [BT656I_TEST_MODES] = "BT656I_TEST_MODES"
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun static const struct nvp6158_pixfmt nvp6158_formats[] = {
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun .code = MEDIA_BUS_FMT_UYVY8_2X8
284*4882a593Smuzhiyun },
285*4882a593Smuzhiyun };
286*4882a593Smuzhiyun
nvp6158_querystd(struct v4l2_subdev * sd,v4l2_std_id * std)287*4882a593Smuzhiyun static int nvp6158_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if ((nvp6158->mode > BT656I_TEST_MODES) &&
292*4882a593Smuzhiyun (nvp6158->mode < NVP6158_DVP_MODES_END)) {
293*4882a593Smuzhiyun /* for vicap detect bt1120 */
294*4882a593Smuzhiyun *std = V4L2_STD_ATSC;
295*4882a593Smuzhiyun } else {
296*4882a593Smuzhiyun *std = V4L2_STD_PAL;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun return 0;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /* sensor register write */
nvp6158_write(struct i2c_client * client,u8 reg,u8 val)302*4882a593Smuzhiyun static int nvp6158_write(struct i2c_client *client, u8 reg, u8 val)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun struct i2c_msg msg;
305*4882a593Smuzhiyun u8 buf[2];
306*4882a593Smuzhiyun int ret;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun dev_info(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
309*4882a593Smuzhiyun buf[0] = reg & 0xFF;
310*4882a593Smuzhiyun buf[1] = val;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun msg.addr = client->addr;
313*4882a593Smuzhiyun msg.flags = client->flags;
314*4882a593Smuzhiyun msg.buf = buf;
315*4882a593Smuzhiyun msg.len = sizeof(buf);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, &msg, 1);
318*4882a593Smuzhiyun if (ret >= 0)
319*4882a593Smuzhiyun return 0;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun dev_err(&client->dev,
322*4882a593Smuzhiyun "nvp6158 write reg(0x%x val:0x%x) failed !\n", reg, val);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun return ret;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* sensor register read */
nvp6158_read(struct i2c_client * client,u8 reg,u8 * val)328*4882a593Smuzhiyun static int nvp6158_read(struct i2c_client *client, u8 reg, u8 *val)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun struct i2c_msg msg[2];
331*4882a593Smuzhiyun u8 buf[1];
332*4882a593Smuzhiyun int ret;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun buf[0] = reg & 0xFF;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun msg[0].addr = client->addr;
337*4882a593Smuzhiyun msg[0].flags = client->flags;
338*4882a593Smuzhiyun msg[0].buf = buf;
339*4882a593Smuzhiyun msg[0].len = sizeof(buf);
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun msg[1].addr = client->addr;
342*4882a593Smuzhiyun msg[1].flags = client->flags | I2C_M_RD;
343*4882a593Smuzhiyun msg[1].buf = buf;
344*4882a593Smuzhiyun msg[1].len = 1;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun ret = i2c_transfer(client->adapter, msg, 2);
347*4882a593Smuzhiyun if (ret >= 0) {
348*4882a593Smuzhiyun *val = buf[0];
349*4882a593Smuzhiyun return 0;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun dev_err(&client->dev, "nvp6158 read reg(0x%x) failed !\n", reg);
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun return ret;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
__nvp6158_power_on(struct nvp6158 * nvp6158)357*4882a593Smuzhiyun static int __nvp6158_power_on(struct nvp6158 *nvp6158)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun u32 i;
360*4882a593Smuzhiyun int ret;
361*4882a593Smuzhiyun struct nvp6158_regulator *regulator;
362*4882a593Smuzhiyun struct device *dev = &nvp6158->client->dev;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun dev_info(dev, "%s(%d)\n", __func__, __LINE__);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(nvp6158->pins_default)) {
367*4882a593Smuzhiyun ret = pinctrl_select_state(nvp6158->pinctrl,
368*4882a593Smuzhiyun nvp6158->pins_default);
369*4882a593Smuzhiyun if (ret < 0)
370*4882a593Smuzhiyun dev_err(dev, "could not set pins. ret=%d\n", ret);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun ret = clk_prepare_enable(nvp6158->xvclk);
374*4882a593Smuzhiyun if (ret < 0) {
375*4882a593Smuzhiyun dev_err(dev, "Failed to enable xvclk\n");
376*4882a593Smuzhiyun return ret;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun if (nvp6158->regulators.regulator) {
380*4882a593Smuzhiyun for (i = 0; i < nvp6158->regulators.cnt; i++) {
381*4882a593Smuzhiyun regulator = nvp6158->regulators.regulator + i;
382*4882a593Smuzhiyun if (IS_ERR(regulator->regulator))
383*4882a593Smuzhiyun continue;
384*4882a593Smuzhiyun regulator_set_voltage(
385*4882a593Smuzhiyun regulator->regulator,
386*4882a593Smuzhiyun regulator->min_uV,
387*4882a593Smuzhiyun regulator->max_uV);
388*4882a593Smuzhiyun if (regulator_enable(regulator->regulator)) {
389*4882a593Smuzhiyun dev_err(dev,
390*4882a593Smuzhiyun "regulator_enable failed!\n");
391*4882a593Smuzhiyun goto disable_clk;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun usleep_range(3000, 5000);
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwr_gpio)) {
398*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwr_gpio, 1);
399*4882a593Smuzhiyun usleep_range(3000, 5000);
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwr2_gpio)) {
403*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwr2_gpio, 1);
404*4882a593Smuzhiyun usleep_range(3000, 5000);
405*4882a593Smuzhiyun }
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwdn_gpio)) {
408*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwdn_gpio, 1);
409*4882a593Smuzhiyun usleep_range(1500, 2000);
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwdn2_gpio)) {
413*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwdn2_gpio, 1);
414*4882a593Smuzhiyun usleep_range(1500, 2000);
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun if (!IS_ERR(nvp6158->rst_gpio)) {
418*4882a593Smuzhiyun gpiod_direction_output(nvp6158->rst_gpio, 0);
419*4882a593Smuzhiyun usleep_range(50000, 100000);
420*4882a593Smuzhiyun gpiod_direction_output(nvp6158->rst_gpio, 1);
421*4882a593Smuzhiyun usleep_range(3000, 5000);
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun if (!IS_ERR(nvp6158->rst2_gpio)) {
425*4882a593Smuzhiyun gpiod_direction_output(nvp6158->rst2_gpio, 0);
426*4882a593Smuzhiyun usleep_range(1500, 2000);
427*4882a593Smuzhiyun gpiod_direction_output(nvp6158->rst2_gpio, 1);
428*4882a593Smuzhiyun usleep_range(3000, 5000);
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun return 0;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun disable_clk:
434*4882a593Smuzhiyun clk_disable_unprepare(nvp6158->xvclk);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun return ret;
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
__nvp6158_power_off(struct nvp6158 * nvp6158)439*4882a593Smuzhiyun static void __nvp6158_power_off(struct nvp6158 *nvp6158)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun u32 i;
442*4882a593Smuzhiyun int ret;
443*4882a593Smuzhiyun struct nvp6158_regulator *regulator;
444*4882a593Smuzhiyun struct device *dev = &nvp6158->client->dev;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun dev_info(dev, "%s(%d)\n", __func__, __LINE__);
447*4882a593Smuzhiyun clk_disable_unprepare(nvp6158->xvclk);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun if (!IS_ERR(nvp6158->rst_gpio))
450*4882a593Smuzhiyun gpiod_direction_output(nvp6158->rst_gpio, 0);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun if (!IS_ERR(nvp6158->rst2_gpio))
453*4882a593Smuzhiyun gpiod_direction_output(nvp6158->rst2_gpio, 0);
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwdn_gpio))
456*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwdn_gpio, 0);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwdn_gpio))
459*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwdn2_gpio, 0);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwr_gpio))
462*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwr_gpio, 0);
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pwr2_gpio))
465*4882a593Smuzhiyun gpiod_direction_output(nvp6158->pwr2_gpio, 0);
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(nvp6158->pins_sleep)) {
468*4882a593Smuzhiyun ret = pinctrl_select_state(nvp6158->pinctrl,
469*4882a593Smuzhiyun nvp6158->pins_sleep);
470*4882a593Smuzhiyun if (ret < 0)
471*4882a593Smuzhiyun dev_err(dev, "could not set pins\n");
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if (nvp6158->regulators.regulator) {
475*4882a593Smuzhiyun for (i = 0; i < nvp6158->regulators.cnt; i++) {
476*4882a593Smuzhiyun regulator = nvp6158->regulators.regulator + i;
477*4882a593Smuzhiyun if (IS_ERR(regulator->regulator))
478*4882a593Smuzhiyun continue;
479*4882a593Smuzhiyun regulator_disable(regulator->regulator);
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun }
483*4882a593Smuzhiyun
nvp6158_power(struct v4l2_subdev * sd,int on)484*4882a593Smuzhiyun static int nvp6158_power(struct v4l2_subdev *sd, int on)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
487*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
488*4882a593Smuzhiyun int ret = 0;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun dev_info(&client->dev, "%s: on %d\n", __func__, on);
491*4882a593Smuzhiyun mutex_lock(&nvp6158->mutex);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun /* If the power state is not modified - no work to do. */
494*4882a593Smuzhiyun if (nvp6158->power_on == !!on)
495*4882a593Smuzhiyun goto exit;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun if (on) {
498*4882a593Smuzhiyun ret = __nvp6158_power_on(nvp6158);
499*4882a593Smuzhiyun if (ret < 0)
500*4882a593Smuzhiyun goto exit;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun nvp6158->power_on = true;
503*4882a593Smuzhiyun } else {
504*4882a593Smuzhiyun __nvp6158_power_off(nvp6158);
505*4882a593Smuzhiyun nvp6158->power_on = false;
506*4882a593Smuzhiyun }
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun exit:
509*4882a593Smuzhiyun mutex_unlock(&nvp6158->mutex);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun return ret;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
515*4882a593Smuzhiyun /*
516*4882a593Smuzhiyun * The resolution of the driver configuration needs to be exactly
517*4882a593Smuzhiyun * the same as the current output resolution of the sensor,
518*4882a593Smuzhiyun * the input width of the isp needs to be 16 aligned,
519*4882a593Smuzhiyun * the input height of the isp needs to be 8 aligned.
520*4882a593Smuzhiyun * Can be cropped to standard resolution by this function,
521*4882a593Smuzhiyun * otherwise it will crop out strange resolution according
522*4882a593Smuzhiyun * to the alignment rules.
523*4882a593Smuzhiyun */
nvp6158_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)524*4882a593Smuzhiyun static int nvp6158_get_selection(struct v4l2_subdev *sd,
525*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
526*4882a593Smuzhiyun struct v4l2_subdev_selection *sel)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
531*4882a593Smuzhiyun sel->r.left = CROP_START(0, 0);
532*4882a593Smuzhiyun sel->r.width = nvp6158->frame_size->width;
533*4882a593Smuzhiyun sel->r.top = CROP_START(0, 0);
534*4882a593Smuzhiyun sel->r.height = nvp6158->frame_size->height;
535*4882a593Smuzhiyun return 0;
536*4882a593Smuzhiyun }
537*4882a593Smuzhiyun return -EINVAL;
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun
nvp6158_initialize_controls(struct nvp6158 * nvp6158)540*4882a593Smuzhiyun static int nvp6158_initialize_controls(struct nvp6158 *nvp6158)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun struct v4l2_ctrl_handler *handler;
543*4882a593Smuzhiyun int ret;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun handler = &nvp6158->ctrl_handler;
546*4882a593Smuzhiyun ret = v4l2_ctrl_handler_init(handler, 2);
547*4882a593Smuzhiyun if (ret)
548*4882a593Smuzhiyun return ret;
549*4882a593Smuzhiyun handler->lock = &nvp6158->mutex;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
552*4882a593Smuzhiyun 0, NVP6158_PIXEL_RATE, 1, NVP6158_PIXEL_RATE);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun if (handler->error) {
555*4882a593Smuzhiyun ret = handler->error;
556*4882a593Smuzhiyun dev_err(&nvp6158->client->dev,
557*4882a593Smuzhiyun "Failed to init controls(%d)\n", ret);
558*4882a593Smuzhiyun goto err_free_handler;
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun nvp6158->subdev.ctrl_handler = handler;
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun return 0;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun err_free_handler:
566*4882a593Smuzhiyun v4l2_ctrl_handler_free(handler);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun return ret;
569*4882a593Smuzhiyun }
nvp6158_get_default_format(struct nvp6158 * nvp6158)570*4882a593Smuzhiyun static void nvp6158_get_default_format(struct nvp6158 *nvp6158)
571*4882a593Smuzhiyun {
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun const struct nvp6158_framesize *fsize = &nvp6158_framesizes[0];
574*4882a593Smuzhiyun const struct nvp6158_framesize *match = NULL;
575*4882a593Smuzhiyun int i = ARRAY_SIZE(nvp6158_framesizes);
576*4882a593Smuzhiyun unsigned int min_err = UINT_MAX;
577*4882a593Smuzhiyun struct v4l2_mbus_framefmt *format = &nvp6158->format;
578*4882a593Smuzhiyun struct nvp6158_default_rect *rect = &nvp6158->defrect;
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun while (i--) {
581*4882a593Smuzhiyun unsigned int err = abs(fsize->width - rect->width)
582*4882a593Smuzhiyun + abs(fsize->height - rect->height);
583*4882a593Smuzhiyun if (err < min_err) {
584*4882a593Smuzhiyun min_err = err;
585*4882a593Smuzhiyun match = fsize;
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun fsize++;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun if (!match)
591*4882a593Smuzhiyun match = &nvp6158_framesizes[0];
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun format->width = match->width;
594*4882a593Smuzhiyun format->height = match->height;
595*4882a593Smuzhiyun format->colorspace = V4L2_COLORSPACE_SRGB;
596*4882a593Smuzhiyun format->code = nvp6158_formats[0].code;
597*4882a593Smuzhiyun if (BT656I_TEST_MODES == nvp6158->mode)
598*4882a593Smuzhiyun format->field = V4L2_FIELD_INTERLACED;
599*4882a593Smuzhiyun else
600*4882a593Smuzhiyun format->field = V4L2_FIELD_NONE;
601*4882a593Smuzhiyun nvp6158->frame_size = match;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun
nvp6158_stream(struct v4l2_subdev * sd,int on)604*4882a593Smuzhiyun static int nvp6158_stream(struct v4l2_subdev *sd, int on)
605*4882a593Smuzhiyun {
606*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
607*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
608*4882a593Smuzhiyun video_init_all video_init;
609*4882a593Smuzhiyun NC_VIVO_CH_FORMATDEF fmt_idx;
610*4882a593Smuzhiyun int ch;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun dev_info(&client->dev, "%s: on: %d, %dx%d\n", __func__, on,
613*4882a593Smuzhiyun nvp6158->frame_size->width,
614*4882a593Smuzhiyun nvp6158->frame_size->height);
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun mutex_lock(&nvp6158->mutex);
617*4882a593Smuzhiyun on = !!on;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun if (nvp6158->streaming == on)
620*4882a593Smuzhiyun goto unlock;
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun if (on) {
623*4882a593Smuzhiyun for (ch = 0; ch < 4; ch++) {
624*4882a593Smuzhiyun fmt_idx = nvp6158->frame_size->fmt_idx;
625*4882a593Smuzhiyun video_init.ch_param[ch].ch = ch;
626*4882a593Smuzhiyun video_init.ch_param[ch].format = fmt_idx;
627*4882a593Smuzhiyun }
628*4882a593Smuzhiyun video_init.mode = nvp6158->mode;
629*4882a593Smuzhiyun nvp6158_start(&video_init, nvp6158->dual_edge ? true : false);
630*4882a593Smuzhiyun #ifdef WORK_QUEUE
631*4882a593Smuzhiyun if (nvp6158->plug_state_check.state_check_wq) {
632*4882a593Smuzhiyun dev_info(&client->dev, "%s queue_delayed_work 1000ms", __func__);
633*4882a593Smuzhiyun queue_delayed_work(nvp6158->plug_state_check.state_check_wq,
634*4882a593Smuzhiyun &nvp6158->plug_state_check.d_work,
635*4882a593Smuzhiyun msecs_to_jiffies(1000));
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun #endif
638*4882a593Smuzhiyun } else {
639*4882a593Smuzhiyun #ifdef WORK_QUEUE
640*4882a593Smuzhiyun cancel_delayed_work_sync(&nvp6158->plug_state_check.d_work);
641*4882a593Smuzhiyun dev_info(&client->dev, "cancle_queue_delayed_work");
642*4882a593Smuzhiyun #endif
643*4882a593Smuzhiyun nvp6158_stop();
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun nvp6158->streaming = on;
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun unlock:
649*4882a593Smuzhiyun mutex_unlock(&nvp6158->mutex);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun return 0;
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun
nvp6158_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)654*4882a593Smuzhiyun static int nvp6158_enum_frame_interval(struct v4l2_subdev *sd,
655*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
656*4882a593Smuzhiyun struct v4l2_subdev_frame_interval_enum *fie)
657*4882a593Smuzhiyun {
658*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
659*4882a593Smuzhiyun struct i2c_client *client = nvp6158->client;
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun dev_dbg(&client->dev, "%s enter.\n", __func__);
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun if (fie->index >= ARRAY_SIZE(nvp6158_framesizes))
664*4882a593Smuzhiyun return -EINVAL;
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun fie->width = nvp6158_framesizes[fie->index].width;
667*4882a593Smuzhiyun fie->height = nvp6158_framesizes[fie->index].height;
668*4882a593Smuzhiyun fie->interval = nvp6158_framesizes[fie->index].max_fps;
669*4882a593Smuzhiyun return 0;
670*4882a593Smuzhiyun }
671*4882a593Smuzhiyun
nvp6158_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)672*4882a593Smuzhiyun static int nvp6158_enum_mbus_code(struct v4l2_subdev *sd,
673*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
674*4882a593Smuzhiyun struct v4l2_subdev_mbus_code_enum *code)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun if (code->index >= ARRAY_SIZE(nvp6158_formats))
677*4882a593Smuzhiyun return -EINVAL;
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun code->code = nvp6158_formats[code->index].code;
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun return 0;
682*4882a593Smuzhiyun }
683*4882a593Smuzhiyun
nvp6158_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)684*4882a593Smuzhiyun static int nvp6158_enum_frame_sizes(struct v4l2_subdev *sd,
685*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
686*4882a593Smuzhiyun struct v4l2_subdev_frame_size_enum *fse)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
689*4882a593Smuzhiyun int i = ARRAY_SIZE(nvp6158_formats);
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: enter!\n", __func__);
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun if (fse->index >= ARRAY_SIZE(nvp6158_framesizes))
694*4882a593Smuzhiyun return -EINVAL;
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun while (--i)
697*4882a593Smuzhiyun if (fse->code == nvp6158_formats[i].code)
698*4882a593Smuzhiyun break;
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun fse->code = nvp6158_formats[i].code;
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun fse->min_width = nvp6158_framesizes[fse->index].width;
703*4882a593Smuzhiyun fse->max_width = fse->min_width;
704*4882a593Smuzhiyun fse->max_height = nvp6158_framesizes[fse->index].height;
705*4882a593Smuzhiyun fse->min_height = fse->max_height;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun return 0;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun /* indicate N4 no signal channel */
nvp6158_no_signal(struct v4l2_subdev * sd,u8 * novid)711*4882a593Smuzhiyun static inline bool nvp6158_no_signal(struct v4l2_subdev *sd, u8 *novid)
712*4882a593Smuzhiyun {
713*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
714*4882a593Smuzhiyun struct i2c_client *client = nvp6158->client;
715*4882a593Smuzhiyun u8 videoloss = 0;
716*4882a593Smuzhiyun int ret;
717*4882a593Smuzhiyun bool no_signal = false;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun nvp6158_write(client, 0xff, 0x00);
720*4882a593Smuzhiyun ret = nvp6158_read(client, 0xa8, &videoloss);
721*4882a593Smuzhiyun if (ret < 0)
722*4882a593Smuzhiyun dev_err(&client->dev, "Failed to read videoloss state!\n");
723*4882a593Smuzhiyun
724*4882a593Smuzhiyun *novid = videoloss;
725*4882a593Smuzhiyun dev_info(&client->dev, "%s: video loss status:0x%x.\n", __func__, videoloss);
726*4882a593Smuzhiyun if (videoloss == 0xf) {
727*4882a593Smuzhiyun dev_info(&client->dev, "%s: all channels No Video detected.\n", __func__);
728*4882a593Smuzhiyun no_signal = true;
729*4882a593Smuzhiyun } else {
730*4882a593Smuzhiyun dev_info(&client->dev, "%s: channel has some video detection.\n", __func__);
731*4882a593Smuzhiyun no_signal = false;
732*4882a593Smuzhiyun }
733*4882a593Smuzhiyun return no_signal;
734*4882a593Smuzhiyun }
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun /* indicate N4 channel locked status */
nvp6158_sync(struct v4l2_subdev * sd,u8 * lock_st)737*4882a593Smuzhiyun static inline bool nvp6158_sync(struct v4l2_subdev *sd, u8 *lock_st)
738*4882a593Smuzhiyun {
739*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
740*4882a593Smuzhiyun u8 video_lock_status = 0;
741*4882a593Smuzhiyun int ret;
742*4882a593Smuzhiyun bool has_sync = false;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun nvp6158_write(client, 0xff, 0x00);
745*4882a593Smuzhiyun ret = nvp6158_read(client, 0xe0, &video_lock_status);
746*4882a593Smuzhiyun if (ret < 0)
747*4882a593Smuzhiyun dev_err(&client->dev, "Failed to read sync state!\n");
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun dev_info(&client->dev, "%s: video AGC LOCK status:0x%x.\n",
750*4882a593Smuzhiyun __func__, video_lock_status);
751*4882a593Smuzhiyun *lock_st = video_lock_status;
752*4882a593Smuzhiyun if (video_lock_status) {
753*4882a593Smuzhiyun dev_info(&client->dev, "%s: channel has AGC LOCK.\n", __func__);
754*4882a593Smuzhiyun has_sync = true;
755*4882a593Smuzhiyun } else {
756*4882a593Smuzhiyun dev_info(&client->dev, "%s: channel has no AGC LOCK.\n", __func__);
757*4882a593Smuzhiyun has_sync = false;
758*4882a593Smuzhiyun }
759*4882a593Smuzhiyun return has_sync;
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun #ifdef WORK_QUEUE
nvp6158_plug_state_check_work(struct work_struct * work)763*4882a593Smuzhiyun static void nvp6158_plug_state_check_work(struct work_struct *work)
764*4882a593Smuzhiyun {
765*4882a593Smuzhiyun struct sensor_state_check_work *params_check =
766*4882a593Smuzhiyun container_of(work, struct sensor_state_check_work, d_work.work);
767*4882a593Smuzhiyun struct nvp6158 *nvp6158 =
768*4882a593Smuzhiyun container_of(params_check, struct nvp6158, plug_state_check);
769*4882a593Smuzhiyun struct i2c_client *client = nvp6158->client;
770*4882a593Smuzhiyun struct v4l2_subdev *sd = &nvp6158->subdev;
771*4882a593Smuzhiyun u8 novid_status = 0x00;
772*4882a593Smuzhiyun u8 sync_status = 0x00;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun nvp6158_no_signal(sd, &novid_status);
775*4882a593Smuzhiyun nvp6158_sync(sd, &sync_status);
776*4882a593Smuzhiyun nvp6158->cur_detect_status = novid_status;
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun /* detect state change to determine is there has plug motion */
779*4882a593Smuzhiyun novid_status = nvp6158->cur_detect_status ^ nvp6158->last_detect_status;
780*4882a593Smuzhiyun if (novid_status)
781*4882a593Smuzhiyun nvp6158->hot_plug = true;
782*4882a593Smuzhiyun else
783*4882a593Smuzhiyun nvp6158->hot_plug = false;
784*4882a593Smuzhiyun nvp6158->last_detect_status = nvp6158->cur_detect_status;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun dev_info(&client->dev, "%s has plug motion? (%s)", __func__,
787*4882a593Smuzhiyun nvp6158->hot_plug ? "true" : "false");
788*4882a593Smuzhiyun if (nvp6158->hot_plug) {
789*4882a593Smuzhiyun dev_info(&client->dev, "queue_delayed_work 1500ms, if has hot plug motion.");
790*4882a593Smuzhiyun queue_delayed_work(nvp6158->plug_state_check.state_check_wq,
791*4882a593Smuzhiyun &nvp6158->plug_state_check.d_work, msecs_to_jiffies(1500));
792*4882a593Smuzhiyun nvp6158_write(client, 0xFF, 0x20);
793*4882a593Smuzhiyun nvp6158_write(client, 0x00, (sync_status << 4) | sync_status);
794*4882a593Smuzhiyun usleep_range(3000, 5000);
795*4882a593Smuzhiyun nvp6158_write(client, 0x00, 0xFF);
796*4882a593Smuzhiyun } else {
797*4882a593Smuzhiyun dev_info(&client->dev, "queue_delayed_work 100ms, if no hot plug motion.");
798*4882a593Smuzhiyun queue_delayed_work(nvp6158->plug_state_check.state_check_wq,
799*4882a593Smuzhiyun &nvp6158->plug_state_check.d_work, msecs_to_jiffies(100));
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun #endif
803*4882a593Smuzhiyun
nvp6158_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * cfg)804*4882a593Smuzhiyun static int nvp6158_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
805*4882a593Smuzhiyun struct v4l2_mbus_config *cfg)
806*4882a593Smuzhiyun {
807*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun cfg->type = V4L2_MBUS_BT656;
810*4882a593Smuzhiyun if (nvp6158->dual_edge == 1) {
811*4882a593Smuzhiyun cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
812*4882a593Smuzhiyun V4L2_MBUS_PCLK_SAMPLE_RISING |
813*4882a593Smuzhiyun V4L2_MBUS_PCLK_SAMPLE_FALLING;
814*4882a593Smuzhiyun } else {
815*4882a593Smuzhiyun cfg->flags = RKMODULE_CAMERA_BT656_CHANNELS |
816*4882a593Smuzhiyun V4L2_MBUS_PCLK_SAMPLE_RISING;
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun return 0;
819*4882a593Smuzhiyun }
820*4882a593Smuzhiyun
nvp6158_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)821*4882a593Smuzhiyun static int nvp6158_get_fmt(struct v4l2_subdev *sd,
822*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
823*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun struct i2c_client *client = v4l2_get_subdevdata(sd);
826*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
829*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
830*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mf;
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun mf = v4l2_subdev_get_try_format(sd, cfg, 0);
833*4882a593Smuzhiyun mutex_lock(&nvp6158->mutex);
834*4882a593Smuzhiyun fmt->format = *mf;
835*4882a593Smuzhiyun mutex_unlock(&nvp6158->mutex);
836*4882a593Smuzhiyun return 0;
837*4882a593Smuzhiyun #else
838*4882a593Smuzhiyun return -ENOTTY;
839*4882a593Smuzhiyun #endif
840*4882a593Smuzhiyun }
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun mutex_lock(&nvp6158->mutex);
843*4882a593Smuzhiyun fmt->format = nvp6158->format;
844*4882a593Smuzhiyun mutex_unlock(&nvp6158->mutex);
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun dev_dbg(&client->dev, "%s: %x %dx%d\n", __func__,
847*4882a593Smuzhiyun nvp6158->format.code, nvp6158->format.width,
848*4882a593Smuzhiyun nvp6158->format.height);
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun return 0;
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun
__nvp6158_try_frame_size(struct v4l2_mbus_framefmt * mf,const struct nvp6158_framesize ** size)853*4882a593Smuzhiyun static void __nvp6158_try_frame_size(struct v4l2_mbus_framefmt *mf,
854*4882a593Smuzhiyun const struct nvp6158_framesize **size)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun const struct nvp6158_framesize *fsize = &nvp6158_framesizes[0];
857*4882a593Smuzhiyun const struct nvp6158_framesize *match = NULL;
858*4882a593Smuzhiyun int i = ARRAY_SIZE(nvp6158_framesizes);
859*4882a593Smuzhiyun unsigned int min_err = UINT_MAX;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun while (i--) {
862*4882a593Smuzhiyun unsigned int err = abs(fsize->width - mf->width)
863*4882a593Smuzhiyun + abs(fsize->height - mf->height);
864*4882a593Smuzhiyun if (err < min_err) {
865*4882a593Smuzhiyun min_err = err;
866*4882a593Smuzhiyun match = fsize;
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun fsize++;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun
871*4882a593Smuzhiyun if (!match)
872*4882a593Smuzhiyun match = &nvp6158_framesizes[0];
873*4882a593Smuzhiyun
874*4882a593Smuzhiyun mf->width = match->width;
875*4882a593Smuzhiyun mf->height = match->height;
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun if (size)
878*4882a593Smuzhiyun *size = match;
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun
nvp6158_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)881*4882a593Smuzhiyun static int nvp6158_set_fmt(struct v4l2_subdev *sd,
882*4882a593Smuzhiyun struct v4l2_subdev_pad_config *cfg,
883*4882a593Smuzhiyun struct v4l2_subdev_format *fmt)
884*4882a593Smuzhiyun {
885*4882a593Smuzhiyun int index = ARRAY_SIZE(nvp6158_formats);
886*4882a593Smuzhiyun struct v4l2_mbus_framefmt *mf = &fmt->format;
887*4882a593Smuzhiyun const struct nvp6158_framesize *size = NULL;
888*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
889*4882a593Smuzhiyun int ret = 0;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun __nvp6158_try_frame_size(mf, &size);
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun while (--index >= 0)
894*4882a593Smuzhiyun if (nvp6158_formats[index].code == mf->code)
895*4882a593Smuzhiyun break;
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun if (index < 0)
898*4882a593Smuzhiyun return -EINVAL;
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun mf->colorspace = V4L2_COLORSPACE_SRGB;
901*4882a593Smuzhiyun mf->code = nvp6158_formats[index].code;
902*4882a593Smuzhiyun mf->field = nvp6158->format.field;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun mutex_lock(&nvp6158->mutex);
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
907*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
908*4882a593Smuzhiyun mf = v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
909*4882a593Smuzhiyun *mf = fmt->format;
910*4882a593Smuzhiyun #else
911*4882a593Smuzhiyun return -ENOTTY;
912*4882a593Smuzhiyun #endif
913*4882a593Smuzhiyun } else {
914*4882a593Smuzhiyun if (nvp6158->streaming) {
915*4882a593Smuzhiyun mutex_unlock(&nvp6158->mutex);
916*4882a593Smuzhiyun return -EBUSY;
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun nvp6158->frame_size = size;
920*4882a593Smuzhiyun nvp6158->format = fmt->format;
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun mutex_unlock(&nvp6158->mutex);
924*4882a593Smuzhiyun return ret;
925*4882a593Smuzhiyun }
926*4882a593Smuzhiyun
nvp6158_get_module_inf(struct nvp6158 * nvp6158,struct rkmodule_inf * inf)927*4882a593Smuzhiyun static void nvp6158_get_module_inf(struct nvp6158 *nvp6158,
928*4882a593Smuzhiyun struct rkmodule_inf *inf)
929*4882a593Smuzhiyun {
930*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
931*4882a593Smuzhiyun strlcpy(inf->base.sensor, NVP6158_NAME, sizeof(inf->base.sensor));
932*4882a593Smuzhiyun strlcpy(inf->base.module, nvp6158->module_name,
933*4882a593Smuzhiyun sizeof(inf->base.module));
934*4882a593Smuzhiyun strlcpy(inf->base.lens, nvp6158->len_name, sizeof(inf->base.lens));
935*4882a593Smuzhiyun }
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun static __maybe_unused void
nvp6158_get_bt656_module_inf(struct nvp6158 * nvp6158,struct rkmodule_bt656_mbus_info * inf)938*4882a593Smuzhiyun nvp6158_get_bt656_module_inf(struct nvp6158 *nvp6158,
939*4882a593Smuzhiyun struct rkmodule_bt656_mbus_info *inf)
940*4882a593Smuzhiyun {
941*4882a593Smuzhiyun memset(inf, 0, sizeof(*inf));
942*4882a593Smuzhiyun inf->flags = RKMODULE_CAMERA_BT656_PARSE_ID_LSB;
943*4882a593Smuzhiyun switch (nvp6158->ch_nums) {
944*4882a593Smuzhiyun case 1:
945*4882a593Smuzhiyun inf->flags |= RKMODULE_CAMERA_BT656_CHANNEL_0;
946*4882a593Smuzhiyun break;
947*4882a593Smuzhiyun case 2:
948*4882a593Smuzhiyun inf->flags |= RKMODULE_CAMERA_BT656_CHANNEL_0 |
949*4882a593Smuzhiyun RKMODULE_CAMERA_BT656_CHANNEL_1;
950*4882a593Smuzhiyun break;
951*4882a593Smuzhiyun case 4:
952*4882a593Smuzhiyun inf->flags |= RKMODULE_CAMERA_BT656_CHANNELS;
953*4882a593Smuzhiyun break;
954*4882a593Smuzhiyun default:
955*4882a593Smuzhiyun inf->flags |= RKMODULE_CAMERA_BT656_CHANNELS;
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun
nvp6158_get_vicap_rst_inf(struct nvp6158 * nvp6158,struct rkmodule_vicap_reset_info * rst_info)959*4882a593Smuzhiyun static void nvp6158_get_vicap_rst_inf(struct nvp6158 *nvp6158,
960*4882a593Smuzhiyun struct rkmodule_vicap_reset_info *rst_info)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun struct i2c_client *client = nvp6158->client;
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun rst_info->is_reset = nvp6158->hot_plug;
965*4882a593Smuzhiyun nvp6158->hot_plug = false;
966*4882a593Smuzhiyun rst_info->src = RKCIF_RESET_SRC_ERR_HOTPLUG;
967*4882a593Smuzhiyun dev_info(&client->dev, "%s: rst_info->is_reset:%d.\n", __func__, rst_info->is_reset);
968*4882a593Smuzhiyun }
969*4882a593Smuzhiyun
nvp6158_set_vicap_rst_inf(struct nvp6158 * nvp6158,struct rkmodule_vicap_reset_info rst_info)970*4882a593Smuzhiyun static void nvp6158_set_vicap_rst_inf(struct nvp6158 *nvp6158,
971*4882a593Smuzhiyun struct rkmodule_vicap_reset_info rst_info)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun nvp6158->is_reset = rst_info.is_reset;
974*4882a593Smuzhiyun }
975*4882a593Smuzhiyun
nvp6158_set_streaming(struct nvp6158 * nvp6158,int on)976*4882a593Smuzhiyun static void nvp6158_set_streaming(struct nvp6158 *nvp6158, int on)
977*4882a593Smuzhiyun {
978*4882a593Smuzhiyun struct i2c_client *client = nvp6158->client;
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun dev_info(&client->dev, "%s: on: %d\n", __func__, on);
982*4882a593Smuzhiyun
983*4882a593Smuzhiyun if (on) {
984*4882a593Smuzhiyun //VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
985*4882a593Smuzhiyun nvp6158_write(client, 0xFF, 0x01);
986*4882a593Smuzhiyun nvp6158_write(client, 0xCA, 0x66);
987*4882a593Smuzhiyun } else {
988*4882a593Smuzhiyun //VDO2/VDO1 disable VCLK_1/VCLK_2_DISABLE
989*4882a593Smuzhiyun nvp6158_write(client, 0xFF, 0x01);
990*4882a593Smuzhiyun nvp6158_write(client, 0xCA, 0x00);
991*4882a593Smuzhiyun }
992*4882a593Smuzhiyun }
993*4882a593Smuzhiyun
nvp6158_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)994*4882a593Smuzhiyun static long nvp6158_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
995*4882a593Smuzhiyun {
996*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
997*4882a593Smuzhiyun long ret = 0;
998*4882a593Smuzhiyun u32 stream = 0;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun switch (cmd) {
1001*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1002*4882a593Smuzhiyun nvp6158_get_module_inf(nvp6158, (struct rkmodule_inf *)arg);
1003*4882a593Smuzhiyun break;
1004*4882a593Smuzhiyun case RKMODULE_GET_BT656_MBUS_INFO:
1005*4882a593Smuzhiyun nvp6158_get_bt656_module_inf(nvp6158,
1006*4882a593Smuzhiyun (struct rkmodule_bt656_mbus_info
1007*4882a593Smuzhiyun *)arg);
1008*4882a593Smuzhiyun break;
1009*4882a593Smuzhiyun case RKMODULE_GET_START_STREAM_SEQ:
1010*4882a593Smuzhiyun if ((nvp6158->mode > BT656_4MUX) &&
1011*4882a593Smuzhiyun (nvp6158->mode < NVP6158_DVP_MODES_END))
1012*4882a593Smuzhiyun *(int *)arg = RKMODULE_START_STREAM_FRONT;
1013*4882a593Smuzhiyun break;
1014*4882a593Smuzhiyun case RKMODULE_GET_VICAP_RST_INFO:
1015*4882a593Smuzhiyun nvp6158_get_vicap_rst_inf(nvp6158, (struct rkmodule_vicap_reset_info *)arg);
1016*4882a593Smuzhiyun break;
1017*4882a593Smuzhiyun case RKMODULE_SET_VICAP_RST_INFO:
1018*4882a593Smuzhiyun nvp6158_set_vicap_rst_inf(nvp6158, *(struct rkmodule_vicap_reset_info *)arg);
1019*4882a593Smuzhiyun break;
1020*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1021*4882a593Smuzhiyun stream = *((u32 *)arg);
1022*4882a593Smuzhiyun nvp6158_set_streaming(nvp6158, !!stream);
1023*4882a593Smuzhiyun break;
1024*4882a593Smuzhiyun default:
1025*4882a593Smuzhiyun ret = -ENOTTY;
1026*4882a593Smuzhiyun break;
1027*4882a593Smuzhiyun }
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun return ret;
1030*4882a593Smuzhiyun }
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
nvp6158_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)1033*4882a593Smuzhiyun static long nvp6158_compat_ioctl32(struct v4l2_subdev *sd,
1034*4882a593Smuzhiyun unsigned int cmd, unsigned long arg)
1035*4882a593Smuzhiyun {
1036*4882a593Smuzhiyun void __user *up = compat_ptr(arg);
1037*4882a593Smuzhiyun struct rkmodule_inf *inf;
1038*4882a593Smuzhiyun struct rkmodule_awb_cfg *cfg;
1039*4882a593Smuzhiyun long ret;
1040*4882a593Smuzhiyun struct rkmodule_bt656_mbus_info *bt565_inf;
1041*4882a593Smuzhiyun int *seq;
1042*4882a593Smuzhiyun struct rkmodule_vicap_reset_info *vicap_rst_inf;
1043*4882a593Smuzhiyun u32 stream = 0;
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun switch (cmd) {
1046*4882a593Smuzhiyun case RKMODULE_GET_MODULE_INFO:
1047*4882a593Smuzhiyun inf = kzalloc(sizeof(*inf), GFP_KERNEL);
1048*4882a593Smuzhiyun if (!inf) {
1049*4882a593Smuzhiyun ret = -ENOMEM;
1050*4882a593Smuzhiyun return ret;
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun ret = nvp6158_ioctl(sd, cmd, inf);
1054*4882a593Smuzhiyun if (!ret) {
1055*4882a593Smuzhiyun ret = copy_to_user(up, inf, sizeof(*inf));
1056*4882a593Smuzhiyun if (ret)
1057*4882a593Smuzhiyun ret = -EFAULT;
1058*4882a593Smuzhiyun }
1059*4882a593Smuzhiyun kfree(inf);
1060*4882a593Smuzhiyun break;
1061*4882a593Smuzhiyun case RKMODULE_AWB_CFG:
1062*4882a593Smuzhiyun cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1063*4882a593Smuzhiyun if (!cfg) {
1064*4882a593Smuzhiyun ret = -ENOMEM;
1065*4882a593Smuzhiyun return ret;
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun ret = copy_from_user(cfg, up, sizeof(*cfg));
1069*4882a593Smuzhiyun if (!ret)
1070*4882a593Smuzhiyun ret = nvp6158_ioctl(sd, cmd, cfg);
1071*4882a593Smuzhiyun else
1072*4882a593Smuzhiyun ret = -EFAULT;
1073*4882a593Smuzhiyun kfree(cfg);
1074*4882a593Smuzhiyun break;
1075*4882a593Smuzhiyun case RKMODULE_GET_BT656_MBUS_INFO:
1076*4882a593Smuzhiyun bt565_inf = kzalloc(sizeof(*bt565_inf), GFP_KERNEL);
1077*4882a593Smuzhiyun if (!bt565_inf) {
1078*4882a593Smuzhiyun ret = -ENOMEM;
1079*4882a593Smuzhiyun return ret;
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun ret = nvp6158_ioctl(sd, cmd, bt565_inf);
1083*4882a593Smuzhiyun if (!ret) {
1084*4882a593Smuzhiyun ret = copy_to_user(up, bt565_inf, sizeof(*bt565_inf));
1085*4882a593Smuzhiyun if (ret)
1086*4882a593Smuzhiyun ret = -EFAULT;
1087*4882a593Smuzhiyun }
1088*4882a593Smuzhiyun kfree(bt565_inf);
1089*4882a593Smuzhiyun break;
1090*4882a593Smuzhiyun case RKMODULE_GET_START_STREAM_SEQ:
1091*4882a593Smuzhiyun seq = kzalloc(sizeof(*seq), GFP_KERNEL);
1092*4882a593Smuzhiyun if (!seq) {
1093*4882a593Smuzhiyun ret = -ENOMEM;
1094*4882a593Smuzhiyun return ret;
1095*4882a593Smuzhiyun }
1096*4882a593Smuzhiyun ret = nvp6158_ioctl(sd, cmd, seq);
1097*4882a593Smuzhiyun if (!ret) {
1098*4882a593Smuzhiyun ret = copy_to_user(up, seq, sizeof(*seq));
1099*4882a593Smuzhiyun if (ret)
1100*4882a593Smuzhiyun ret = -EFAULT;
1101*4882a593Smuzhiyun }
1102*4882a593Smuzhiyun kfree(seq);
1103*4882a593Smuzhiyun break;
1104*4882a593Smuzhiyun case RKMODULE_GET_VICAP_RST_INFO:
1105*4882a593Smuzhiyun vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
1106*4882a593Smuzhiyun if (!vicap_rst_inf) {
1107*4882a593Smuzhiyun ret = -ENOMEM;
1108*4882a593Smuzhiyun return ret;
1109*4882a593Smuzhiyun }
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun ret = nvp6158_ioctl(sd, cmd, vicap_rst_inf);
1112*4882a593Smuzhiyun if (!ret) {
1113*4882a593Smuzhiyun ret = copy_to_user(up, vicap_rst_inf, sizeof(*vicap_rst_inf));
1114*4882a593Smuzhiyun if (ret)
1115*4882a593Smuzhiyun ret = -EFAULT;
1116*4882a593Smuzhiyun }
1117*4882a593Smuzhiyun kfree(vicap_rst_inf);
1118*4882a593Smuzhiyun break;
1119*4882a593Smuzhiyun case RKMODULE_SET_VICAP_RST_INFO:
1120*4882a593Smuzhiyun vicap_rst_inf = kzalloc(sizeof(*vicap_rst_inf), GFP_KERNEL);
1121*4882a593Smuzhiyun if (!vicap_rst_inf) {
1122*4882a593Smuzhiyun ret = -ENOMEM;
1123*4882a593Smuzhiyun return ret;
1124*4882a593Smuzhiyun }
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun ret = copy_from_user(vicap_rst_inf, up, sizeof(*vicap_rst_inf));
1127*4882a593Smuzhiyun if (!ret)
1128*4882a593Smuzhiyun ret = nvp6158_ioctl(sd, cmd, vicap_rst_inf);
1129*4882a593Smuzhiyun else
1130*4882a593Smuzhiyun ret = -EFAULT;
1131*4882a593Smuzhiyun kfree(vicap_rst_inf);
1132*4882a593Smuzhiyun break;
1133*4882a593Smuzhiyun case RKMODULE_SET_QUICK_STREAM:
1134*4882a593Smuzhiyun ret = copy_from_user(&stream, up, sizeof(u32));
1135*4882a593Smuzhiyun if (!ret)
1136*4882a593Smuzhiyun ret = nvp6158_ioctl(sd, cmd, &stream);
1137*4882a593Smuzhiyun else
1138*4882a593Smuzhiyun ret = -EFAULT;
1139*4882a593Smuzhiyun break;
1140*4882a593Smuzhiyun default:
1141*4882a593Smuzhiyun ret = -ENOIOCTLCMD;
1142*4882a593Smuzhiyun break;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun return ret;
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun #endif
1148*4882a593Smuzhiyun
nvp6158_runtime_resume(struct device * dev)1149*4882a593Smuzhiyun static int nvp6158_runtime_resume(struct device *dev)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1152*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1153*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
1154*4882a593Smuzhiyun
1155*4882a593Smuzhiyun return __nvp6158_power_on(nvp6158);
1156*4882a593Smuzhiyun }
1157*4882a593Smuzhiyun
nvp6158_runtime_suspend(struct device * dev)1158*4882a593Smuzhiyun static int nvp6158_runtime_suspend(struct device *dev)
1159*4882a593Smuzhiyun {
1160*4882a593Smuzhiyun struct i2c_client *client = to_i2c_client(dev);
1161*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1162*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun __nvp6158_power_off(nvp6158);
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun return 0;
1167*4882a593Smuzhiyun }
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun static const struct dev_pm_ops nvp6158_pm_ops = {
1170*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(nvp6158_runtime_suspend,
1171*4882a593Smuzhiyun nvp6158_runtime_resume, NULL)
1172*4882a593Smuzhiyun };
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops nvp6158_video_ops = {
1175*4882a593Smuzhiyun .s_stream = nvp6158_stream,
1176*4882a593Smuzhiyun .querystd = nvp6158_querystd,
1177*4882a593Smuzhiyun };
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops nvp6158_subdev_pad_ops = {
1180*4882a593Smuzhiyun .enum_mbus_code = nvp6158_enum_mbus_code,
1181*4882a593Smuzhiyun .enum_frame_size = nvp6158_enum_frame_sizes,
1182*4882a593Smuzhiyun .get_fmt = nvp6158_get_fmt,
1183*4882a593Smuzhiyun .set_fmt = nvp6158_set_fmt,
1184*4882a593Smuzhiyun .get_selection = nvp6158_get_selection,
1185*4882a593Smuzhiyun .enum_frame_interval = nvp6158_enum_frame_interval,
1186*4882a593Smuzhiyun .get_mbus_config = nvp6158_g_mbus_config,
1187*4882a593Smuzhiyun };
1188*4882a593Smuzhiyun
1189*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops nvp6158_core_ops = {
1190*4882a593Smuzhiyun .s_power = nvp6158_power,
1191*4882a593Smuzhiyun .ioctl = nvp6158_ioctl,
1192*4882a593Smuzhiyun #ifdef CONFIG_COMPAT
1193*4882a593Smuzhiyun .compat_ioctl32 = nvp6158_compat_ioctl32,
1194*4882a593Smuzhiyun #endif
1195*4882a593Smuzhiyun };
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun static const struct v4l2_subdev_ops nvp6158_subdev_ops = {
1198*4882a593Smuzhiyun .core = &nvp6158_core_ops,
1199*4882a593Smuzhiyun .video = &nvp6158_video_ops,
1200*4882a593Smuzhiyun .pad = &nvp6158_subdev_pad_ops,
1201*4882a593Smuzhiyun };
1202*4882a593Smuzhiyun
get_dvp_mode(struct nvp6158 * nvp6158)1203*4882a593Smuzhiyun static void get_dvp_mode(struct nvp6158 *nvp6158)
1204*4882a593Smuzhiyun {
1205*4882a593Smuzhiyun struct device *dev = &nvp6158->client->dev;
1206*4882a593Smuzhiyun char mode[128];
1207*4882a593Smuzhiyun u32 i;
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun sprintf(mode, "%s_%dMUX", nvp6158->dvp_mode, nvp6158->ch_nums);
1210*4882a593Smuzhiyun dev_info(dev, "combined dvp mode is(%s)\n", mode);
1211*4882a593Smuzhiyun for (i = 0; i < NVP6158_DVP_MODES_END; i++) {
1212*4882a593Smuzhiyun if (!strcmp(mode, nvp6158_dvp_mode_lists[i]))
1213*4882a593Smuzhiyun break;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun if (i < NVP6158_DVP_MODES_END)
1217*4882a593Smuzhiyun nvp6158->mode = i;
1218*4882a593Smuzhiyun else
1219*4882a593Smuzhiyun nvp6158->mode = BT656I_TEST_MODES;
1220*4882a593Smuzhiyun dev_info(dev, "get dvp mode (%s)\n", nvp6158_dvp_mode_lists[nvp6158->mode]);
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun
nvp6158_parse_dts(struct nvp6158 * nvp6158)1223*4882a593Smuzhiyun static int nvp6158_parse_dts(struct nvp6158 *nvp6158)
1224*4882a593Smuzhiyun {
1225*4882a593Smuzhiyun int ret;
1226*4882a593Smuzhiyun int elem_size, elem_index;
1227*4882a593Smuzhiyun const char *str = "";
1228*4882a593Smuzhiyun struct property *prop;
1229*4882a593Smuzhiyun struct nvp6158_regulator *regulator;
1230*4882a593Smuzhiyun struct device *dev = &nvp6158->client->dev;
1231*4882a593Smuzhiyun struct device_node *np = of_node_get(dev->of_node);
1232*4882a593Smuzhiyun
1233*4882a593Smuzhiyun nvp6158->xvclk = devm_clk_get(dev, "xvclk");
1234*4882a593Smuzhiyun if (IS_ERR(nvp6158->xvclk)) {
1235*4882a593Smuzhiyun dev_err(dev, "Failed to get xvclk\n");
1236*4882a593Smuzhiyun return -EINVAL;
1237*4882a593Smuzhiyun }
1238*4882a593Smuzhiyun ret = clk_set_rate(nvp6158->xvclk, NVP6158_XVCLK_FREQ);
1239*4882a593Smuzhiyun if (ret < 0) {
1240*4882a593Smuzhiyun dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
1241*4882a593Smuzhiyun return ret;
1242*4882a593Smuzhiyun }
1243*4882a593Smuzhiyun if (clk_get_rate(nvp6158->xvclk) != NVP6158_XVCLK_FREQ)
1244*4882a593Smuzhiyun dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
1245*4882a593Smuzhiyun
1246*4882a593Smuzhiyun nvp6158->pinctrl = devm_pinctrl_get(dev);
1247*4882a593Smuzhiyun if (!IS_ERR(nvp6158->pinctrl)) {
1248*4882a593Smuzhiyun nvp6158->pins_default =
1249*4882a593Smuzhiyun pinctrl_lookup_state(nvp6158->pinctrl,
1250*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_DEFAULT);
1251*4882a593Smuzhiyun if (IS_ERR(nvp6158->pins_default))
1252*4882a593Smuzhiyun dev_err(dev, "could not get default pinstate\n");
1253*4882a593Smuzhiyun
1254*4882a593Smuzhiyun nvp6158->pins_sleep =
1255*4882a593Smuzhiyun pinctrl_lookup_state(nvp6158->pinctrl,
1256*4882a593Smuzhiyun OF_CAMERA_PINCTRL_STATE_SLEEP);
1257*4882a593Smuzhiyun if (IS_ERR(nvp6158->pins_sleep))
1258*4882a593Smuzhiyun dev_err(dev, "could not get sleep pinstate\n");
1259*4882a593Smuzhiyun } else {
1260*4882a593Smuzhiyun dev_err(dev, "no pinctrl\n");
1261*4882a593Smuzhiyun }
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun elem_size = of_property_count_elems_of_size(
1264*4882a593Smuzhiyun np,
1265*4882a593Smuzhiyun OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
1266*4882a593Smuzhiyun sizeof(u32));
1267*4882a593Smuzhiyun prop = of_find_property(
1268*4882a593Smuzhiyun np,
1269*4882a593Smuzhiyun OF_CAMERA_MODULE_REGULATORS,
1270*4882a593Smuzhiyun NULL);
1271*4882a593Smuzhiyun if (elem_size > 0 && !IS_ERR_OR_NULL(prop)) {
1272*4882a593Smuzhiyun nvp6158->regulators.regulator =
1273*4882a593Smuzhiyun devm_kzalloc(&nvp6158->client->dev,
1274*4882a593Smuzhiyun elem_size * sizeof(struct nvp6158_regulator),
1275*4882a593Smuzhiyun GFP_KERNEL);
1276*4882a593Smuzhiyun if (!nvp6158->regulators.regulator)
1277*4882a593Smuzhiyun dev_err(dev, "could not malloc nvp6158_regulator\n");
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun nvp6158->regulators.cnt = elem_size;
1280*4882a593Smuzhiyun
1281*4882a593Smuzhiyun str = NULL;
1282*4882a593Smuzhiyun elem_index = 0;
1283*4882a593Smuzhiyun regulator = nvp6158->regulators.regulator;
1284*4882a593Smuzhiyun if (regulator) {
1285*4882a593Smuzhiyun do {
1286*4882a593Smuzhiyun str = of_prop_next_string(prop, str);
1287*4882a593Smuzhiyun if (!str) {
1288*4882a593Smuzhiyun dev_err(dev, "%s is not match %s in dts\n",
1289*4882a593Smuzhiyun OF_CAMERA_MODULE_REGULATORS,
1290*4882a593Smuzhiyun OF_CAMERA_MODULE_REGULATOR_VOLTAGES);
1291*4882a593Smuzhiyun break;
1292*4882a593Smuzhiyun }
1293*4882a593Smuzhiyun regulator->regulator =
1294*4882a593Smuzhiyun devm_regulator_get_optional(dev, str);
1295*4882a593Smuzhiyun if (IS_ERR(regulator->regulator))
1296*4882a593Smuzhiyun dev_err(dev, "devm_regulator_get %s failed\n",
1297*4882a593Smuzhiyun str);
1298*4882a593Smuzhiyun of_property_read_u32_index(
1299*4882a593Smuzhiyun np,
1300*4882a593Smuzhiyun OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
1301*4882a593Smuzhiyun elem_index++,
1302*4882a593Smuzhiyun ®ulator->min_uV);
1303*4882a593Smuzhiyun regulator->max_uV = regulator->min_uV;
1304*4882a593Smuzhiyun regulator++;
1305*4882a593Smuzhiyun } while (--elem_size);
1306*4882a593Smuzhiyun }
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun if (of_property_read_string(np,
1310*4882a593Smuzhiyun RK_CAMERA_MODULE_DVP_MODE,
1311*4882a593Smuzhiyun &nvp6158->dvp_mode)) {
1312*4882a593Smuzhiyun nvp6158->dvp_mode = NVP6158_DEFAULT_DVP_MODE;
1313*4882a593Smuzhiyun dev_warn(dev,
1314*4882a593Smuzhiyun "can not get module %s from dts, use default(%s)!\n",
1315*4882a593Smuzhiyun RK_CAMERA_MODULE_DVP_MODE,
1316*4882a593Smuzhiyun NVP6158_DEFAULT_DVP_MODE);
1317*4882a593Smuzhiyun } else {
1318*4882a593Smuzhiyun dev_info(dev,
1319*4882a593Smuzhiyun "get module %s from dts, dvp mode(%s)!\n",
1320*4882a593Smuzhiyun RK_CAMERA_MODULE_DVP_MODE, nvp6158->dvp_mode);
1321*4882a593Smuzhiyun }
1322*4882a593Smuzhiyun
1323*4882a593Smuzhiyun if (of_property_read_u32(np,
1324*4882a593Smuzhiyun RK_CAMERA_MODULE_CHANNEL_NUMS,
1325*4882a593Smuzhiyun &nvp6158->ch_nums)) {
1326*4882a593Smuzhiyun nvp6158->ch_nums = NVP6158_DEFAULT_CHANNEL_NUMS;
1327*4882a593Smuzhiyun dev_warn(dev,
1328*4882a593Smuzhiyun "can not get module %s from dts, use default(%d)!\n",
1329*4882a593Smuzhiyun RK_CAMERA_MODULE_CHANNEL_NUMS,
1330*4882a593Smuzhiyun NVP6158_DEFAULT_CHANNEL_NUMS);
1331*4882a593Smuzhiyun } else {
1332*4882a593Smuzhiyun dev_info(dev,
1333*4882a593Smuzhiyun "get module %s from dts, channel_nums(%d)!\n",
1334*4882a593Smuzhiyun RK_CAMERA_MODULE_DVP_MODE, nvp6158->ch_nums);
1335*4882a593Smuzhiyun }
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun if (of_property_read_u32(np,
1338*4882a593Smuzhiyun RK_CAMERA_MODULE_DUAL_EDGE,
1339*4882a593Smuzhiyun &nvp6158->dual_edge)) {
1340*4882a593Smuzhiyun nvp6158->dual_edge = NVP6158_DEFAULT_DUAL_EDGE;
1341*4882a593Smuzhiyun dev_warn(dev,
1342*4882a593Smuzhiyun "can not get module %s from dts, use default(%d)!\n",
1343*4882a593Smuzhiyun RK_CAMERA_MODULE_DUAL_EDGE,
1344*4882a593Smuzhiyun NVP6158_DEFAULT_DUAL_EDGE);
1345*4882a593Smuzhiyun } else {
1346*4882a593Smuzhiyun dev_info(dev,
1347*4882a593Smuzhiyun "get module %s from dts, dual_edge(%d)!\n",
1348*4882a593Smuzhiyun RK_CAMERA_MODULE_DUAL_EDGE, nvp6158->dual_edge);
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun if (of_property_read_u32_array(np,
1354*4882a593Smuzhiyun RK_CAMERA_MODULE_DEFAULT_RECT,
1355*4882a593Smuzhiyun (unsigned int *)&nvp6158->defrect, 2)) {
1356*4882a593Smuzhiyun nvp6158->defrect.width = NVP6158_DEFAULT_WIDTH;
1357*4882a593Smuzhiyun nvp6158->defrect.height = NVP6158_DEFAULT_HEIGHT;
1358*4882a593Smuzhiyun dev_warn(dev,
1359*4882a593Smuzhiyun "can not get module %s from dts, use default wxh(%dx%d)!\n",
1360*4882a593Smuzhiyun RK_CAMERA_MODULE_DEFAULT_RECT,
1361*4882a593Smuzhiyun NVP6158_DEFAULT_WIDTH, NVP6158_DEFAULT_HEIGHT);
1362*4882a593Smuzhiyun } else {
1363*4882a593Smuzhiyun dev_info(dev,
1364*4882a593Smuzhiyun "get module %s from dts, wxh(%dx%d)!\n",
1365*4882a593Smuzhiyun RK_CAMERA_MODULE_DEFAULT_RECT,
1366*4882a593Smuzhiyun nvp6158->defrect.width,
1367*4882a593Smuzhiyun nvp6158->defrect.height);
1368*4882a593Smuzhiyun }
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun /* AHD_PWR_EN */
1371*4882a593Smuzhiyun nvp6158->pwr_gpio = devm_gpiod_get(dev, "pwr", GPIOD_OUT_LOW);
1372*4882a593Smuzhiyun if (IS_ERR(nvp6158->pwr_gpio))
1373*4882a593Smuzhiyun dev_warn(dev, "can not find pd-gpios, error %ld\n",
1374*4882a593Smuzhiyun PTR_ERR(nvp6158->pwr_gpio));
1375*4882a593Smuzhiyun /* AHD CAM_PWR_EN*/
1376*4882a593Smuzhiyun nvp6158->pwr2_gpio = devm_gpiod_get(dev, "pwr2", GPIOD_OUT_LOW);
1377*4882a593Smuzhiyun if (IS_ERR(nvp6158->pwr2_gpio))
1378*4882a593Smuzhiyun dev_warn(dev, "can not find pd2-gpios, error %ld\n",
1379*4882a593Smuzhiyun PTR_ERR(nvp6158->pwr2_gpio));
1380*4882a593Smuzhiyun
1381*4882a593Smuzhiyun nvp6158->rst_gpio = devm_gpiod_get(dev, "rst", GPIOD_OUT_LOW);
1382*4882a593Smuzhiyun if (IS_ERR(nvp6158->rst_gpio))
1383*4882a593Smuzhiyun dev_warn(dev, "can not find rst-gpios, error %ld\n",
1384*4882a593Smuzhiyun PTR_ERR(nvp6158->rst_gpio));
1385*4882a593Smuzhiyun
1386*4882a593Smuzhiyun nvp6158->rst2_gpio = devm_gpiod_get(dev, "rst2", GPIOD_OUT_LOW);
1387*4882a593Smuzhiyun if (IS_ERR(nvp6158->rst2_gpio))
1388*4882a593Smuzhiyun dev_warn(dev, "can not find rst2-gpios, error %ld\n",
1389*4882a593Smuzhiyun PTR_ERR(nvp6158->rst2_gpio));
1390*4882a593Smuzhiyun
1391*4882a593Smuzhiyun nvp6158->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
1392*4882a593Smuzhiyun if (IS_ERR(nvp6158->pwdn_gpio))
1393*4882a593Smuzhiyun dev_warn(dev, "can not find pwd-gpios, error %ld\n",
1394*4882a593Smuzhiyun PTR_ERR(nvp6158->pwdn_gpio));
1395*4882a593Smuzhiyun
1396*4882a593Smuzhiyun nvp6158->pwdn2_gpio = devm_gpiod_get(dev, "pwdn2", GPIOD_OUT_LOW);
1397*4882a593Smuzhiyun if (IS_ERR(nvp6158->pwdn2_gpio))
1398*4882a593Smuzhiyun dev_warn(dev, "can not find pwd2-gpios, error %ld\n",
1399*4882a593Smuzhiyun PTR_ERR(nvp6158->pwdn2_gpio));
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun return 0;
1402*4882a593Smuzhiyun }
1403*4882a593Smuzhiyun
1404*4882a593Smuzhiyun
nvp6158_probe(struct i2c_client * client,const struct i2c_device_id * id)1405*4882a593Smuzhiyun static int nvp6158_probe(struct i2c_client *client,
1406*4882a593Smuzhiyun const struct i2c_device_id *id)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun struct device *dev = &client->dev;
1409*4882a593Smuzhiyun struct device_node *node = dev->of_node;
1410*4882a593Smuzhiyun struct nvp6158 *nvp6158;
1411*4882a593Smuzhiyun struct v4l2_subdev *sd;
1412*4882a593Smuzhiyun __maybe_unused char facing[2];
1413*4882a593Smuzhiyun int ret, index;
1414*4882a593Smuzhiyun
1415*4882a593Smuzhiyun dev_info(dev, "driver version: %02x.%02x.%02x",
1416*4882a593Smuzhiyun DRIVER_VERSION >> 16,
1417*4882a593Smuzhiyun (DRIVER_VERSION & 0xff00) >> 8,
1418*4882a593Smuzhiyun DRIVER_VERSION & 0x00ff);
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun nvp6158 = devm_kzalloc(dev, sizeof(*nvp6158), GFP_KERNEL);
1421*4882a593Smuzhiyun if (!nvp6158)
1422*4882a593Smuzhiyun return -ENOMEM;
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1425*4882a593Smuzhiyun &nvp6158->module_index);
1426*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1427*4882a593Smuzhiyun &nvp6158->module_facing);
1428*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1429*4882a593Smuzhiyun &nvp6158->module_name);
1430*4882a593Smuzhiyun ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1431*4882a593Smuzhiyun &nvp6158->len_name);
1432*4882a593Smuzhiyun if (ret) {
1433*4882a593Smuzhiyun dev_err(dev, "could not get %s!\n", RKMODULE_CAMERA_LENS_NAME);
1434*4882a593Smuzhiyun return -EINVAL;
1435*4882a593Smuzhiyun }
1436*4882a593Smuzhiyun
1437*4882a593Smuzhiyun nvp6158->client = client;
1438*4882a593Smuzhiyun
1439*4882a593Smuzhiyun ret = nvp6158_parse_dts(nvp6158);
1440*4882a593Smuzhiyun if (ret) {
1441*4882a593Smuzhiyun dev_err(dev, "Failed to analyze dts\n");
1442*4882a593Smuzhiyun return ret;
1443*4882a593Smuzhiyun }
1444*4882a593Smuzhiyun get_dvp_mode(nvp6158);
1445*4882a593Smuzhiyun
1446*4882a593Smuzhiyun mutex_init(&nvp6158->mutex);
1447*4882a593Smuzhiyun nvp6158_get_default_format(nvp6158);
1448*4882a593Smuzhiyun
1449*4882a593Smuzhiyun sd = &nvp6158->subdev;
1450*4882a593Smuzhiyun v4l2_i2c_subdev_init(sd, client, &nvp6158_subdev_ops);
1451*4882a593Smuzhiyun ret = nvp6158_initialize_controls(nvp6158);
1452*4882a593Smuzhiyun if (ret)
1453*4882a593Smuzhiyun goto err_destroy_mutex;
1454*4882a593Smuzhiyun
1455*4882a593Smuzhiyun __nvp6158_power_on(nvp6158);
1456*4882a593Smuzhiyun ret = nvp6158_init(i2c_adapter_id(client->adapter));
1457*4882a593Smuzhiyun if (ret) {
1458*4882a593Smuzhiyun dev_err(dev, "Failed to init nvp6158\n");
1459*4882a593Smuzhiyun goto err_power_off;
1460*4882a593Smuzhiyun }
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1463*4882a593Smuzhiyun sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1464*4882a593Smuzhiyun #endif
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1467*4882a593Smuzhiyun for (index = 0; index < nvp6158->ch_nums; index++)
1468*4882a593Smuzhiyun nvp6158->pad[index].flags = MEDIA_PAD_FL_SOURCE;
1469*4882a593Smuzhiyun sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1470*4882a593Smuzhiyun ret = media_entity_pads_init(&sd->entity, nvp6158->ch_nums, nvp6158->pad);
1471*4882a593Smuzhiyun if (ret < 0)
1472*4882a593Smuzhiyun goto err_power_off;
1473*4882a593Smuzhiyun #endif
1474*4882a593Smuzhiyun
1475*4882a593Smuzhiyun memset(facing, 0, sizeof(facing));
1476*4882a593Smuzhiyun if (strcmp(nvp6158->module_facing, "back") == 0)
1477*4882a593Smuzhiyun facing[0] = 'b';
1478*4882a593Smuzhiyun else
1479*4882a593Smuzhiyun facing[0] = 'f';
1480*4882a593Smuzhiyun
1481*4882a593Smuzhiyun snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1482*4882a593Smuzhiyun nvp6158->module_index, facing,
1483*4882a593Smuzhiyun NVP6158_NAME, dev_name(sd->dev));
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun ret = v4l2_async_register_subdev_sensor_common(sd);
1486*4882a593Smuzhiyun if (ret) {
1487*4882a593Smuzhiyun dev_err(dev, "v4l2 async register subdev failed\n");
1488*4882a593Smuzhiyun goto err_clean_entity;
1489*4882a593Smuzhiyun }
1490*4882a593Smuzhiyun pm_runtime_set_active(dev);
1491*4882a593Smuzhiyun pm_runtime_enable(dev);
1492*4882a593Smuzhiyun pm_runtime_idle(dev);
1493*4882a593Smuzhiyun #ifdef WORK_QUEUE
1494*4882a593Smuzhiyun /* init work_queue for state_check */
1495*4882a593Smuzhiyun INIT_DELAYED_WORK(&nvp6158->plug_state_check.d_work, nvp6158_plug_state_check_work);
1496*4882a593Smuzhiyun nvp6158->plug_state_check.state_check_wq =
1497*4882a593Smuzhiyun create_singlethread_workqueue("nvp6158_work_queue");
1498*4882a593Smuzhiyun if (nvp6158->plug_state_check.state_check_wq == NULL) {
1499*4882a593Smuzhiyun dev_err(dev, "%s(%d): %s create failed.\n", __func__, __LINE__,
1500*4882a593Smuzhiyun "nvp6158_work_queue");
1501*4882a593Smuzhiyun }
1502*4882a593Smuzhiyun nvp6158->cur_detect_status = 0x0;
1503*4882a593Smuzhiyun nvp6158->last_detect_status = 0x0;
1504*4882a593Smuzhiyun nvp6158->hot_plug = false;
1505*4882a593Smuzhiyun nvp6158->is_reset = 0;
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun #endif
1508*4882a593Smuzhiyun return 0;
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun err_clean_entity:
1511*4882a593Smuzhiyun #if defined(CONFIG_MEDIA_CONTROLLER)
1512*4882a593Smuzhiyun media_entity_cleanup(&sd->entity);
1513*4882a593Smuzhiyun #endif
1514*4882a593Smuzhiyun err_power_off:
1515*4882a593Smuzhiyun __nvp6158_power_off(nvp6158);
1516*4882a593Smuzhiyun err_destroy_mutex:
1517*4882a593Smuzhiyun mutex_destroy(&nvp6158->mutex);
1518*4882a593Smuzhiyun
1519*4882a593Smuzhiyun return ret;
1520*4882a593Smuzhiyun }
1521*4882a593Smuzhiyun
nvp6158_remove(struct i2c_client * client)1522*4882a593Smuzhiyun static int nvp6158_remove(struct i2c_client *client)
1523*4882a593Smuzhiyun {
1524*4882a593Smuzhiyun struct v4l2_subdev *sd = i2c_get_clientdata(client);
1525*4882a593Smuzhiyun struct nvp6158 *nvp6158 = to_nvp6158(sd);
1526*4882a593Smuzhiyun
1527*4882a593Smuzhiyun nvp6158_exit();
1528*4882a593Smuzhiyun v4l2_ctrl_handler_free(&nvp6158->ctrl_handler);
1529*4882a593Smuzhiyun mutex_destroy(&nvp6158->mutex);
1530*4882a593Smuzhiyun
1531*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1532*4882a593Smuzhiyun if (!pm_runtime_status_suspended(&client->dev))
1533*4882a593Smuzhiyun __nvp6158_power_off(nvp6158);
1534*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1535*4882a593Smuzhiyun #ifdef WORK_QUEUE
1536*4882a593Smuzhiyun if (nvp6158->plug_state_check.state_check_wq != NULL)
1537*4882a593Smuzhiyun destroy_workqueue(nvp6158->plug_state_check.state_check_wq);
1538*4882a593Smuzhiyun #endif
1539*4882a593Smuzhiyun return 0;
1540*4882a593Smuzhiyun }
1541*4882a593Smuzhiyun
1542*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
1543*4882a593Smuzhiyun static const struct of_device_id nvp6158_of_match[] = {
1544*4882a593Smuzhiyun { .compatible = "nvp6158-v4l2" },
1545*4882a593Smuzhiyun {},
1546*4882a593Smuzhiyun };
1547*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, nvp6158_of_match);
1548*4882a593Smuzhiyun #endif
1549*4882a593Smuzhiyun
1550*4882a593Smuzhiyun static const struct i2c_device_id nvp6158_match_id[] = {
1551*4882a593Smuzhiyun { "nvp6158-v4l2", 0 },
1552*4882a593Smuzhiyun { },
1553*4882a593Smuzhiyun };
1554*4882a593Smuzhiyun
1555*4882a593Smuzhiyun static struct i2c_driver nvp6158_i2c_driver = {
1556*4882a593Smuzhiyun .driver = {
1557*4882a593Smuzhiyun .name = NVP6158_NAME,
1558*4882a593Smuzhiyun .pm = &nvp6158_pm_ops,
1559*4882a593Smuzhiyun .of_match_table = of_match_ptr(nvp6158_of_match),
1560*4882a593Smuzhiyun },
1561*4882a593Smuzhiyun .probe = &nvp6158_probe,
1562*4882a593Smuzhiyun .remove = &nvp6158_remove,
1563*4882a593Smuzhiyun .id_table = nvp6158_match_id,
1564*4882a593Smuzhiyun };
1565*4882a593Smuzhiyun
sensor_mod_init(void)1566*4882a593Smuzhiyun static int __init sensor_mod_init(void)
1567*4882a593Smuzhiyun {
1568*4882a593Smuzhiyun return i2c_add_driver(&nvp6158_i2c_driver);
1569*4882a593Smuzhiyun }
1570*4882a593Smuzhiyun
sensor_mod_exit(void)1571*4882a593Smuzhiyun static void __exit sensor_mod_exit(void)
1572*4882a593Smuzhiyun {
1573*4882a593Smuzhiyun i2c_del_driver(&nvp6158_i2c_driver);
1574*4882a593Smuzhiyun }
1575*4882a593Smuzhiyun
1576*4882a593Smuzhiyun device_initcall_sync(sensor_mod_init);
1577*4882a593Smuzhiyun module_exit(sensor_mod_exit);
1578*4882a593Smuzhiyun
1579*4882a593Smuzhiyun MODULE_DESCRIPTION("nvp6158 sensor driver");
1580*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1581