xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/nvp6158_drv/nvp6158_drv.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /********************************************************************************
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun *  Copyright (C) 2017 	NEXTCHIP Inc. All rights reserved.
5*4882a593Smuzhiyun *  Copyright (c) 2021 	Rockchip Electronics Co. Ltd.All rights reserved.
6*4882a593Smuzhiyun *  Module		: install driver main
7*4882a593Smuzhiyun *  Description	: driver main
8*4882a593Smuzhiyun *  Author		:
9*4882a593Smuzhiyun *  Date         :
10*4882a593Smuzhiyun *  Version		: Version 2.0
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun ********************************************************************************
13*4882a593Smuzhiyun *  History      :
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun ********************************************************************************/
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/version.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/types.h>
21*4882a593Smuzhiyun #include <linux/errno.h>
22*4882a593Smuzhiyun #include <linux/fcntl.h>
23*4882a593Smuzhiyun #include <linux/mm.h>
24*4882a593Smuzhiyun #include <linux/proc_fs.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #ifndef CONFIG_HISI_SNAPSHOT_BOOT
27*4882a593Smuzhiyun #include <linux/miscdevice.h>
28*4882a593Smuzhiyun #endif
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #include <linux/fs.h>
31*4882a593Smuzhiyun #include <linux/slab.h>
32*4882a593Smuzhiyun #include <linux/init.h>
33*4882a593Smuzhiyun #include <linux/uaccess.h>
34*4882a593Smuzhiyun #include <asm/io.h>
35*4882a593Smuzhiyun //#include <asm/system.h>
36*4882a593Smuzhiyun #include <linux/interrupt.h>
37*4882a593Smuzhiyun #include <linux/ioport.h>
38*4882a593Smuzhiyun #include <linux/string.h>
39*4882a593Smuzhiyun #include <linux/list.h>
40*4882a593Smuzhiyun #include <asm/delay.h>
41*4882a593Smuzhiyun #include <linux/timer.h>
42*4882a593Smuzhiyun #include <linux/delay.h>
43*4882a593Smuzhiyun #include <linux/proc_fs.h>
44*4882a593Smuzhiyun #include <linux/poll.h>
45*4882a593Smuzhiyun #include <asm/bitops.h>
46*4882a593Smuzhiyun #include <linux/uaccess.h>
47*4882a593Smuzhiyun #include <asm/irq.h>
48*4882a593Smuzhiyun #include <linux/moduleparam.h>
49*4882a593Smuzhiyun #include <linux/ioport.h>
50*4882a593Smuzhiyun #include <linux/interrupt.h>
51*4882a593Smuzhiyun #include <linux/semaphore.h>
52*4882a593Smuzhiyun #include <linux/kthread.h>
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #include <linux/i2c.h>
55*4882a593Smuzhiyun #include <linux/i2c-dev.h>
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun //#include "gpio_i2c.h"
58*4882a593Smuzhiyun #include "nvp6158_video.h"
59*4882a593Smuzhiyun #include "nvp6158_coax_protocol.h"
60*4882a593Smuzhiyun #include "nvp6158_motion.h"
61*4882a593Smuzhiyun #include "nvp6158_common.h"
62*4882a593Smuzhiyun #include "nvp6158_audio.h"
63*4882a593Smuzhiyun #include "nvp6158_video_auto_detect.h"
64*4882a593Smuzhiyun //#include "acp_firmup.h"
65*4882a593Smuzhiyun #include "nvp6158_video_eq.h"
66*4882a593Smuzhiyun #include "nvp6158_drv.h"
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun //#define STREAM_ON_DEFLAULT
69*4882a593Smuzhiyun /*BT601 is not used by Nextchip */
70*4882a593Smuzhiyun //#define BT601
71*4882a593Smuzhiyun #define BT1120
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define AF_CNT	1
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #ifdef CONFIG_HISI_SNAPSHOT_BOOT
76*4882a593Smuzhiyun #include "himedia.h"
77*4882a593Smuzhiyun #define DEV_NAME "nvp6158"
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static struct i2c_board_info nvp6158_hi_info =
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun     I2C_BOARD_INFO("nvp6158", 0x60),
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun static bool nvp6158_init_state;
85*4882a593Smuzhiyun unsigned int nvp6158_gCoaxFirmUpdateFlag[16] = {0,};
86*4882a593Smuzhiyun unsigned char nvp6158_det_mode[16] = {NVP6158_DET_MODE_AUTO,};
87*4882a593Smuzhiyun struct semaphore nvp6158_lock;
88*4882a593Smuzhiyun extern unsigned char nvp6158_ch_mode_status[16];
89*4882a593Smuzhiyun extern unsigned char nvp6158_ch_vfmt_status[16];
90*4882a593Smuzhiyun extern unsigned char nvp6158_acp_isp_wr_en[16];
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define NVP6158_DRIVER_VER "1.1.01"
93*4882a593Smuzhiyun #define NVP6158_HW_REG(reg)         *((volatile unsigned int *)(reg))
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun int nvp6158_g_soc_chiptype = 0x3521;
96*4882a593Smuzhiyun int nvp6158_chip_id[4];
97*4882a593Smuzhiyun int nvp6158_rev_id[4];
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun unsigned int nvp6158_cnt = 0;
100*4882a593Smuzhiyun unsigned int nvp6158_iic_addr[4] = {0x60, 0x62, 0x64, 0x66};
101*4882a593Smuzhiyun struct i2c_client* nvp6158_client;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /*******************************************************************************
104*4882a593Smuzhiyun *	Description		: Get rev ID
105*4882a593Smuzhiyun *	Argurments		: dec(slave address)
106*4882a593Smuzhiyun *	Return value	: rev ID
107*4882a593Smuzhiyun *	Modify			:
108*4882a593Smuzhiyun *	warning			:
109*4882a593Smuzhiyun *******************************************************************************/
nvp6158_check_rev(unsigned int dec)110*4882a593Smuzhiyun static int nvp6158_check_rev(unsigned int dec)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun 	int ret;
113*4882a593Smuzhiyun 	gpio_i2c_write(dec, 0xFF, 0x00);
114*4882a593Smuzhiyun 	ret = gpio_i2c_read(dec, 0xf5);
115*4882a593Smuzhiyun 	return ret;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /*******************************************************************************
119*4882a593Smuzhiyun *	Description		: Get Device ID
120*4882a593Smuzhiyun *	Argurments		: dec(slave address)
121*4882a593Smuzhiyun *	Return value	: Device ID
122*4882a593Smuzhiyun *	Modify			:
123*4882a593Smuzhiyun *	warning			:
124*4882a593Smuzhiyun *******************************************************************************/
nvp6158_check_id(unsigned int dec)125*4882a593Smuzhiyun static int nvp6158_check_id(unsigned int dec)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	int ret;
128*4882a593Smuzhiyun 	gpio_i2c_write(dec, 0xFF, 0x00);
129*4882a593Smuzhiyun 	ret = gpio_i2c_read(dec, 0xf4);
130*4882a593Smuzhiyun 	return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun /*******************************************************************************
134*4882a593Smuzhiyun  *	Description		: Check decoder count
135*4882a593Smuzhiyun  *	Argurments		: void
136*4882a593Smuzhiyun  *	Return value	: (total chip count - 1) or -1(not found any chip)
137*4882a593Smuzhiyun  *	Modify			:
138*4882a593Smuzhiyun  *	warning			:
139*4882a593Smuzhiyun  *******************************************************************************/
nvp6158_check_decoder_count(void)140*4882a593Smuzhiyun static int nvp6158_check_decoder_count(void)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	int chip;
143*4882a593Smuzhiyun 	int ret = -1;
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun     /* check Device ID of maxium 4chip on the slave address,
146*4882a593Smuzhiyun      * manage slave address. chip count. */
147*4882a593Smuzhiyun 	for(chip = 0; chip < 4; chip ++) {
148*4882a593Smuzhiyun 		nvp6158_chip_id[chip] = nvp6158_check_id(nvp6158_iic_addr[chip]);
149*4882a593Smuzhiyun 		nvp6158_rev_id[chip]  = nvp6158_check_rev(nvp6158_iic_addr[chip]);
150*4882a593Smuzhiyun 		if( (nvp6158_chip_id[chip] != NVP6158_R0_ID ) && (nvp6158_chip_id[chip] != NVP6158C_R0_ID) &&
151*4882a593Smuzhiyun 			(nvp6158_chip_id[chip] != NVP6168_R0_ID ) && (nvp6158_chip_id[chip] != NVP6168C_R0_ID)) {
152*4882a593Smuzhiyun 			printk("[NVP6158_DRV]Device ID Error... 0x%x\n", nvp6158_chip_id[chip]);
153*4882a593Smuzhiyun 		} else {
154*4882a593Smuzhiyun 			printk("[NVP6158_DRV]Device (0x%x) ID OK... 0x%x\n", nvp6158_iic_addr[chip], nvp6158_chip_id[chip]);
155*4882a593Smuzhiyun 			printk("[NVP6158_DRV]Device (0x%x) REV ... 0x%x\n", nvp6158_iic_addr[chip], nvp6158_rev_id[chip]);
156*4882a593Smuzhiyun 			nvp6158_iic_addr[nvp6158_cnt] = nvp6158_iic_addr[chip];
157*4882a593Smuzhiyun 			if(nvp6158_cnt<chip)
158*4882a593Smuzhiyun 				nvp6158_iic_addr[chip] = 0xFF;
159*4882a593Smuzhiyun 			nvp6158_chip_id[nvp6158_cnt] = nvp6158_chip_id[chip];
160*4882a593Smuzhiyun 			nvp6158_rev_id[nvp6158_cnt]  = nvp6158_rev_id[chip];
161*4882a593Smuzhiyun 			nvp6158_cnt++;
162*4882a593Smuzhiyun 		}
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	printk("[NVP6158_DRV]Chip Count = %d\n", nvp6158_cnt);
166*4882a593Smuzhiyun 	printk("[NVP6158_DRV]Address [0x%x][0x%x][0x%x][0x%x]\n", nvp6158_iic_addr[0],
167*4882a593Smuzhiyun 			nvp6158_iic_addr[1], nvp6158_iic_addr[2], nvp6158_iic_addr[3]);
168*4882a593Smuzhiyun 	printk("[NVP6158_DRV]Chip Id [0x%x][0x%x][0x%x][0x%x]\n", nvp6158_chip_id[0],
169*4882a593Smuzhiyun 			nvp6158_chip_id[1], nvp6158_chip_id[2], nvp6158_chip_id[3]);
170*4882a593Smuzhiyun 	printk("[NVP6158_DRV]Rev Id [0x%x][0x%x][0x%x][0x%x]\n", nvp6158_rev_id[0],
171*4882a593Smuzhiyun 			nvp6158_rev_id[1], nvp6158_rev_id[2], nvp6158_rev_id[3]);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	ret = nvp6158_cnt;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	return ret;
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun /*******************************************************************************
179*4882a593Smuzhiyun  *	Description		: Video decoder initial
180*4882a593Smuzhiyun  *	Argurments		: void
181*4882a593Smuzhiyun  *	Return value	: void
182*4882a593Smuzhiyun  *	Modify			:
183*4882a593Smuzhiyun  *	warning			:
184*4882a593Smuzhiyun  *******************************************************************************/
nvp6158_video_decoder_init(void)185*4882a593Smuzhiyun static void nvp6158_video_decoder_init(void)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	int chip = 0;
188*4882a593Smuzhiyun 	unsigned char ch = 0;
189*4882a593Smuzhiyun 	video_input_auto_detect vin_auto_det;
190*4882a593Smuzhiyun #ifdef _NVP6168_USE_MANUAL_MODE_
191*4882a593Smuzhiyun 	video_input_manual_mode vin_manual_det;
192*4882a593Smuzhiyun #endif
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
195*4882a593Smuzhiyun 	/* initialize common value of AHD */
196*4882a593Smuzhiyun 	for(chip = 0; chip < nvp6158_cnt; chip++) {
197*4882a593Smuzhiyun 		nvp6158_common_init(chip);
198*4882a593Smuzhiyun 		if(nvp6158_chip_id[chip] == NVP6158C_R0_ID || nvp6158_chip_id[chip] == NVP6158_R0_ID) {
199*4882a593Smuzhiyun 			nvp6158_additional_for3MoverDef(chip);
200*4882a593Smuzhiyun 		} else {
201*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x01 );
202*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x97, 0x00); // CH_RST ON
203*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x97, 0x0f); // CH_RST OFF
204*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x7a, 0x0f); // Clock Auto ON
205*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xca, 0xff); // VCLK_EN, VDO_EN
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 			for(ch = 0; ch < 4; ch++) {
208*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x05 + ch);
209*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x00, 0xd0);
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x05, 0x04);
212*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x08, 0x55);
213*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x47, 0xEE);
214*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x59, 0x00);
215*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x76, 0x00);
216*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x77, 0x80);
217*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0x00);
218*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x79, 0x11);
219*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0xB8, 0xB8); // H_PLL_BYPASS
220*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x7B, 0x11); // v_rst_on
221*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0xb9, 0x72);
222*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0xB8, 0xB8); // No Video Set
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x00);
225*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x00+ch, 0x10);
226*4882a593Smuzhiyun 				gpio_i2c_write(nvp6158_iic_addr[chip], 0x22+(ch*0x04), 0x0b);
227*4882a593Smuzhiyun 			}
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x13);
230*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x12, 0x04);
231*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x2E, 0x10);
232*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x30, 0x00);
233*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x77, 0xff);
234*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x3a, 0xff);
235*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x3b, 0xff);
236*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x3c, 0xff);
237*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x3d, 0xff);
238*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x3e, 0xff);
239*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x3f, 0x0f);
240*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x70, 0x00);
241*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x72, 0x05);
242*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x7A, 0xf0);
243*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x61, 0x03);
244*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x62, 0x00);
245*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x63, 0x03);
246*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x64, 0x00);
247*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x65, 0x03);
248*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x66, 0x00);
249*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x67, 0x03);
250*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x68, 0x00);
251*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x60, 0x0f);
252*4882a593Smuzhiyun //				gpio_i2c_write(nvp6158_iic_addr[chip], 0x60, 0x00);
253*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x07, 0x47);
254*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x59, 0x24);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 			/* SAM Range */
257*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x74, 0x00);
258*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x76, 0x00);
259*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x78, 0x00);
260*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x75, 0xff);
261*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x77, 0xff);
262*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x79, 0xff);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x01, 0x0c);
265*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x2f, 0xc8);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 			// EQ Stage Get
268*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x73, 0x23);
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x09);
271*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x96, 0x03);
272*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xB6, 0x03);
273*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xD6, 0x03);
274*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xF6, 0x03);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 			/********************************************************
277*4882a593Smuzhiyun 			 * Audio Default Setting
278*4882a593Smuzhiyun 			 ********************************************************/
279*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0xff, 0x01);
280*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x05, 0x09);
281*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x58, 0x02);
282*4882a593Smuzhiyun 			gpio_i2c_write(nvp6158_iic_addr[chip], 0x59, 0x00);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 		}
285*4882a593Smuzhiyun 	}
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
288*4882a593Smuzhiyun 		nvp6158_det_mode[ch] = NVP6158_DET_MODE_AUTO;
289*4882a593Smuzhiyun 		vin_auto_det.ch = ch % 4;
290*4882a593Smuzhiyun 		vin_auto_det.devnum = ch / 4;
291*4882a593Smuzhiyun 	#ifdef _NVP6168_USE_MANUAL_MODE_
292*4882a593Smuzhiyun 		vin_manual_det.ch = ch % 4;
293*4882a593Smuzhiyun 		vin_manual_det.dev_num = ch / 4;
294*4882a593Smuzhiyun 	#endif
295*4882a593Smuzhiyun 		if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID) {
296*4882a593Smuzhiyun 			nvp6158_video_input_auto_detect_set(&vin_auto_det);
297*4882a593Smuzhiyun 			nvp6158_set_chnmode(ch, NC_VIVO_CH_FORMATDEF_UNKNOWN);
298*4882a593Smuzhiyun 		} else {
299*4882a593Smuzhiyun 			nvp6168_video_input_auto_detect_set(&vin_auto_det);
300*4882a593Smuzhiyun 		#ifdef _NVP6168_USE_MANUAL_MODE_
301*4882a593Smuzhiyun 			nvp6168_video_input_manual_mode_set(&vin_manual_det);
302*4882a593Smuzhiyun 		#endif
303*4882a593Smuzhiyun 			nvp6168_set_chnmode(ch, NC_VIVO_CH_FORMATDEF_UNKNOWN);
304*4882a593Smuzhiyun 		}
305*4882a593Smuzhiyun 	}
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 	for(chip = 0; chip < nvp6158_cnt; chip++) {
308*4882a593Smuzhiyun 		if(nvp6158_chip_id[chip] == NVP6158_R0_ID || nvp6158_chip_id[chip] == NVP6168_R0_ID) {
309*4882a593Smuzhiyun 			//set nvp6158 output mode of 4port, 0~3 port is available
310*4882a593Smuzhiyun 			nvp6158_set_portmode(chip, 0, NVP6158_OUTMODE_1MUX_FHD, 0);
311*4882a593Smuzhiyun 			nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 1);
312*4882a593Smuzhiyun 			nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 2);
313*4882a593Smuzhiyun 			nvp6158_set_portmode(chip, 3, NVP6158_OUTMODE_1MUX_FHD, 3);
314*4882a593Smuzhiyun 		} else {//if(nvp6158_chip_id[chip] == NVP6158C_R0_ID)
315*4882a593Smuzhiyun 			//set nvp6158C output mode of 2port, 1/2 port is available
316*4882a593Smuzhiyun 			nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_FHD, 0);
317*4882a593Smuzhiyun 			nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_FHD, 1);
318*4882a593Smuzhiyun 		}
319*4882a593Smuzhiyun 	}
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 
nvp6158_open(struct inode * inode,struct file * file)324*4882a593Smuzhiyun int nvp6158_open(struct inode * inode, struct file * file)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	printk("[DRV] Nvp6158 Driver Open\n");
327*4882a593Smuzhiyun 	printk("[DRV] Nvp6158 Driver Ver::%s\n", NVP6158_DRIVER_VER);
328*4882a593Smuzhiyun 	return 0;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
nvp6158_close(struct inode * inode,struct file * file)331*4882a593Smuzhiyun int nvp6158_close(struct inode * inode, struct file * file)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	printk("[DRV] Nvp6158 Driver Close\n");
334*4882a593Smuzhiyun 	return 0;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun unsigned int nvp6158_g_vloss=0xFFFF;
338*4882a593Smuzhiyun 
nvp6158_native_ioctl(struct file * file,unsigned int cmd,unsigned long arg)339*4882a593Smuzhiyun long nvp6158_native_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	unsigned int __user *argp = (unsigned int __user *)arg;
342*4882a593Smuzhiyun 	int cpy2usr_ret;
343*4882a593Smuzhiyun 	unsigned char i;
344*4882a593Smuzhiyun 	//unsigned char oCableDistance = 0;
345*4882a593Smuzhiyun 	video_equalizer_info_s s_eq_dist;
346*4882a593Smuzhiyun 	nvp6158_opt_mode optmode;
347*4882a593Smuzhiyun 	//nvp6158_video_mode vmode;
348*4882a593Smuzhiyun 	nvp6158_chn_mode schnmode;
349*4882a593Smuzhiyun 	nvp6158_video_adjust v_adj;
350*4882a593Smuzhiyun 	NVP6158_INFORMATION_S vfmt;
351*4882a593Smuzhiyun 	nvp6158_coax_str coax_val;
352*4882a593Smuzhiyun 	nvp6158_input_videofmt_ch vfmt_ch;
353*4882a593Smuzhiyun 	nvp6124_i2c_mode i2c;
354*4882a593Smuzhiyun 	FIRMWARE_UP_FILE_INFO coax_fw_val;
355*4882a593Smuzhiyun 	motion_mode motion_set;
356*4882a593Smuzhiyun 	//int ret=0;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	/* you must skip other command to improve speed of f/w update
360*4882a593Smuzhiyun 	 * when you are updating cam's f/w up. we need to review and test */
361*4882a593Smuzhiyun 	//if( acp_dvr_checkFWUpdateStatus( cmd ) == -1 )
362*4882a593Smuzhiyun 	//{
363*4882a593Smuzhiyun 		//printk(">>>>> DRV[%s:%d] Now cam f/w update mode. so Skip other command.\n", __func__, __LINE__ );
364*4882a593Smuzhiyun 		//return 0;
365*4882a593Smuzhiyun 	//}
366*4882a593Smuzhiyun 	down(&nvp6158_lock);
367*4882a593Smuzhiyun 	switch (cmd) {
368*4882a593Smuzhiyun 		case IOC_VDEC_SET_I2C : // nextchip demoboard test
369*4882a593Smuzhiyun 			if (copy_from_user(&i2c, argp, sizeof(nvp6124_i2c_mode))) {
370*4882a593Smuzhiyun 				up(&nvp6158_lock);
371*4882a593Smuzhiyun 				return -1;
372*4882a593Smuzhiyun 			}
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 			if(i2c.flag == 0) {// read
375*4882a593Smuzhiyun 				gpio_i2c_write(i2c.slaveaddr, 0xFF, i2c.bank);
376*4882a593Smuzhiyun 				i2c.data = gpio_i2c_read(i2c.slaveaddr, i2c.address);
377*4882a593Smuzhiyun 			} else {//write
378*4882a593Smuzhiyun 				gpio_i2c_write(i2c.slaveaddr, 0xFF, i2c.bank);
379*4882a593Smuzhiyun 				gpio_i2c_write(i2c.slaveaddr, i2c.address, i2c.data);
380*4882a593Smuzhiyun 			}
381*4882a593Smuzhiyun 			if(copy_to_user(argp, &i2c, sizeof(nvp6124_i2c_mode)))
382*4882a593Smuzhiyun 				printk("IOC_VDEC_I2C error\n");
383*4882a593Smuzhiyun 		break;
384*4882a593Smuzhiyun 		case IOC_VDEC_GET_VIDEO_LOSS: // Not use
385*4882a593Smuzhiyun 			//nvp6158_g_vloss = nvp6158_getvideoloss();
386*4882a593Smuzhiyun 			if(copy_to_user(argp, &nvp6158_g_vloss, sizeof(unsigned int)))
387*4882a593Smuzhiyun 				printk("IOC_VDEC_GET_VIDEO_LOSS error\n");
388*4882a593Smuzhiyun 			break;
389*4882a593Smuzhiyun 		case IOC_VDEC_GET_EQ_DIST:
390*4882a593Smuzhiyun         		if (copy_from_user(&s_eq_dist, argp, sizeof(video_equalizer_info_s))) {
391*4882a593Smuzhiyun 				up(&nvp6158_lock);
392*4882a593Smuzhiyun 				return -1;
393*4882a593Smuzhiyun 			}
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 			s_eq_dist.distance = nvp6158_get_eq_dist(&s_eq_dist);
396*4882a593Smuzhiyun 			if(copy_to_user(argp, &s_eq_dist, sizeof(video_equalizer_info_s)))
397*4882a593Smuzhiyun 				printk("IOC_VDEC_GET_EQ_DIST error\n");
398*4882a593Smuzhiyun 			break;
399*4882a593Smuzhiyun 		case IOC_VDEC_SET_EQUALIZER:
400*4882a593Smuzhiyun 			if (copy_from_user(&s_eq_dist, argp, sizeof(video_equalizer_info_s))) {
401*4882a593Smuzhiyun 				up(&nvp6158_lock);
402*4882a593Smuzhiyun 				return -1;
403*4882a593Smuzhiyun 			}
404*4882a593Smuzhiyun 			if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
405*4882a593Smuzhiyun 				nvp6158_set_equalizer(&s_eq_dist);
406*4882a593Smuzhiyun 			else
407*4882a593Smuzhiyun 				nvp6168_set_equalizer(&s_eq_dist);
408*4882a593Smuzhiyun 			break;
409*4882a593Smuzhiyun 		case IOC_VDEC_GET_DRIVERVER:
410*4882a593Smuzhiyun 			if(copy_to_user(argp, &NVP6158_DRIVER_VER, sizeof(NVP6158_DRIVER_VER)))
411*4882a593Smuzhiyun 				printk("IOC_VDEC_GET_DRIVERVER error\n");
412*4882a593Smuzhiyun 			break;
413*4882a593Smuzhiyun 		case IOC_VDEC_ACP_WRITE:
414*4882a593Smuzhiyun 			/*if (copy_from_user(&ispdata, argp, sizeof(nvp6158_acp_rw_data)))
415*4882a593Smuzhiyun 				return -1;
416*4882a593Smuzhiyun 			if(ispdata.opt == 0)
417*4882a593Smuzhiyun 				acp_isp_write(ispdata.ch, ispdata.addr, ispdata.data);
418*4882a593Smuzhiyun 			else
419*4882a593Smuzhiyun 			{
420*4882a593Smuzhiyun 				ispdata.data = acp_isp_read(ispdata.ch, ispdata.addr);
421*4882a593Smuzhiyun 				if(copy_to_user(argp, &ispdata, sizeof(nvp6158_acp_rw_data)))
422*4882a593Smuzhiyun 					printk("IOC_VDEC_ACP_WRITE error\n");
423*4882a593Smuzhiyun 			}*/
424*4882a593Smuzhiyun 			break;
425*4882a593Smuzhiyun 		case IOC_VDEC_ACP_WRITE_EXTENTION:
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 			break;
428*4882a593Smuzhiyun 		case IOC_VDEC_PTZ_ACP_READ:
429*4882a593Smuzhiyun 			//if (copy_from_user(&vfmt, argp, sizeof(nvp6158_input_videofmt)))
430*4882a593Smuzhiyun 			//	return -1;
431*4882a593Smuzhiyun 			//for(i=0;i<(4*nvp6158_cnt);i++)
432*4882a593Smuzhiyun 			//{
433*4882a593Smuzhiyun 			//	if(1)
434*4882a593Smuzhiyun 			//	{
435*4882a593Smuzhiyun 					/* read A-CP */
436*4882a593Smuzhiyun 					//if(((nvp6158_g_vloss>>i)&0x01) == 0x00)
437*4882a593Smuzhiyun 					//	acp_read(&vfmt, i);
438*4882a593Smuzhiyun 			//	}
439*4882a593Smuzhiyun 			//}
440*4882a593Smuzhiyun 			//if(copy_to_user(argp, &vfmt, sizeof(nvp6158_input_videofmt)))
441*4882a593Smuzhiyun 			//	printk("IOC_VDEC_PTZ_ACP_READ error\n");
442*4882a593Smuzhiyun 			break;
443*4882a593Smuzhiyun 		case IOC_VDEC_PTZ_ACP_READ_EACH_CH:
444*4882a593Smuzhiyun 			if (copy_from_user(&vfmt_ch, argp, sizeof(nvp6158_input_videofmt_ch))) {
445*4882a593Smuzhiyun 				up(&nvp6158_lock);
446*4882a593Smuzhiyun 				return -1;
447*4882a593Smuzhiyun 			}
448*4882a593Smuzhiyun 			/* read A-CP */
449*4882a593Smuzhiyun 			if(((nvp6158_g_vloss>>vfmt_ch.ch) & 0x01) == 0x00) {
450*4882a593Smuzhiyun 				//acp_read(&vfmt_ch.vfmt, vfmt_ch.ch);
451*4882a593Smuzhiyun 			}
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 			if(copy_to_user(argp, &vfmt_ch, sizeof(nvp6158_input_videofmt_ch)))
454*4882a593Smuzhiyun 				printk("IOC_VDEC_PTZ_ACP_READ_EACH_CH error\n");
455*4882a593Smuzhiyun 			break;
456*4882a593Smuzhiyun 		case IOC_VDEC_GET_INPUT_VIDEO_FMT:
457*4882a593Smuzhiyun 			if (copy_from_user(&vfmt, argp, sizeof(NVP6158_INFORMATION_S))) {
458*4882a593Smuzhiyun 				up(&nvp6158_lock);
459*4882a593Smuzhiyun 				return -1;
460*4882a593Smuzhiyun 			}
461*4882a593Smuzhiyun 			if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
462*4882a593Smuzhiyun 				nvp6158_video_fmt_det(vfmt.ch, &vfmt);
463*4882a593Smuzhiyun 			else
464*4882a593Smuzhiyun 				nvp6168_video_fmt_det(vfmt.ch, &vfmt);
465*4882a593Smuzhiyun 			if(copy_to_user(argp, &vfmt, sizeof(NVP6158_INFORMATION_S)))
466*4882a593Smuzhiyun 				printk("IOC_VDEC_GET_INPUT_VIDEO_FMT error\n");
467*4882a593Smuzhiyun 			break;
468*4882a593Smuzhiyun 		case IOC_VDEC_SET_CHDETMODE:
469*4882a593Smuzhiyun 			if (copy_from_user(&nvp6158_det_mode, argp, sizeof(unsigned char) * 16)) {
470*4882a593Smuzhiyun 				up(&nvp6158_lock);
471*4882a593Smuzhiyun 				return -1;
472*4882a593Smuzhiyun 			}
473*4882a593Smuzhiyun 			for(i = 0; i<(nvp6158_cnt * 4); i++) {
474*4882a593Smuzhiyun 				printk("IOC_VDEC_SET_CHNMODE nvp6158_det_mode[%d]==%d\n",
475*4882a593Smuzhiyun 						i, nvp6158_det_mode[i]);
476*4882a593Smuzhiyun 				if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
477*4882a593Smuzhiyun 					nvp6158_set_chnmode(i, NC_VIVO_CH_FORMATDEF_UNKNOWN);
478*4882a593Smuzhiyun 				else
479*4882a593Smuzhiyun 					nvp6168_set_chnmode(i, NC_VIVO_CH_FORMATDEF_UNKNOWN);
480*4882a593Smuzhiyun 			}
481*4882a593Smuzhiyun 			break;
482*4882a593Smuzhiyun 		case IOC_VDEC_SET_CHNMODE:
483*4882a593Smuzhiyun 			if (copy_from_user(&schnmode, argp, sizeof(nvp6158_chn_mode))) {
484*4882a593Smuzhiyun 				up(&nvp6158_lock);
485*4882a593Smuzhiyun 				return -1;
486*4882a593Smuzhiyun 			}
487*4882a593Smuzhiyun 			if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID) {
488*4882a593Smuzhiyun 				if(0 == nvp6158_set_chnmode(schnmode.ch, schnmode.chmode))
489*4882a593Smuzhiyun 					printk("IOC_VDEC_SET_CHNMODE OK\n");
490*4882a593Smuzhiyun 			} else {
491*4882a593Smuzhiyun 				if(0 == nvp6168_set_chnmode(schnmode.ch, schnmode.chmode))
492*4882a593Smuzhiyun 					printk("IOC_VDEC_SET_CHNMODE OK\n");
493*4882a593Smuzhiyun 			}
494*4882a593Smuzhiyun 			break;
495*4882a593Smuzhiyun 		case IOC_VDEC_SET_OUTPORTMODE:
496*4882a593Smuzhiyun             		if(copy_from_user(&optmode, argp, sizeof(nvp6158_opt_mode))) {
497*4882a593Smuzhiyun 				up(&nvp6158_lock);
498*4882a593Smuzhiyun 				return -1;
499*4882a593Smuzhiyun 			}
500*4882a593Smuzhiyun 			nvp6158_set_portmode(optmode.chipsel, optmode.portsel, optmode.portmode, optmode.chid);
501*4882a593Smuzhiyun 			break;
502*4882a593Smuzhiyun 		case IOC_VDEC_SET_BRIGHTNESS:
503*4882a593Smuzhiyun             		if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
504*4882a593Smuzhiyun 				up(&nvp6158_lock);
505*4882a593Smuzhiyun 				return -1;
506*4882a593Smuzhiyun 			}
507*4882a593Smuzhiyun 			//nvp6158_video_set_brightness(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
508*4882a593Smuzhiyun 			break;
509*4882a593Smuzhiyun 		case IOC_VDEC_SET_CONTRAST:
510*4882a593Smuzhiyun 			if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
511*4882a593Smuzhiyun 				up(&nvp6158_lock);
512*4882a593Smuzhiyun 				return -1;
513*4882a593Smuzhiyun 			}
514*4882a593Smuzhiyun 			//nvp6158_video_set_contrast(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
515*4882a593Smuzhiyun 			break;
516*4882a593Smuzhiyun 		case IOC_VDEC_SET_HUE:
517*4882a593Smuzhiyun 			if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
518*4882a593Smuzhiyun 				up(&nvp6158_lock);
519*4882a593Smuzhiyun 				return -1;
520*4882a593Smuzhiyun 			}
521*4882a593Smuzhiyun 			//nvp6158_video_set_hue(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
522*4882a593Smuzhiyun 			break;
523*4882a593Smuzhiyun 		case IOC_VDEC_SET_SATURATION:
524*4882a593Smuzhiyun 			if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
525*4882a593Smuzhiyun 				up(&nvp6158_lock);
526*4882a593Smuzhiyun 				return -1;
527*4882a593Smuzhiyun 			}
528*4882a593Smuzhiyun 			//nvp6158_video_set_saturation(v_adj.ch, v_adj.value, nvp6158_ch_vfmt_status[v_adj.ch]);
529*4882a593Smuzhiyun 			break;
530*4882a593Smuzhiyun 		case IOC_VDEC_SET_SHARPNESS:
531*4882a593Smuzhiyun 			if(copy_from_user(&v_adj, argp, sizeof(nvp6158_video_adjust))) {
532*4882a593Smuzhiyun 				up(&nvp6158_lock);
533*4882a593Smuzhiyun 				return -1;
534*4882a593Smuzhiyun 			}
535*4882a593Smuzhiyun 			nvp6158_video_set_sharpness(v_adj.ch, v_adj.value);
536*4882a593Smuzhiyun 			break;
537*4882a593Smuzhiyun 		/*----------------------- Coaxial Protocol ----------------------*/
538*4882a593Smuzhiyun 		case IOC_VDEC_COAX_TX_INIT:   //SK_CHANGE 170703
539*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
540*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_TX_INIT error\n");
541*4882a593Smuzhiyun 			nvp6158_coax_tx_init(&coax_val);
542*4882a593Smuzhiyun 				break;
543*4882a593Smuzhiyun 		case IOC_VDEC_COAX_TX_16BIT_INIT:   //SK_CHANGE 170703
544*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
545*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_TX_INIT error\n");
546*4882a593Smuzhiyun 			nvp6158_coax_tx_16bit_init(&coax_val);
547*4882a593Smuzhiyun 				break;
548*4882a593Smuzhiyun 		case IOC_VDEC_COAX_TX_CMD_SEND: //SK_CHANGE 170703
549*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
550*4882a593Smuzhiyun 				printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
551*4882a593Smuzhiyun 			nvp6158_coax_tx_cmd_send(&coax_val);
552*4882a593Smuzhiyun 				break;
553*4882a593Smuzhiyun 		case IOC_VDEC_COAX_TX_16BIT_CMD_SEND: //SK_CHANGE 170703
554*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
555*4882a593Smuzhiyun 				printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
556*4882a593Smuzhiyun 			nvp6158_coax_tx_16bit_cmd_send(&coax_val);
557*4882a593Smuzhiyun 				break;
558*4882a593Smuzhiyun 			case IOC_VDEC_COAX_TX_CVI_NEW_CMD_SEND: //SK_CHANGE 170703
559*4882a593Smuzhiyun 				if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
560*4882a593Smuzhiyun 					printk(" IOC_VDEC_COAX_TX_CMD_SEND error\n");
561*4882a593Smuzhiyun 				nvp6158_coax_tx_cvi_new_cmd_send(&coax_val);
562*4882a593Smuzhiyun 					break;
563*4882a593Smuzhiyun 		case IOC_VDEC_COAX_RX_INIT:
564*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
565*4882a593Smuzhiyun 				printk(" IOC_VDEC_COAX_RX_INIT error\n");
566*4882a593Smuzhiyun 			nvp6158_coax_rx_init(&coax_val);
567*4882a593Smuzhiyun 			break;
568*4882a593Smuzhiyun 		case IOC_VDEC_COAX_RX_DATA_READ:
569*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
570*4882a593Smuzhiyun 			printk(" IOC_VDEC_COAX_RX_DATA_READ error\n");
571*4882a593Smuzhiyun 			nvp6158_coax_rx_data_get(&coax_val);
572*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_val, sizeof(nvp6158_coax_str));
573*4882a593Smuzhiyun 			break;
574*4882a593Smuzhiyun 		case IOC_VDEC_COAX_RX_BUF_CLEAR:
575*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
576*4882a593Smuzhiyun 				printk(" IOC_VDEC_COAX_RX_BUF_CLEAR error\n");
577*4882a593Smuzhiyun 			nvp6158_coax_rx_buffer_clear(&coax_val);
578*4882a593Smuzhiyun 			break;
579*4882a593Smuzhiyun 		case IOC_VDEC_COAX_RX_DEINIT:
580*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
581*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_RX_DEINIT error\n");
582*4882a593Smuzhiyun 			nvp6158_coax_rx_deinit(&coax_val);
583*4882a593Smuzhiyun 			break;
584*4882a593Smuzhiyun 		/*=============== Coaxial Protocol A-CP Option ===============*/
585*4882a593Smuzhiyun 		case IOC_VDEC_COAX_RT_NRT_MODE_CHANGE_SET:
586*4882a593Smuzhiyun 			if(copy_from_user(&coax_val, argp, sizeof(nvp6158_coax_str)))
587*4882a593Smuzhiyun 			printk(" IOC_VDEC_COAX_SHOT_SET error\n");
588*4882a593Smuzhiyun 			nvp6158_coax_option_rt_nrt_mode_change_set(&coax_val);
589*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_val, sizeof(nvp6158_coax_str));
590*4882a593Smuzhiyun 			break;
591*4882a593Smuzhiyun 		/*=========== Coaxial Protocol Firmware Update ==============*/
592*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_ACP_HEADER_GET:
593*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
594*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_READY_CMD_SET error\n");
595*4882a593Smuzhiyun 			nvp6158_coax_fw_ready_header_check_from_isp_recv(&coax_fw_val);
596*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
597*4882a593Smuzhiyun 			break;
598*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_READY_CMD_SET:
599*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
600*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_READY_CMD_SET error\n");
601*4882a593Smuzhiyun 			nvp6158_coax_fw_ready_cmd_to_isp_send(&coax_fw_val);
602*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
603*4882a593Smuzhiyun 			break;
604*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_READY_ACK_GET:
605*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
606*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_READY_ISP_STATUS_GET error\n");
607*4882a593Smuzhiyun 			nvp6158_coax_fw_ready_cmd_ack_from_isp_recv(&coax_fw_val);
608*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
609*4882a593Smuzhiyun 			break;
610*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_START_CMD_SET:
611*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
612*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
613*4882a593Smuzhiyun 			nvp6158_coax_fw_start_cmd_to_isp_send(&coax_fw_val);
614*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
615*4882a593Smuzhiyun 			break;
616*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_START_ACK_GET:
617*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
618*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
619*4882a593Smuzhiyun 			nvp6158_coax_fw_start_cmd_ack_from_isp_recv(&coax_fw_val);
620*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
621*4882a593Smuzhiyun 			break;
622*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_SEND_DATA_SET:
623*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
624*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
625*4882a593Smuzhiyun 			nvp6158_coax_fw_one_packet_data_to_isp_send(&coax_fw_val);
626*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
627*4882a593Smuzhiyun 			break;
628*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_SEND_ACK_GET:
629*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
630*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
631*4882a593Smuzhiyun 			nvp6158_coax_fw_one_packet_data_ack_from_isp_recv(&coax_fw_val);
632*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
633*4882a593Smuzhiyun 			break;
634*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_END_CMD_SET:
635*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
636*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
637*4882a593Smuzhiyun 			nvp6158_coax_fw_end_cmd_to_isp_send(&coax_fw_val);
638*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
639*4882a593Smuzhiyun 			break;
640*4882a593Smuzhiyun 		case IOC_VDEC_COAX_FW_END_ACK_GET:
641*4882a593Smuzhiyun 			if(copy_from_user(&coax_fw_val, argp, sizeof(FIRMWARE_UP_FILE_INFO)))
642*4882a593Smuzhiyun 				printk("IOC_VDEC_COAX_FW_START_CMD_SET error\n");
643*4882a593Smuzhiyun 			nvp6158_coax_fw_end_cmd_ack_from_isp_recv(&coax_fw_val);
644*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &coax_fw_val, sizeof(FIRMWARE_UP_FILE_INFO));
645*4882a593Smuzhiyun 			break;
646*4882a593Smuzhiyun 		/*=========== Coaxial Protocol Firmware Update END ==============*/
647*4882a593Smuzhiyun 		/*----------------------- MOTION ----------------------*/
648*4882a593Smuzhiyun 		case IOC_VDEC_MOTION_DETECTION_GET :
649*4882a593Smuzhiyun 			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
650*4882a593Smuzhiyun 				printk("IOC_VDEC_MOTION_SET error\n");
651*4882a593Smuzhiyun 			nvp6158_motion_detection_get(&motion_set);
652*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &motion_set, sizeof(motion_mode));
653*4882a593Smuzhiyun 		break;
654*4882a593Smuzhiyun 		case IOC_VDEC_MOTION_SET :
655*4882a593Smuzhiyun 			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
656*4882a593Smuzhiyun 				printk("IOC_VDEC_MOTION_SET error\n");
657*4882a593Smuzhiyun 			nvp6158_motion_onoff_set(&motion_set);
658*4882a593Smuzhiyun 			break;
659*4882a593Smuzhiyun 		case IOC_VDEC_MOTION_PIXEL_SET :
660*4882a593Smuzhiyun 			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
661*4882a593Smuzhiyun 				printk("IOC_VDEC_MOTION_Pixel_SET error\n");
662*4882a593Smuzhiyun 			nvp6158_motion_pixel_onoff_set(&motion_set);
663*4882a593Smuzhiyun 		break;
664*4882a593Smuzhiyun 		case IOC_VDEC_MOTION_PIXEL_GET :
665*4882a593Smuzhiyun 			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
666*4882a593Smuzhiyun 				printk("IOC_VDEC_MOTION_Pixel_SET error\n");
667*4882a593Smuzhiyun 			nvp6158_motion_pixel_onoff_get(&motion_set);
668*4882a593Smuzhiyun 			cpy2usr_ret = copy_to_user(argp, &motion_set, sizeof(motion_mode));
669*4882a593Smuzhiyun 			break;
670*4882a593Smuzhiyun 		case IOC_VDEC_MOTION_ALL_PIXEL_SET :
671*4882a593Smuzhiyun 			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
672*4882a593Smuzhiyun 				printk("IOC_VDEC_MOTION_Pixel_SET error\n");
673*4882a593Smuzhiyun 			nvp6158_motion_pixel_all_onoff_set(&motion_set);
674*4882a593Smuzhiyun 		break;
675*4882a593Smuzhiyun 		case IOC_VDEC_MOTION_TSEN_SET :
676*4882a593Smuzhiyun 			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
677*4882a593Smuzhiyun 				printk("IOC_VDEC_MOTION_TSEN_SET error\n");
678*4882a593Smuzhiyun 			nvp6158_motion_tsen_set(&motion_set);
679*4882a593Smuzhiyun 		break;
680*4882a593Smuzhiyun 		case IOC_VDEC_MOTION_PSEN_SET :
681*4882a593Smuzhiyun 			if(copy_from_user(&motion_set, argp, sizeof(motion_set)))
682*4882a593Smuzhiyun 				printk("IOC_VDEC_MOTION_PSEN_SET error\n");
683*4882a593Smuzhiyun 			nvp6158_motion_psen_set(&motion_set);
684*4882a593Smuzhiyun 		break;
685*4882a593Smuzhiyun 		default:
686*4882a593Smuzhiyun             //printk("drv:invalid nc decoder ioctl cmd[%x]\n", cmd);
687*4882a593Smuzhiyun 			break;
688*4882a593Smuzhiyun 	}
689*4882a593Smuzhiyun 	up(&nvp6158_lock);
690*4882a593Smuzhiyun 	return 0;
691*4882a593Smuzhiyun }
692*4882a593Smuzhiyun 
693*4882a593Smuzhiyun #ifdef TEST
nvp6158_set_bt656_601_mode(void)694*4882a593Smuzhiyun void nvp6158_set_bt656_601_mode(void)
695*4882a593Smuzhiyun {
696*4882a593Smuzhiyun 	unsigned char ch = 0;
697*4882a593Smuzhiyun 	int chip = 0;
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
700*4882a593Smuzhiyun 	for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
701*4882a593Smuzhiyun 		nvp6158_set_chnmode(ch, AHD20_1080P_30P);
702*4882a593Smuzhiyun 	}
703*4882a593Smuzhiyun 
704*4882a593Smuzhiyun 	for(chip = 0; chip < nvp6158_cnt; chip++) {
705*4882a593Smuzhiyun 		nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
706*4882a593Smuzhiyun 		nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
707*4882a593Smuzhiyun 	}
708*4882a593Smuzhiyun 	//VDO1 diabled
709*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xFF, 0x01);
710*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xCA, 0x64);
711*4882a593Smuzhiyun #ifdef BT601
712*4882a593Smuzhiyun 	//BT601 test
713*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xFF, 0x01);
714*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xA8, 0x80); //BT601 out
715*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xAB, 0x80); //BT601 out
716*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xBD, 0x00); //BT601 VSYNC HSYNC
717*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xBE, 0x00); //BT601 VSYNC HSYNC
718*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xA9, 0x10); //CH1 Signal out for BT601 (MPP1 = V_BLK1, MPP2=H_BLK1)
719*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xAA, 0x20); //CH2 Signal out for BT601 (MPP3 = V_BLK1, MPP4=H_BLK1)
720*4882a593Smuzhiyun #endif
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun 
nvp6158_set_bt1120_720P_mode(void)723*4882a593Smuzhiyun void nvp6158_set_bt1120_720P_mode(void)
724*4882a593Smuzhiyun {
725*4882a593Smuzhiyun 	unsigned char ch = 0;
726*4882a593Smuzhiyun 	int chip = 0;
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
729*4882a593Smuzhiyun 	for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
730*4882a593Smuzhiyun 		nvp6158_set_chnmode(ch, AHD20_720P_30P);
731*4882a593Smuzhiyun 	}
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	for(chip = 0; chip < nvp6158_cnt; chip ++) {
734*4882a593Smuzhiyun 		nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
735*4882a593Smuzhiyun 		nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
736*4882a593Smuzhiyun 	}
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun 
nvp6158_set_bt1120_1080P_mode(void)739*4882a593Smuzhiyun void nvp6158_set_bt1120_1080P_mode(void)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun 	unsigned char ch = 0;
742*4882a593Smuzhiyun 	int chip = 0;
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	printk("[NVP6158_DRV] %s(%d) \n", __func__, __LINE__);
745*4882a593Smuzhiyun 	for(ch = 0; ch < nvp6158_cnt * 4; ch++) {
746*4882a593Smuzhiyun 		nvp6158_set_chnmode(ch, AHD20_1080P_30P);
747*4882a593Smuzhiyun 	}
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	for(chip = 0; chip < nvp6158_cnt; chip++) {
750*4882a593Smuzhiyun 		nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
751*4882a593Smuzhiyun 		nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
752*4882a593Smuzhiyun 	}
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun #endif
755*4882a593Smuzhiyun 
nvp6158_start(video_init_all * video_init,bool dual_edge)756*4882a593Smuzhiyun void nvp6158_start(video_init_all *video_init, bool dual_edge)
757*4882a593Smuzhiyun {
758*4882a593Smuzhiyun 	unsigned char ch = 0;
759*4882a593Smuzhiyun 	int chip = 0;
760*4882a593Smuzhiyun 	NC_VIVO_CH_FORMATDEF fmt_idx;
761*4882a593Smuzhiyun 	NVP6158_DVP_MODE mode;
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun 	fmt_idx = video_init->ch_param[0].format;
764*4882a593Smuzhiyun 	mode = video_init->mode;
765*4882a593Smuzhiyun 	down(&nvp6158_lock);
766*4882a593Smuzhiyun 	nvp6158_video_decoder_init();
767*4882a593Smuzhiyun 	/* initialize Audio
768*4882a593Smuzhiyun 	 * recmaster, pbmaster, ch_num, samplerate, bits */
769*4882a593Smuzhiyun 	if(nvp6158_chip_id[0] == NVP6158C_R0_ID || nvp6158_chip_id[0] == NVP6158_R0_ID)
770*4882a593Smuzhiyun 		nvp6158_audio_init(1,0,16,0,0);
771*4882a593Smuzhiyun 	else
772*4882a593Smuzhiyun 		nvp6168_audio_init(1,0,16,0,0);
773*4882a593Smuzhiyun 
774*4882a593Smuzhiyun 	switch (fmt_idx) {
775*4882a593Smuzhiyun 		/* normal output */
776*4882a593Smuzhiyun 		case AHD20_720P_25P:
777*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
778*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_720P_25P);
779*4882a593Smuzhiyun 			break;
780*4882a593Smuzhiyun 		case AHD20_720P_30P:
781*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
782*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_720P_30P);
783*4882a593Smuzhiyun 			break;
784*4882a593Smuzhiyun 		case AHD20_1080P_25P:
785*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
786*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_1080P_25P);
787*4882a593Smuzhiyun 			break;
788*4882a593Smuzhiyun 		case AHD20_1080P_30P:
789*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
790*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_1080P_30P);
791*4882a593Smuzhiyun 			break;
792*4882a593Smuzhiyun 		case AHD30_3M_18P:
793*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
794*4882a593Smuzhiyun 				if (dual_edge)
795*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_3M_30P);
796*4882a593Smuzhiyun 				else
797*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_3M_18P);
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 			}
800*4882a593Smuzhiyun 			break;
801*4882a593Smuzhiyun 		case AHD30_4M_15P:
802*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
803*4882a593Smuzhiyun 				if (dual_edge)
804*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_4M_30P);
805*4882a593Smuzhiyun 				else
806*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_4M_15P);
807*4882a593Smuzhiyun 			}
808*4882a593Smuzhiyun 			break;
809*4882a593Smuzhiyun 		case AHD30_5M_12_5P:
810*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
811*4882a593Smuzhiyun 				if (dual_edge)
812*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_5M_20P);
813*4882a593Smuzhiyun 				else
814*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_5M_12_5P);
815*4882a593Smuzhiyun 			}
816*4882a593Smuzhiyun 			break;
817*4882a593Smuzhiyun 		case AHD30_8M_7_5P:
818*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++) {
819*4882a593Smuzhiyun 				if (dual_edge)
820*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_8M_15P);
821*4882a593Smuzhiyun 				else
822*4882a593Smuzhiyun 					nvp6158_set_chnmode(ch, AHD30_8M_7_5P);
823*4882a593Smuzhiyun 			}
824*4882a593Smuzhiyun 			break;
825*4882a593Smuzhiyun 
826*4882a593Smuzhiyun 		/* test output */
827*4882a593Smuzhiyun 		case AHD20_SD_SH720_NT:
828*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
829*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_SD_SH720_NT); /* 720*480i*/
830*4882a593Smuzhiyun 			break;
831*4882a593Smuzhiyun 		case AHD20_SD_SH720_PAL:
832*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
833*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_SD_SH720_PAL); /* 720*576i*/
834*4882a593Smuzhiyun 			break;
835*4882a593Smuzhiyun 		case AHD20_SD_H960_PAL:
836*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
837*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_SD_H960_PAL); /* 960*576i*/
838*4882a593Smuzhiyun 			break;
839*4882a593Smuzhiyun 		case AHD20_SD_H960_EX_PAL:
840*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
841*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_SD_H960_EX_PAL); /*1920*576i*/
842*4882a593Smuzhiyun 			break;
843*4882a593Smuzhiyun 		default:
844*4882a593Smuzhiyun 			for (ch = 0; ch < nvp6158_cnt * 4; ch++)
845*4882a593Smuzhiyun 				nvp6158_set_chnmode(ch, AHD20_1080P_30P);
846*4882a593Smuzhiyun 			break;
847*4882a593Smuzhiyun 	}
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	nvp6158_set_colorpattern();
850*4882a593Smuzhiyun 	//nvp6158_set_colorpattern2();
851*4882a593Smuzhiyun 	//nvp6158_set_colorpattern3();
852*4882a593Smuzhiyun 
853*4882a593Smuzhiyun 	switch (mode) {
854*4882a593Smuzhiyun 		/* normal output */
855*4882a593Smuzhiyun 		case BT656_1MUX:
856*4882a593Smuzhiyun 			if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
857*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
858*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
859*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
860*4882a593Smuzhiyun 				}
861*4882a593Smuzhiyun 			} else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
862*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
863*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_HD, 0);
864*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_HD, 1);
865*4882a593Smuzhiyun 				}
866*4882a593Smuzhiyun 			} else if ((fmt_idx == AHD30_3M_18P) || (fmt_idx == AHD30_4M_15P) ||
867*4882a593Smuzhiyun 					(fmt_idx == AHD30_5M_12_5P) || (fmt_idx == AHD30_8M_7_5P)) {
868*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
869*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
870*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
871*4882a593Smuzhiyun 				}
872*4882a593Smuzhiyun 			} else if ((fmt_idx == AHD20_1080P_50P) || (fmt_idx == AHD20_1080P_60P) ||
873*4882a593Smuzhiyun 					(fmt_idx == AHD30_3M_30P) || (fmt_idx == AHD30_4M_30P) ||
874*4882a593Smuzhiyun 					(fmt_idx == AHD30_3M_25P) || (fmt_idx == AHD30_4M_25P) ||
875*4882a593Smuzhiyun 					(fmt_idx == AHD30_5M_20P) || (fmt_idx == AHD30_8M_15P)) {
876*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
877*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_FHD, 0);
878*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_FHD, 1);
879*4882a593Smuzhiyun 				}
880*4882a593Smuzhiyun 			}
881*4882a593Smuzhiyun 			//standard sync head
882*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x00);
883*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0x54, 0x00);
884*4882a593Smuzhiyun 			//VDO2/VDO1 enabled VCLK_1/2_EN
885*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x01);
886*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xCA, 0x66);
887*4882a593Smuzhiyun 			break;
888*4882a593Smuzhiyun 		case BT656_2MUX:
889*4882a593Smuzhiyun 			if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
890*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
891*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_FHD, 0);
892*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_FHD, 0);
893*4882a593Smuzhiyun 				}
894*4882a593Smuzhiyun 			} else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
895*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
896*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_HD, 0);
897*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_HD, 0);
898*4882a593Smuzhiyun 				}
899*4882a593Smuzhiyun 			}
900*4882a593Smuzhiyun 			//standard sync head
901*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x00);
902*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0x54, 0x00);
903*4882a593Smuzhiyun 			//VDO2 enabled VDO1 disabled VCLK_1_EN
904*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x01);
905*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xCA, 0x66);
906*4882a593Smuzhiyun 			break;
907*4882a593Smuzhiyun 		case BT1120_1MUX:
908*4882a593Smuzhiyun 			if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
909*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
910*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
911*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_1080P, 0);
912*4882a593Smuzhiyun 				}
913*4882a593Smuzhiyun 			} else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
914*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
915*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
916*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_BT1120S_720P, 1);
917*4882a593Smuzhiyun 				}
918*4882a593Smuzhiyun 			}
919*4882a593Smuzhiyun 			//VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
920*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x01);
921*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xCA, 0x66);
922*4882a593Smuzhiyun 			break;
923*4882a593Smuzhiyun 		case BT1120_2MUX:
924*4882a593Smuzhiyun 			if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
925*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
926*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_BT1120S_1080P, 0);
927*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_BT1120S_1080P, 1);
928*4882a593Smuzhiyun 				}
929*4882a593Smuzhiyun 			} else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
930*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
931*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_2MUX_BT1120S_720P, 0);
932*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_2MUX_BT1120S_720P, 1);
933*4882a593Smuzhiyun 				}
934*4882a593Smuzhiyun 			}
935*4882a593Smuzhiyun 			//VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
936*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x01);
937*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xCA, 0x66);
938*4882a593Smuzhiyun 			break;
939*4882a593Smuzhiyun 		case BT1120_4MUX:
940*4882a593Smuzhiyun 			if ((fmt_idx == AHD20_1080P_25P) || (fmt_idx == AHD20_1080P_30P)) {
941*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
942*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_4MUX_BT1120S_1080P, 0);
943*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_4MUX_BT1120S_1080P, 1);
944*4882a593Smuzhiyun 				}
945*4882a593Smuzhiyun 			} else if ((fmt_idx == AHD20_720P_25P) || (fmt_idx == AHD20_720P_30P)) {
946*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
947*4882a593Smuzhiyun 					if (dual_edge) {
948*4882a593Smuzhiyun 						nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_4MUX_BT1120S_DDR, 0);
949*4882a593Smuzhiyun 						nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_4MUX_BT1120S_DDR, 1);
950*4882a593Smuzhiyun 					} else {
951*4882a593Smuzhiyun 						nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_4MUX_BT1120S, 0);
952*4882a593Smuzhiyun 						nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_4MUX_BT1120S, 1);
953*4882a593Smuzhiyun 					}
954*4882a593Smuzhiyun 				}
955*4882a593Smuzhiyun 			}
956*4882a593Smuzhiyun 			//VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
957*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x01);
958*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xCA, 0x66);
959*4882a593Smuzhiyun 			break;
960*4882a593Smuzhiyun 		/* test output */
961*4882a593Smuzhiyun 		case BT656I_TEST_MODES:
962*4882a593Smuzhiyun 			if (fmt_idx == AHD20_SD_H960_EX_PAL) {
963*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
964*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_HD, 0);
965*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_HD, 1);
966*4882a593Smuzhiyun 				}
967*4882a593Smuzhiyun 			} else {
968*4882a593Smuzhiyun 				for (chip = 0; chip < nvp6158_cnt; chip++) {
969*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 1, NVP6158_OUTMODE_1MUX_SD, 0);
970*4882a593Smuzhiyun 					nvp6158_set_portmode(chip, 2, NVP6158_OUTMODE_1MUX_SD, 1);
971*4882a593Smuzhiyun 				}
972*4882a593Smuzhiyun 			}
973*4882a593Smuzhiyun 			//VDO2 enabled VDO1 disabled VCLK_1_EN
974*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xFF, 0x01);
975*4882a593Smuzhiyun 			//gpio_i2c_write(0x60, 0xCA, 0x64);
976*4882a593Smuzhiyun 			//VDO2/VDO1 enabled VCLK_1_EN/VCLK_2_EN
977*4882a593Smuzhiyun 			gpio_i2c_write(0x60, 0xCA, 0x66);
978*4882a593Smuzhiyun 			break;
979*4882a593Smuzhiyun 		default:
980*4882a593Smuzhiyun 			printk("mode %d not supported yet\n", mode);
981*4882a593Smuzhiyun 			break;
982*4882a593Smuzhiyun 	}
983*4882a593Smuzhiyun 	up(&nvp6158_lock);
984*4882a593Smuzhiyun }
985*4882a593Smuzhiyun 
nvp6158_stop(void)986*4882a593Smuzhiyun void nvp6158_stop(void)
987*4882a593Smuzhiyun {
988*4882a593Smuzhiyun 	unsigned char ch = 0;
989*4882a593Smuzhiyun 
990*4882a593Smuzhiyun 	down(&nvp6158_lock);
991*4882a593Smuzhiyun 	//VDO_1/2 disabled, VCLK_x disabled
992*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xFF, 0x01);
993*4882a593Smuzhiyun 	gpio_i2c_write(0x60, 0xCA, 0x00);
994*4882a593Smuzhiyun 
995*4882a593Smuzhiyun 	for(ch = 0; ch < 4;ch++) {
996*4882a593Smuzhiyun 		nvp6158_channel_reset(ch);
997*4882a593Smuzhiyun 	}
998*4882a593Smuzhiyun 	up(&nvp6158_lock);
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun 
1001*4882a593Smuzhiyun /*******************************************************************************
1002*4882a593Smuzhiyun  *	Description		: i2c client initial
1003*4882a593Smuzhiyun  *	Argurments		: int
1004*4882a593Smuzhiyun  *	Return value	: 0
1005*4882a593Smuzhiyun  *	Modify			:
1006*4882a593Smuzhiyun  *	warning			:
1007*4882a593Smuzhiyun  *******************************************************************************/
nvp6158_i2c_client_init(int i2c_bus)1008*4882a593Smuzhiyun static int nvp6158_i2c_client_init(int i2c_bus)
1009*4882a593Smuzhiyun {
1010*4882a593Smuzhiyun     struct i2c_adapter* i2c_adap;
1011*4882a593Smuzhiyun 
1012*4882a593Smuzhiyun     printk("[DRV] I2C Client Init \n");
1013*4882a593Smuzhiyun     i2c_adap = i2c_get_adapter(i2c_bus);
1014*4882a593Smuzhiyun 
1015*4882a593Smuzhiyun     nvp6158_client = i2c_new_client_device(i2c_adap, &nvp6158_hi_info);
1016*4882a593Smuzhiyun     i2c_put_adapter(i2c_adap);
1017*4882a593Smuzhiyun 
1018*4882a593Smuzhiyun     return 0;
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun /*******************************************************************************
1022*4882a593Smuzhiyun  *	Description		: i2c client release
1023*4882a593Smuzhiyun  *	Argurments		: void
1024*4882a593Smuzhiyun  *	Return value	: void
1025*4882a593Smuzhiyun  *	Modify			:
1026*4882a593Smuzhiyun  *	warning			:
1027*4882a593Smuzhiyun  *******************************************************************************/
nvp6158_i2c_client_exit(void)1028*4882a593Smuzhiyun void nvp6158_i2c_client_exit(void)
1029*4882a593Smuzhiyun {
1030*4882a593Smuzhiyun     i2c_unregister_device(nvp6158_client);
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun 
nvp6158_init(int i2c_bus)1033*4882a593Smuzhiyun int nvp6158_init(int i2c_bus)
1034*4882a593Smuzhiyun {
1035*4882a593Smuzhiyun 	int ret = 0;
1036*4882a593Smuzhiyun #ifdef FMT_SETTING_SAMPLE
1037*4882a593Smuzhiyun 	int dev_num = 0;
1038*4882a593Smuzhiyun #endif
1039*4882a593Smuzhiyun 
1040*4882a593Smuzhiyun 	if (nvp6158_init_state)
1041*4882a593Smuzhiyun 		return 0;
1042*4882a593Smuzhiyun 
1043*4882a593Smuzhiyun 	ret = nvp6158_i2c_client_init(i2c_bus);
1044*4882a593Smuzhiyun 	if (ret) {
1045*4882a593Smuzhiyun 		printk(KERN_ERR "ERROR: could not find nvp6158\n");
1046*4882a593Smuzhiyun 		return ret;
1047*4882a593Smuzhiyun 	}
1048*4882a593Smuzhiyun 
1049*4882a593Smuzhiyun 	/* decoder count function */
1050*4882a593Smuzhiyun 	ret = nvp6158_check_decoder_count();
1051*4882a593Smuzhiyun 	if (ret <= 0) {
1052*4882a593Smuzhiyun 		printk(KERN_ERR "ERROR: could not find nvp6158 devices:%#x\n", ret);
1053*4882a593Smuzhiyun 		nvp6158_i2c_client_exit();
1054*4882a593Smuzhiyun 		return -ENODEV;
1055*4882a593Smuzhiyun 	}
1056*4882a593Smuzhiyun 
1057*4882a593Smuzhiyun 	/* initialize semaphore */
1058*4882a593Smuzhiyun 	sema_init(&nvp6158_lock, 1);
1059*4882a593Smuzhiyun 	nvp6158_init_state = true;
1060*4882a593Smuzhiyun 
1061*4882a593Smuzhiyun 	return 0;
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun 
nvp6158_exit(void)1064*4882a593Smuzhiyun void nvp6158_exit(void)
1065*4882a593Smuzhiyun {
1066*4882a593Smuzhiyun 	nvp6158_i2c_client_exit();
1067*4882a593Smuzhiyun 	nvp6158_init_state = false;
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun /*******************************************************************************
1071*4882a593Smuzhiyun *	End of file
1072*4882a593Smuzhiyun *******************************************************************************/
1073*4882a593Smuzhiyun 
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