xref: /OK3568_Linux_fs/kernel/drivers/media/i2c/noon010pc30.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Driver for SiliconFile NOON010PC30 CIF (1/11") Image Sensor with ISP
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Initial register configuration based on a driver authored by
9*4882a593Smuzhiyun  * HeungJun Kim <riverful.kim@samsung.com>.
10*4882a593Smuzhiyun  */
11*4882a593Smuzhiyun 
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/gpio.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
17*4882a593Smuzhiyun #include <media/i2c/noon010pc30.h>
18*4882a593Smuzhiyun #include <linux/videodev2.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <media/v4l2-ctrls.h>
21*4882a593Smuzhiyun #include <media/v4l2-device.h>
22*4882a593Smuzhiyun #include <media/v4l2-mediabus.h>
23*4882a593Smuzhiyun #include <media/v4l2-subdev.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun static int debug;
26*4882a593Smuzhiyun module_param(debug, int, 0644);
27*4882a593Smuzhiyun MODULE_PARM_DESC(debug, "Enable module debug trace. Set to 1 to enable.");
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define MODULE_NAME		"NOON010PC30"
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun  * Register offsets within a page
33*4882a593Smuzhiyun  * b15..b8 - page id, b7..b0 - register address
34*4882a593Smuzhiyun  */
35*4882a593Smuzhiyun #define POWER_CTRL_REG		0x0001
36*4882a593Smuzhiyun #define PAGEMODE_REG		0x03
37*4882a593Smuzhiyun #define DEVICE_ID_REG		0x0004
38*4882a593Smuzhiyun #define NOON010PC30_ID		0x86
39*4882a593Smuzhiyun #define VDO_CTL_REG(n)		(0x0010 + (n))
40*4882a593Smuzhiyun #define SYNC_CTL_REG		0x0012
41*4882a593Smuzhiyun /* Window size and position */
42*4882a593Smuzhiyun #define WIN_ROWH_REG		0x0013
43*4882a593Smuzhiyun #define WIN_ROWL_REG		0x0014
44*4882a593Smuzhiyun #define WIN_COLH_REG		0x0015
45*4882a593Smuzhiyun #define WIN_COLL_REG		0x0016
46*4882a593Smuzhiyun #define WIN_HEIGHTH_REG		0x0017
47*4882a593Smuzhiyun #define WIN_HEIGHTL_REG		0x0018
48*4882a593Smuzhiyun #define WIN_WIDTHH_REG		0x0019
49*4882a593Smuzhiyun #define WIN_WIDTHL_REG		0x001A
50*4882a593Smuzhiyun #define HBLANKH_REG		0x001B
51*4882a593Smuzhiyun #define HBLANKL_REG		0x001C
52*4882a593Smuzhiyun #define VSYNCH_REG		0x001D
53*4882a593Smuzhiyun #define VSYNCL_REG		0x001E
54*4882a593Smuzhiyun /* VSYNC control */
55*4882a593Smuzhiyun #define VS_CTL_REG(n)		(0x00A1 + (n))
56*4882a593Smuzhiyun /* page 1 */
57*4882a593Smuzhiyun #define ISP_CTL_REG(n)		(0x0110 + (n))
58*4882a593Smuzhiyun #define YOFS_REG		0x0119
59*4882a593Smuzhiyun #define DARK_YOFS_REG		0x011A
60*4882a593Smuzhiyun #define SAT_CTL_REG		0x0120
61*4882a593Smuzhiyun #define BSAT_REG		0x0121
62*4882a593Smuzhiyun #define RSAT_REG		0x0122
63*4882a593Smuzhiyun /* Color correction */
64*4882a593Smuzhiyun #define CMC_CTL_REG		0x0130
65*4882a593Smuzhiyun #define CMC_OFSGH_REG		0x0133
66*4882a593Smuzhiyun #define CMC_OFSGL_REG		0x0135
67*4882a593Smuzhiyun #define CMC_SIGN_REG		0x0136
68*4882a593Smuzhiyun #define CMC_GOFS_REG		0x0137
69*4882a593Smuzhiyun #define CMC_COEF_REG(n)		(0x0138 + (n))
70*4882a593Smuzhiyun #define CMC_OFS_REG(n)		(0x0141 + (n))
71*4882a593Smuzhiyun /* Gamma correction */
72*4882a593Smuzhiyun #define GMA_CTL_REG		0x0160
73*4882a593Smuzhiyun #define GMA_COEF_REG(n)		(0x0161 + (n))
74*4882a593Smuzhiyun /* Lens Shading */
75*4882a593Smuzhiyun #define LENS_CTRL_REG		0x01D0
76*4882a593Smuzhiyun #define LENS_XCEN_REG		0x01D1
77*4882a593Smuzhiyun #define LENS_YCEN_REG		0x01D2
78*4882a593Smuzhiyun #define LENS_RC_REG		0x01D3
79*4882a593Smuzhiyun #define LENS_GC_REG		0x01D4
80*4882a593Smuzhiyun #define LENS_BC_REG		0x01D5
81*4882a593Smuzhiyun #define L_AGON_REG		0x01D6
82*4882a593Smuzhiyun #define L_AGOFF_REG		0x01D7
83*4882a593Smuzhiyun /* Page 3 - Auto Exposure */
84*4882a593Smuzhiyun #define AE_CTL_REG(n)		(0x0310 + (n))
85*4882a593Smuzhiyun #define AE_CTL9_REG		0x032C
86*4882a593Smuzhiyun #define AE_CTL10_REG		0x032D
87*4882a593Smuzhiyun #define AE_YLVL_REG		0x031C
88*4882a593Smuzhiyun #define AE_YTH_REG(n)		(0x031D + (n))
89*4882a593Smuzhiyun #define AE_WGT_REG		0x0326
90*4882a593Smuzhiyun #define EXP_TIMEH_REG		0x0333
91*4882a593Smuzhiyun #define EXP_TIMEM_REG		0x0334
92*4882a593Smuzhiyun #define EXP_TIMEL_REG		0x0335
93*4882a593Smuzhiyun #define EXP_MMINH_REG		0x0336
94*4882a593Smuzhiyun #define EXP_MMINL_REG		0x0337
95*4882a593Smuzhiyun #define EXP_MMAXH_REG		0x0338
96*4882a593Smuzhiyun #define EXP_MMAXM_REG		0x0339
97*4882a593Smuzhiyun #define EXP_MMAXL_REG		0x033A
98*4882a593Smuzhiyun /* Page 4 - Auto White Balance */
99*4882a593Smuzhiyun #define AWB_CTL_REG(n)		(0x0410 + (n))
100*4882a593Smuzhiyun #define AWB_ENABE		0x80
101*4882a593Smuzhiyun #define AWB_WGHT_REG		0x0419
102*4882a593Smuzhiyun #define BGAIN_PAR_REG(n)	(0x044F + (n))
103*4882a593Smuzhiyun /* Manual white balance, when AWB_CTL2[0]=1 */
104*4882a593Smuzhiyun #define MWB_RGAIN_REG		0x0466
105*4882a593Smuzhiyun #define MWB_BGAIN_REG		0x0467
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun /* The token to mark an array end */
108*4882a593Smuzhiyun #define REG_TERM		0xFFFF
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun struct noon010_format {
111*4882a593Smuzhiyun 	u32 code;
112*4882a593Smuzhiyun 	enum v4l2_colorspace colorspace;
113*4882a593Smuzhiyun 	u16 ispctl1_reg;
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun struct noon010_frmsize {
117*4882a593Smuzhiyun 	u16 width;
118*4882a593Smuzhiyun 	u16 height;
119*4882a593Smuzhiyun 	int vid_ctl1;
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static const char * const noon010_supply_name[] = {
123*4882a593Smuzhiyun 	"vdd_core", "vddio", "vdda"
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun #define NOON010_NUM_SUPPLIES ARRAY_SIZE(noon010_supply_name)
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun struct noon010_info {
129*4882a593Smuzhiyun 	struct v4l2_subdev sd;
130*4882a593Smuzhiyun 	struct media_pad pad;
131*4882a593Smuzhiyun 	struct v4l2_ctrl_handler hdl;
132*4882a593Smuzhiyun 	struct regulator_bulk_data supply[NOON010_NUM_SUPPLIES];
133*4882a593Smuzhiyun 	u32 gpio_nreset;
134*4882a593Smuzhiyun 	u32 gpio_nstby;
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* Protects the struct members below */
137*4882a593Smuzhiyun 	struct mutex lock;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	const struct noon010_format *curr_fmt;
140*4882a593Smuzhiyun 	const struct noon010_frmsize *curr_win;
141*4882a593Smuzhiyun 	unsigned int apply_new_cfg:1;
142*4882a593Smuzhiyun 	unsigned int streaming:1;
143*4882a593Smuzhiyun 	unsigned int hflip:1;
144*4882a593Smuzhiyun 	unsigned int vflip:1;
145*4882a593Smuzhiyun 	unsigned int power:1;
146*4882a593Smuzhiyun 	u8 i2c_reg_page;
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun struct i2c_regval {
150*4882a593Smuzhiyun 	u16 addr;
151*4882a593Smuzhiyun 	u16 val;
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun /* Supported resolutions. */
155*4882a593Smuzhiyun static const struct noon010_frmsize noon010_sizes[] = {
156*4882a593Smuzhiyun 	{
157*4882a593Smuzhiyun 		.width		= 352,
158*4882a593Smuzhiyun 		.height		= 288,
159*4882a593Smuzhiyun 		.vid_ctl1	= 0,
160*4882a593Smuzhiyun 	}, {
161*4882a593Smuzhiyun 		.width		= 176,
162*4882a593Smuzhiyun 		.height		= 144,
163*4882a593Smuzhiyun 		.vid_ctl1	= 0x10,
164*4882a593Smuzhiyun 	}, {
165*4882a593Smuzhiyun 		.width		= 88,
166*4882a593Smuzhiyun 		.height		= 72,
167*4882a593Smuzhiyun 		.vid_ctl1	= 0x20,
168*4882a593Smuzhiyun 	},
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun /* Supported pixel formats. */
172*4882a593Smuzhiyun static const struct noon010_format noon010_formats[] = {
173*4882a593Smuzhiyun 	{
174*4882a593Smuzhiyun 		.code		= MEDIA_BUS_FMT_YUYV8_2X8,
175*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
176*4882a593Smuzhiyun 		.ispctl1_reg	= 0x03,
177*4882a593Smuzhiyun 	}, {
178*4882a593Smuzhiyun 		.code		= MEDIA_BUS_FMT_YVYU8_2X8,
179*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
180*4882a593Smuzhiyun 		.ispctl1_reg	= 0x02,
181*4882a593Smuzhiyun 	}, {
182*4882a593Smuzhiyun 		.code		= MEDIA_BUS_FMT_VYUY8_2X8,
183*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
184*4882a593Smuzhiyun 		.ispctl1_reg	= 0,
185*4882a593Smuzhiyun 	}, {
186*4882a593Smuzhiyun 		.code		= MEDIA_BUS_FMT_UYVY8_2X8,
187*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
188*4882a593Smuzhiyun 		.ispctl1_reg	= 0x01,
189*4882a593Smuzhiyun 	}, {
190*4882a593Smuzhiyun 		.code		= MEDIA_BUS_FMT_RGB565_2X8_BE,
191*4882a593Smuzhiyun 		.colorspace	= V4L2_COLORSPACE_JPEG,
192*4882a593Smuzhiyun 		.ispctl1_reg	= 0x40,
193*4882a593Smuzhiyun 	},
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun static const struct i2c_regval noon010_base_regs[] = {
197*4882a593Smuzhiyun 	{ WIN_COLL_REG,		0x06 },	{ HBLANKL_REG,		0x7C },
198*4882a593Smuzhiyun 	/* Color corection and saturation */
199*4882a593Smuzhiyun 	{ ISP_CTL_REG(0),	0x30 }, { ISP_CTL_REG(2),	0x30 },
200*4882a593Smuzhiyun 	{ YOFS_REG,		0x80 }, { DARK_YOFS_REG,	0x04 },
201*4882a593Smuzhiyun 	{ SAT_CTL_REG,		0x1F }, { BSAT_REG,		0x90 },
202*4882a593Smuzhiyun 	{ CMC_CTL_REG,		0x0F }, { CMC_OFSGH_REG,	0x3C },
203*4882a593Smuzhiyun 	{ CMC_OFSGL_REG,	0x2C }, { CMC_SIGN_REG,		0x3F },
204*4882a593Smuzhiyun 	{ CMC_COEF_REG(0),	0x79 }, { CMC_OFS_REG(0),	0x00 },
205*4882a593Smuzhiyun 	{ CMC_COEF_REG(1),	0x39 }, { CMC_OFS_REG(1),	0x00 },
206*4882a593Smuzhiyun 	{ CMC_COEF_REG(2),	0x00 }, { CMC_OFS_REG(2),	0x00 },
207*4882a593Smuzhiyun 	{ CMC_COEF_REG(3),	0x11 }, { CMC_OFS_REG(3),	0x8B },
208*4882a593Smuzhiyun 	{ CMC_COEF_REG(4),	0x65 }, { CMC_OFS_REG(4),	0x07 },
209*4882a593Smuzhiyun 	{ CMC_COEF_REG(5),	0x14 }, { CMC_OFS_REG(5),	0x04 },
210*4882a593Smuzhiyun 	{ CMC_COEF_REG(6),	0x01 }, { CMC_OFS_REG(6),	0x9C },
211*4882a593Smuzhiyun 	{ CMC_COEF_REG(7),	0x33 }, { CMC_OFS_REG(7),	0x89 },
212*4882a593Smuzhiyun 	{ CMC_COEF_REG(8),	0x74 }, { CMC_OFS_REG(8),	0x25 },
213*4882a593Smuzhiyun 	/* Automatic white balance */
214*4882a593Smuzhiyun 	{ AWB_CTL_REG(0),	0x78 }, { AWB_CTL_REG(1),	0x2E },
215*4882a593Smuzhiyun 	{ AWB_CTL_REG(2),	0x20 }, { AWB_CTL_REG(3),	0x85 },
216*4882a593Smuzhiyun 	/* Auto exposure */
217*4882a593Smuzhiyun 	{ AE_CTL_REG(0),	0xDC }, { AE_CTL_REG(1),	0x81 },
218*4882a593Smuzhiyun 	{ AE_CTL_REG(2),	0x30 }, { AE_CTL_REG(3),	0xA5 },
219*4882a593Smuzhiyun 	{ AE_CTL_REG(4),	0x40 }, { AE_CTL_REG(5),	0x51 },
220*4882a593Smuzhiyun 	{ AE_CTL_REG(6),	0x33 }, { AE_CTL_REG(7),	0x7E },
221*4882a593Smuzhiyun 	{ AE_CTL9_REG,		0x00 }, { AE_CTL10_REG,		0x02 },
222*4882a593Smuzhiyun 	{ AE_YLVL_REG,		0x44 },	{ AE_YTH_REG(0),	0x34 },
223*4882a593Smuzhiyun 	{ AE_YTH_REG(1),	0x30 },	{ AE_WGT_REG,		0xD5 },
224*4882a593Smuzhiyun 	/* Lens shading compensation */
225*4882a593Smuzhiyun 	{ LENS_CTRL_REG,	0x01 }, { LENS_XCEN_REG,	0x80 },
226*4882a593Smuzhiyun 	{ LENS_YCEN_REG,	0x70 }, { LENS_RC_REG,		0x53 },
227*4882a593Smuzhiyun 	{ LENS_GC_REG,		0x40 }, { LENS_BC_REG,		0x3E },
228*4882a593Smuzhiyun 	{ REG_TERM,		0 },
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun 
to_noon010(struct v4l2_subdev * sd)231*4882a593Smuzhiyun static inline struct noon010_info *to_noon010(struct v4l2_subdev *sd)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun 	return container_of(sd, struct noon010_info, sd);
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun 
to_sd(struct v4l2_ctrl * ctrl)236*4882a593Smuzhiyun static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
237*4882a593Smuzhiyun {
238*4882a593Smuzhiyun 	return &container_of(ctrl->handler, struct noon010_info, hdl)->sd;
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun 
set_i2c_page(struct noon010_info * info,struct i2c_client * client,unsigned int reg)241*4882a593Smuzhiyun static inline int set_i2c_page(struct noon010_info *info,
242*4882a593Smuzhiyun 			       struct i2c_client *client, unsigned int reg)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun 	u32 page = reg >> 8 & 0xFF;
245*4882a593Smuzhiyun 	int ret = 0;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
248*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
249*4882a593Smuzhiyun 		if (!ret)
250*4882a593Smuzhiyun 			info->i2c_reg_page = page;
251*4882a593Smuzhiyun 	}
252*4882a593Smuzhiyun 	return ret;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun 
cam_i2c_read(struct v4l2_subdev * sd,u32 reg_addr)255*4882a593Smuzhiyun static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
258*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
259*4882a593Smuzhiyun 	int ret = set_i2c_page(info, client, reg_addr);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	if (ret)
262*4882a593Smuzhiyun 		return ret;
263*4882a593Smuzhiyun 	return i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun 
cam_i2c_write(struct v4l2_subdev * sd,u32 reg_addr,u32 val)266*4882a593Smuzhiyun static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun 	struct i2c_client *client = v4l2_get_subdevdata(sd);
269*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
270*4882a593Smuzhiyun 	int ret = set_i2c_page(info, client, reg_addr);
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 	if (ret)
273*4882a593Smuzhiyun 		return ret;
274*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(client, reg_addr & 0xFF, val);
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
noon010_bulk_write_reg(struct v4l2_subdev * sd,const struct i2c_regval * msg)277*4882a593Smuzhiyun static inline int noon010_bulk_write_reg(struct v4l2_subdev *sd,
278*4882a593Smuzhiyun 					 const struct i2c_regval *msg)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun 	while (msg->addr != REG_TERM) {
281*4882a593Smuzhiyun 		int ret = cam_i2c_write(sd, msg->addr, msg->val);
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 		if (ret)
284*4882a593Smuzhiyun 			return ret;
285*4882a593Smuzhiyun 		msg++;
286*4882a593Smuzhiyun 	}
287*4882a593Smuzhiyun 	return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun /* Device reset and sleep mode control */
noon010_power_ctrl(struct v4l2_subdev * sd,bool reset,bool sleep)291*4882a593Smuzhiyun static int noon010_power_ctrl(struct v4l2_subdev *sd, bool reset, bool sleep)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
294*4882a593Smuzhiyun 	u8 reg = sleep ? 0xF1 : 0xF0;
295*4882a593Smuzhiyun 	int ret = 0;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	if (reset) {
298*4882a593Smuzhiyun 		ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
299*4882a593Smuzhiyun 		udelay(20);
300*4882a593Smuzhiyun 	}
301*4882a593Smuzhiyun 	if (!ret) {
302*4882a593Smuzhiyun 		ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
303*4882a593Smuzhiyun 		if (reset && !ret)
304*4882a593Smuzhiyun 			info->i2c_reg_page = -1;
305*4882a593Smuzhiyun 	}
306*4882a593Smuzhiyun 	return ret;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun /* Automatic white balance control */
noon010_enable_autowhitebalance(struct v4l2_subdev * sd,int on)310*4882a593Smuzhiyun static int noon010_enable_autowhitebalance(struct v4l2_subdev *sd, int on)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun 	int ret;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	ret = cam_i2c_write(sd, AWB_CTL_REG(1), on ? 0x2E : 0x2F);
315*4882a593Smuzhiyun 	if (!ret)
316*4882a593Smuzhiyun 		ret = cam_i2c_write(sd, AWB_CTL_REG(0), on ? 0xFB : 0x7B);
317*4882a593Smuzhiyun 	return ret;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun /* Called with struct noon010_info.lock mutex held */
noon010_set_flip(struct v4l2_subdev * sd,int hflip,int vflip)321*4882a593Smuzhiyun static int noon010_set_flip(struct v4l2_subdev *sd, int hflip, int vflip)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
324*4882a593Smuzhiyun 	int reg, ret;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	reg = cam_i2c_read(sd, VDO_CTL_REG(1));
327*4882a593Smuzhiyun 	if (reg < 0)
328*4882a593Smuzhiyun 		return reg;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 	reg &= 0x7C;
331*4882a593Smuzhiyun 	if (hflip)
332*4882a593Smuzhiyun 		reg |= 0x01;
333*4882a593Smuzhiyun 	if (vflip)
334*4882a593Smuzhiyun 		reg |= 0x02;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	ret = cam_i2c_write(sd, VDO_CTL_REG(1), reg | 0x80);
337*4882a593Smuzhiyun 	if (!ret) {
338*4882a593Smuzhiyun 		info->hflip = hflip;
339*4882a593Smuzhiyun 		info->vflip = vflip;
340*4882a593Smuzhiyun 	}
341*4882a593Smuzhiyun 	return ret;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun /* Configure resolution and color format */
noon010_set_params(struct v4l2_subdev * sd)345*4882a593Smuzhiyun static int noon010_set_params(struct v4l2_subdev *sd)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	int ret = cam_i2c_write(sd, VDO_CTL_REG(0),
350*4882a593Smuzhiyun 				info->curr_win->vid_ctl1);
351*4882a593Smuzhiyun 	if (ret)
352*4882a593Smuzhiyun 		return ret;
353*4882a593Smuzhiyun 	return cam_i2c_write(sd, ISP_CTL_REG(0),
354*4882a593Smuzhiyun 			     info->curr_fmt->ispctl1_reg);
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun /* Find nearest matching image pixel size. */
noon010_try_frame_size(struct v4l2_mbus_framefmt * mf,const struct noon010_frmsize ** size)358*4882a593Smuzhiyun static int noon010_try_frame_size(struct v4l2_mbus_framefmt *mf,
359*4882a593Smuzhiyun 				  const struct noon010_frmsize **size)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun 	unsigned int min_err = ~0;
362*4882a593Smuzhiyun 	int i = ARRAY_SIZE(noon010_sizes);
363*4882a593Smuzhiyun 	const struct noon010_frmsize *fsize = &noon010_sizes[0],
364*4882a593Smuzhiyun 		*match = NULL;
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	while (i--) {
367*4882a593Smuzhiyun 		int err = abs(fsize->width - mf->width)
368*4882a593Smuzhiyun 				+ abs(fsize->height - mf->height);
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 		if (err < min_err) {
371*4882a593Smuzhiyun 			min_err = err;
372*4882a593Smuzhiyun 			match = fsize;
373*4882a593Smuzhiyun 		}
374*4882a593Smuzhiyun 		fsize++;
375*4882a593Smuzhiyun 	}
376*4882a593Smuzhiyun 	if (match) {
377*4882a593Smuzhiyun 		mf->width  = match->width;
378*4882a593Smuzhiyun 		mf->height = match->height;
379*4882a593Smuzhiyun 		if (size)
380*4882a593Smuzhiyun 			*size = match;
381*4882a593Smuzhiyun 		return 0;
382*4882a593Smuzhiyun 	}
383*4882a593Smuzhiyun 	return -EINVAL;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun /* Called with info.lock mutex held */
power_enable(struct noon010_info * info)387*4882a593Smuzhiyun static int power_enable(struct noon010_info *info)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun 	int ret;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	if (info->power) {
392*4882a593Smuzhiyun 		v4l2_info(&info->sd, "%s: sensor is already on\n", __func__);
393*4882a593Smuzhiyun 		return 0;
394*4882a593Smuzhiyun 	}
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	if (gpio_is_valid(info->gpio_nstby))
397*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nstby, 0);
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	if (gpio_is_valid(info->gpio_nreset))
400*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nreset, 0);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	ret = regulator_bulk_enable(NOON010_NUM_SUPPLIES, info->supply);
403*4882a593Smuzhiyun 	if (ret)
404*4882a593Smuzhiyun 		return ret;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	if (gpio_is_valid(info->gpio_nreset)) {
407*4882a593Smuzhiyun 		msleep(50);
408*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nreset, 1);
409*4882a593Smuzhiyun 	}
410*4882a593Smuzhiyun 	if (gpio_is_valid(info->gpio_nstby)) {
411*4882a593Smuzhiyun 		udelay(1000);
412*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nstby, 1);
413*4882a593Smuzhiyun 	}
414*4882a593Smuzhiyun 	if (gpio_is_valid(info->gpio_nreset)) {
415*4882a593Smuzhiyun 		udelay(1000);
416*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nreset, 0);
417*4882a593Smuzhiyun 		msleep(100);
418*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nreset, 1);
419*4882a593Smuzhiyun 		msleep(20);
420*4882a593Smuzhiyun 	}
421*4882a593Smuzhiyun 	info->power = 1;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	v4l2_dbg(1, debug, &info->sd,  "%s: sensor is on\n", __func__);
424*4882a593Smuzhiyun 	return 0;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun /* Called with info.lock mutex held */
power_disable(struct noon010_info * info)428*4882a593Smuzhiyun static int power_disable(struct noon010_info *info)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun 	int ret;
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun 	if (!info->power) {
433*4882a593Smuzhiyun 		v4l2_info(&info->sd, "%s: sensor is already off\n", __func__);
434*4882a593Smuzhiyun 		return 0;
435*4882a593Smuzhiyun 	}
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	ret = regulator_bulk_disable(NOON010_NUM_SUPPLIES, info->supply);
438*4882a593Smuzhiyun 	if (ret)
439*4882a593Smuzhiyun 		return ret;
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	if (gpio_is_valid(info->gpio_nstby))
442*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nstby, 0);
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	if (gpio_is_valid(info->gpio_nreset))
445*4882a593Smuzhiyun 		gpio_set_value(info->gpio_nreset, 0);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	info->power = 0;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	v4l2_dbg(1, debug, &info->sd,  "%s: sensor is off\n", __func__);
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun 	return 0;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun 
noon010_s_ctrl(struct v4l2_ctrl * ctrl)454*4882a593Smuzhiyun static int noon010_s_ctrl(struct v4l2_ctrl *ctrl)
455*4882a593Smuzhiyun {
456*4882a593Smuzhiyun 	struct v4l2_subdev *sd = to_sd(ctrl);
457*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
458*4882a593Smuzhiyun 	int ret = 0;
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun 	v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
461*4882a593Smuzhiyun 		 __func__, ctrl->id, ctrl->val);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	mutex_lock(&info->lock);
464*4882a593Smuzhiyun 	/*
465*4882a593Smuzhiyun 	 * If the device is not powered up by the host driver do
466*4882a593Smuzhiyun 	 * not apply any controls to H/W at this time. Instead
467*4882a593Smuzhiyun 	 * the controls will be restored right after power-up.
468*4882a593Smuzhiyun 	 */
469*4882a593Smuzhiyun 	if (!info->power)
470*4882a593Smuzhiyun 		goto unlock;
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	switch (ctrl->id) {
473*4882a593Smuzhiyun 	case V4L2_CID_AUTO_WHITE_BALANCE:
474*4882a593Smuzhiyun 		ret = noon010_enable_autowhitebalance(sd, ctrl->val);
475*4882a593Smuzhiyun 		break;
476*4882a593Smuzhiyun 	case V4L2_CID_BLUE_BALANCE:
477*4882a593Smuzhiyun 		ret = cam_i2c_write(sd, MWB_BGAIN_REG, ctrl->val);
478*4882a593Smuzhiyun 		break;
479*4882a593Smuzhiyun 	case V4L2_CID_RED_BALANCE:
480*4882a593Smuzhiyun 		ret =  cam_i2c_write(sd, MWB_RGAIN_REG, ctrl->val);
481*4882a593Smuzhiyun 		break;
482*4882a593Smuzhiyun 	default:
483*4882a593Smuzhiyun 		ret = -EINVAL;
484*4882a593Smuzhiyun 	}
485*4882a593Smuzhiyun unlock:
486*4882a593Smuzhiyun 	mutex_unlock(&info->lock);
487*4882a593Smuzhiyun 	return ret;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun 
noon010_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)490*4882a593Smuzhiyun static int noon010_enum_mbus_code(struct v4l2_subdev *sd,
491*4882a593Smuzhiyun 				  struct v4l2_subdev_pad_config *cfg,
492*4882a593Smuzhiyun 				  struct v4l2_subdev_mbus_code_enum *code)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun 	if (code->index >= ARRAY_SIZE(noon010_formats))
495*4882a593Smuzhiyun 		return -EINVAL;
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	code->code = noon010_formats[code->index].code;
498*4882a593Smuzhiyun 	return 0;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun 
noon010_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)501*4882a593Smuzhiyun static int noon010_get_fmt(struct v4l2_subdev *sd,
502*4882a593Smuzhiyun 			   struct v4l2_subdev_pad_config *cfg,
503*4882a593Smuzhiyun 			   struct v4l2_subdev_format *fmt)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
506*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
509*4882a593Smuzhiyun 		if (cfg) {
510*4882a593Smuzhiyun 			mf = v4l2_subdev_get_try_format(sd, cfg, 0);
511*4882a593Smuzhiyun 			fmt->format = *mf;
512*4882a593Smuzhiyun 		}
513*4882a593Smuzhiyun 		return 0;
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun 	mf = &fmt->format;
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	mutex_lock(&info->lock);
518*4882a593Smuzhiyun 	mf->width = info->curr_win->width;
519*4882a593Smuzhiyun 	mf->height = info->curr_win->height;
520*4882a593Smuzhiyun 	mf->code = info->curr_fmt->code;
521*4882a593Smuzhiyun 	mf->colorspace = info->curr_fmt->colorspace;
522*4882a593Smuzhiyun 	mf->field = V4L2_FIELD_NONE;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	mutex_unlock(&info->lock);
525*4882a593Smuzhiyun 	return 0;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun /* Return nearest media bus frame format. */
noon010_try_fmt(struct v4l2_subdev * sd,struct v4l2_mbus_framefmt * mf)529*4882a593Smuzhiyun static const struct noon010_format *noon010_try_fmt(struct v4l2_subdev *sd,
530*4882a593Smuzhiyun 					    struct v4l2_mbus_framefmt *mf)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun 	int i = ARRAY_SIZE(noon010_formats);
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	while (--i)
535*4882a593Smuzhiyun 		if (mf->code == noon010_formats[i].code)
536*4882a593Smuzhiyun 			break;
537*4882a593Smuzhiyun 	mf->code = noon010_formats[i].code;
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	return &noon010_formats[i];
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun 
noon010_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)542*4882a593Smuzhiyun static int noon010_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
543*4882a593Smuzhiyun 			   struct v4l2_subdev_format *fmt)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
546*4882a593Smuzhiyun 	const struct noon010_frmsize *size = NULL;
547*4882a593Smuzhiyun 	const struct noon010_format *nf;
548*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf;
549*4882a593Smuzhiyun 	int ret = 0;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	nf = noon010_try_fmt(sd, &fmt->format);
552*4882a593Smuzhiyun 	noon010_try_frame_size(&fmt->format, &size);
553*4882a593Smuzhiyun 	fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
554*4882a593Smuzhiyun 	fmt->format.field = V4L2_FIELD_NONE;
555*4882a593Smuzhiyun 
556*4882a593Smuzhiyun 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
557*4882a593Smuzhiyun 		if (cfg) {
558*4882a593Smuzhiyun 			mf = v4l2_subdev_get_try_format(sd, cfg, 0);
559*4882a593Smuzhiyun 			*mf = fmt->format;
560*4882a593Smuzhiyun 		}
561*4882a593Smuzhiyun 		return 0;
562*4882a593Smuzhiyun 	}
563*4882a593Smuzhiyun 	mutex_lock(&info->lock);
564*4882a593Smuzhiyun 	if (!info->streaming) {
565*4882a593Smuzhiyun 		info->apply_new_cfg = 1;
566*4882a593Smuzhiyun 		info->curr_fmt = nf;
567*4882a593Smuzhiyun 		info->curr_win = size;
568*4882a593Smuzhiyun 	} else {
569*4882a593Smuzhiyun 		ret = -EBUSY;
570*4882a593Smuzhiyun 	}
571*4882a593Smuzhiyun 	mutex_unlock(&info->lock);
572*4882a593Smuzhiyun 	return ret;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun /* Called with struct noon010_info.lock mutex held */
noon010_base_config(struct v4l2_subdev * sd)576*4882a593Smuzhiyun static int noon010_base_config(struct v4l2_subdev *sd)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun 	int ret = noon010_bulk_write_reg(sd, noon010_base_regs);
579*4882a593Smuzhiyun 	if (!ret)
580*4882a593Smuzhiyun 		ret = noon010_set_params(sd);
581*4882a593Smuzhiyun 	if (!ret)
582*4882a593Smuzhiyun 		ret = noon010_set_flip(sd, 1, 0);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	return ret;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun 
noon010_s_power(struct v4l2_subdev * sd,int on)587*4882a593Smuzhiyun static int noon010_s_power(struct v4l2_subdev *sd, int on)
588*4882a593Smuzhiyun {
589*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
590*4882a593Smuzhiyun 	int ret;
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	mutex_lock(&info->lock);
593*4882a593Smuzhiyun 	if (on) {
594*4882a593Smuzhiyun 		ret = power_enable(info);
595*4882a593Smuzhiyun 		if (!ret)
596*4882a593Smuzhiyun 			ret = noon010_base_config(sd);
597*4882a593Smuzhiyun 	} else {
598*4882a593Smuzhiyun 		noon010_power_ctrl(sd, false, true);
599*4882a593Smuzhiyun 		ret = power_disable(info);
600*4882a593Smuzhiyun 	}
601*4882a593Smuzhiyun 	mutex_unlock(&info->lock);
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	/* Restore the controls state */
604*4882a593Smuzhiyun 	if (!ret && on)
605*4882a593Smuzhiyun 		ret = v4l2_ctrl_handler_setup(&info->hdl);
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	return ret;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun 
noon010_s_stream(struct v4l2_subdev * sd,int on)610*4882a593Smuzhiyun static int noon010_s_stream(struct v4l2_subdev *sd, int on)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
613*4882a593Smuzhiyun 	int ret = 0;
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun 	mutex_lock(&info->lock);
616*4882a593Smuzhiyun 	if (!info->streaming != !on) {
617*4882a593Smuzhiyun 		ret = noon010_power_ctrl(sd, false, !on);
618*4882a593Smuzhiyun 		if (!ret)
619*4882a593Smuzhiyun 			info->streaming = on;
620*4882a593Smuzhiyun 	}
621*4882a593Smuzhiyun 	if (!ret && on && info->apply_new_cfg) {
622*4882a593Smuzhiyun 		ret = noon010_set_params(sd);
623*4882a593Smuzhiyun 		if (!ret)
624*4882a593Smuzhiyun 			info->apply_new_cfg = 0;
625*4882a593Smuzhiyun 	}
626*4882a593Smuzhiyun 	mutex_unlock(&info->lock);
627*4882a593Smuzhiyun 	return ret;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun 
noon010_log_status(struct v4l2_subdev * sd)630*4882a593Smuzhiyun static int noon010_log_status(struct v4l2_subdev *sd)
631*4882a593Smuzhiyun {
632*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 	v4l2_ctrl_handler_log_status(&info->hdl, sd->name);
635*4882a593Smuzhiyun 	return 0;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun 
noon010_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)638*4882a593Smuzhiyun static int noon010_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
639*4882a593Smuzhiyun {
640*4882a593Smuzhiyun 	struct v4l2_mbus_framefmt *mf = v4l2_subdev_get_try_format(sd, fh->pad, 0);
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun 	mf->width = noon010_sizes[0].width;
643*4882a593Smuzhiyun 	mf->height = noon010_sizes[0].height;
644*4882a593Smuzhiyun 	mf->code = noon010_formats[0].code;
645*4882a593Smuzhiyun 	mf->colorspace = V4L2_COLORSPACE_JPEG;
646*4882a593Smuzhiyun 	mf->field = V4L2_FIELD_NONE;
647*4882a593Smuzhiyun 	return 0;
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun static const struct v4l2_subdev_internal_ops noon010_subdev_internal_ops = {
651*4882a593Smuzhiyun 	.open = noon010_open,
652*4882a593Smuzhiyun };
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun static const struct v4l2_ctrl_ops noon010_ctrl_ops = {
655*4882a593Smuzhiyun 	.s_ctrl = noon010_s_ctrl,
656*4882a593Smuzhiyun };
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun static const struct v4l2_subdev_core_ops noon010_core_ops = {
659*4882a593Smuzhiyun 	.s_power	= noon010_s_power,
660*4882a593Smuzhiyun 	.log_status	= noon010_log_status,
661*4882a593Smuzhiyun };
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun static const struct v4l2_subdev_pad_ops noon010_pad_ops = {
664*4882a593Smuzhiyun 	.enum_mbus_code	= noon010_enum_mbus_code,
665*4882a593Smuzhiyun 	.get_fmt	= noon010_get_fmt,
666*4882a593Smuzhiyun 	.set_fmt	= noon010_set_fmt,
667*4882a593Smuzhiyun };
668*4882a593Smuzhiyun 
669*4882a593Smuzhiyun static const struct v4l2_subdev_video_ops noon010_video_ops = {
670*4882a593Smuzhiyun 	.s_stream	= noon010_s_stream,
671*4882a593Smuzhiyun };
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun static const struct v4l2_subdev_ops noon010_ops = {
674*4882a593Smuzhiyun 	.core	= &noon010_core_ops,
675*4882a593Smuzhiyun 	.pad	= &noon010_pad_ops,
676*4882a593Smuzhiyun 	.video	= &noon010_video_ops,
677*4882a593Smuzhiyun };
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun /* Return 0 if NOON010PC30L sensor type was detected or -ENODEV otherwise. */
noon010_detect(struct i2c_client * client,struct noon010_info * info)680*4882a593Smuzhiyun static int noon010_detect(struct i2c_client *client, struct noon010_info *info)
681*4882a593Smuzhiyun {
682*4882a593Smuzhiyun 	int ret;
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	ret = power_enable(info);
685*4882a593Smuzhiyun 	if (ret)
686*4882a593Smuzhiyun 		return ret;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
689*4882a593Smuzhiyun 	if (ret < 0)
690*4882a593Smuzhiyun 		dev_err(&client->dev, "I2C read failed: 0x%X\n", ret);
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun 	power_disable(info);
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	return ret == NOON010PC30_ID ? 0 : -ENODEV;
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun 
noon010_probe(struct i2c_client * client,const struct i2c_device_id * id)697*4882a593Smuzhiyun static int noon010_probe(struct i2c_client *client,
698*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
699*4882a593Smuzhiyun {
700*4882a593Smuzhiyun 	struct noon010_info *info;
701*4882a593Smuzhiyun 	struct v4l2_subdev *sd;
702*4882a593Smuzhiyun 	const struct noon010pc30_platform_data *pdata
703*4882a593Smuzhiyun 		= client->dev.platform_data;
704*4882a593Smuzhiyun 	int ret;
705*4882a593Smuzhiyun 	int i;
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun 	if (!pdata) {
708*4882a593Smuzhiyun 		dev_err(&client->dev, "No platform data!\n");
709*4882a593Smuzhiyun 		return -EIO;
710*4882a593Smuzhiyun 	}
711*4882a593Smuzhiyun 
712*4882a593Smuzhiyun 	info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
713*4882a593Smuzhiyun 	if (!info)
714*4882a593Smuzhiyun 		return -ENOMEM;
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	mutex_init(&info->lock);
717*4882a593Smuzhiyun 	sd = &info->sd;
718*4882a593Smuzhiyun 	v4l2_i2c_subdev_init(sd, client, &noon010_ops);
719*4882a593Smuzhiyun 	/* Static name; NEVER use in new drivers! */
720*4882a593Smuzhiyun 	strscpy(sd->name, MODULE_NAME, sizeof(sd->name));
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun 	sd->internal_ops = &noon010_subdev_internal_ops;
723*4882a593Smuzhiyun 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
724*4882a593Smuzhiyun 
725*4882a593Smuzhiyun 	v4l2_ctrl_handler_init(&info->hdl, 3);
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
728*4882a593Smuzhiyun 			  V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
729*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
730*4882a593Smuzhiyun 			  V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
731*4882a593Smuzhiyun 	v4l2_ctrl_new_std(&info->hdl, &noon010_ctrl_ops,
732*4882a593Smuzhiyun 			  V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun 	sd->ctrl_handler = &info->hdl;
735*4882a593Smuzhiyun 
736*4882a593Smuzhiyun 	ret = info->hdl.error;
737*4882a593Smuzhiyun 	if (ret)
738*4882a593Smuzhiyun 		goto np_err;
739*4882a593Smuzhiyun 
740*4882a593Smuzhiyun 	info->i2c_reg_page	= -1;
741*4882a593Smuzhiyun 	info->gpio_nreset	= -EINVAL;
742*4882a593Smuzhiyun 	info->gpio_nstby	= -EINVAL;
743*4882a593Smuzhiyun 	info->curr_fmt		= &noon010_formats[0];
744*4882a593Smuzhiyun 	info->curr_win		= &noon010_sizes[0];
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun 	if (gpio_is_valid(pdata->gpio_nreset)) {
747*4882a593Smuzhiyun 		ret = devm_gpio_request_one(&client->dev, pdata->gpio_nreset,
748*4882a593Smuzhiyun 					    GPIOF_OUT_INIT_LOW,
749*4882a593Smuzhiyun 					    "NOON010PC30 NRST");
750*4882a593Smuzhiyun 		if (ret) {
751*4882a593Smuzhiyun 			dev_err(&client->dev, "GPIO request error: %d\n", ret);
752*4882a593Smuzhiyun 			goto np_err;
753*4882a593Smuzhiyun 		}
754*4882a593Smuzhiyun 		info->gpio_nreset = pdata->gpio_nreset;
755*4882a593Smuzhiyun 		gpio_export(info->gpio_nreset, 0);
756*4882a593Smuzhiyun 	}
757*4882a593Smuzhiyun 
758*4882a593Smuzhiyun 	if (gpio_is_valid(pdata->gpio_nstby)) {
759*4882a593Smuzhiyun 		ret = devm_gpio_request_one(&client->dev, pdata->gpio_nstby,
760*4882a593Smuzhiyun 					    GPIOF_OUT_INIT_LOW,
761*4882a593Smuzhiyun 					    "NOON010PC30 NSTBY");
762*4882a593Smuzhiyun 		if (ret) {
763*4882a593Smuzhiyun 			dev_err(&client->dev, "GPIO request error: %d\n", ret);
764*4882a593Smuzhiyun 			goto np_err;
765*4882a593Smuzhiyun 		}
766*4882a593Smuzhiyun 		info->gpio_nstby = pdata->gpio_nstby;
767*4882a593Smuzhiyun 		gpio_export(info->gpio_nstby, 0);
768*4882a593Smuzhiyun 	}
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	for (i = 0; i < NOON010_NUM_SUPPLIES; i++)
771*4882a593Smuzhiyun 		info->supply[i].supply = noon010_supply_name[i];
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun 	ret = devm_regulator_bulk_get(&client->dev, NOON010_NUM_SUPPLIES,
774*4882a593Smuzhiyun 				 info->supply);
775*4882a593Smuzhiyun 	if (ret)
776*4882a593Smuzhiyun 		goto np_err;
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun 	info->pad.flags = MEDIA_PAD_FL_SOURCE;
779*4882a593Smuzhiyun 	sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
780*4882a593Smuzhiyun 	ret = media_entity_pads_init(&sd->entity, 1, &info->pad);
781*4882a593Smuzhiyun 	if (ret < 0)
782*4882a593Smuzhiyun 		goto np_err;
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	ret = noon010_detect(client, info);
785*4882a593Smuzhiyun 	if (!ret)
786*4882a593Smuzhiyun 		return 0;
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun np_err:
789*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&info->hdl);
790*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
791*4882a593Smuzhiyun 	return ret;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun 
noon010_remove(struct i2c_client * client)794*4882a593Smuzhiyun static int noon010_remove(struct i2c_client *client)
795*4882a593Smuzhiyun {
796*4882a593Smuzhiyun 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
797*4882a593Smuzhiyun 	struct noon010_info *info = to_noon010(sd);
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	v4l2_device_unregister_subdev(sd);
800*4882a593Smuzhiyun 	v4l2_ctrl_handler_free(&info->hdl);
801*4882a593Smuzhiyun 	media_entity_cleanup(&sd->entity);
802*4882a593Smuzhiyun 
803*4882a593Smuzhiyun 	return 0;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun static const struct i2c_device_id noon010_id[] = {
807*4882a593Smuzhiyun 	{ MODULE_NAME, 0 },
808*4882a593Smuzhiyun 	{ },
809*4882a593Smuzhiyun };
810*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, noon010_id);
811*4882a593Smuzhiyun 
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun static struct i2c_driver noon010_i2c_driver = {
814*4882a593Smuzhiyun 	.driver = {
815*4882a593Smuzhiyun 		.name = MODULE_NAME
816*4882a593Smuzhiyun 	},
817*4882a593Smuzhiyun 	.probe		= noon010_probe,
818*4882a593Smuzhiyun 	.remove		= noon010_remove,
819*4882a593Smuzhiyun 	.id_table	= noon010_id,
820*4882a593Smuzhiyun };
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun module_i2c_driver(noon010_i2c_driver);
823*4882a593Smuzhiyun 
824*4882a593Smuzhiyun MODULE_DESCRIPTION("Siliconfile NOON010PC30 camera driver");
825*4882a593Smuzhiyun MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
826*4882a593Smuzhiyun MODULE_LICENSE("GPL");
827